Difference between revisions of "GPU/Internal Registers"

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(GPUREG_GSH_INPUTBUFFER_CONFIG GPUREG_VSH_INPUTBUFFER_CONFIG)
(bunch of shader registers)
Line 3,308: Line 3,308:
  
 
This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.
 
This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.
 +
 +
==== GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW ====
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-3
 +
| Index of geometry shader input register which the 1st attribute will be stored in.
 +
|-
 +
| 4-7
 +
| Index of geometry shader input register which the 2nd attribute will be stored in.
 +
|-
 +
| 8-11
 +
| Index of geometry shader input register which the 3rd attribute will be stored in.
 +
|-
 +
| 12-15
 +
| Index of geometry shader input register which the 4th attribute will be stored in.
 +
|-
 +
| 16-19
 +
| Index of geometry shader input register which the 5th attribute will be stored in.
 +
|-
 +
| 20-23
 +
| Index of geometry shader input register which the 6th attribute will be stored in.
 +
|-
 +
| 24-27
 +
| Index of geometry shader input register which the 7th attribute will be stored in.
 +
|-
 +
| 28-31
 +
| Index of geometry shader input register which the 8th attribute will be stored in.
 +
|}
 +
 +
This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
 +
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.
 +
 +
==== GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH ====
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-3
 +
| Index of geometry shader input register which the 9th attribute will be stored in.
 +
|-
 +
| 4-7
 +
| Index of geometry shader input register which the 10th attribute will be stored in.
 +
|-
 +
| 8-11
 +
| Index of geometry shader input register which the 11th attribute will be stored in.
 +
|-
 +
| 12-15
 +
| Index of geometry shader input register which the 12th attribute will be stored in.
 +
|-
 +
| 16-19
 +
| Index of geometry shader input register which the 13th attribute will be stored in.
 +
|-
 +
| 20-23
 +
| Index of geometry shader input register which the 14th attribute will be stored in.
 +
|-
 +
| 24-27
 +
| Index of geometry shader input register which the 15th attribute will be stored in.
 +
|-
 +
| 28-31
 +
| Index of geometry shader input register which the 16th attribute will be stored in.
 +
|}
 +
 +
This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes.
 +
For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.
 +
 +
==== GPUREG_GSH_OUTMAP_MASK ====
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0
 +
| Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
 +
|-
 +
| 1
 +
| Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
 +
|-
 +
| 2
 +
| Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
 +
|-
 +
| 3
 +
| Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
 +
|-
 +
| 4
 +
| Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
 +
|-
 +
| 5
 +
| Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
 +
|-
 +
| 6
 +
| Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
 +
|}
 +
 +
This register toggles the geometry shader unit's output registers.
 +
 +
==== GPUREG_GSH_FLOATUNIFORM_CONFIG ====
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-6
 +
| Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
 +
|-
 +
| 31
 +
| Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32)
 +
|}
 +
 +
This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_GSH_FLOATUNIFORM_DATA|GPUREG_GSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.
 +
 +
==== GPUREG_GSH_FLOATUNIFORM_DATA ====
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-31
 +
| Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details)
 +
|}
 +
 +
This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_GSH_FLOATUNIFORM_CONFIG|GPUREG_GSH_FLOATUNIFORM_CONFIG]].
 +
 +
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
 +
 +
** first word : ZZWWWWWW
 +
** second word : YYYYZZZZ
 +
** third word : XXXXXXYY
 +
 +
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
 +
 +
=== GPUREG_GSH_CODE_CONFIG ===
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-11
 +
| Target geometry shader code offset for data transfer.
 +
|}
 +
 +
This register is used to set the offset at which upcoming geometry shader code data transferred through [[#GPUREG_GSH_CODE_DATA|GPUREG_GSH_CODE_DATA]] should be written.
 +
 +
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
 +
 +
=== GPUREG_GSH_CODE_DATA ===
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-31
 +
| Geometry shader instruction data.
 +
|}
 +
 +
This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by [[#GPUREG_GSH_CODE_CONFIG|GPUREG_GSH_CODE_CONFIG]]. The offset in question is incremented after each write to this register.
 +
 +
=== GPUREG_GSH_OPDESCS_CONFIG ===
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-6
 +
| Target geometry shader operand descriptor offset for data transfer.
 +
|}
 +
 +
This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through [[#GPUREG_GSH_OPDESCS_DATA|GPUREG_GSH_OPDESCS_DATA]] should be written.
 +
 +
=== GPUREG_GSH_OPDESCS_DATA ===
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-31
 +
| Geometry shader operand descriptor data.
 +
|}
 +
 +
This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by [[#GPUREG_GSH_OPDESCS_CONFIG|GPUREG_GSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.
  
 
=== Vertex shader registers ===
 
=== Vertex shader registers ===
Line 3,487: Line 3,670:
  
 
This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.
 
This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.
 +
 +
==== GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW ====
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-3
 +
| Index of vertex shader input register which the 1st attribute will be stored in.
 +
|-
 +
| 4-7
 +
| Index of vertex shader input register which the 2nd attribute will be stored in.
 +
|-
 +
| 8-11
 +
| Index of vertex shader input register which the 3rd attribute will be stored in.
 +
|-
 +
| 12-15
 +
| Index of vertex shader input register which the 4th attribute will be stored in.
 +
|-
 +
| 16-19
 +
| Index of vertex shader input register which the 5th attribute will be stored in.
 +
|-
 +
| 20-23
 +
| Index of vertex shader input register which the 6th attribute will be stored in.
 +
|-
 +
| 24-27
 +
| Index of vertex shader input register which the 7th attribute will be stored in.
 +
|-
 +
| 28-31
 +
| Index of vertex shader input register which the 8th attribute will be stored in.
 +
|}
 +
 +
This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
 +
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.
 +
 +
==== GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH ====
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-3
 +
| Index of vertex shader input register which the 9th attribute will be stored in.
 +
|-
 +
| 4-7
 +
| Index of vertex shader input register which the 10th attribute will be stored in.
 +
|-
 +
| 8-11
 +
| Index of vertex shader input register which the 11th attribute will be stored in.
 +
|-
 +
| 12-15
 +
| Index of vertex shader input register which the 12th attribute will be stored in.
 +
|-
 +
| 16-19
 +
| Index of vertex shader input register which the 13th attribute will be stored in.
 +
|-
 +
| 20-23
 +
| Index of vertex shader input register which the 14th attribute will be stored in.
 +
|-
 +
| 24-27
 +
| Index of vertex shader input register which the 15th attribute will be stored in.
 +
|-
 +
| 28-31
 +
| Index of vertex shader input register which the 16th attribute will be stored in.
 +
|}
 +
 +
This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes.
 +
For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.
 +
 +
==== GPUREG_VSH_OUTMAP_MASK ====
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0
 +
| Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
 +
|-
 +
| 1
 +
| Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
 +
|-
 +
| 2
 +
| Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
 +
|-
 +
| 3
 +
| Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
 +
|-
 +
| 4
 +
| Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
 +
|-
 +
| 5
 +
| Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
 +
|-
 +
| 6
 +
| Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
 +
|-
 +
| 7
 +
| Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled)
 +
|-
 +
| 8
 +
| Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled)
 +
|-
 +
| 9
 +
| Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled)
 +
|-
 +
| 10
 +
| Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled)
 +
|-
 +
| 11
 +
| Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled)
 +
|-
 +
| 12
 +
| Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled)
 +
|-
 +
| 13
 +
| Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled)
 +
|-
 +
| 14
 +
| Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled)
 +
|-
 +
| 15
 +
| Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled)
 +
|}
 +
 +
This register toggles the vertex shader units' output registers.
 +
 +
==== GPUREG_VSH_FLOATUNIFORM_CONFIG ====
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-6
 +
| Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
 +
|-
 +
| 31
 +
| Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32)
 +
|}
 +
 +
This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]], though writing to one register does not make writing to the other mandatory.
 +
 +
==== GPUREG_VSH_FLOATUNIFORM_DATA ====
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-31
 +
| Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details)
 +
|}
 +
 +
This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]]. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]].
 +
 +
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
 +
 +
** first word : ZZWWWWWW
 +
** second word : YYYYZZZZ
 +
** third word : XXXXXXYY
 +
 +
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
 +
 +
=== GPUREG_VSH_CODE_CONFIG ===
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-11
 +
| Target vertex shader code offset for data transfer.
 +
|}
 +
 +
This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODE_DATA|GPUREG_VSH_CODE_DATA]] should be written.
 +
 +
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
 +
 +
=== GPUREG_VSH_CODE_CONFIG ===
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-11
 +
| Target vertex shader code offset for data transfer.
 +
|}
 +
 +
This register is used to set the offset at which upcoming vertex shader code data transferred through [[#GPUREG_VSH_CODE_DATA|GPUREG_VSH_CODE_DATA]] should be written.
 +
 +
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.
 +
 +
=== GPUREG_VSH_CODE_DATA ===
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-31
 +
| Vertex shader instruction data.
 +
|}
 +
 +
This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by [[#GPUREG_VSH_CODE_CONFIG|GPUREG_VSH_CODE_CONFIG]]. The offset in question is incremented after each write to this register.
 +
 +
=== GPUREG_VSH_OPDESCS_CONFIG ===
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-6
 +
| Target vertex shader operand descriptor offset for data transfer.
 +
|}
 +
 +
This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through [[#GPUREG_VSH_OPDESCS_DATA|GPUREG_VSH_OPDESCS_DATA]] should be written.
 +
 +
=== GPUREG_VSH_OPDESCS_DATA ===
 +
 +
{| class="wikitable" border="1"
 +
! Bits
 +
! Description
 +
|-
 +
| 0-31
 +
| Vertex shader operand descriptor data.
 +
|}
 +
 +
This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by [[#GPUREG_VSH_OPDESCS_CONFIG|GPUREG_VSH_OPDESCS_CONFIG]]. The offset in question is incremented after each write to this register.

Revision as of 04:09, 17 December 2014

(this page is hugely WIP)

Overview

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

Types

There are three main types of registers :

  • configuration registers, which directly map to various rendering properties (for example : GPUREG_FACECULLING_CONFIG)
  • data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : GPUREG_GSH_CODE_DATA)
  • action triggering registers, which tell the GPU to do something, like draw a primitive (for example : GPUREG_DRAWARRAYS)

Aliases

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU Commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to GPUREG_VSH_FLOATUNIFORM_DATA so that a consecutively writing command based at 02C0 will write its first parameter to GPUREG_VSH_FLOATUNIFORM_CONFIG and ever subsequent ones to GPUREG_VSH_FLOATUNIFORM_DATA

Register list

Register ID Register name Notes
0000 GPUREG_0000
0001 GPUREG_0001
0002 GPUREG_0002
0003 GPUREG_0003
0004 GPUREG_0004
0005 GPUREG_0005
0006 GPUREG_0006
0007 GPUREG_0007
0008 GPUREG_0008
0009 GPUREG_0009
000A GPUREG_000A
000B GPUREG_000B
000C GPUREG_000C
000D GPUREG_000D
000E GPUREG_000E
000F GPUREG_000F
0010 GPUREG_FINALIZE
0011 GPUREG_0011
0012 GPUREG_0012
0013 GPUREG_0013
0014 GPUREG_0014
0015 GPUREG_0015
0016 GPUREG_0016
0017 GPUREG_0017
0018 GPUREG_0018
0019 GPUREG_0019
001A GPUREG_001A
001B GPUREG_001B
001C GPUREG_001C
001D GPUREG_001D
001E GPUREG_001E
001F GPUREG_001F
0020 GPUREG_0020
0021 GPUREG_0021
0022 GPUREG_0022
0023 GPUREG_0023
0024 GPUREG_0024
0025 GPUREG_0025
0026 GPUREG_0026
0027 GPUREG_0027
0028 GPUREG_0028
0029 GPUREG_0029
002A GPUREG_002A
002B GPUREG_002B
002C GPUREG_002C
002D GPUREG_002D
002E GPUREG_002E
002F GPUREG_002F
0030 GPUREG_0030
0031 GPUREG_0031
0032 GPUREG_0032
0033 GPUREG_0033
0034 GPUREG_0034
0035 GPUREG_0035
0036 GPUREG_0036
0037 GPUREG_0037
0038 GPUREG_0038
0039 GPUREG_0039
003A GPUREG_003A
003B GPUREG_003B
003C GPUREG_003C
003D GPUREG_003D
003E GPUREG_003E
003F GPUREG_003F
0040 GPUREG_FACECULLING_CONFIG
0041 GPUREG_0041
0042 GPUREG_0042
0043 GPUREG_0043
0044 GPUREG_0044
0045 GPUREG_0045
0046 GPUREG_0046
0047 GPUREG_0047
0048 GPUREG_0048
0049 GPUREG_0049
004A GPUREG_004A
004B GPUREG_004B
004C GPUREG_004C
004D GPUREG_DEPTHRANGE_NEAR
004E GPUREG_DEPTHRANGE_FAR
004F GPUREG_SH_OUTMAP_TOTAL
0050 GPUREG_SH_OUTMAP_O0
0051 GPUREG_SH_OUTMAP_O1
0052 GPUREG_SH_OUTMAP_O2
0053 GPUREG_SH_OUTMAP_O3
0054 GPUREG_SH_OUTMAP_O4
0055 GPUREG_SH_OUTMAP_O5
0056 GPUREG_SH_OUTMAP_O6
0057 GPUREG_0057
0058 GPUREG_0058
0059 GPUREG_0059
005A GPUREG_005A
005B GPUREG_005B
005C GPUREG_005C
005D GPUREG_005D
005E GPUREG_005E
005F GPUREG_005F
0060 GPUREG_0060
0061 GPUREG_0061
0062 GPUREG_0062
0063 GPUREG_0063
0064 GPUREG_0064
0065 GPUREG_SCISSORTEST_MODE
0066 GPUREG_SCISSORTEST_POS
0067 GPUREG_SCISSORTEST_DIM
0068 GPUREG_0068
0069 GPUREG_0069
006A GPUREG_006A
006B GPUREG_006B
006C GPUREG_006C
006D GPUREG_006D
006E GPUREG_006E
006F GPUREG_006F
0070 GPUREG_0070
0071 GPUREG_0071
0072 GPUREG_0072
0073 GPUREG_0073
0074 GPUREG_0074
0075 GPUREG_0075
0076 GPUREG_0076
0077 GPUREG_0077
0078 GPUREG_0078
0079 GPUREG_0079
007A GPUREG_007A
007B GPUREG_007B
007C GPUREG_007C
007D GPUREG_007D
007E GPUREG_007E
007F GPUREG_007F
0080 GPUREG_TEXUNITS_CONFIG
0081 GPUREG_0081
0082 GPUREG_TEXUNIT0_DIM
0083 GPUREG_TEXUNIT0_PARAM
0084 GPUREG_0084
0085 GPUREG_TEXUNIT0_LOC
0086 GPUREG_0086
0087 GPUREG_0087
0088 GPUREG_0088
0089 GPUREG_0089
008A GPUREG_008A
008B GPUREG_008B
008C GPUREG_008C
008D GPUREG_008D
008E GPUREG_TEXUNIT0_TYPE
008F GPUREG_008F
0090 GPUREG_0090
0091 GPUREG_0091
0092 GPUREG_TEXUNIT1_DIM
0093 GPUREG_TEXUNIT1_PARAM
0094 GPUREG_0094
0095 GPUREG_TEXUNIT1_LOC
0096 GPUREG_TEXUNIT1_TYPE
0097 GPUREG_0097
0098 GPUREG_0098
0099 GPUREG_0099
009A GPUREG_TEXUNIT2_DIM
009B GPUREG_TEXUNIT2_PARAM
009C GPUREG_009C
009D GPUREG_TEXUNIT2_LOC
009E GPUREG_TEXUNIT2_TYPE
009F GPUREG_009F
00A0 GPUREG_00A0
00A1 GPUREG_00A1
00A2 GPUREG_00A2
00A3 GPUREG_00A3
00A4 GPUREG_00A4
00A5 GPUREG_00A5
00A6 GPUREG_00A6
00A7 GPUREG_00A7
00A8 GPUREG_00A8
00A9 GPUREG_00A9
00AA GPUREG_00AA
00AB GPUREG_00AB
00AC GPUREG_00AC
00AD GPUREG_00AD
00AE GPUREG_00AE
00AF GPUREG_00AF
00B0 GPUREG_00B0
00B1 GPUREG_00B1
00B2 GPUREG_00B2
00B3 GPUREG_00B3
00B4 GPUREG_00B4
00B5 GPUREG_00B5
00B6 GPUREG_00B6
00B7 GPUREG_00B7
00B8 GPUREG_00B8
00B9 GPUREG_00B9
00BA GPUREG_00BA
00BB GPUREG_00BB
00BC GPUREG_00BC
00BD GPUREG_00BD
00BE GPUREG_00BE
00BF GPUREG_00BF
00C0 GPUREG_TEXENV0_CONFIG0
00C1 GPUREG_TEXENV0_CONFIG1
00C2 GPUREG_TEXENV0_CONFIG2
00C3 GPUREG_TEXENV0_CONFIG3
00C4 GPUREG_TEXENV0_CONFIG4
00C5 GPUREG_00C5
00C6 GPUREG_00C6
00C7 GPUREG_00C7
00C8 GPUREG_TEXENV1_CONFIG0
00C9 GPUREG_TEXENV1_CONFIG1
00CA GPUREG_TEXENV1_CONFIG2
00CB GPUREG_TEXENV1_CONFIG3
00CC GPUREG_TEXENV1_CONFIG4
00CD GPUREG_00CD
00CE GPUREG_00CE
00CF GPUREG_00CF
00D0 GPUREG_TEXENV2_CONFIG0
00D1 GPUREG_TEXENV2_CONFIG1
00D2 GPUREG_TEXENV2_CONFIG2
00D3 GPUREG_TEXENV2_CONFIG3
00D4 GPUREG_TEXENV2_CONFIG4
00D5 GPUREG_00D5
00D6 GPUREG_00D6
00D7 GPUREG_00D7
00D8 GPUREG_TEXENV3_CONFIG0
00D9 GPUREG_TEXENV3_CONFIG1
00DA GPUREG_TEXENV3_CONFIG2
00DB GPUREG_TEXENV3_CONFIG3
00DC GPUREG_TEXENV3_CONFIG4
00DD GPUREG_00DD
00DE GPUREG_00DE
00DF GPUREG_00DF
00E0 GPUREG_00E0
00E1 GPUREG_00E1
00E2 GPUREG_00E2
00E3 GPUREG_00E3
00E4 GPUREG_00E4
00E5 GPUREG_00E5
00E6 GPUREG_00E6
00E7 GPUREG_00E7
00E8 GPUREG_00E8
00E9 GPUREG_00E9
00EA GPUREG_00EA
00EB GPUREG_00EB
00EC GPUREG_00EC
00ED GPUREG_00ED
00EE GPUREG_00EE
00EF GPUREG_00EF
00F0 GPUREG_TEXENV4_CONFIG0
00F1 GPUREG_TEXENV4_CONFIG1
00F2 GPUREG_TEXENV4_CONFIG2
00F3 GPUREG_TEXENV4_CONFIG3
00F4 GPUREG_TEXENV4_CONFIG4
00F5 GPUREG_00F5
00F6 GPUREG_00F6
00F7 GPUREG_00F7
00F8 GPUREG_TEXENV5_CONFIG0
00F9 GPUREG_TEXENV5_CONFIG1
00FA GPUREG_TEXENV5_CONFIG2
00FB GPUREG_TEXENV5_CONFIG3
00FC GPUREG_TEXENV5_CONFIG4
00FD GPUREG_00FD
00FE GPUREG_00FE
00FF GPUREG_00FF
0100 GPUREG_COLOROUTPUT_CONFIG ?
0101 GPUREG_BLEND_CONFIG
0102 GPUREG_COLORLOGICOP_CONFIG
0103 GPUREG_BLEND_COLOR
0104 GPUREG_ALPHATEST_CONFIG
0105 GPUREG_STENCILTEST_CONFIG
0106 GPUREG_STENCILOP_CONFIG
0107 GPUREG_DEPTHTEST_CONFIG
0108 GPUREG_0108
0109 GPUREG_0109
010A GPUREG_010A
010B GPUREG_010B
010C GPUREG_010C
010D GPUREG_010D
010E GPUREG_010E
010F GPUREG_010F
0110 GPUREG_0110
0111 GPUREG_0111
0112 GPUREG_0112
0113 GPUREG_0113
0114 GPUREG_0114
0115 GPUREG_0115
0116 GPUREG_DEPTHBUFFER_FORMAT
0117 GPUREG_COLORBUFFER_FORMAT
0118 GPUREG_0118
0119 GPUREG_0119
011A GPUREG_011A
011B GPUREG_011B
011C GPUREG_DEPTHBUFFER_LOC
011D GPUREG_COLORBUFFER_LOC
011E GPUREG_OUTBUFFER_DIM
011F GPUREG_011F
0120 GPUREG_0120
0121 GPUREG_0121
0122 GPUREG_0122
0123 GPUREG_0123
0124 GPUREG_0124
0125 GPUREG_0125
0126 GPUREG_0126
0127 GPUREG_0127
0128 GPUREG_0128
0129 GPUREG_0129
012A GPUREG_012A
012B GPUREG_012B
012C GPUREG_012C
012D GPUREG_012D
012E GPUREG_012E
012F GPUREG_012F
0130 GPUREG_0130
0131 GPUREG_0131
0132 GPUREG_0132
0133 GPUREG_0133
0134 GPUREG_0134
0135 GPUREG_0135
0136 GPUREG_0136
0137 GPUREG_0137
0138 GPUREG_0138
0139 GPUREG_0139
013A GPUREG_013A
013B GPUREG_013B
013C GPUREG_013C
013D GPUREG_013D
013E GPUREG_013E
013F GPUREG_013F
0140 GPUREG_0140
0141 GPUREG_0141
0142 GPUREG_0142
0143 GPUREG_0143
0144 GPUREG_0144
0145 GPUREG_0145
0146 GPUREG_0146
0147 GPUREG_0147
0148 GPUREG_0148
0149 GPUREG_0149
014A GPUREG_014A
014B GPUREG_014B
014C GPUREG_014C
014D GPUREG_014D
014E GPUREG_014E
014F GPUREG_014F
0150 GPUREG_0150
0151 GPUREG_0151
0152 GPUREG_0152
0153 GPUREG_0153
0154 GPUREG_0154
0155 GPUREG_0155
0156 GPUREG_0156
0157 GPUREG_0157
0158 GPUREG_0158
0159 GPUREG_0159
015A GPUREG_015A
015B GPUREG_015B
015C GPUREG_015C
015D GPUREG_015D
015E GPUREG_015E
015F GPUREG_015F
0160 GPUREG_0160
0161 GPUREG_0161
0162 GPUREG_0162
0163 GPUREG_0163
0164 GPUREG_0164
0165 GPUREG_0165
0166 GPUREG_0166
0167 GPUREG_0167
0168 GPUREG_0168
0169 GPUREG_0169
016A GPUREG_016A
016B GPUREG_016B
016C GPUREG_016C
016D GPUREG_016D
016E GPUREG_016E
016F GPUREG_016F
0170 GPUREG_0170
0171 GPUREG_0171
0172 GPUREG_0172
0173 GPUREG_0173
0174 GPUREG_0174
0175 GPUREG_0175
0176 GPUREG_0176
0177 GPUREG_0177
0178 GPUREG_0178
0179 GPUREG_0179
017A GPUREG_017A
017B GPUREG_017B
017C GPUREG_017C
017D GPUREG_017D
017E GPUREG_017E
017F GPUREG_017F
0180 GPUREG_0180
0181 GPUREG_0181
0182 GPUREG_0182
0183 GPUREG_0183
0184 GPUREG_0184
0185 GPUREG_0185
0186 GPUREG_0186
0187 GPUREG_0187
0188 GPUREG_0188
0189 GPUREG_0189
018A GPUREG_018A
018B GPUREG_018B
018C GPUREG_018C
018D GPUREG_018D
018E GPUREG_018E
018F GPUREG_018F
0190 GPUREG_0190
0191 GPUREG_0191
0192 GPUREG_0192
0193 GPUREG_0193
0194 GPUREG_0194
0195 GPUREG_0195
0196 GPUREG_0196
0197 GPUREG_0197
0198 GPUREG_0198
0199 GPUREG_0199
019A GPUREG_019A
019B GPUREG_019B
019C GPUREG_019C
019D GPUREG_019D
019E GPUREG_019E
019F GPUREG_019F
01A0 GPUREG_01A0
01A1 GPUREG_01A1
01A2 GPUREG_01A2
01A3 GPUREG_01A3
01A4 GPUREG_01A4
01A5 GPUREG_01A5
01A6 GPUREG_01A6
01A7 GPUREG_01A7
01A8 GPUREG_01A8
01A9 GPUREG_01A9
01AA GPUREG_01AA
01AB GPUREG_01AB
01AC GPUREG_01AC
01AD GPUREG_01AD
01AE GPUREG_01AE
01AF GPUREG_01AF
01B0 GPUREG_01B0
01B1 GPUREG_01B1
01B2 GPUREG_01B2
01B3 GPUREG_01B3
01B4 GPUREG_01B4
01B5 GPUREG_01B5
01B6 GPUREG_01B6
01B7 GPUREG_01B7
01B8 GPUREG_01B8
01B9 GPUREG_01B9
01BA GPUREG_01BA
01BB GPUREG_01BB
01BC GPUREG_01BC
01BD GPUREG_01BD
01BE GPUREG_01BE
01BF GPUREG_01BF
01C0 GPUREG_01C0
01C1 GPUREG_01C1
01C2 GPUREG_01C2
01C3 GPUREG_01C3
01C4 GPUREG_01C4
01C5 GPUREG_01C5
01C6 GPUREG_01C6
01C7 GPUREG_01C7
01C8 GPUREG_01C8
01C9 GPUREG_01C9
01CA GPUREG_01CA
01CB GPUREG_01CB
01CC GPUREG_01CC
01CD GPUREG_01CD
01CE GPUREG_01CE
01CF GPUREG_01CF
01D0 GPUREG_01D0
01D1 GPUREG_01D1
01D2 GPUREG_01D2
01D3 GPUREG_01D3
01D4 GPUREG_01D4
01D5 GPUREG_01D5
01D6 GPUREG_01D6
01D7 GPUREG_01D7
01D8 GPUREG_01D8
01D9 GPUREG_01D9
01DA GPUREG_01DA
01DB GPUREG_01DB
01DC GPUREG_01DC
01DD GPUREG_01DD
01DE GPUREG_01DE
01DF GPUREG_01DF
01E0 GPUREG_01E0
01E1 GPUREG_01E1
01E2 GPUREG_01E2
01E3 GPUREG_01E3
01E4 GPUREG_01E4
01E5 GPUREG_01E5
01E6 GPUREG_01E6
01E7 GPUREG_01E7
01E8 GPUREG_01E8
01E9 GPUREG_01E9
01EA GPUREG_01EA
01EB GPUREG_01EB
01EC GPUREG_01EC
01ED GPUREG_01ED
01EE GPUREG_01EE
01EF GPUREG_01EF
01F0 GPUREG_01F0
01F1 GPUREG_01F1
01F2 GPUREG_01F2
01F3 GPUREG_01F3
01F4 GPUREG_01F4
01F5 GPUREG_01F5
01F6 GPUREG_01F6
01F7 GPUREG_01F7
01F8 GPUREG_01F8
01F9 GPUREG_01F9
01FA GPUREG_01FA
01FB GPUREG_01FB
01FC GPUREG_01FC
01FD GPUREG_01FD
01FE GPUREG_01FE
01FF GPUREG_01FF
0200 GPUREG_ATTRIBBUFFERS_LOC
0201 GPUREG_ATTRIBBUFFERS_FORMAT_LOW
0202 GPUREG_ATTRIBBUFFERS_FORMAT_HIGH
0203 GPUREG_ATTRIBBUFFER0_CONFIG0
0204 GPUREG_ATTRIBBUFFER0_CONFIG1
0205 GPUREG_ATTRIBBUFFER0_CONFIG2
0206 GPUREG_ATTRIBBUFFER1_CONFIG0
0207 GPUREG_ATTRIBBUFFER1_CONFIG1
0208 GPUREG_ATTRIBBUFFER1_CONFIG2
0209 GPUREG_ATTRIBBUFFER2_CONFIG0
020A GPUREG_ATTRIBBUFFER2_CONFIG1
020B GPUREG_ATTRIBBUFFER2_CONFIG2
020C GPUREG_ATTRIBBUFFER3_CONFIG0
020D GPUREG_ATTRIBBUFFER3_CONFIG1
020E GPUREG_ATTRIBBUFFER3_CONFIG2
020F GPUREG_ATTRIBBUFFER4_CONFIG0
0210 GPUREG_ATTRIBBUFFER4_CONFIG1
0211 GPUREG_ATTRIBBUFFER4_CONFIG2
0212 GPUREG_ATTRIBBUFFER5_CONFIG0
0213 GPUREG_ATTRIBBUFFER5_CONFIG1
0214 GPUREG_ATTRIBBUFFER5_CONFIG2
0215 GPUREG_ATTRIBBUFFER6_CONFIG0
0216 GPUREG_ATTRIBBUFFER6_CONFIG1
0217 GPUREG_ATTRIBBUFFER6_CONFIG2
0218 GPUREG_ATTRIBBUFFER7_CONFIG0
0219 GPUREG_ATTRIBBUFFER7_CONFIG1
021A GPUREG_ATTRIBBUFFER7_CONFIG2
021B GPUREG_ATTRIBBUFFER8_CONFIG0
021C GPUREG_ATTRIBBUFFER8_CONFIG1
021D GPUREG_ATTRIBBUFFER8_CONFIG2
021E GPUREG_ATTRIBBUFFER9_CONFIG0
021F GPUREG_ATTRIBBUFFER9_CONFIG1
0220 GPUREG_ATTRIBBUFFER9_CONFIG2
0221 GPUREG_ATTRIBBUFFERA_CONFIG0
0222 GPUREG_ATTRIBBUFFERA_CONFIG1
0223 GPUREG_ATTRIBBUFFERA_CONFIG2
0224 GPUREG_ATTRIBBUFFERB_CONFIG0
0225 GPUREG_ATTRIBBUFFERB_CONFIG1
0226 GPUREG_ATTRIBBUFFERB_CONFIG2
0227 GPUREG_INDEXBUFFER_CONFIG
0228 GPUREG_NUMVERTICES
0229 GPUREG_GEOSTAGE_CONFIG ?
022A GPUREG_022A
022B GPUREG_022B
022C GPUREG_022C
022D GPUREG_022D
022E GPUREG_DRAWARRAYS
022F GPUREG_DRAWELEMENTS
0230 GPUREG_0230
0231 GPUREG_0231
0232 GPUREG_0232
0233 GPUREG_0233
0234 GPUREG_0234
0235 GPUREG_0235
0236 GPUREG_0236
0237 GPUREG_0237
0238 GPUREG_0238
0239 GPUREG_0239
023A GPUREG_023A
023B GPUREG_023B
023C GPUREG_023C
023D GPUREG_023D
023E GPUREG_023E
023F GPUREG_023F
0240 GPUREG_0240
0241 GPUREG_0241
0242 GPUREG_0242
0243 GPUREG_0243
0244 GPUREG_0244
0245 GPUREG_0245
0246 GPUREG_0246
0247 GPUREG_0247
0248 GPUREG_0248
0249 GPUREG_0249
024A GPUREG_024A
024B GPUREG_024B
024C GPUREG_024C
024D GPUREG_024D
024E GPUREG_024E
024F GPUREG_024F
0250 GPUREG_0250
0251 GPUREG_0251
0252 GPUREG_0252
0253 GPUREG_0253
0254 GPUREG_0254
0255 GPUREG_0255
0256 GPUREG_0256
0257 GPUREG_0257
0258 GPUREG_0258
0259 GPUREG_0259
025A GPUREG_025A
025B GPUREG_025B
025C GPUREG_025C
025D GPUREG_025D
025E GPUREG_PRIMITIVE_CONFIG ?
025F GPUREG_025F
0260 GPUREG_0260
0261 GPUREG_0261
0262 GPUREG_0262
0263 GPUREG_0263
0264 GPUREG_0264
0265 GPUREG_0265
0266 GPUREG_0266
0267 GPUREG_0267
0268 GPUREG_0268
0269 GPUREG_0269
026A GPUREG_026A
026B GPUREG_026B
026C GPUREG_026C
026D GPUREG_026D
026E GPUREG_026E
026F GPUREG_026F
0270 GPUREG_0270
0271 GPUREG_0271
0272 GPUREG_0272
0273 GPUREG_0273
0274 GPUREG_0274
0275 GPUREG_0275
0276 GPUREG_0276
0277 GPUREG_0277
0278 GPUREG_0278
0279 GPUREG_0279
027A GPUREG_027A
027B GPUREG_027B
027C GPUREG_027C
027D GPUREG_027D
027E GPUREG_027E
027F GPUREG_027F
Geometry shader registers
0280 GPUREG_GSH_BOOLUNIFORM
0281 GPUREG_GSH_INTUNIFORM_I0
0282 GPUREG_GSH_INTUNIFORM_I1
0283 GPUREG_GSH_INTUNIFORM_I2
0284 GPUREG_GSH_INTUNIFORM_I3
0285 GPUREG_0285
0286 GPUREG_0286
0287 GPUREG_0287
0288 GPUREG_0288
0289 GPUREG_GSH_INPUTBUFFER_CONFIG
028A GPUREG_GSH_ENTRYPOINT
028B GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW
028C GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH
028D GPUREG_GSH_OUTMAP_MASK
028E GPUREG_028E
028F GPUREG_028F
0290 GPUREG_GSH_FLOATUNIFORM_CONFIG
0291 GPUREG_GSH_FLOATUNIFORM_DATA
0292 GPUREG_GSH_FLOATUNIFORM_DATA
0293 GPUREG_GSH_FLOATUNIFORM_DATA
0294 GPUREG_GSH_FLOATUNIFORM_DATA
0295 GPUREG_GSH_FLOATUNIFORM_DATA
0296 GPUREG_GSH_FLOATUNIFORM_DATA
0297 GPUREG_GSH_FLOATUNIFORM_DATA
0298 GPUREG_GSH_FLOATUNIFORM_DATA
0299 GPUREG_0299
029A GPUREG_029A
029B GPUREG_GSH_CODE_CONFIG ?
029C GPUREG_GSH_CODE_DATA
029D GPUREG_029D
029E GPUREG_029E
029F GPUREG_029F
02A0 GPUREG_02A0
02A1 GPUREG_02A1
02A2 GPUREG_02A2
02A3 GPUREG_02A3
02A4 GPUREG_02A4
02A5 GPUREG_GSH_OPDESCS_CONFIG
02A6 GPUREG_GSH_OPDESCS_DATA
02A7 GPUREG_02A7
02A8 GPUREG_02A8
02A9 GPUREG_02A9
02AA GPUREG_02AA
02AB GPUREG_02AB
02AC GPUREG_02AC
02AD GPUREG_02AD
02AE GPUREG_02AE
02AF GPUREG_02AF
Vertex shader registers
02B0 GPUREG_VSH_BOOLUNIFORM
02B1 GPUREG_VSH_INTUNIFORM_I0
02B2 GPUREG_VSH_INTUNIFORM_I1
02B3 GPUREG_VSH_INTUNIFORM_I2
02B4 GPUREG_VSH_INTUNIFORM_I3
02B5 GPUREG_02B5
02B6 GPUREG_02B6
02B7 GPUREG_02B7
02B8 GPUREG_02B8
02B9 GPUREG_VSH_INPUTBUFFER_CONFIG
02BA GPUREG_VSH_ENTRYPOINT
02BB GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW
02BC GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH
02BD GPUREG_VSH_OUTMAP_MASK
02BE GPUREG_02BE
02BF GPUREG_02BF
02C0 GPUREG_VSH_FLOATUNIFORM_CONFIG
02C1 GPUREG_VSH_FLOATUNIFORM_DATA
02C2 GPUREG_VSH_FLOATUNIFORM_DATA
02C3 GPUREG_VSH_FLOATUNIFORM_DATA
02C4 GPUREG_VSH_FLOATUNIFORM_DATA
02C5 GPUREG_VSH_FLOATUNIFORM_DATA
02C6 GPUREG_VSH_FLOATUNIFORM_DATA
02C7 GPUREG_VSH_FLOATUNIFORM_DATA
02C8 GPUREG_VSH_FLOATUNIFORM_DATA
02C9 GPUREG_02C9
02CA GPUREG_02CA
02CB GPUREG_VSH_CODE_CONFIG ?
02CC GPUREG_VSH_CODE_DATA
02CD GPUREG_02CD
02CE GPUREG_02CE
02CF GPUREG_02CF
02D0 GPUREG_02D0
02D1 GPUREG_02D1
02D2 GPUREG_02D2
02D3 GPUREG_02D3
02D4 GPUREG_02D4
02D5 GPUREG_VSH_OPDESCS_CONFIG ?
02D6 GPUREG_VSH_OPDESCS_DATA
Unknown registers
02D7 GPUREG_02D7
02D8 GPUREG_02D8
02D9 GPUREG_02D9
02DA GPUREG_02DA
02DB GPUREG_02DB
02DC GPUREG_02DC
02DD GPUREG_02DD
02DE GPUREG_02DE
02DF GPUREG_02DF
02E0 GPUREG_02E0
02E1 GPUREG_02E1
02E2 GPUREG_02E2
02E3 GPUREG_02E3
02E4 GPUREG_02E4
02E5 GPUREG_02E5
02E6 GPUREG_02E6
02E7 GPUREG_02E7
02E8 GPUREG_02E8
02E9 GPUREG_02E9
02EA GPUREG_02EA
02EB GPUREG_02EB
02EC GPUREG_02EC
02ED GPUREG_02ED
02EE GPUREG_02EE
02EF GPUREG_02EF
02F0 GPUREG_02F0
02F1 GPUREG_02F1
02F2 GPUREG_02F2
02F3 GPUREG_02F3
02F4 GPUREG_02F4
02F5 GPUREG_02F5
02F6 GPUREG_02F6
02F7 GPUREG_02F7
02F8 GPUREG_02F8
02F9 GPUREG_02F9
02FA GPUREG_02FA
02FB GPUREG_02FB
02FC GPUREG_02FC
02FD GPUREG_02FD
02FE GPUREG_02FE
02FF GPUREG_02FF

GPUREG_FINALIZE

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software. Failure to write to this register in any command buffer will result in the GPU hanging.

GPUREG_GEOSTAGE_CONFIG

Bits Description
0-7 Geometry stage mode. (0=Vertex shader only, 2=Vertex shader + geometry shader)
0-7 Unknown. Often set to 1.
0-7 Unknown.
0-7 Unknown. Often set to 0.

This register configures the geometry stage of the GPU pipeline.

Geometry shader registers

GPUREG_GSH_BOOLUNIFORM

Bits Description
0 Value of geometry shader unit's b0 boolean register. (0=true, 1=false)
1 Value of geometry shader unit's b1 boolean register. (0=true, 1=false)
2 Value of geometry shader unit's b2 boolean register. (0=true, 1=false)
3 Value of geometry shader unit's b3 boolean register. (0=true, 1=false)
4 Value of geometry shader unit's b4 boolean register. (0=true, 1=false)
5 Value of geometry shader unit's b5 boolean register. (0=true, 1=false)
6 Value of geometry shader unit's b6 boolean register. (0=true, 1=false)
7 Value of geometry shader unit's b7 boolean register. (0=true, 1=false)
8 Value of geometry shader unit's b8 boolean register. (0=true, 1=false)
9 Value of geometry shader unit's b9 boolean register. (0=true, 1=false)
10 Value of geometry shader unit's b10 boolean register. (0=true, 1=false)
11 Value of geometry shader unit's b11 boolean register. (0=true, 1=false)
12 Value of geometry shader unit's b12 boolean register. (0=true, 1=false)
13 Value of geometry shader unit's b13 boolean register. (0=true, 1=false)
14 Value of geometry shader unit's b14 boolean register. (0=true, 1=false)
15 Value of geometry shader unit's b15 boolean register. (0=true, 1=false)
16-31 Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang

This register is used to set the geometry shader unit's boolean registers.

GPUREG_GSH_INTUNIFORM_I0

Bits Description
0-7 Value for geometry shader's i0.x (u8, 0-255)
8-15 Value for geometry shader's i0.y (u8, 0-255)
16-23 Value for geometry shader's i0.z (u8, 0-255)
24-31 Value for geometry shader's i0.w (u8, 0-255)

This register is used to set the geometry shader's i0 integer register.

GPUREG_GSH_INTUNIFORM_I1

Bits Description
0-7 Value for geometry shader's i1.x (u8, 0-255)
8-15 Value for geometry shader's i1.y (u8, 0-255)
16-23 Value for geometry shader's i1.z (u8, 0-255)
24-31 Value for geometry shader's i1.w (u8, 0-255)

This register is used to set the geometry shader's i1 integer register.

GPUREG_GSH_INTUNIFORM_I2

Bits Description
0-7 Value for geometry shader's i2.x (u8, 0-255)
8-15 Value for geometry shader's i2.y (u8, 0-255)
16-23 Value for geometry shader's i2.z (u8, 0-255)
24-31 Value for geometry shader's i2.w (u8, 0-255)

This register is used to set the geometry shader's i2 integer register.

GPUREG_GSH_INTUNIFORM_I3

Bits Description
0-7 Value for geometry shader's i3.x (u8, 0-255)
8-15 Value for geometry shader's i3.y (u8, 0-255)
16-23 Value for geometry shader's i3.z (u8, 0-255)
24-31 Value for geometry shader's i3.w (u8, 0-255)

This register is used to set the geometry shader's i3 integer register.

GPUREG_GSH_INPUTBUFFER_CONFIG

Bits Description
0-7 Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
8-23 Unknown. These bits typically aren't updated by games.
24-31 Unknown. This is typically set to 8 for geometry shaders.

This register is used to configure the geometry shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.


GPUREG_GSH_ENTRYPOINT

Bits Description
0-15 Geometry shader unit entrypoint, in words.
16-31 Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang

This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.

GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW

Bits Description
0-3 Index of geometry shader input register which the 1st attribute will be stored in.
4-7 Index of geometry shader input register which the 2nd attribute will be stored in.
8-11 Index of geometry shader input register which the 3rd attribute will be stored in.
12-15 Index of geometry shader input register which the 4th attribute will be stored in.
16-19 Index of geometry shader input register which the 5th attribute will be stored in.
20-23 Index of geometry shader input register which the 6th attribute will be stored in.
24-27 Index of geometry shader input register which the 7th attribute will be stored in.
28-31 Index of geometry shader input register which the 8th attribute will be stored in.

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.

GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH

Bits Description
0-3 Index of geometry shader input register which the 9th attribute will be stored in.
4-7 Index of geometry shader input register which the 10th attribute will be stored in.
8-11 Index of geometry shader input register which the 11th attribute will be stored in.
12-15 Index of geometry shader input register which the 12th attribute will be stored in.
16-19 Index of geometry shader input register which the 13th attribute will be stored in.
20-23 Index of geometry shader input register which the 14th attribute will be stored in.
24-27 Index of geometry shader input register which the 15th attribute will be stored in.
28-31 Index of geometry shader input register which the 16th attribute will be stored in.

This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.

GPUREG_GSH_OUTMAP_MASK

Bits Description
0 Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
1 Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
2 Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
3 Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
4 Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
5 Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
6 Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)

This register toggles the geometry shader unit's output registers.

GPUREG_GSH_FLOATUNIFORM_CONFIG

Bits Description
0-6 Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
31 Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32)

This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before GPUREG_GSH_FLOATUNIFORM_DATA, though writing to one register does not make writing to the other mandatory.

GPUREG_GSH_FLOATUNIFORM_DATA

Bits Description
0-31 Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details)

This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with GPUREG_GSH_FLOATUNIFORM_CONFIG. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to GPUREG_GSH_FLOATUNIFORM_CONFIG.

  • In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :

** first word : ZZWWWWWW ** second word : YYYYZZZZ ** third word : XXXXXXYY

  • In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

GPUREG_GSH_CODE_CONFIG

Bits Description
0-11 Target geometry shader code offset for data transfer.

This register is used to set the offset at which upcoming geometry shader code data transferred through GPUREG_GSH_CODE_DATA should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.

GPUREG_GSH_CODE_DATA

Bits Description
0-31 Geometry shader instruction data.

This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by GPUREG_GSH_CODE_CONFIG. The offset in question is incremented after each write to this register.

GPUREG_GSH_OPDESCS_CONFIG

Bits Description
0-6 Target geometry shader operand descriptor offset for data transfer.

This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through GPUREG_GSH_OPDESCS_DATA should be written.

GPUREG_GSH_OPDESCS_DATA

Bits Description
0-31 Geometry shader operand descriptor data.

This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by GPUREG_GSH_OPDESCS_CONFIG. The offset in question is incremented after each write to this register.

Vertex shader registers

GPUREG_VSH_BOOLUNIFORM

Bits Description
0 Value of vertex shader unit's b0 boolean register. (0=true, 1=false)
1 Value of vertex shader unit's b1 boolean register. (0=true, 1=false)
2 Value of vertex shader unit's b2 boolean register. (0=true, 1=false)
3 Value of vertex shader unit's b3 boolean register. (0=true, 1=false)
4 Value of vertex shader unit's b4 boolean register. (0=true, 1=false)
5 Value of vertex shader unit's b5 boolean register. (0=true, 1=false)
6 Value of vertex shader unit's b6 boolean register. (0=true, 1=false)
7 Value of vertex shader unit's b7 boolean register. (0=true, 1=false)
8 Value of vertex shader unit's b8 boolean register. (0=true, 1=false)
9 Value of vertex shader unit's b9 boolean register. (0=true, 1=false)
10 Value of vertex shader unit's b10 boolean register. (0=true, 1=false)
11 Value of vertex shader unit's b11 boolean register. (0=true, 1=false)
12 Value of vertex shader unit's b12 boolean register. (0=true, 1=false)
13 Value of vertex shader unit's b13 boolean register. (0=true, 1=false)
14 Value of vertex shader unit's b14 boolean register. (0=true, 1=false)
15 Value of vertex shader unit's b15 boolean register. (0=true, 1=false)
16-31 Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang

This register is used to set the vertex shader unit's boolean registers.

GPUREG_VSH_INTUNIFORM_I0

Bits Description
0-7 Value for vertex shader's i0.x (u8, 0-255)
8-15 Value for vertex shader's i0.y (u8, 0-255)
16-23 Value for vertex shader's i0.z (u8, 0-255)
24-31 Value for vertex shader's i0.w (u8, 0-255)

This register is used to set the vertex shader's i0 integer register.

GPUREG_VSH_INTUNIFORM_I1

Bits Description
0-7 Value for vertex shader's i1.x (u8, 0-255)
8-15 Value for vertex shader's i1.y (u8, 0-255)
16-23 Value for vertex shader's i1.z (u8, 0-255)
24-31 Value for vertex shader's i1.w (u8, 0-255)

This register is used to set the vertex shader's i1 integer register.

GPUREG_VSH_INTUNIFORM_I2

Bits Description
0-7 Value for vertex shader's i2.x (u8, 0-255)
8-15 Value for vertex shader's i2.y (u8, 0-255)
16-23 Value for vertex shader's i2.z (u8, 0-255)
24-31 Value for vertex shader's i2.w (u8, 0-255)

This register is used to set the vertex shader's i2 integer register.

GPUREG_VSH_INTUNIFORM_I3

Bits Description
0-7 Value for vertex shader's i3.x (u8, 0-255)
8-15 Value for vertex shader's i3.y (u8, 0-255)
16-23 Value for vertex shader's i3.z (u8, 0-255)
24-31 Value for vertex shader's i3.w (u8, 0-255)

This register is used to set the vertex shader's i3 integer register.

GPUREG_VSH_INPUTBUFFER_CONFIG

Bits Description
0-7 Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register)
8-23 Unknown. These bits typically aren't updated by games.
24-31 Unknown. This is typically set to 0xA for vertex shaders.

This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.

GPUREG_VSH_ENTRYPOINT

Bits Description
0-15 Vertex shader entrypoint, in words.
16-31 Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang

This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW

Bits Description
0-3 Index of vertex shader input register which the 1st attribute will be stored in.
4-7 Index of vertex shader input register which the 2nd attribute will be stored in.
8-11 Index of vertex shader input register which the 3rd attribute will be stored in.
12-15 Index of vertex shader input register which the 4th attribute will be stored in.
16-19 Index of vertex shader input register which the 5th attribute will be stored in.
20-23 Index of vertex shader input register which the 6th attribute will be stored in.
24-27 Index of vertex shader input register which the 7th attribute will be stored in.
28-31 Index of vertex shader input register which the 8th attribute will be stored in.

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.

GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH

Bits Description
0-3 Index of vertex shader input register which the 9th attribute will be stored in.
4-7 Index of vertex shader input register which the 10th attribute will be stored in.
8-11 Index of vertex shader input register which the 11th attribute will be stored in.
12-15 Index of vertex shader input register which the 12th attribute will be stored in.
16-19 Index of vertex shader input register which the 13th attribute will be stored in.
20-23 Index of vertex shader input register which the 14th attribute will be stored in.
24-27 Index of vertex shader input register which the 15th attribute will be stored in.
28-31 Index of vertex shader input register which the 16th attribute will be stored in.

This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.

GPUREG_VSH_OUTMAP_MASK

Bits Description
0 Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled)
1 Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled)
2 Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled)
3 Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled)
4 Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled)
5 Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled)
6 Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled)
7 Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled)
8 Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled)
9 Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled)
10 Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled)
11 Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled)
12 Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled)
13 Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled)
14 Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled)
15 Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled)

This register toggles the vertex shader units' output registers.

GPUREG_VSH_FLOATUNIFORM_CONFIG

Bits Description
0-6 Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95)
31 Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32)

This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before GPUREG_VSH_FLOATUNIFORM_DATA, though writing to one register does not make writing to the other mandatory.

GPUREG_VSH_FLOATUNIFORM_DATA

Bits Description
0-31 Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details)

This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with GPUREG_VSH_FLOATUNIFORM_CONFIG. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to GPUREG_VSH_FLOATUNIFORM_CONFIG.

  • In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :

** first word : ZZWWWWWW ** second word : YYYYZZZZ ** third word : XXXXXXYY

  • In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

GPUREG_VSH_CODE_CONFIG

Bits Description
0-11 Target vertex shader code offset for data transfer.

This register is used to set the offset at which upcoming vertex shader code data transferred through GPUREG_VSH_CODE_DATA should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.

GPUREG_VSH_CODE_CONFIG

Bits Description
0-11 Target vertex shader code offset for data transfer.

This register is used to set the offset at which upcoming vertex shader code data transferred through GPUREG_VSH_CODE_DATA should be written.

NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long.

GPUREG_VSH_CODE_DATA

Bits Description
0-31 Vertex shader instruction data.

This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by GPUREG_VSH_CODE_CONFIG. The offset in question is incremented after each write to this register.

GPUREG_VSH_OPDESCS_CONFIG

Bits Description
0-6 Target vertex shader operand descriptor offset for data transfer.

This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through GPUREG_VSH_OPDESCS_DATA should be written.

GPUREG_VSH_OPDESCS_DATA

Bits Description
0-31 Vertex shader operand descriptor data.

This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by GPUREG_VSH_OPDESCS_CONFIG. The offset in question is incremented after each write to this register.

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