Difference between revisions of "GPU/Internal Registers"
m (not vsh specific (need better name)) |
(Consistency ftw. I don't really like the term "consecutive writing mode", but that's better than making no sense.) |
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== Aliases == | == Aliases == | ||
| − | It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the GPU | + | It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for [[GPU Commands]], which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_CONFIG|GPUREG_VSH_FLOATUNIFORM_CONFIG]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATA|GPUREG_VSH_FLOATUNIFORM_DATA]] |
== Register list == | == Register list == | ||
| Line 341: | Line 341: | ||
|- | |- | ||
| 004F | | 004F | ||
| − | | [[# | + | | [[#GPUREG_VSH_OUTMAP_TOTAL|GPUREG_VSH_OUTMAP_TOTAL]] |
| | | | ||
|- | |- | ||
| 0050 | | 0050 | ||
| − | | [[# | + | | [[#GPUREG_VSH_OUTMAP_O0|GPUREG_VSH_OUTMAP_O0]] |
| | | | ||
|- | |- | ||
| 0051 | | 0051 | ||
| − | | [[# | + | | [[#GPUREG_VSH_OUTMAP_O1|GPUREG_VSH_OUTMAP_O1]] |
| | | | ||
|- | |- | ||
| 0052 | | 0052 | ||
| − | | [[# | + | | [[#GPUREG_VSH_OUTMAP_O2|GPUREG_VSH_OUTMAP_O2]] |
| | | | ||
|- | |- | ||
| 0053 | | 0053 | ||
| − | | [[# | + | | [[#GPUREG_VSH_OUTMAP_O3|GPUREG_VSH_OUTMAP_O3]] |
| | | | ||
|- | |- | ||
| 0054 | | 0054 | ||
| − | | [[# | + | | [[#GPUREG_VSH_OUTMAP_O4|GPUREG_VSH_OUTMAP_O4]] |
| | | | ||
|- | |- | ||
| 0055 | | 0055 | ||
| − | | [[# | + | | [[#GPUREG_VSH_OUTMAP_O5|GPUREG_VSH_OUTMAP_O5]] |
| | | | ||
|- | |- | ||
| 0056 | | 0056 | ||
| − | | [[# | + | | [[#GPUREG_VSH_OUTMAP_O6|GPUREG_VSH_OUTMAP_O6]] |
| | | | ||
|- | |- | ||
| Line 2,629: | Line 2,629: | ||
|- | |- | ||
| 028B | | 028B | ||
| − | | [[# | + | | [[#GPUREG_028B|GPUREG_028B]] |
| | | | ||
|- | |- | ||
| 028C | | 028C | ||
| − | | [[# | + | | [[#GPUREG_028C|GPUREG_028C]] |
| | | | ||
|- | |- | ||
| 028D | | 028D | ||
| − | | [[# | + | | [[#GPUREG_028D|GPUREG_028D]] |
| | | | ||
|- | |- | ||
Revision as of 14:27, 12 December 2014
(this page is hugely WIP)
Overview
GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.
Types
There are three main types of registers :
- configuration registers, which directly map to various rendering properties (for example : GPUREG_FACECULLING_CONFIG)
- data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : GPUREG_GSH_CODE_DATA)
- action triggering registers, which tell the GPU to do something, like draw a primitive (for example : GPUREG_DRAWARRAYS)
Aliases
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU Commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to GPUREG_VSH_FLOATUNIFORM_DATA so that a consecutively writing command based at 02C0 will write its first parameter to GPUREG_VSH_FLOATUNIFORM_CONFIG and ever subsequent ones to GPUREG_VSH_FLOATUNIFORM_DATA
Register list
GPUREG_FINALIZE
Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software. Failure to write to this register in any command buffer will result in the GPU hanging.