Difference between revisions of "IO Registers"

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m (moved IO to IO Registers)

Revision as of 22:29, 27 September 2014

Overview

Category Physical address start Comments
CONFIG 0x10000000
IRQ 0x10001000
NDMA 0x10002000
TIMER 0x10003000
CTRCARD 0x10004000 / 0x10005000
SDMC / NAND 0x10006000 / 0x10007000 0x10007000 is apparently not used on retail
PXI 0x10008000
AES 0x10009000
SHA 0x1000A000
RSA 0x1000B000
XDMA 0x1000C000 CoreLink™ DMA-330. Info
SPICARD 0x1000D800
CONFIG 0x10010000
? 0x10011000
? 0x10012000
? 0x10018000 Used during TWL_FIRM.
? 0x10100000
HASH 0x10101000
? 0x10110000
? 0x10111000 Used by TwlBg.
CSND / DSP 0x10103000
DSP 0x10140000
PDN / CODEC 0x10141000
SPI 0x10142000
SPI 0x10143000 Only used under TWL_FIRM?
I2C 0x10144000
CODEC 0x10145000
PAD / HID / PTM 0x10146000
GPIO 0x10147000
I2C 0x10148000
SPI 0x10160000
I2C 0x10161000
MIC 0x10162000
PXI 0x10163000
NTRCARD 0x10164000
MP 0x10165000
MP 0x10174000
MP 0x10178000
CDMA 0x10200000 CoreLink™ DMA-330. Info
? 0x10202000
DSP 0x10203000
GPU? 0x1020F000
HASH 0x10301000
LCD 0x10400000

IO registers starting at physical address 0x10200000 are not accessible from the ARM9(which includes all LCD/GPU registers).

ARM11 kernel virtual address mappings for these registers varies for different builds.