Difference between revisions of "CSND Registers"

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=0x1EC03000=
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{| class="wikitable" border="1"
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!  NAME
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!  PHYSICAL ADDRESS
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!  WIDTH
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!  DESCRIPTION
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|-
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| REG_DSP_FIFO
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| 0x1ED03000
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| 2
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|
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|-
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| REG_DSP_??
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| 0x1ED03004
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| 2
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| ???
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|-
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| REG_DSP_FIFO_CNT
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| 0x1ED03008
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| 2
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|
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|-
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| REG_DSP_??
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| 0x1ED03010
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| 2
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| ???
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|-
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| REG_DSP_STATUS
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| 0x1ED0300C
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| 2
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|
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|-
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| REG_DSP_??
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| 0x1ED03014
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| 2
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| ???
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|-
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| REG_DSP_??
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| 0x1ED03018
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| 2
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| ???
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|-
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| REG_DSP_??
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| 0x1ED0301C
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| 2
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| ???
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|-
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| REG_DSP_PORT<0-2>
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| 0x1ED03020
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| 3*8=0x18
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|
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|}
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=== REG_DSP_STATUS ===
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bit1,8: FIFO WRITE ERRORS?
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bit6: FIFO_READ_READY
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bit7: FIFO_WRITE_READY
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bit9: ???
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bit10-12: PORT<0-2>_RECV_READY
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bit13-15: PORT<0-2>_SEND_READY
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 +
 
=0x1EC03400=
 
=0x1EC03400=
 
The channel registers are based at 0x1EC03400(process virtual address). There's 0x20-bytes total for each channel slot, thus the base-address for a channel's slot is determined with: 0x1EC03400 + (channel_index*0x20). The below offsets are relative to these channel register slots.
 
The channel registers are based at 0x1EC03400(process virtual address). There's 0x20-bytes total for each channel slot, thus the base-address for a channel's slot is determined with: 0x1EC03400 + (channel_index*0x20). The below offsets are relative to these channel register slots.

Revision as of 13:07, 29 June 2014

0x1EC03000

NAME PHYSICAL ADDRESS WIDTH DESCRIPTION
REG_DSP_FIFO 0x1ED03000 2
REG_DSP_?? 0x1ED03004 2 ???
REG_DSP_FIFO_CNT 0x1ED03008 2
REG_DSP_?? 0x1ED03010 2 ???
REG_DSP_STATUS 0x1ED0300C 2
REG_DSP_?? 0x1ED03014 2 ???
REG_DSP_?? 0x1ED03018 2 ???
REG_DSP_?? 0x1ED0301C 2 ???
REG_DSP_PORT<0-2> 0x1ED03020 3*8=0x18

REG_DSP_STATUS

bit1,8: FIFO WRITE ERRORS?

bit6: FIFO_READ_READY

bit7: FIFO_WRITE_READY

bit9: ???

bit10-12: PORT<0-2>_RECV_READY

bit13-15: PORT<0-2>_SEND_READY


0x1EC03400

The channel registers are based at 0x1EC03400(process virtual address). There's 0x20-bytes total for each channel slot, thus the base-address for a channel's slot is determined with: 0x1EC03400 + (channel_index*0x20). The below offsets are relative to these channel register slots.

Relative offset Size Description
0x0 2 REG_CSNDCHANX_CNT. For Type0 Cmd 0xE, CSND module basically writes this value here: u16 (cmdword[2] & 0xFFFF).
0x2 2 For Type0 Cmd 0xE, CSND module writes this value here: 0 - (cmdword[2]>>16).
0x4 2 For Type0 Cmd 0xE, CSND module writes value 0 here.
0x6 2 For Type0 Cmd 0xE, CSND module writes value 0 here.
0x8 2 For Type0 Cmd 0xE, CSND module writes this value here: (u16)cmdword[4].
0xA 2 For Type0 Cmd 0xE, CSND module writes this value here: cmdword[4]>>16.
0xC 4 This is the audio data physical address, for the main channel.
0x10 4 This is the audio data total byte-size. The CSND module masks the size loaded from the Type0 command-data with value 0x7FFFFFF, which is then used when writing these registers.
0x14 4 This is the audio data physical address, for the second channel. When this is not 0x0 stereo audio is used, otherwise mono audio is used.
0x18 4 When CSND module handles type0 Cmd 0xE with encoding!=IMA-ADPCM, CSND module sets this to zero. This register can be initialized via CSND module type0 Cmd 0xB.
0x1C 4 CSND module writes value zero here immediately after it writes to chanslotreg+0x18.