GPU/Internal Registers: Difference between revisions
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=== GPUREG_TEXUNIT''i''_ADDR''i'' === | === GPUREG_TEXUNIT''i''_ADDR''i'' === | ||
First ADDR register: | |||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Bits | ! Bits | ||
! Description | ! Description | ||
|- | |- | ||
| 0- | | 0-27 | ||
| | | Texture physical address >> 3 | ||
|} | |||
Subsequent ADDR registers: | |||
{| class="wikitable" border="1" | |||
! Bits | |||
! Description | |||
|- | |||
| 0-21 | |||
| Texture physical address >> 3 (upper 6 bits reused from first ADDR register) | |||
|} | |} | ||