Difference between revisions of "Video Capture"

From 3dbrew
Jump to navigation Jump to search
Line 44: Line 44:
  
 
And the TP to get Clock, Vertical-Sync and Horizontal-Sync.
 
And the TP to get Clock, Vertical-Sync and Horizontal-Sync.
 +
 +
== Captured Video Control Signals ==
 +
 +
The following picutres show plots of the control signals CLK (TP189), HSYNC (TP190) and VSYNC (TP191). The used sample rate were 50MHz.
 +
 +
The full plot shows about 2.6ms.
 +
 +
[[File:Stp_PCLK_VSYNC_HSYNC_full.jpg|1200px]]
 +
 +
This plot shows 1.28us, mainly featuring the clock
 +
 +
[[File:Stp_PCLK_VSYNC_HSYNC_0..64.jpg|1200px]]
 +
 +
Setup
 +
 +
The signal capturing was done by using an DE10-NANO FPGA development board, Intel signal tap analyzer and 5 wires soldered to the TPs of an EU-O3DS (roughly 25cm long, parallel wired).
 +
 +
VCD and CVS files:
 +
[[Media: Stp_PCLK_VSYNC_HSYNC.7z]]
 +
(to view the VCD file use GTK Wave or similar programs).
  
 
== Links ==
 
== Links ==

Revision as of 18:33, 27 April 2020

This page documents the procedure of capturing the video signal of the upper and lower screens of the 3DS.

The information on this page was found by 3DBrew User: Matyapiro31

Pinout point.jpg

Lower Screen Dump

Test Points on the front of the board:

# Name TP RED # Name TP GREEN # Name TP BLUE
10 CN2-31 184 R0 20 CN2-39 186 G0 24 CN1-34 188 B0
12 CN2-32 178 R1 19 CN2-40 180 G1 18 CN1-33 182 B1
13 CN2-33 172 R2 21 CN1-40 174 G2 17 CN1-32 176 B2
11 CN2-34 166 R3 14 CN1-39 above 180 G3 23 CN1-31 170 B3
2 CN2-35 183 R4 22 CN1-38 185 G4 5 CN1-30 187 B4
3 CN2-36 177 R5 16 CN1-37 179 G5 6 CN1-29 181 B5
1 CN2-37 171 R6 15 CN1-36 below 179 G6 7 CN1-28 175 B6
4 CN2-38 165 R7 9 CN1-35 167 G7 8 CN1-27 169 B7
# Name TP Description
25 CN2-30 189 CLK
26 CN2-28 191 VSYNC
27 CN2-27 190 HSYNC

This table (taken from the picture above) shows which TP (test-point) to get the bit of the corresponding color (R=red, G=green, B=blue).

And the TP to get Clock, Vertical-Sync and Horizontal-Sync.

Captured Video Control Signals

The following picutres show plots of the control signals CLK (TP189), HSYNC (TP190) and VSYNC (TP191). The used sample rate were 50MHz.

The full plot shows about 2.6ms.

Stp PCLK VSYNC HSYNC full.jpg

This plot shows 1.28us, mainly featuring the clock

Stp PCLK VSYNC HSYNC 0..64.jpg

Setup

The signal capturing was done by using an DE10-NANO FPGA development board, Intel signal tap analyzer and 5 wires soldered to the TPs of an EU-O3DS (roughly 25cm long, parallel wired).

VCD and CVS files: Media: Stp_PCLK_VSYNC_HSYNC.7z (to view the VCD file use GTK Wave or similar programs).

Links

Retrieved from "https://www.3dbrew.org/w/index.php?title=Video_Capture&oldid=21178"