Difference between revisions of "NDMA Registers"
| Line 1: | Line 1: | ||
| − | 3DS NDMA has 8 channels. | + | 3DS NDMA has 8 channels. The first 0x100-bytes of this IO mem is mirrored at 0x10002100, repeated every 0x100-bytes until the end of the 0x1000-byte IO mem. |
== Registers == | == Registers == | ||
Revision as of 19:03, 14 February 2015
3DS NDMA has 8 channels. The first 0x100-bytes of this IO mem is mirrored at 0x10002100, repeated every 0x100-bytes until the end of the 0x1000-byte IO mem.
Registers
| NAME | ADDRESS | WIDTH |
|---|---|---|
| REG_NDMAGCNT | 0x10002000 | 4 |
| REG_NDMASAD(n) | 0x10002004 + (n*0x1c) | 4 |
| REG_NDMADAD(n) | 0x10002008 + (n*0x1c) | 4 |
| REG_NDMATCNT(n) | 0x1000200c + (n*0x1c) | 4 |
| REG_NDMAWCNT(n) | 0x10002010 + (n*0x1c) | 4 |
| REG_NDMABCNT(n) | 0x10002014 + (n*0x1c) | 4 |
| REG_NDMAFDATA(n) | 0x10002018 + (n*0x1c) | 4 |
| REG_NDMACNT(n) | 0x1000201C + (n*0x1c) | 4 |
REG_NDMAGCNT
| BIT | DESCRIPTION |
|---|---|
| 19-16 | Cycle selection. |
| 31 | DMA arbitration method. 0=Fixed method, 1=Round robin |
REG_NDMASAD
| BIT | DESCRIPTION |
|---|---|
| 31-0 | Source data address. Must be multiple of 4. |
Like old DMA, REG_NDMASAD is copied to internal registers when written to.
REG_NDMADAD
| BIT | DESCRIPTION |
|---|---|
| 31-0 | Destination data address. Must be multiple of 4. |
Like old DMA, REG_NDMADAD is copied to internal registers when written to.
REG_NDMATCNT
| BIT | DESCRIPTION |
|---|---|
| 27-0 | Total number of words transferred. |
REG_NDMAWCNT
| BIT | DESCRIPTION |
|---|---|
| 23-0 | Number of words to transfer. |
REG_NDMABCNT
| BIT | DESCRIPTION |
|---|---|
| 15-0 | Interval timer. |
| 17-16 | Prescaler. 0=System freq, 1=1/4th freq, 2=1/16th freq, 3=1/64th freq. |
REG_NDMAFDATA
| BIT | DESCRIPTION |
|---|---|
| 31-0 | Fill data. |
REG_NDMACNT
| BIT | DESCRIPTION |
|---|---|
| 11-10 | Destination address update method. 0=Increment, 1=Decrement, 2=Fixed. |
| 12 | Destination address reload flag. |
| 14-13 | Source address update method. 0=Increment, 1=Decrement, 2=Fixed, 3=No address (for filling) |
| 15 | Source address reload flag. |
| 19-16 | Block transfer word count = (1<<x) words. |
| 27-24 | Startup mode. |
| 28 | Immediate mode. |
| 29 | Repeating mode. |
| 30 | IRQ enable |
| 31 | Enable/busy flag. |
Startup modes (27-24)
???
Block transfers
First, a word is always 32 bits. Second, the block transfer specified in REG_NDMACNT is the smallest atom of data that will be transferred in a burst. The bus is monopolized until this block is transferred, without splitting up.
The next block transfer will happen after the specified time in the REG_NDMABCNT interval timer, until done.
Immediate mode
Transfers the words specified in REG_NDMAWCNT immediately following block transfer rules. REG_NDMATCNT and repeating mode are ignored.
Repeating mode
Transfers the words specified in REG_NDMAWCNT following the startup mode event. REG_DMATCNT is ignored.
No immediate and no repeating mode
Transfers the words specified in REG_NDMAWCNT for each startup event, and gets disabled when the total number of words in REG_NDMATCNT are transferred.