Difference between revisions of "GSPGPU:WriteHWRegsWithMask"
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(Created page with "=Request= {| class="wikitable" border="1" |- ! Index Word ! Description |- | 0 | Header code [0x00020084] |- | 1 | GPU address based at 0x1EB00000, must be word-aligned |- ...") |
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=Request= | =Request= | ||
| − | {| | + | {{IPC/Request|Request}} |
| − | | | + | {{IPC/RequestHeader|0x0002|2|4}} |
| − | + | {{IPC/RequestEntry|[[GPU]] address based at 0x1EB00000, must be word-aligned}} | |
| − | + | {{IPC/RequestEntry|<nowiki>Size, must be <=0x80 and word-aligned</nowiki>}} | |
| − | | | + | {{IPC/TranslateStaticBuffer|Data pointer|0}} |
| − | | | + | {{IPC/TranslateStaticBuffer|Mask data pointer|1}} |
| − | + | {{IPC/RequestEnd}} | |
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| − | | [[GPU]] address based at 0x1EB00000, must be word-aligned | ||
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| − | | Data pointer | ||
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| − | | Mask data pointer | ||
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=Response= | =Response= | ||
| − | {| | + | {{IPC/Request|Response}} |
| − | | | + | {{IPC/RequestHeader|0x0002|2|0}} |
| − | + | {{IPC/RequestEntry|Header code}} | |
| − | + | {{IPC/RequestEntry|Result code}} | |
| − | | | + | {{IPC/RequestEnd}} |
| − | | 0 | ||
| − | | Header code | ||
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| − | | Result code | ||
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=Description= | =Description= | ||
The GPU register offset must be <0x420000. GPU register = (register & ~maskword) | (data & maskword). | The GPU register offset must be <0x420000. GPU register = (register & ~maskword) | (data & maskword). | ||
Latest revision as of 12:50, 18 September 2024
Request[edit]
| Request Word | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| 0 |
| ||||||||
| 1 | GPU address based at 0x1EB00000, must be word-aligned | ||||||||
| 2 | Size, must be <=0x80 and word-aligned | ||||||||
| 3 | Descriptor for static buffer (id 0) | ||||||||
| 4 | Data pointer | ||||||||
| 5 | Descriptor for static buffer (id 1) | ||||||||
| 6 | Mask data pointer |
Response[edit]
| Response Word | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|
| 0 |
| ||||||||
| 1 | Header code | ||||||||
| 2 | Result code |
Description[edit]
The GPU register offset must be <0x420000. GPU register = (register & ~maskword) | (data & maskword).