Difference between revisions of "DSP Registers"

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 +
=Registers=
 +
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
−
!  NAME
+
!  Old3DS
−
!  PHYSICAL ADDRESS
+
!  Name
−
!  WIDTH
+
!  Physical Address
 +
!  Width
 +
!  Used by
 
|-
 
|-
−
| DSP_PDATA
+
| style="background: green" | Yes
 +
| [[#DSP_PDATA|DSP_PDATA]]
 
| 0x10203000
 
| 0x10203000
 
| 2
 
| 2
 +
|
 
|-
 
|-
−
| DSP_PADR
+
| style="background: green" | Yes
 +
| [[#DSP_PADR|DSP_PADR]]
 
| 0x10203004
 
| 0x10203004
 
| 2
 
| 2
 +
|
 
|-
 
|-
−
| DSP_PCFG
+
| style="background: green" | Yes
 +
| [[#DSP_PCFG|DSP_PCFG]]
 
| 0x10203008
 
| 0x10203008
 
| 2
 
| 2
 +
|
 
|-
 
|-
−
| DSP_PSTS
+
| style="background: green" | Yes
 +
| [[#DSP_PSTS|DSP_PSTS]]
 
| 0x1020300C
 
| 0x1020300C
 
| 2
 
| 2
 +
|
 
|-
 
|-
−
| DSP_PSEM
+
| style="background: green" | Yes
 +
| [[#DSP_PSEM|DSP_PSEM]]
 
| 0x10203010
 
| 0x10203010
 
| 2
 
| 2
 +
|
 
|-
 
|-
−
| DSP_PMASK
+
| style="background: green" | Yes
 +
| [[#DSP_PMASK|DSP_PMASK]]
 
| 0x10203014
 
| 0x10203014
 
| 2
 
| 2
 +
|
 
|-
 
|-
−
| DSP_PCLEAR
+
| style="background: green" | Yes
 +
| [[#DSP_PCLEAR|DSP_PCLEAR]]
 
| 0x10203018
 
| 0x10203018
 
| 2
 
| 2
 +
|
 
|-
 
|-
−
| DSP_SEM
+
| style="background: green" | Yes
 +
| [[#DSP_SEM|DSP_SEM]]
 
| 0x1020301C
 
| 0x1020301C
 
| 2
 
| 2
 +
|
 
|-
 
|-
−
| DSP_CMD0
+
| style="background: green" | Yes
 +
| [[#DSP_CMD0|DSP_CMD0]]
 
| 0x10203020
 
| 0x10203020
 
| 2
 
| 2
 +
|
 
|-
 
|-
−
| DSP_REP0
+
| style="background: green" | Yes
 +
| [[#DSP_REP0|DSP_REP0]]
 
| 0x10203024
 
| 0x10203024
 
| 2
 
| 2
 +
|
 
|-
 
|-
−
| DSP_CMD1
+
| style="background: green" | Yes
 +
| [[#DSP_CMD1|DSP_CMD1]]
 
| 0x10203028
 
| 0x10203028
 
| 2
 
| 2
 +
|
 
|-
 
|-
−
| DSP_REP1
+
| style="background: green" | Yes
 +
| [[#DSP_REP1|DSP_REP1]]
 
| 0x1020302C
 
| 0x1020302C
 
| 2
 
| 2
 +
|
 
|-
 
|-
−
| DSP_CMD2
+
| style="background: green" | Yes
 +
| [[#DSP_CMD2|DSP_CMD2]]
 
| 0x10203030
 
| 0x10203030
 
| 2
 
| 2
 +
|
 
|-
 
|-
−
| DSP_REP2
+
| style="background: green" | Yes
 +
| [[#DSP_REP2|DSP_REP2]]
 
| 0x10203034
 
| 0x10203034
 
| 2
 
| 2
 +
|
 
|}
 
|}
  
−
=== DSP_PDATA - DSP Transfer Data Read FIFO (R) ===
+
== DSP_PDATA ==
−
0-15  Data (one stage of the 16-stage Read FIFO)
+
Data (one stage of the 16-stage Read FIFO).
  
−
=== DSP_PDATA - DSP Transfer Data Write FIFO (W)  ===
+
== DSP_PADR ==
−
0-15  Data (one stage of the 16-stage Write FIFO)
+
Lower 16bit of Address in DSP Memory. Note: The upper 16bit of Address must be configued in the DMA register (inside of the DSP).
  
−
=== DSP_PADR - DSP Transfer Address (W) ===
+
== DSP_PCFG - DSP Configuration (R/W)  (16bit) ==
−
0-15  Lower 16bit of Address in DSP Memory
 
−
Note: The upper 16bit of Address must be configued in the DMA register (inside
 
−
of the DSP).
 
  
−
=== DSP_PCFG - DSP Configuration (R/W)  (16bit) ===
+
{| class="wikitable" border="1"
−
  0     DSP Reset (0=Release, 1=Reset)  ;should be held "1" for 8 DSP clks
+
!  Bits
−
  1     Address Auto-Increment (0=Off, 1=On)
+
!  Description
−
  2-3  DSP Read Data Length (0=1 word, 1=8 words, 2=16 words, 3=Free-Run)
+
|-
−
  4     DSP Read Start Flag (mem transfer via Read FIFO) (1=Start)
+
| 0
−
  5     Interrupt Enable Read FIFO Full      (0=Off, 1=On)
+
| DSP Reset (0=Release, 1=Reset)  ;should be held "1" for 8 DSP clks
−
  6     Interrupt Enable Read FIFO Not-Empty (0=Off, 1=On)
+
|-
−
  7     Interrupt Enable Write FIFO Full    (0=Off, 1=On)
+
| 1
−
  8     Interrupt Enable Write FIFO Empty    (0=Off, 1=On)
+
| Address Auto-Increment (0=Off, 1=On)
−
  9     Interrupt Enable Reply Register 0    (0=Off, 1=On)
+
|-
−
  10   Interrupt Enable Reply Register 1    (0=Off, 1=On)
+
| 2-3   
−
  11   Interrupt Enable Reply Register 2    (0=Off, 1=On)
+
| DSP Read Data Length (0=1 word, 1=8 words, 2=16 words, 3=Free-Run)
−
  12-15 DSP Memory Transfer (0=Data Memory, 1=MMIO Register, 5=Program Memory)
+
|-
 +
| 4
 +
| DSP Read Start Flag (mem transfer via Read FIFO) (1=Start)
 +
|-
 +
| 5
 +
| Interrupt Enable Read FIFO Full      (0=Off, 1=On)
 +
|-
 +
| 6
 +
| Interrupt Enable Read FIFO Not-Empty (0=Off, 1=On)
 +
|-
 +
| 7
 +
| Interrupt Enable Write FIFO Full    (0=Off, 1=On)
 +
|-
 +
| 8
 +
| Interrupt Enable Write FIFO Empty    (0=Off, 1=On)
 +
|-
 +
| 9
 +
| Interrupt Enable Reply Register 0    (0=Off, 1=On)
 +
|-
 +
| 10
 +
| Interrupt Enable Reply Register 1    (0=Off, 1=On)
 +
|-
 +
| 11
 +
| Interrupt Enable Reply Register 2    (0=Off, 1=On)
 +
|-
 +
| 12-15
 +
| DSP Memory Transfer (0=Data Memory, 1=MMIO Register, 5=Program Memory)
 +
|}
  
−
=== DSP_PSTS - DSP Status (R)          (16bit) ===
+
== DSP_PSTS ==
−
  0     Read Transfer Underway Flag  (0=No, 1=Yes/From DSP Memory)
+
{| class="wikitable" border="1"
−
  1     Write Transfer Underway Flag (0=No, 1=Yes/To DSP Memory)
+
!  Bits
−
  2     Peripheral Reset Flag (0=No/Ready, 1=Reset/Busy)
+
!  Description
−
  3-4   Unused
+
|-
−
  5     Read FIFO Full Flag      (0=No, 1=Yes)
+
| 0
−
  6     Read FIFO Not-Empty Flag (0=No, 1=Yes) ;ARM11 may read DSP_PDATA
+
| Read Transfer Underway Flag  (0=No, 1=Yes/From DSP Memory)
−
  7     Write FIFO Full Flag    (0=No, 1=Yes)
+
|-
−
  8     Write FIFO Empty Flag    (0=No, 1=Yes)
+
| 1
−
  9     Semaphore IRQ Flag (0=None, 1=IRQ)
+
| Write Transfer Underway Flag (0=No, 1=Yes/To DSP Memory)
−
  10   Reply Register 0 Update Flag (0=Was Written by DSP, 1=No)
+
|-
−
  11   Reply Register 1 Update Flag (0=Was Written by DSP, 1=No)
+
| 2
−
  12   Reply Register 2 Update Flag (0=Was Written by DSP, 1=No)
+
| Peripheral Reset Flag (0=No/Ready, 1=Reset/Busy)
−
  13   Command Register 0 Read Flag (0=Was Read by DSP, 1=No)
+
|-
−
  14   Command Register 1 Read Flag (0=Was Read by DSP, 1=No)
+
| 3-4
−
  15   Command Register 2 Read Flag (0=Was Read by DSP, 1=No)
+
| Unused
 +
|-
 +
| 5
 +
| Read FIFO Full Flag      (0=No, 1=Yes)
 +
|-
 +
| 6
 +
| Read FIFO Not-Empty Flag (0=No, 1=Yes) ;ARM11 may read DSP_PDATA
 +
|-
 +
| 7
 +
| Write FIFO Full Flag    (0=No, 1=Yes)
 +
|-
 +
| 8
 +
| Write FIFO Empty Flag    (0=No, 1=Yes)
 +
|-
 +
| 9
 +
| Semaphore IRQ Flag (0=None, 1=IRQ)
 +
|-
 +
| 10
 +
| Reply Register 0 Update Flag (0=Was Written by DSP, 1=No)
 +
|-
 +
| 11
 +
| Reply Register 1 Update Flag (0=Was Written by DSP, 1=No)
 +
|-
 +
| 12
 +
| Reply Register 2 Update Flag (0=Was Written by DSP, 1=No)
 +
|-
 +
| 13
 +
| Command Register 0 Read Flag (0=Was Read by DSP, 1=No)
 +
|-
 +
| 14
 +
| Command Register 1 Read Flag (0=Was Read by DSP, 1=No)
 +
|-
 +
| 15
 +
| Command Register 2 Read Flag (0=Was Read by DSP, 1=No)
 +
|}
 
Unknown if/when bit10-15 get reset... maybe after reading the status?
 
Unknown if/when bit10-15 get reset... maybe after reading the status?
  
−
=== DSP_PSEM - ARM11-to-DSP Semaphore        (16bit) ===
+
== DSP_PSEM ==
−
  0-15  DSP-to-ARM11 Semaphore 0..15 Flags (0=Off, 1=On)
+
DSP-to-ARM11 Semaphore 0..15 Flags (0=Off, 1=On). Reportedly these flags are sent in ARM11-to-DSP direction. Confusingly, the other DSP_Pxxx registers are for opposite direction?
−
Reportedly these flags are sent in ARM11-to-DSP direction.
 
−
Confusingly, the other DSP_Pxxx registers are for opposite direction?
 
  
−
=== DSP_PMASK - DSP-to-ARM11 Semaphore Mask (16bit) ===
+
== DSP_PMASK ==
−
  0-15  DSP-to-ARM11 Semaphore 0..15 Interrupt Disable (0=Enable, 1=Disable)
+
DSP-to-ARM11 Semaphore 0..15 Interrupt Disable (0=Enable, 1=Disable)
  
−
=== DSP_PCLEAR - DSP-to-ARM11 Semaphore Clear (W) (16bit) ===
+
== DSP_PCLEAR ==
−
  0-15  DSP-to-ARM11 Semaphore 0..15 Clear (0=No Change, 1=Clear)
+
DSP-to-ARM11 Semaphore 0..15 Clear (0=No Change, 1=Clear). Reportedly clears bits in DSP_PSEM. [that's probably nonsense, clearing bits in DSP_SEM would make more sense]
−
Reportedly clears bits in DSP_PSEM. [that's probably nonsense, clearing bits in DSP_SEM would make more sense]
 
  
−
=== DSP_SEM - DSP-to-ARM9 Semaphore Data (R) (16bit) ===
+
== DSP_SEM ==
−
  0-15  DSP-to-ARM11 Semaphore 0..15 Flags (0=Off, 1=On)
+
DSP-to-ARM11 Semaphore 0..15 Flags (0=Off, 1=On). Reportedly these flags are received in DSP-to-ARM11 direction.
−
Reportedly these flags are received in DSP-to-ARM11 direction.
 
  
−
=== DSP_CMDX - DSP Command Reg. X (R/W) (ARM11 to DSP) (16bit) ===
+
== DSP_CMDX ==
−
  0-15  Command/Data to DSP
+
Command/Data to DSP.
  
−
=== DSP_REPX - DSP Reply Register X (R) (DSP to ARM9) (16bit) ===
+
== DSP_REPX ==
−
  0-15  Reply/Data from DSP
+
Reply/Data from DSP.

Latest revision as of 13:24, 15 April 2016

Registers[edit]

Old3DS Name Physical Address Width Used by
Yes DSP_PDATA 0x10203000 2
Yes DSP_PADR 0x10203004 2
Yes DSP_PCFG 0x10203008 2
Yes DSP_PSTS 0x1020300C 2
Yes DSP_PSEM 0x10203010 2
Yes DSP_PMASK 0x10203014 2
Yes DSP_PCLEAR 0x10203018 2
Yes DSP_SEM 0x1020301C 2
Yes DSP_CMD0 0x10203020 2
Yes DSP_REP0 0x10203024 2
Yes DSP_CMD1 0x10203028 2
Yes DSP_REP1 0x1020302C 2
Yes DSP_CMD2 0x10203030 2
Yes DSP_REP2 0x10203034 2

DSP_PDATA[edit]

Data (one stage of the 16-stage Read FIFO).

DSP_PADR[edit]

Lower 16bit of Address in DSP Memory. Note: The upper 16bit of Address must be configued in the DMA register (inside of the DSP).

DSP_PCFG - DSP Configuration (R/W) (16bit)[edit]

Bits Description
0 DSP Reset (0=Release, 1=Reset) ;should be held "1" for 8 DSP clks
1 Address Auto-Increment (0=Off, 1=On)
2-3 DSP Read Data Length (0=1 word, 1=8 words, 2=16 words, 3=Free-Run)
4 DSP Read Start Flag (mem transfer via Read FIFO) (1=Start)
5 Interrupt Enable Read FIFO Full (0=Off, 1=On)
6 Interrupt Enable Read FIFO Not-Empty (0=Off, 1=On)
7 Interrupt Enable Write FIFO Full (0=Off, 1=On)
8 Interrupt Enable Write FIFO Empty (0=Off, 1=On)
9 Interrupt Enable Reply Register 0 (0=Off, 1=On)
10 Interrupt Enable Reply Register 1 (0=Off, 1=On)
11 Interrupt Enable Reply Register 2 (0=Off, 1=On)
12-15 DSP Memory Transfer (0=Data Memory, 1=MMIO Register, 5=Program Memory)

DSP_PSTS[edit]

Bits Description
0 Read Transfer Underway Flag (0=No, 1=Yes/From DSP Memory)
1 Write Transfer Underway Flag (0=No, 1=Yes/To DSP Memory)
2 Peripheral Reset Flag (0=No/Ready, 1=Reset/Busy)
3-4 Unused
5 Read FIFO Full Flag (0=No, 1=Yes)
6 Read FIFO Not-Empty Flag (0=No, 1=Yes) ;ARM11 may read DSP_PDATA
7 Write FIFO Full Flag (0=No, 1=Yes)
8 Write FIFO Empty Flag (0=No, 1=Yes)
9 Semaphore IRQ Flag (0=None, 1=IRQ)
10 Reply Register 0 Update Flag (0=Was Written by DSP, 1=No)
11 Reply Register 1 Update Flag (0=Was Written by DSP, 1=No)
12 Reply Register 2 Update Flag (0=Was Written by DSP, 1=No)
13 Command Register 0 Read Flag (0=Was Read by DSP, 1=No)
14 Command Register 1 Read Flag (0=Was Read by DSP, 1=No)
15 Command Register 2 Read Flag (0=Was Read by DSP, 1=No)

Unknown if/when bit10-15 get reset... maybe after reading the status?

DSP_PSEM[edit]

DSP-to-ARM11 Semaphore 0..15 Flags (0=Off, 1=On). Reportedly these flags are sent in ARM11-to-DSP direction. Confusingly, the other DSP_Pxxx registers are for opposite direction?

DSP_PMASK[edit]

DSP-to-ARM11 Semaphore 0..15 Interrupt Disable (0=Enable, 1=Disable)

DSP_PCLEAR[edit]

DSP-to-ARM11 Semaphore 0..15 Clear (0=No Change, 1=Clear). Reportedly clears bits in DSP_PSEM. [that's probably nonsense, clearing bits in DSP_SEM would make more sense]

DSP_SEM[edit]

DSP-to-ARM11 Semaphore 0..15 Flags (0=Off, 1=On). Reportedly these flags are received in DSP-to-ARM11 direction.

DSP_CMDX[edit]

Command/Data to DSP.

DSP_REPX[edit]

Reply/Data from DSP.

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