Difference between revisions of "CONFIG11 Registers"

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−
== Registers ==
+
= Registers =
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
−
!  NAME
+
!  Old3DS
−
!  PHYSICAL ADDRESS
+
!  Name
−
!  ARM11 PROCESS ADDRESS
+
!  Address
−
!  WIDTH
+
!  Width
 +
!  Used by
 
|-
 
|-
 +
| style="background: green" | Yes
 +
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7>
 +
| 0x10140000
 +
| 1*8
 +
| Boot11, Process9, [[DSP Services]]
 +
|-
 +
| style="background: green" | Yes
 +
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7>
 +
| 0x10140008
 +
| 1*8
 +
| Boot11, Process9, [[DSP Services]]
 +
|-style="border-top: double"
 +
| style="background: green" | Yes
 +
| [[#CFG11_NULLPAGE_CNT|CFG11_NULLPAGE_CNT]]
 +
| 0x10140100
 +
| 4
 +
|
 +
|-
 +
| style="background: green" | Yes
 +
| [[#CFG11_FIQ_MASK|CFG11_FIQ_MASK]]
 +
| 0x10140104
 +
| 1
 +
| Kernel11.
 +
|-
 +
| style="background: green" | Yes
 +
| Debug related bitfield?
 +
Observed: 0b1100(N3DS)/0b0000(O3DS)
 +
| 0x10140105
 +
| 1
 +
|
 +
|-
 +
| style="background: green" | Yes
 +
| [[#CFG11_CDMA_CNT|CFG_CDMA_CNT]]
 +
| 0x1014010C
 +
| 2
 +
| TwlBg
 +
|-
 +
| style="background: green" | Yes
 +
| [[#CFG11_GPUPROT|CFG11_GPUPROT]]
 +
| 0x10140140
 +
| 4
 +
| Kernel11
 +
|-
 +
| style="background: green" | Yes
 +
| [[#CFG11_WIFICNT|CFG11_WIFICNT]]
 +
| 0x10140180
 +
| 1
 +
| TwlBg, [[NWM Services]]
 +
|-
 +
| style="background: green" | Yes
 +
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]
 +
| 0x101401C0
 +
| 2
 +
| [[SPI Services]], TwlBg
 +
|-style="border-top: double"
 +
| style="background: green" | Yes
 
| ?
 
| ?
−
| 0x10141008
+
| 0x10140200
−
| 0x1EC41008
 
 
| 4
 
| 4
 +
|
 +
|-style="border-top: double"
 +
| style="background: red" | No
 +
| [[#CFG11_GPU_N3DS_CNT|CFG11_GPU_N3DS_CNT]]
 +
| 0x10140400
 +
| 1
 +
| NewKernel11
 
|-
 
|-
−
| ?
+
| style="background: red" | No
−
| 0x1014100C
+
| [[#CFG11_CDMA_PERIPHERALS|CFG11_CDMA_PERIPHERALS]]
−
| 0x1EC4100C
+
| 0x10140410
 
| 4
 
| 4
 +
| NewKernel11
 +
|-
 +
| style="background: red" | No
 +
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]
 +
| 0x10140420
 +
| 1
 +
| NewKernel11
 
|-
 
|-
−
| PDN_TWLMODE?
+
| style="background: red" | No
−
| 0x10141100
+
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]
−
|
+
| 0x10140424
−
| 2
+
| 4
 +
| NewKernel11
 
|-
 
|-
 +
| style="background: red" | No
 
| ?
 
| ?
−
| 0x10141110
+
| 0x10140428
 +
| 4
 
|
 
|
 +
|-style="border-top: double"
 +
| style="background: green" | Yes
 +
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]
 +
| 0x10140FFC
 
| 2
 
| 2
 +
| Boot11, Kernel11
 +
|}
 +
 +
== CFG11_SHAREDWRAM_32K_CODE ==
 +
Used for mapping 32K chunks of shared WRAM for DSP data.
 +
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| ?
+
| 0-1
−
| 0x10141112
+
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)
−
|  
+
|-
−
| 2
+
| 2-4
 +
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)
 +
|-
 +
| 5-6
 +
| Not used (0)
 +
|-
 +
| 7
 +
| Enable (0=Disable, 1=Enable)
 +
|}
 +
 
 +
== CFG11_SHAREDWRAM_32K_DATA ==
 +
Used for mapping 32K chunks of shared WRAM for DSP data.
 +
 
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
|-
 +
| 0-1
 +
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)
 +
|-
 +
| 2-4
 +
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)
 +
|-
 +
| 5-6
 +
| Not used (0)
 +
|-
 +
| 7
 +
| Enable (0=Disable, 1=Enable)
 +
|}
 +
 
 +
== CFG11_NULLPAGE_CNT ==
 +
{| class="wikitable" border="1"
 +
!  Bit
 +
!  Description
 
|-
 
|-
−
| ?
+
| 0
−
| 0x10141114
+
| Trap all ''data'' accesses to physmem addresses 0x0000 to 0x1000
−
|
 
−
| 2
 
 
|-
 
|-
−
| ?
+
| 16
−
| 0x10141116
+
| Unknown
−
|  
+
|}
−
| 2
+
 
 +
The reset value of this register is 0x10000.
 +
 
 +
== CFG11_FIQ_MASK ==
 +
Write bit N to mask FIQ interrutps on core N? (judging from what Kernel11 does -- it only ever configures FIQ for core1)
 +
 
 +
Reset value: 0xF
 +
 
 +
== CFG11_CDMA_CNT ==
 +
Write 1 to enable, to disable.
 +
 
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 
|-
 
|-
−
| PDN_LCD
+
| 0
−
| 0x10141200
+
| Enable Microphone DMA (CDMA 0x00)
−
| 0x1EC41200
 
−
| 1
 
 
|-
 
|-
−
| PDN_BACKLIGHT
 
−
| 0x10141202
 
−
| 0x1EC41202
 
 
| 1
 
| 1
 +
| Enable NTRCARD DMA on Arm11 side (CDMA 0x01)
 
|-
 
|-
 +
| 2-4
 
| ?
 
| ?
−
| 0x10141210
+
|-
−
| 0x1EC41210
+
| 5
 +
| WiFi. Enabled during kernel init since 11.4.
 +
|}
 +
 
 +
== CFG11_SPI_CNT ==
 +
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.
 +
{| class="wikitable" border="1"
 +
!  Bit
 +
!  Description
 +
|-
 +
| 0
 +
| Enable [[SPI Registers]] 0x10160800.
 +
|-
 
| 1
 
| 1
 +
| Enable [[SPI Registers]] 0x10142800.
 +
|-
 +
| 2
 +
| Enable [[SPI Registers]] 0x10143800.
 +
|}
 +
 +
== CFG11_GPU_N3DS_CNT ==
 +
{| class="wikitable" border="1"
 +
!  Bit
 +
!  Description
 +
|-
 +
| 0
 +
| Enable N3DS mode? (enables access to the extra N3DS FCRAM banks, etc.)
 
|-
 
|-
−
| PDN_CODEC
 
−
| 0x10141220
 
−
| 0x1EC41220
 
 
| 1
 
| 1
 +
| Texture related? (observing texture glitches when disabling this bit)
 +
|}
 +
 +
== CFG11_CDMA_PERIPHERALS ==
 +
{| class="wikitable" border="1"
 +
!  Bit
 +
!  Description
 +
|-
 +
| 0-17
 +
| CDMA Peripheral 0x00-0x11 data request target (0=Old CDMA, 1=New CDMA)
 +
|-
 +
| 18-31
 +
| Unused
 +
|}
 +
 +
== CFG11_BOOTROM_OVERLAY_CNT ==
 +
Bit0: Enable bootrom overlay functionality.
 +
 +
== CFG11_BOOTROM_OVERLAY_VAL ==
 +
The 32-bit value to overlay data-reads to bootrom with. See [[PDN Registers#PDN_LGR_CPU_CNT<0-3>|PDN_LGR_CPU_CNT]]<0-3>.
 +
 +
== CFG11_SOCINFO ==
 +
Read-only register. Identifies the maximum mode-switching capabilities of the SoC.
 +
 +
* CTR: O3DS
 +
* LGR1: N3DS prototype, 4 cores (orginally 2), up to 535MHz, no L2C (see below)
 +
* LGR2: retail N3DS, 4 cores, up to 804MHz, has L2C
 +
 +
Kernel code suggests that devices that support LGR1 but not LGR2 only had 2 cores. All cores (the number of which can be read from MPCORE SCU registers) are usable in LGR1 mode.
 +
 +
{| class="wikitable" border="1"
 +
!  Bits
 +
!  Description
 +
!  Used by
 +
|-
 +
| 0
 +
| CTR mode (1 on all 3DSes)
 +
| Boot11
 
|-
 
|-
−
| PDN_CAMERA
 
−
| 0x10141224
 
−
| 0x1EC41224
 
 
| 1
 
| 1
 +
| LGR1 (1 on all N3DSes, orginally 2 cores, and 2x clockrate)
 +
| Kernel11
 
|-
 
|-
−
| ?
+
| 2
−
| 0x10141230
+
| LGR2 (1 on all released N3DSes, 4 cores and 3x clockrate)
−
| 0x1EC41230
+
| Kernel11
−
| 1
+
|}
 +
 
 +
==CFG11_GPUPROT==
 +
{| class="wikitable" border="1"
 +
!  Old3DS
 +
!  Bits
 +
!  Description
 +
|-
 +
| style="background: green" | Yes
 +
| 3-0
 +
| Old FCRAM DMA cutoff size, 0 = no protection.
 +
|-
 +
| style="background: red" | No
 +
| 7-4
 +
| New FCRAM DMA cutoff size, 0 = no protection.
 +
|-
 +
| style="background: green" | Yes
 +
| 8
 +
| AXIWRAM protection, 0 = accessible.
 +
|-
 +
| style="background: red" | No
 +
| 10-9
 +
| QTM DMA cutoff size
 +
|-
 +
| style="background: green" | Yes
 +
| 31-11
 +
| Zeroes
 
|}
 
|}
  
−
==0x1EC41008 and  0x1EC4100C==
+
For the old FCRAM DMA cutoff, it protects starting from 0x28000000-(0x800000*x) until end of FCRAM. There is no way to protect the first 0x800000-bytes.
−
These are the PDN PTM registers used for the [[PDN_Services|PDN]] PTM service.
 
  
−
==PDN_LCD==
+
For the new FCRAM DMA cutoff, it protects starting from 0x30000000-(0x800000*x) until end of FCRAM. When the old FCRAM cutoff is set to non-zero, the first 0x800000-bytes bytes of new FCRAM are protected.
−
This one seems to control the LCD displays?
 
  
−
==PDN_BACKLIGHT==
+
On New3DS the old+new FCRAM cutoff can be used at the same time, however this isn't done officially.
−
This is the power register used for the LCD backlights.
 
  
−
bit0 = turn on/off LCD backlight, rest = always 0.
+
For the QTM DMA cutoff, it protects starting from 0x1F400000-(0x100000*x) until end of QTM mem.
  
−
==PDN_CODEC==
+
On cold boot this reg is set to 0.
−
This is the power register used for the [[PDN_Services|PDN]] CODEC service.
 
  
−
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.
+
When this register is set to value 0, the GPU can access the entire FCRAM, AXIWRAM, and on New3DS all QTM-mem.
  
−
==PDN_CAMERA==
+
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with [[11.3.0-36|v11.3]].
−
This is the power register used for the [[PDN_Services|PDN]] camera service.
 
  
−
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.
+
==CFG11_WIFICNT==
 +
{| class="wikitable" border="1"
 +
!  Old3DS
 +
!  Bits
 +
!  Description
 +
|-
 +
| style="background: green" | Yes
 +
| 0
 +
| Enable wifi subsystem
 +
|}

Latest revision as of 00:56, 27 January 2021

Registers[edit]

Old3DS Name Address Width Used by
Yes CFG11_SHAREDWRAM_32K_CODE<0-7> 0x10140000 1*8 Boot11, Process9, DSP Services
Yes CFG11_SHAREDWRAM_32K_DATA<0-7> 0x10140008 1*8 Boot11, Process9, DSP Services
Yes CFG11_NULLPAGE_CNT 0x10140100 4
Yes CFG11_FIQ_MASK 0x10140104 1 Kernel11.
Yes Debug related bitfield?

Observed: 0b1100(N3DS)/0b0000(O3DS)

0x10140105 1
Yes CFG_CDMA_CNT 0x1014010C 2 TwlBg
Yes CFG11_GPUPROT 0x10140140 4 Kernel11
Yes CFG11_WIFICNT 0x10140180 1 TwlBg, NWM Services
Yes CFG11_SPI_CNT 0x101401C0 2 SPI Services, TwlBg
Yes ? 0x10140200 4
No CFG11_GPU_N3DS_CNT 0x10140400 1 NewKernel11
No CFG11_CDMA_PERIPHERALS 0x10140410 4 NewKernel11
No CFG11_BOOTROM_OVERLAY_CNT 0x10140420 1 NewKernel11
No CFG11_BOOTROM_OVERLAY_VAL 0x10140424 4 NewKernel11
No ? 0x10140428 4
Yes CFG11_SOCINFO 0x10140FFC 2 Boot11, Kernel11

CFG11_SHAREDWRAM_32K_CODE[edit]

Used for mapping 32K chunks of shared WRAM for DSP data.

Bits Description
0-1 Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)
2-4 Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)
5-6 Not used (0)
7 Enable (0=Disable, 1=Enable)

CFG11_SHAREDWRAM_32K_DATA[edit]

Used for mapping 32K chunks of shared WRAM for DSP data.

Bits Description
0-1 Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)
2-4 Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)
5-6 Not used (0)
7 Enable (0=Disable, 1=Enable)

CFG11_NULLPAGE_CNT[edit]

Bit Description
0 Trap all data accesses to physmem addresses 0x0000 to 0x1000
16 Unknown

The reset value of this register is 0x10000.

CFG11_FIQ_MASK[edit]

Write bit N to mask FIQ interrutps on core N? (judging from what Kernel11 does -- it only ever configures FIQ for core1)

Reset value: 0xF

CFG11_CDMA_CNT[edit]

Write 1 to enable, to disable.

Bits Description
0 Enable Microphone DMA (CDMA 0x00)
1 Enable NTRCARD DMA on Arm11 side (CDMA 0x01)
2-4 ?
5 WiFi. Enabled during kernel init since 11.4.

CFG11_SPI_CNT[edit]

When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.

Bit Description
0 Enable SPI Registers 0x10160800.
1 Enable SPI Registers 0x10142800.
2 Enable SPI Registers 0x10143800.

CFG11_GPU_N3DS_CNT[edit]

Bit Description
0 Enable N3DS mode? (enables access to the extra N3DS FCRAM banks, etc.)
1 Texture related? (observing texture glitches when disabling this bit)

CFG11_CDMA_PERIPHERALS[edit]

Bit Description
0-17 CDMA Peripheral 0x00-0x11 data request target (0=Old CDMA, 1=New CDMA)
18-31 Unused

CFG11_BOOTROM_OVERLAY_CNT[edit]

Bit0: Enable bootrom overlay functionality.

CFG11_BOOTROM_OVERLAY_VAL[edit]

The 32-bit value to overlay data-reads to bootrom with. See PDN_LGR_CPU_CNT<0-3>.

CFG11_SOCINFO[edit]

Read-only register. Identifies the maximum mode-switching capabilities of the SoC.

  • CTR: O3DS
  • LGR1: N3DS prototype, 4 cores (orginally 2), up to 535MHz, no L2C (see below)
  • LGR2: retail N3DS, 4 cores, up to 804MHz, has L2C

Kernel code suggests that devices that support LGR1 but not LGR2 only had 2 cores. All cores (the number of which can be read from MPCORE SCU registers) are usable in LGR1 mode.

Bits Description Used by
0 CTR mode (1 on all 3DSes) Boot11
1 LGR1 (1 on all N3DSes, orginally 2 cores, and 2x clockrate) Kernel11
2 LGR2 (1 on all released N3DSes, 4 cores and 3x clockrate) Kernel11

CFG11_GPUPROT[edit]

Old3DS Bits Description
Yes 3-0 Old FCRAM DMA cutoff size, 0 = no protection.
No 7-4 New FCRAM DMA cutoff size, 0 = no protection.
Yes 8 AXIWRAM protection, 0 = accessible.
No 10-9 QTM DMA cutoff size
Yes 31-11 Zeroes

For the old FCRAM DMA cutoff, it protects starting from 0x28000000-(0x800000*x) until end of FCRAM. There is no way to protect the first 0x800000-bytes.

For the new FCRAM DMA cutoff, it protects starting from 0x30000000-(0x800000*x) until end of FCRAM. When the old FCRAM cutoff is set to non-zero, the first 0x800000-bytes bytes of new FCRAM are protected.

On New3DS the old+new FCRAM cutoff can be used at the same time, however this isn't done officially.

For the QTM DMA cutoff, it protects starting from 0x1F400000-(0x100000*x) until end of QTM mem.

On cold boot this reg is set to 0.

When this register is set to value 0, the GPU can access the entire FCRAM, AXIWRAM, and on New3DS all QTM-mem.

Initialized during kernel boot, and used with SVC 0x59 which was implemented with v11.3.

CFG11_WIFICNT[edit]

Old3DS Bits Description
Yes 0 Enable wifi subsystem
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