Difference between revisions of "RSA Registers"

Revision as of 00:02, 15 August 2012

Registers

NAME	PHYSICAL ADDRESS	WIDTH
REG_RSACNT	0x1000B000	0x04
REG_RSASLOT0	0x1000B100	0x10
REG_RSASLOT1	0x1000B110	0x10
REG_RSASLOT2	0x1000B120	0x10
REG_RSASLOT3	0x1000B130	0x10
REG_RSAEXPFIFO	0x1000B200	0x04
REG_RSAMOD	0x1000B400	0x100
REG_RSATXT	0x1000B800	0x100

REG_RSACNT

Bit	Description
0	Start (1=Enable/Busy, 0=Idle)
1	?
4-7	Keyslot
8	Endianness (1=Little endian, 0=Big endian)
9	Word order (0=Normal order, 1=Reversed)

REG_RSASLOT

Start	Width	Description
0x0	0x4	REG_RSASLOTCNT
0x4	0x4	REG_RSASLOTSIZE
0x8	0x4	?
0xC	0x4	?

REG_RSASLOTCNT

Bits	Description
0	Key status (1=Key has been set, 0=Key has not been set yet)
1	Key write-protect
31-2	?

REG_RSASLOTSIZE

This contains the RSA size for this slot, in words. Normally this is 0x40 for RSA-2048.

REG_RSAEXPFIFO

The 0x100-byte private or public exponent is written to this write-only FIFO.

REG_RSAMOD

The RSA key modulo for the selected keyslot can be written here. When writing the RSA modulo, the modulo must align with the end of the register area.

REG_RSATXT

The RSA signature can be written here, and the data read from here is the message. When writing the RSA signature, the signature must be prepended with zeroes until it is a multiple of 8 bytes, and the end of the signature must align with the end of the register area.

The PKCS message padding must be manually checked by software, as hardware will only do raw RSA operations.

Keyslots usage

Keyslot	Description
0	Arbitrary
1	CXI access desc (following the exheader)
2-3	Unused

@@ Line 53: / Line 53: @@
 | Keyslot
 |-
-| 8-9
+| 8
-| Should be set to 0x3 before accessing REG_RSATXT and REG_RSAMOD
+| Endianness (1=Little endian, 0=Big endian)
+|-
+| 9
+| Word order (0=Normal order, 1=Reversed)
 |}