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Line 9:
Line 9: + + + + + + Line 32:
Line 38: − + Line 38:
Line 44: − + Line 147:
Line 153: − + Line 154:
Line 160: − + − + − + − - Unknown synchronization/blanking (unknown where it happens)+ Line 175:
Line 181: − + − + − + + + + − + − + + + Line 230:
Line 241: − + Line 308:
Line 319: − + − Bit 3: null (unwritable) − Bit 4-7: unknown − Bit 8-9: DMA size − Bit 10-15: null (unwritable) − Bit 16-31: unknown − − DMA sizes (in bytes): − 0 - 64 − 1 - 128 − 2 - 256 − 3 - ??? Line 375:
Line 375: − + − |- − | 3 − | ? − + + + + + + + + − 0 - A (output image as normal)+ − 1 - AA (output a single line twice, aka framebuffer A is interlaced with itself)+ − 2 - AB (interlace framebuffer A and framebuffer B)+ − 3 - BA (same as above, but the line from framebuffer B is outputted first)+ + + + + − 0 is used by bottom screen at all times. − 1 is used by the top screen in 2D mode. − 2 is used by top screen in 3D mode. − 3 goes unused in userland. − + Line 400:
Line 404: − + + + + + + + + − + − + − + + + + + − + − − + − + − + − +
Clarity bit6 alternative mode, clean up interlacing language, elaborate how fb interlacing works, and minor cleanup on the text below the fb format register table
! Name
! Name
! Comments
! Comments
|-
| 0x1EF00000
| 0x10400000
| 4
| Hardware ID
| Bit2: new model
|-
|-
| 0x1EF00004
| 0x1EF00004
| 4
| 4
| VRAM bank control
| VRAM bank control
| Bits 8-11 = bank[i] disabled; other bits are unused
| Bits 8-11 = bank[i] disabled; other bits are unused.
|-
|-
| 0x1EF00034
| 0x1EF00034
| 4
| 4
| GPU Busy
| GPU Busy
| Bit31 = cmd-list busy, bit27 = PSC0 busy, bit26 = PSC1 busy.
| Bit26 = PSC0, bit27 = PSC1, Bit30 = PPF, Bit31 = P3D
|-
|-
| 0x1EF00050
| 0x1EF00050
All pixel and scanline timing values are 12bits, unless noted. This also applies to those fields where two u16 are combined into one register. Each u16 field is only 12bits in size. timin
All pixel and scanline timing values are 12bits, unless noted. This also applies to those fields where two u16 are combined into one register. Each u16 field is only 12bits in size. timin
The horizontal timing parameter order is as follows (values may overflow through xTotal register value):
The horizontal timing parameter order is as follows (values may overflow through HTotal register value):
0x10 < 0x14 <= 0x60.LO <= 0x04 <= 0x60.HI <= 0x08 <= 0x0C <= 0x10
0x10 < 0x14 <= 0x60.LO <= 0x04 <= 0x60.HI <= 0x08 <= 0x0C <= 0x10
0x18 <= 0x60.LO
0x18 <= 0x60.LO
There is an inherent latch order, where if two simultenaous events occur, one event wins over another.
There is an inherent latch order, where if two simultenaous events occur, one event wins over another.
Known latched modes (in no particular order):
Known latched modes (in order):
- HSync (triggers a line to the LCD to move to the next line)
- HSync (triggers a line to the LCD to move to the next line)
- Back porch (area between HSync and border being displayed, min 16 pixel clocks, otherwise the screen gets glitchy)
- Back porch (area between HSync and border being displayed, no pixels pushed, min 16 pixel clocks, otherwise the screen gets glitchy)
- Left border start (no image data is being displayed, just a configurable solid color)
- Left border start (no image data is being displayed, just a configurable solid color)
- Image start (pixel data is being DMA'd from video memory or main RAM)
- Image start (pixel data is being DMA'd from video memory or main RAM)
- Right border start/Image end (border color is being displayed after the main image)
- Right border start/Image end (border color is being displayed after the main image)
- Front porch (68 clock min, otherwise the screen doesn't sync properly, and really glitches out)
- Unknown synchronization (supposed to be probably right border end, but this mode seems to be broken or not do anything)
- Front porch (no pixels pushed, 68 clock min, otherwise the screen doesn't sync properly, and really glitches out)
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
| 0x04
| 0x04
| HParam5
| HStart
|
| Determines when the image is going to be displayed in the visible region (register 0x60).
|-
|-
| 0x08
| 0x08
| HParam7
| HBR
| Right border start(?). Does nothing.
While this register seems to have no impact on the image whatsoever, it still has to be set to a valid value.
|
|
|-
|-
| 0x0C
| 0x0C
| HParam8
| HPF
|
| Front porch. The image is blanked during this period, and no pixels are pushed to the LCD.
Unknown why, but a single dot of red is displayed before entering this mode.
|-
|-
| 0x10
| 0x10
VClock = PClock / (HTotal + 1) / (VTotal + 1)
VClock = PClock / (HTotal + 1) / (VTotal + 1)
Setting this to 494 lowers framerate to about 50.040660858 Hz ((268111856 / 24) / (250 + 1) / (494 + 1)).
Setting this to 494 lowers framerate to about 50.040660858 Hz ((268111856 / 24) / (450 + 1) / (494 + 1)).
|-
|-
| 0x28
| 0x28
| 0x70
| 0x70
| Framebuffer format and other settings
| Framebuffer format and other settings
| Bit 0-2: framebuffer format
| See [[#Framebuffer_format|framebuffer format]]
|-
|-
| 0x74
| 0x74
|-
|-
| 2-0
| 2-0
| Color format
| [[#Framebuffer_color_formats|Color format]]
|-
|-
| 5-4
| 5-4
| Framebuffer scanline output mode (interlace config)
| Framebuffer interlacing mode
0 - A (no interlacing)
1 - AA (scanline doubling)
2 - AB (interlace enable)
3 - BA (same as above, but the fields are inverted)
In AB and BA interlace modes, a scanline from each framebuffer is output in an alternating manner. In AB mode, Framebuffer A is output on the frist display scanline. Similarly, in BA mode, Framebuffer B gets output to the first display scanline.
The way AB and BA modes work, is that a scanline is output, the framebuffer stride value is added to the internal scanline pointer value, and the other framebuffer is selected. And this alternates until the end of the draw region.
AA interlacing works like AB interlacing, except both internal framebuffer pointers are set to the Framebuffer A pointer value.
In A mode (no interlacing), it doesn't switch to the other framebuffer at the end of outpuitting a scanline to the display.
Bottom screen has this set to 0 (A mode, no interlacing) at all times.
Top screen uses AB interlacing in 3D mode (with 3D slider enabled), and A mode (no interlacing) in 2D mode.
|-
|-
| 6
| 6
| Scan doubling enable?* (used by top screen)
| Alternative pixel output mode*
|-
|-
| 7
| 7
|-
|-
| 9-8
| 9-8
| Value 1 = unknown: get rid of rainbow strip on top of screen, 3 = unknown: black screen.
| DMA size
0 - 4 FCRAM words (32 bytes)
1 - 8 FCRAM words (64 bytes)
2 - 16 FCRAM words (128 bytes)
3 - ???
FCRAM doesn't support DMA size 3, as it can only burst up to 16 words (128 bytes), and will show a black screen instead.
|-
|-
| 15-10
| 31-16
| Unused?
| Unknown
|}
|}
* The weird thing about scan doubling, is that it works different between the bottom and top LCD. On the bottom LCD, it doubles the number of outputted pixels (so the same pixel is outputted twice, effectively doing column doubling). However on the top screen, it does scanline doubling instead. Considering that the bottom screen's table doesn't work on the top screen, this could give a hint as to how the top screen receives the pixel data from the PDC.
<nowiki>*</nowiki> The weird thing about bit6, is that it works different between the bottom and top LCD. On the bottom LCD, it doubles the number of outputted pixels (so the same pixel is outputted twice, effectively doing pixel/column doubling). However on the top screen, it does scanline doubling instead.
Most likely the top screen receives two pixels at once per clock unit, outputting two scanlines simultaneously.
On a 2DS, it seems to have no effect on the top part of the display, and on the bottom screen it just shifts the framebuffer to the right two pixels.
On a 2DS, it seems to have no effect on the top part of the display, and on the bottom screen it just shifts the framebuffer to the right two pixels.
GSP module only allows the LCD stereoscopy (3D) to be enabled when bit5=1 and bit6=0 here. When GSP module updates this register, GSP module will automatically disable the stereoscopy if those bits are not set for enabling stereoscopy.
GSP module only allows the LCD stereoscopy to be enabled when bit5=1 and bit6=0 here. When GSP module updates this register, GSP module will automatically disable the stereoscopy if those bits are not set for enabling stereoscopy.
When both interlacing and scan doubling are disabled, the full resolution of the top screen (240x800) can be utilized if the PDC registers are updated to accomodate this higher resolution. GSP contains tables for this mode (gsp mode == 1). GSP automatically applies this mode if both bit5 and bit6 are cleared. This is also the default, and the only valid mode for the bottom screen in userland.
When both interlacing and alternative mode is disabled (bit6=0), the full resolution of the top screen (240x800) can be utilized if the PDC registers are updated to accomodate this higher resolution. GSP contains tables for this mode (gsp mode == 1). GSP automatically applies this mode if both bit5 and bit6 are cleared. This is also the default, and the only valid mode for the bottom screen in userland.
If only AB interlacing is enabled, gsp detects this as a request to switch to 3D mode (gsp mode == 2), and enables the parallax barrier.
If only AB interlacing is enabled (bit5=1, bit6=0), gsp detects this as a request to switch to 3D mode (gsp mode == 2), and enables the parallax barrier.
It's unknown how to control this, but some other PDC registers control if interlacing should be done by true interleaving (both framebuffers are treated as 240x400), or skipping lines (both framebuffers are treated as 240x800)
It's unknown how to control this, but some other PDC registers control if interlacing should be done by true interleaving (both framebuffers are treated as 240x400), or by skipping lines (both framebuffers are treated as 240x800).
If only scan doubling is enabled, gsp detects it as a request to switch back to 2D mode for the top screen (gsp mode == 0). This is also the default mode for the top screen.
If only alternative mode is enabled (bit5=0, bit6=1), gsp detects it as a request to switch back to 2D mode for the top screen (gsp mode == 0). This is also the default mode for the top screen.
Both interlacing and scan doubling can't be enabled in usermode, but it works as expected in baremetal.
Both interlacing and scan doubling can't be enabled in usermode, but it works as expected in baremetal.