Difference between revisions of "I2S Registers"

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= Registers =
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{| class="wikitable" border="1"
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!  Old3DS
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!  Name
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!  Address
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!  Width
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!  Used by
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|-
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| style="background: green" | Yes
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| [[#I2S1_CNT|I2S1_CNT]]
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| 0x10145000
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| 2
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| Codec sysmodule, AgbBg, TwlBg
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|-
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| style="background: green" | Yes
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| [[#I2S2_CNT|I2S2_CNT]]
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| 0x10145002
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| 2
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| Codec sysmodule, AgbBg, TwlBg
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|}
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 +
 
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==I2S1_CNT==
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{| class="wikitable" border="1"
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!  Bit
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!  Description
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|-
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| 0-5
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| DSP volume (doesn't affect csnd).
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|-
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| 6-11
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| GBA hardware master volume. And DSi too?
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|-
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| 12
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| Unknown purpose. Maybe direction for microphone input?
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|-
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| 13
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| I2S frequency. 0=32.728498046875 kHz, 1=47.605088068181818181818 kHz.
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|-
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| 14
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| First MCLK output. 0=8.3784955 MHz, 1=16.756991 MHz.
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|-
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| 15
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| Enable (0=Disabled, 1=Enabled)
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|}
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This I2S line is used the DSP, GBA hardware and microphone.
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This is usually set to 0xC800 or 0xC820 when the DSP is active.
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==I2S2_CNT==
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{| class="wikitable" border="1"
 +
!  Bit
 +
!  Description
 +
|-
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| 0-12
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| Unused (0).
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|-
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| 13
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| I2S frequency. 0=32.728498046875 kHz, 1=47.605088068181818181818 kHz.
 +
|-
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| 14
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| Second MCLK output. Connected to the CODEC chip. 0=8.3784955 MHz, 1=16.756991 MHz.
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|-
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| 15
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| Enable (0=Disabled, 1=Enabled)
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|}
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This I2S line is used by CSND.
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 +
Usually set to 0xE000.

Latest revision as of 20:03, 26 September 2024

Registers[edit]

Old3DS Name Address Width Used by
Yes I2S1_CNT 0x10145000 2 Codec sysmodule, AgbBg, TwlBg
Yes I2S2_CNT 0x10145002 2 Codec sysmodule, AgbBg, TwlBg


I2S1_CNT[edit]

Bit Description
0-5 DSP volume (doesn't affect csnd).
6-11 GBA hardware master volume. And DSi too?
12 Unknown purpose. Maybe direction for microphone input?
13 I2S frequency. 0=32.728498046875 kHz, 1=47.605088068181818181818 kHz.
14 First MCLK output. 0=8.3784955 MHz, 1=16.756991 MHz.
15 Enable (0=Disabled, 1=Enabled)

This I2S line is used the DSP, GBA hardware and microphone.

This is usually set to 0xC800 or 0xC820 when the DSP is active.


I2S2_CNT[edit]

Bit Description
0-12 Unused (0).
13 I2S frequency. 0=32.728498046875 kHz, 1=47.605088068181818181818 kHz.
14 Second MCLK output. Connected to the CODEC chip. 0=8.3784955 MHz, 1=16.756991 MHz.
15 Enable (0=Disabled, 1=Enabled)

This I2S line is used by CSND.

Usually set to 0xE000.