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GSP Shared Memory: Difference between revisions

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=unk info=
=Interrupt info=
The unk info structure is located at sharedmemvadr + threadindex*0x40.
The Interrupt info structure is located at sharedmemvadr + process_gsp_index*0x40.
 
{| class="wikitable" border="1"
|-
!  Index Byte
!  Description
|-
| 0x0
| Offset from the count where to save incoming interrupts
|-
| 0x1
| Count (max 0x20 for PDC, 0x34 for others)
|-
| 0x2
| Missed other interrupts (set to 1 when 0 and count >= 0x34)
|-
| 0x3
| Flags (bit0 = skip PDC)
|-
| 0x4-0x7
| Missed PDC0 (incremented when flags.bit0 is clear and count >= 0x20)
|-
| 0x8-0xB
| Missed PDC1 (same as above)
|-
| 0xC-0x3F
| Interrupt list (u8) (0=PSC0, 1=PSC1, 2=PDC0/VBlankTop, 3=PDC1/VBlankBottom, 4=PPF, 5=P3D, 6=DMA)
|}
 
GSP fills the interrupt list, then triggers the event set with [[GSPGPU:RegisterInterruptRelayQueue|RegisterInterruptRelayQueue]] for the specified process(es).
 
PDC interrupts are sent to all processes; other interrupts are only sent to the process with GPU rights.


=Framebuffer info=
=Framebuffer info=
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=Command Buffer Header=
=Command Buffer Header=
The command buffer is located at sharedmem + 0x800 + [[GSPGPU:RegisterInterruptRelayQueue|threadindex]]*0x200. After writing the command data to shared memory, [[GSPGPU:TriggerCmdReqQueue|TriggerCmdReqQueue]] must be used to trigger GSP processing for the command when the total commands field is value 1.
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
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|  u32 Error code for the last GX command which failed
|  u32 Error code for the last GX command which failed
|}
|}
The command buffer is located at sharedmem + 0x800 + [[GSPGPU:RegisterInterruptRelayQueue|threadindex]]*0x200. After writing the command data to shared memory, [[GSPGPU:TriggerCmdReqQueue|TriggerCmdReqQueue]] must be used to trigger GSP processing for the command when the total commands field is value 1.


=Command Header=
=Command Header=
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=Commands=
=Commands=


==GX RequestDma==
== Trigger DMA Request ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
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|-
|-
| 7
| 7
| Flag: when source buffer is not located in VRAM and this flag is non-zero, svcFlushProcessDataCache is used with the source buffer.
| Flush source (0 = don't flush, 1 = flush)
|}
|}


This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM.
This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM. When flushing is enabled and the source buffer is not located within VRAM, svcFlushProcessDataCache is used to flush the source buffer.


==GX SetCommandList Last==
== Trigger Command List Processing ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
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|-
|-
| 3
| 3
| Flag, bit0 is written to GSP module state
| Update gas additive blend results (0 = don't update, 1 = update)
|-
|-
| 6-4
| 6-4
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|-
|-
| 7
| 7
| When non-zero, call svcFlushProcessDataCache() with the specified buffer
| Flush buffer (0 = don't flush, 1 = flush)
|}
|}


This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU_Commands|GPU commands]].
This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU/Internal_Registers|GPU commands]]. When flushing is enabled, svcFlushProcessDataCache is used to flush the buffer.


==GX SetMemoryFill==
== Trigger Memory Fill ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
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|-
|-
| 1
| 1
| Buf0 start address
| Buf0 start address (0 = don't fill anything)
|-
|-
| 2
| 2
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|-
|-
| 4
| 4
| Buf1 start address
| Buf1 start address (0 = don't fill anything)
|-
|-
| 5
| 5
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|-
|-
| 7
| 7
| The low u16 is width0, while the high u16 is width1 (?)
| Control0 <nowiki>|</nowiki> (Control1 << 16)
|}
|}


This commands converts the specified addresses to physical addresses, then writes these addresses and the specified parameters to the [[GPU]] registers at 0x1EF00010 and 0x1EF00020. Doing so fills the specified buffers with the associated 4-byte value. This is used to clear GPU framebuffers.
This command converts the specified addresses to physical addresses, then writes these addresses and the specified parameters to the [[GPU]] registers at 0x1EF00010 and 0x1EF00020. Doing so fills the specified buffers with the associated 4-byte value. This is used to clear GPU framebuffers.
The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped.
The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped.


==GX SetDisplayTransfer==
The values of Control0 and Control1 give information about the type of memory fill. See [[GPU/External_Registers#Memory Fill|here]] for more information about memory fill parameters.
 
== Trigger Display Transfer ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
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|}
|}


This command converts the specified addresses to physical addresses, then writes these physical addresses and parameters to the [[GPU]] registers at 0x1EF00C00. This GPU command copies the already rendered framebuffer data from the input GPU framebuffer address to the specified output LCD framebuffer. The input framebuffer is normally located in VRAM. Note that unlike the LCD framebuffers, the GPU framebuffer seems to use fixed-point/floats for the color format.
This command converts the specified addresses to physical addresses, then writes these physical addresses and parameters to the [[GPU]] registers at 0x1EF00C00. This GPU command copies the already rendered framebuffer data from the input GPU framebuffer address to the specified output LCD framebuffer. The input framebuffer is normally located in VRAM.
 
The GPU color buffer is stored in the same Z-curve (tiled) format as textures. By default, SetDisplayTransfer converts the given buffer from the tiled format to a linear format adapted to the LCD framebuffers.
 
Display transfers are performed asynchronously, so after requesting a display transfer you should wait for the PPF interrupt to fire before reading the output data.


==GX SetTextureCopy==
Some color formats seem to require specific input / output sizes when performing a display transfer, doing an RGB5A1->RGBA4 display transfer would never fire the PPF interrupt with a 32x32 buffer, increasing the buffer to 128x128 made it fire correctly.
 
== Trigger Texture Copy ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
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|-
|-
| 1
| 1
| Input buffer address
| Input buffer address.
|-
|-
| 2
| 2
| Output buffer address
| Output buffer address.
|-
|-
| 3
| 3
| Size
| Total bytes to copy, not including gaps.
|-
|-
| 4
| 4
| Input [[GPU|dimensions]]?
| Bits 0-15: Size of input line, in bytes. Bits 16-31: Gap between input lines, in bytes.
|-
|-
| 5
| 5
| Output dimensions?
| Same as 4, but for the output.
|-
|-
| 6
| 6
| Flags, normally this is 0x8, with bit2 optionally set when either of the dimensions fields are set.
| Flags, corresponding to the [[GPU/External_Registers#Transfer_Engine|Transfer Engine flags]]. However, for TextureCopy commands, bit 3 is always set, bit 2 is set if any output dimension is smaller than the input, and other bits are always 0.
|-
|-
| 7
| 7
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|}
|}


This command is similar to cmd3, this command also writes to the [[GPU]] registers at 0x1EF00C00.
This command is similar to cmd3. It also triggers the [[GPU/External_Registers#Transfer_Engine|GPU Transfer Engine]], but setting the TextureCopy parameters.


==GX SetCommandList First ==
== Flush Cache Regions ==
{| class="wikitable" border="1"
{| class="wikitable" border="1"
|-
|-
Retrieved from "https://www.3dbrew.org/wiki/GSP_Shared_Memory"