GSP Shared Memory: Difference between revisions
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=Interrupt info= | =Interrupt info= | ||
The Interrupt info structure is located at sharedmemvadr + process_gsp_index*0x40. | The Interrupt info structure is located at sharedmemvadr + process_gsp_index*0x40. | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
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|- | |- | ||
| 0x0 | | 0x0 | ||
| | | Offset from the count where to save incoming interrupts | ||
|- | |- | ||
| 0x1 | | 0x1 | ||
| | | Count (max 0x20 for PDC, 0x34 for others) | ||
|- | |- | ||
| 0x2 | | 0x2 | ||
| | | Missed other interrupts (set to 1 when 0 and count >= 0x34) | ||
|- | |- | ||
| 0x3 | | 0x3 | ||
| | | Flags (bit0 = skip PDC) | ||
|- | |- | ||
| 0x4-0x7 | | 0x4-0x7 | ||
| | | Missed PDC0 (incremented when flags.bit0 is clear and count >= 0x20) | ||
|- | |- | ||
| 0x8-0xB | | 0x8-0xB | ||
| | | Missed PDC1 (same as above) | ||
|- | |- | ||
| 0xC-0x3F | | 0xC-0x3F | ||
| u8 | | Interrupt list (u8) (0=PSC0, 1=PSC1, 2=PDC0/VBlankTop, 3=PDC1/VBlankBottom, 4=PPF, 5=P3D, 6=DMA) | ||
|} | |} | ||
GSP fills the interrupt list, then triggers the event set with [[GSPGPU:RegisterInterruptRelayQueue|RegisterInterruptRelayQueue]] for the specified process(es). | |||
PDC interrupts are sent to all processes; other interrupts are only sent to the process with GPU rights. | |||
=Framebuffer info= | =Framebuffer info= | ||
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|- | |- | ||
| 7 | | 7 | ||
| | | Flush source (0 = don't flush, 1 = flush) | ||
|} | |} | ||
This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM. | This command is normally used to DMA data from the application GSP [[Memory_layout|heap]] to VRAM. When flushing is enabled and the source buffer is not located within VRAM, svcFlushProcessDataCache is used to flush the source buffer. | ||
== Trigger Command List Processing == | == Trigger Command List Processing == | ||
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|- | |- | ||
| 3 | | 3 | ||
| | | Update gas additive blend results (0 = don't update, 1 = update) | ||
|- | |- | ||
| 6-4 | | 6-4 | ||
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|- | |- | ||
| 7 | | 7 | ||
| | | Flush buffer (0 = don't flush, 1 = flush) | ||
|} | |} | ||
This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU/Internal_Registers|GPU commands]]. | This command converts the specified address to a physical address, then writes the physical address and size to the [[GPU]] registers at 0x1EF018E0. This buffer contains [[GPU/Internal_Registers|GPU commands]]. When flushing is enabled, svcFlushProcessDataCache is used to flush the buffer. | ||
== Trigger Memory Fill == | == Trigger Memory Fill == | ||
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|- | |- | ||
| 7 | | 7 | ||
| | | Control0 <nowiki>|</nowiki> (Control1 << 16) | ||
|} | |} | ||
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The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped. | The associated buffer address must not be <= to the main buffer address, thus the associated buffer address must not be zero as well. When the bufX address is zero, processing for the bufX parameters is skipped. | ||
The values of | The values of Control0 and Control1 give information about the type of memory fill. See [[GPU/External_Registers#Memory Fill|here]] for more information about memory fill parameters. | ||
== Trigger Display Transfer == | == Trigger Display Transfer == |