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I2C Registers: Difference between revisions

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System info →Device 3
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| 0xa6
| 0xa6
| "i2c::HID"
| "i2c::HID"
| Debug(?) gyroscope. The device table in I2C-module had the device address changed from 0xA6 to 0xD6 with [[8.0.0-18]].
| Gyroscope. The device table in I2C-module had the device address changed from 0xA6 to 0xD6 with [[8.0.0-18]].
|-
|-
| 10
| 10
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| 0xa4
| 0xa4
| "i2c::HID"
| "i2c::HID"
| DebugPad
| DebugPad (slightly modified [https://wiibrew.org/wiki/Wiimote/Extension_Controllers/Classic_Controller_Pro Wii Classic Controller Pro])
|-
|-
| 13
| 13
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   s* = shared register (explaination below this table)
   s* = shared register (explaination below this table)
   ds = dynamic shared (explaination below this table)
   ds = dynamic shared (explaination below this table)
Reading or writing multiple bytes from/to single-byte registers increments the register ID along with it. For example reading two bytes from reg 0x00 reads regs 0x00 and 0x01.
This is not the case for multibyte regs (0x29, 0x2D, 0x4F, 0x61 and 0x7F), plus reg 0x60.
{| class="wikitable" border="1"
{| class="wikitable" border="1"
!  REGISTER
!  REGISTER
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   bit0: RTC clock value got reset to defaults
   bit0: RTC clock value got reset to defaults
   bit1: Watchdog reset happened
   bit1: Watchdog reset happened
   bit5: TWL volume mode (0: 8-step, 1: 32-step)
   bit5: TWL MCU reg: volume mode (0: 8-step, 1: 32-step)
   bit6: Is in TWL mode
   bit6: TWL MCU reg: NTR (0) vs TWL mode (1)
  bit7: TWL MCU reg: Uses NAND
|-
|-
| 0x03
| 0x03
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   bit22: Volume slider position change
   bit22: Volume slider position change
   bit23: ??? Register 0x0E update
   bit23: ??? Register 0x0E update
   bit24: ??? (the off event for below bit)
   bit24: GPU off
   bit25: ??? (triggered when something related to the GPU is turned on, most likely backlight)
   bit25: GPU on
   bit26: ??? (???)
   bit26: bottom backlight off
   bit27: ??? (???)
   bit27: bottom backlight on
   bit28: ??? (???)
   bit28: top backlight off
   bit29: ??? backlight on?
   bit29: top backlight on
   bit30: bit set by mcu sysmodule
   bit30: bit set by mcu sysmodule
   bit31: bit set by mcu sysmodule
   bit31: bit set by mcu sysmodule
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   bit0: power off
   bit0: power off
   bit1: full reboot (unused). Discards things like [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]]
   bit1: full reboot (unused). Discards things like [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]]
   bit2: reboot. Preserves [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]], etc.
    - Asserts RESET1 via PMIC command (?) (deasserts nRESET1). This could be the reset that controls some CFG9 registers
   bit3: reset FCRAM (present in by LgyBg. Unused because a system reboot does the same thing & a PDN reg also implements this function.
    - Asserts RESET2 (P0.1 = 0, PM0.1 = 0 (output)) (deasserts nRESET2)
    - Asserts FCRAM_RESET (P3.0 = 0) (deasserts nFCRAM_RESET)
   bit2: normal reboot. Preserves [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]], etc.
    - Asserts RESET2 (P0.1 = 0, PM0.1 = 0)
    - If in NTR emulation mode (see reg 0x02), asserts FCRAM_RESET (P3.0 = 0)
    - Resets TWL MCU i2c registers
   bit3: FCRAM reset (present in by LgyBg. Unused because a system reboot does the same thing & a PDN reg also possibly implements this function)
    - Asserts FCRAM_RESET (P3.0 = 0)
   bit4: signal that sleep mode is about to be entered (used by PTM)
   bit4: signal that sleep mode is about to be entered (used by PTM)
Bit 4 sets a bit at a RAM address which seems to control the watcdog timer state, then this bit is immediately unmasked. This field has a bitmask of 0x0F.  
Bit 4 sets a bit at a RAM address which seems to control the watcdog timer state, then this bit is immediately unmasked. This field has a bitmask of 0x0F.
 
If any of the reset bits is set, the MCU waits for 5ms, then deasserts RESET1 (via PMIC), RESET2 (PM0.1 = 1 (input)) and FCRAM_RESET (P3.0 = 1), and reinitializes some other various registers after a 100ms delay.
|-
|-
| 0x21
| 0x21
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| 0x29
| 0x29
| sd(5)
| sd(5)
| ??
| rw
| Power mode indicator state (read-write)
| Power mode indicator state (read-write)
   1 = forced default blue
   1 = forced default blue
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|-
|-
| 0x3F
| 0x3F
| s
| d
| wo
| wo
| 2 bits
| 2 bits
   bit0: turns off P00 and sets it to output mode (seems to kill the entire SoC)
   bit0: Asserts RESET1 (P0.0 = 0, PM0.0 = 0 (output)) but does NOT deassert it (wtf?). This seems to kill the entire SoC: is it because it doesn't deassert it, or does it not deassert it because the SoC hangs anyway? This is the pin that controls some security-critical regs like CFG9_BOOTENV!
   bit1: turns on a prohibited bit in an RTC Control register and turns P12 into an output
   bit1: turns on a prohibited bit in an RTC Control register and turns P12 into an output
|-
|-
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|-
|-
| 0x60
| 0x60
| ds
| d
| rw
| rw
| Free register bank address select
| Free register bank address (index) select
Selects the index to read from in the free register bank, up to 200 (?). Used with reg 0x61.
Selects the index to read from in the free register bank, up to 200. Used in conjunction with reg 0x61.
 
Reading from this register seem to read N bytes from the bank while incrementing the internal index by the same amount.


   byte 0: bit0 = "WirelessDisabled", bit1 = "SoftwareClosed", bit2 = "PowerOffInitiated", bit3 = "LgyNativeResolution", bit4 = "LegacyJumpProhibited"
   byte 0: bit0 = "WirelessDisabled", bit1 = "SoftwareClosed", bit2 = "PowerOffInitiated", bit3 = "LgyNativeResolution", bit4 = "LegacyJumpProhibited"
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|-
|-
| 0x61
| 0x61
| ds(0x100)
| d(200)
| rw
| rw
| Free register bank, data is read from/written to here.
| Free register bank, data is read from/written to here.


Writing to here seems to increment the internal index?
Accessing N bytes of this register increments the selected index by N.
|-
|-
| 0x62 - 0x7E
| 0x62 - 0x7E
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|}
|}


This is the DebugPad device, see [[HID_Shared_Memory|here]].
This is a [https://wiibrew.org/wiki/Wiimote/Extension_Controllers/Classic_Controller_Pro Wii Classic Controller Pro] which was slightly modified to have an encrypted device type of 0xF0 [https://wiibrew.org/wiki/Wiimote/Extension_Controllers#The_New_Way instead of 0xFD].
 
See [[HID_Shared_Memory#Offset_0x238|here]] for the HID shared memory report format.


== Device 13 ==
== Device 13 ==
Retrieved from "https://www.3dbrew.org/wiki/I2C_Registers"