Difference between revisions of "SPI Registers"

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(→‎Registers: Use same naming scheme as NDMA)
Line 20: Line 20:
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]0
+
| [[#NSPI_CNT|NSPI_CNT]]0
 
| 0x10142800
 
| 0x10142800
 
| 4
 
| 4
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|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_DONE|SPI_NEW_DONE]]0
+
| [[#NSPI_DONE|NSPI_DONE]]0
 
| 0x10142804
 
| 0x10142804
 
| 4
 
| 4
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|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]0
+
| [[#NSPI_BLKLEN|NSPI_BLKLEN]]0
 
| 0x10142808
 
| 0x10142808
 
| 4
 
| 4
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|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]0
+
| [[#NSPI_FIFO|NSPI_FIFO]]0
 
| 0x1014280C
 
| 0x1014280C
 
| 4
 
| 4
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|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]0
+
| [[#NSPI_STATUS|NSPI_STATUS]]0
 
| 0x10142810
 
| 0x10142810
 
| 4
 
| 4
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|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]1
+
| [[#NSPI_CNT|NSPI_CNT]]1
 
| 0x10143800
 
| 0x10143800
 
| 4
 
| 4
Line 86: Line 86:
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_DONE|SPI_NEW_DONE]]1
+
| [[#NSPI_DONE|NSPI_DONE]]1
 
| 0x10143804
 
| 0x10143804
 
| 4
 
| 4
Line 92: Line 92:
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]1
+
| [[#NSPI_BLKLEN|NSPI_BLKLEN]]1
 
| 0x10143808
 
| 0x10143808
 
| 4
 
| 4
Line 98: Line 98:
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]1
+
| [[#NSPI_FIFO|NSPI_FIFO]]1
 
| 0x1014380C
 
| 0x1014380C
 
| 4
 
| 4
Line 104: Line 104:
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]1
+
| [[#NSPI_STATUS|NSPI_STATUS]]1
 
| 0x10143810
 
| 0x10143810
 
| 4
 
| 4
Line 140: Line 140:
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]2
+
| [[#NSPI_CNT|NSPI_CNT]]2
 
| 0x10160800
 
| 0x10160800
 
| 4
 
| 4
Line 146: Line 146:
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_DONE|SPI_NEW_DONE]]2
+
| [[#NSPI_DONE|NSPI_DONE]]2
 
| 0x10160804
 
| 0x10160804
 
| 4
 
| 4
Line 152: Line 152:
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]2
+
| [[#NSPI_BLKLEN|NSPI_BLKLEN]]2
 
| 0x10160808
 
| 0x10160808
 
| 4
 
| 4
Line 158: Line 158:
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]2
+
| [[#NSPI_FIFO|NSPI_FIFO]]2
 
| 0x1016080C
 
| 0x1016080C
 
| 4
 
| 4
Line 164: Line 164:
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
−
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]2
+
| [[#NSPI_STATUS|NSPI_STATUS]]2
 
| 0x10160810
 
| 0x10160810
 
| 4
 
| 4
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|}
 
|}
  
−
== SPI_NEW_CNT ==
+
== NSPI_CNT ==
 
This is an alternative faster interface introduced with the 3DS.
 
This is an alternative faster interface introduced with the 3DS.
  
Line 275: Line 275:
 
|}
 
|}
  
−
== SPI_NEW_DONE ==
+
== NSPI_DONE ==
−
This register reads as 1 after starting a transfer. When the transfer is finished, a 0 has to be written to this register. This is probaly the Chip Select line.
+
This register reads as 1 after starting a transfer. When the transfer is finished, a 0 has to be written to this register. This is probably the Chip Select line.
  
−
==SPI_NEW_BLKLEN==
+
==NSPI_BLKLEN==
 
The number of bytes to be sent/read is written to this register.
 
The number of bytes to be sent/read is written to this register.
  
−
==SPI_NEW_FIFO==
+
==NSPI_FIFO==
 
32-bit FIFO for reading/writing the SPI payload.
 
32-bit FIFO for reading/writing the SPI payload.
  
−
==SPI_NEW_STATUS==
+
==NSPI_STATUS==
 
Bit0: FIFO busy. At transfer start and every 32 bytes the FIFO becomes busy.
 
Bit0: FIFO busy. At transfer start and every 32 bytes the FIFO becomes busy.

Revision as of 19:36, 7 May 2019

Registers

Old3DS Name Address Width Used by
Yes SPI_CNT0 0x10142000 2
Yes SPI_DATA0 0x10142002 1
Yes NSPI_CNT0 0x10142800 4
Yes NSPI_DONE0 0x10142804 4
Yes NSPI_BLKLEN0 0x10142808 4
Yes NSPI_FIFO0 0x1014280C 4
Yes NSPI_STATUS0 0x10142810 4
Yes ? Same as SPICARD + 0x814. Unused by SPI sysmodule. 0x10142814 4
Yes ? Unused by SPI sysmodule. 0x10142818 4
Yes ? Unused by SPI sysmodule. 0x1014281C 4
Yes SPI_CNT1 0x10143000 2
Yes SPI_DATA1 0x10143002 1
Yes NSPI_CNT1 0x10143800 4
Yes NSPI_DONE1 0x10143804 4
Yes NSPI_BLKLEN1 0x10143808 4
Yes NSPI_FIFO1 0x1014380C 4
Yes NSPI_STATUS1 0x10143810 4
Yes ? Same as SPICARD + 0x814. Unused by SPI sysmodule. 0x10143814 4
Yes ? Unused by SPI sysmodule. 0x10143818 4
Yes ? Unused by SPI sysmodule. 0x1014381C 4
Yes SPI_CNT2 0x10160000 2
Yes SPI_DATA2 0x10160002 1
Yes NSPI_CNT2 0x10160800 4
Yes NSPI_DONE2 0x10160804 4
Yes NSPI_BLKLEN2 0x10160808 4
Yes NSPI_FIFO2 0x1016080C 4
Yes NSPI_STATUS2 0x10160810 4
Yes ? Same as SPICARD + 0x814. Unused by SPI sysmodule. 0x10160814 4
Yes ? Unused by SPI sysmodule. 0x10160818 4
Yes ? Unused by SPI sysmodule. 0x1016081C 4

There are two register interfaces: the old NDS/DSi one and an alternative faster interface introduced with the 3DS.

To toggle between those interfaces, use the CFG11_SPI_CNT register.

SPI_CNT

This is the old NDS/DSi SPI interface.

Bits Name
0-1 Baudrate (0=4MHz, 1=2MHz, 2=1MHz, 3=512KHz)
2-6 This was added with 3DS.
7 Busy Flag (0=Ready, 1=Busy) (presumably Read-only)
8-9 Device Select (0=Powerman., 1=Firmware, 2=Touchscreen)
10 Transfer Size (0=8bit/Normal, 1=16bit/Bugged)
11 Chipselect Hold (0=Deselect after transfer, 1=Keep selected)
12-13 Not used (Zero)
14 Interrupt Request (0=Disable, 1=Enable)
15 SPI Bus Enable (0=Disable, 1=Enable)

NSPI_CNT

This is an alternative faster interface introduced with the 3DS.

Bits Name
0-2 Baudrate?
6-7 Device Select
12 Bus mode 0=1 bit, 1=4 bit
13 Transfer Direction? (0=Incoming, 1=Outgoing)
15 Busy/enable
Device id Device select bits
0, 3, >=6 0
1, 4 1
2, 5 2
Device id Used baudrate
3 5
0 2

NSPI_DONE

This register reads as 1 after starting a transfer. When the transfer is finished, a 0 has to be written to this register. This is probably the Chip Select line.

NSPI_BLKLEN

The number of bytes to be sent/read is written to this register.

NSPI_FIFO

32-bit FIFO for reading/writing the SPI payload.

NSPI_STATUS

Bit0: FIFO busy. At transfer start and every 32 bytes the FIFO becomes busy.

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