Line 367: |
Line 367: |
| |} | | |} |
| | | |
− | [[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG: | + | [[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_SOCINFO: |
| {| class="wikitable" border="1" | | {| class="wikitable" border="1" |
| ! Register value | | ! Register value |
| ! Higher-clockrate bit set in svcKernelSetState Param0 | | ! Higher-clockrate bit set in svcKernelSetState Param0 |
− | ! CFG11_MPCORE_CFG bit2 set | + | ! CFG11_SOCINFO bit2 set |
| ! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state | | ! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state |
| ! Clock-rate multiplier | | ! Clock-rate multiplier |
Line 405: |
Line 405: |
| |} | | |} |
| | | |
− | Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code). | + | Note that the above CFG11_SOCINFO bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code). |
| | | |
| The following register value(s) were tested on New3DS by patching the kernel: | | The following register value(s) were tested on New3DS by patching the kernel: |