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Line 8:
Line 8: − + − + − + Line 34:
Line 34: − + − + Line 57:
Line 57: − + − +
Register cleanup
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|-
| 0x00010000
| 0x00010000
| This loads the u32s from 0x1EC41000+8 and 0x1EC41000+12, then writes those to cmdreplyword[2] and cmdreplyword[3].
| This loads [[CONFIG11 Registers|CFG11_PTM_0]] and [[CONFIG11 Registers|CFG11_PTM_1]], then writes them to cmdreplyword[2] and cmdreplyword[3].
|-
|-
| 0x00020080
| 0x00020080
| u32 0x1EC41000+12 = cmdword[2] & cmdword[1]. This then writes cmdword[1] to u32 0x1EC41000+8. u32 0x1EC41000+12 = cmdword[2] & ~cmdword[1].
| [[CONFIG11 Registers|CFG11_PTM_1]] = cmdword[2] & cmdword[1]. This then writes cmdword[1] to [[CONFIG11 Registers|CFG11_PTM_0]]. [[CONFIG11 Registers|CFG11_PTM_1]] = cmdword[2] & ~cmdword[1].
|-
|-
| 0x00030040
| 0x00030040
| This writes cmdword[1] to u32 0x1EC41000+12.
| This writes cmdword[1] to [[CONFIG11 Registers|CFG11_PTM_1]].
|}
|}
|-
|-
| 0x00010040
| 0x00010040
| This sets bit0 in u8 *(0x1EC41000+0x220) to u8 cmd+4.
| This sets bit0 in [[CONFIG11 Registers#CFG11_CODEC_CNT|CFG11_CODEC_CNT]] to u8 cmd+4.
|-
|-
| 0x00020040
| 0x00020040
| This sets bit1 in u8 *(0x1EC41000+0x220) to u8 cmd+4.
| This sets bit1 in [[CONFIG11 Registers#CFG11_CODEC_CNT|CFG11_CODEC_CNT]] to u8 cmd+4.
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|}
|-
|-
| 0x00010040
| 0x00010040
| This sets bit0 in u8 *(0x1EC41000+0x224) to u8 cmd+4.
| This sets bit0 in [[CONFIG11 Registers#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]] to u8 cmd+4.
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|-
| 0x000200000
| 0x000200000
| This writes u8 *(0x1EC41000+0x224) & 1 to u8 cmdreply+8.
| This writes [[CONFIG11 Registers#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]] & 1 to u8 cmdreply+8.
|}
|}