Difference between revisions of "PXI Registers"

From 3dbrew
Jump to navigation Jump to search
(clear up notes on sync cc profi200)
 
(One intermediate revision by the same user not shown)
Line 11: Line 11:
 
| 0x10008000
 
| 0x10008000
 
| 4
 
| 4
|
+
| Boot9, Process9
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
 
| [[#PXI_CNT|PXI_CNT]]9
 
| [[#PXI_CNT|PXI_CNT]]9
 
| 0x10008004
 
| 0x10008004
| 4
+
| 2
|
+
| Boot9, Process9
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
Line 35: Line 35:
 
| 0x10163000
 
| 0x10163000
 
| 4
 
| 4
|
+
| Boot11
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
 
| [[#PXI_CNT|PXI_CNT]]11
 
| [[#PXI_CNT|PXI_CNT]]11
 
| 0x10163004
 
| 0x10163004
| 4
+
| 2
|
+
| Boot11
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes

Latest revision as of 01:56, 6 January 2017

Registers[edit]

Old3DS Name Address Width Used by
Yes PXI_SYNC9 0x10008000 4 Boot9, Process9
Yes PXI_CNT9 0x10008004 2 Boot9, Process9
Yes PXI_SEND9 0x10008008 4
Yes PXI_RECV9 0x1000800C 4
Yes PXI_SYNC11 0x10163000 4 Boot11
Yes PXI_CNT11 0x10163004 2 Boot11
Yes PXI_SEND11 0x10163008 4
Yes PXI_RECV11 0x1016300C 4

The PXI registers are similar to those on DS.

PXI_SYNC[edit]

Bit RW Description
0-7 R Data received from remote bits 8-15 (unrelated to SEND/RECV FIFOs)
8-15 R/W Data sent to remote bits 0-7
23 ? ?
29 W? Trigger PXI_SYNC11 IRQ (if enabled)
30 W? Trigger PXI_SYNC9 IRQ (if enabled)
31 RW PXI_SYNC IRQ enable (for local processor)

This can also be accessed as 4 u8 registers.

PXI_CNT[edit]

Bit RW Description
0 R Send Fifo Empty Status (0=Not Empty, 1=Empty)
1 R Send Fifo Full Status (0=Not Full, 1=Full)
2 R/W Send Fifo Empty IRQ (0=Disable, 1=Enable)
3 W Send Fifo Clear (0=Nothing, 1=Flush Send Fifo)
8 R Receive Fifo Empty (0=Not Empty, 1=Empty)
9 R Receive Fifo Full (0=Not Full, 1=Full)
10 R/W Receive Fifo Not Empty IRQ (0=Disable, 1=Enable)
14 R/W Error, Read Empty/Send Full (0=No Error, 1=Error/Acknowledge)
15 R/W Enable Send/Receive Fifo (0=Disable, 1=Enable)