Difference between revisions of "PXI Registers"

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= Protocol =
 
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The communication protocol for normal PXI commands is documented below. The size of cmd_buf is calculated from the cmd_hdr. With newer FIRM the total size for command header + buffer must be at most 0x40 words, otherwise Process9 will panic.
 
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Each pxi_id corresponds to a Process9 PXI [[PXI_Services|command-handler]](called from threads) which handles the actual command processing. With newer FIRM the pxi_id must be in a certain range.
 
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There's a dedicated Process9 thread for receiving data from PXI(in newer FIRM this is the main-thread), once it finishes receiving a request it copies the cmd_buf into a buffer for the corresponding pxi_id then signals an event so that the cmd-handler thread can process it. Once a cmd-handler thread finishes processing a command, the thread itself then sends the response over PXI. This means that multiple commands for different pxiIDs can be be handled at the same time, even when one cmd-handler completely hangs/etc for example.
 
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Process9 will execute [[SVC|svcBreak]] when it receives a PXI command with a pxi_id where another cmmand with that same pxi_id is still being processed by the command-handler(this won't happen with commands sent by the ARM11 PXI-module, since it waits for the command reply before sending another command request for that same pxi_id).
 
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==Request==
 
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A11->A9 (u32) pxi_id
 
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A11->A9 (u32) cmd_hdr
 
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A11->A9 (u32[]) cmd_buf
 
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==Response==
 
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A9->A11 (u32) pxi_id
 
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A9->A11 (u32) cmd_hdr
 
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A9->A11 (u32[]) cmd_buf
 
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==pxi_id==
 
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0 = pxi_mc
 
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1 = pxi_fs
 
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2 = pxi_fs
 
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3 = pxi_fs
 
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4 = pxi_fs
 
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5 = pxi_pm
 
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6 = pxi_dev
 
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7 = pxi_am
 
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8 = pxi_ps
 
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9 = stubbed
 
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= Registers =
 
= Registers =
 
{| class="wikitable" border="1"
 
{| class="wikitable" border="1"
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| 0x10008000
 
| 0x10008000
 
| 4
 
| 4
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|
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| Boot9, Process9
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
 
| [[#PXI_CNT|PXI_CNT]]9
 
| [[#PXI_CNT|PXI_CNT]]9
 
| 0x10008004
 
| 0x10008004
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| 4
+
| 2
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|
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| Boot9, Process9
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
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| 0x10163000
 
| 0x10163000
 
| 4
 
| 4
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|
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| Boot11
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
 
| [[#PXI_CNT|PXI_CNT]]11
 
| [[#PXI_CNT|PXI_CNT]]11
 
| 0x10163004
 
| 0x10163004
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| 4
+
| 2
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|
+
| Boot11
 
|-
 
|-
 
| style="background: green" | Yes
 
| style="background: green" | Yes
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| 0-7
 
| 0-7
 
| R
 
| R
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| Data received from remote
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| Data received from remote bits 8-15 (unrelated to SEND/RECV FIFOs)
 
|-
 
|-
 
| 8-15
 
| 8-15
 
| R/W
 
| R/W
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| Data sent to remote
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| Data sent to remote bits 0-7
 
|-
 
|-
 
| 23
 
| 23
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|-
 
|-
 
| 31
 
| 31
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| R/W
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| RW
 
| PXI_SYNC IRQ enable (for local processor)
 
| PXI_SYNC IRQ enable (for local processor)
 
|}
 
|}

Latest revision as of 01:56, 6 January 2017

Registers[edit]

Old3DS Name Address Width Used by
Yes PXI_SYNC9 0x10008000 4 Boot9, Process9
Yes PXI_CNT9 0x10008004 2 Boot9, Process9
Yes PXI_SEND9 0x10008008 4
Yes PXI_RECV9 0x1000800C 4
Yes PXI_SYNC11 0x10163000 4 Boot11
Yes PXI_CNT11 0x10163004 2 Boot11
Yes PXI_SEND11 0x10163008 4
Yes PXI_RECV11 0x1016300C 4

The PXI registers are similar to those on DS.

PXI_SYNC[edit]

Bit RW Description
0-7 R Data received from remote bits 8-15 (unrelated to SEND/RECV FIFOs)
8-15 R/W Data sent to remote bits 0-7
23 ? ?
29 W? Trigger PXI_SYNC11 IRQ (if enabled)
30 W? Trigger PXI_SYNC9 IRQ (if enabled)
31 RW PXI_SYNC IRQ enable (for local processor)

This can also be accessed as 4 u8 registers.

PXI_CNT[edit]

Bit RW Description
0 R Send Fifo Empty Status (0=Not Empty, 1=Empty)
1 R Send Fifo Full Status (0=Not Full, 1=Full)
2 R/W Send Fifo Empty IRQ (0=Disable, 1=Enable)
3 W Send Fifo Clear (0=Nothing, 1=Flush Send Fifo)
8 R Receive Fifo Empty (0=Not Empty, 1=Empty)
9 R Receive Fifo Full (0=Not Full, 1=Full)
10 R/W Receive Fifo Not Empty IRQ (0=Disable, 1=Enable)
14 R/W Error, Read Empty/Send Full (0=No Error, 1=Error/Acknowledge)
15 R/W Enable Send/Receive Fifo (0=Disable, 1=Enable)
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