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| == Interrupts == | | == Interrupts == |
| | | |
− | Interrupt priority is 0-0xF. A priority of 0xF means that the interrupt is masked. | + | Interrupt priority is 0-0xF. A priority of 0xF means that the interrupt is disabled. |
| | | |
| = Private Interrupts = | | = Private Interrupts = |
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| | 0x4 | | | 0x4 |
| | u8 | | | u8 |
− | | Interrupt will be masked by the IRQ handler as soon as it is acknowledged | + | | Interrupt will be disabled by the IRQ handler as soon as it is acknowledged. |
| + | Ignored for FIQ: the FIQ handler always sets bit2 of [[PDN_Registers#PDN_FIQ_CNT|PDN_FIQ_CNT]] |
| |- | | |- |
| | 0x5 | | | 0x5 |
| | u8 | | | u8 |
− | | Interrupt is masked | + | | Interrupt is disabled |
| |- | | |- |
| | 0x6 | | | 0x6 |