Difference between revisions of "SPI Registers"

From 3dbrew
Jump to navigation Jump to search
(This looks more sensible, feel free to proofread and correct)
(Let's play this a bit safer.)
Line 151: Line 151:
 
|-  
 
|-  
 
| 8-9
 
| 8-9
| Device Select      (0=Firmware, 1=Touchscreen, 2=Powerman., 3=???)
+
| Device Select      (available devices: firmware, touchscreen, powerman., but no idea about the value-device mapping)
 
|-
 
|-
 
| 10
 
| 10

Revision as of 19:09, 27 June 2016

Registers

Old3DS Name Address Width Used by
Yes SPI_CNT0 0x10142000 2
Yes SPI_DATA0 0x10142002 1
Yes SPI_NEW_CNT0 0x10142800 4
Yes SPI_NEW_DONE0 0x10142804 4
Yes SPI_NEW_BLKLEN0 0x10142808 4
Yes SPI_NEW_FIFO0 0x1014280C 4
Yes SPI_NEW_STATUS0 0x10142810 4
Yes SPI_CNT1 0x10143000 2
Yes SPI_DATA1 0x10143002 1
Yes SPI_NEW_CNT1 0x10143800 4
Yes SPI_NEW_DONE1 0x10143804 4
Yes SPI_NEW_BLKLEN1 0x10143808 4
Yes SPI_NEW_FIFO1 0x1014380C 4
Yes SPI_NEW_STATUS1 0x10143810 4
Yes SPI_CNT2 0x10160000 2
Yes SPI_DATA2 0x10160002 1
Yes SPI_NEW_CNT2 0x10160800 4
Yes SPI_NEW_DONE2 0x10160804 4
Yes SPI_NEW_BLKLEN2 0x10160808 4
Yes SPI_NEW_FIFO2 0x1016080C 4
Yes SPI_NEW_STATUS2 0x10160810 4

SPI_CNT

This is the old NDS/DSi SPI interface.

Bits Name
0-1 Baudrate (0=4MHz, 1=2MHz, 2=1MHz, 3=512KHz)
2-6 Not used (Zero)
7 Busy Flag (0=Ready, 1=Busy) (presumably Read-only)
8-9 Device Select (available devices: firmware, touchscreen, powerman., but no idea about the value-device mapping)
10 Transfer Size (0=8bit/Normal, 1=16bit/Bugged)
11 Chipselect Hold (0=Deselect after transfer, 1=Keep selected)
12-13 Not used (Zero)
14 Interrupt Request (0=Disable, 1=Enable)
15 SPI Bus Enable (0=Disable, 1=Enable)

SPI_NEW_CNT

This is an alternative faster interface introduced with the 3DS.

Bits Name
0-5 Baudrate?
6-7 Device Select
13 Transfer Direction? (0=Incoming, 1=Outgoing)
15 Busy/enable
Device id Device select bits
0, 3, >=6 0
1, 4 1
2, 5 2
Device id Used baudrate
3 5
0 2

SPI_NEW_DONE

When the transfer is finished, a 0 has to be written to this register.

SPI_NEW_BLKLEN

The number of bytes to be sent/read is written to this register.

SPI_NEW_FIFO

32-bit FIFO for reading/writing the SPI payload.

SPI_NEW_STATUS

Bit0: FIFO busy.