Difference between revisions of "GPU/Internal Registers"
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| − | | [[# | + | | [[#GPUREG_TEXUNIT1_ADDR|GPUREG_TEXUNIT1_ADDR]] |
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|PICA_REG_TEXTURE1_ADDR | |PICA_REG_TEXTURE1_ADDR | ||
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| − | | [[# | + | | [[#GPUREG_TEXUNIT2_ADDR|GPUREG_TEXUNIT2_ADDR]] |
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|PICA_REG_TEXTURE2_ADDR | |PICA_REG_TEXTURE2_ADDR | ||
Revision as of 05:58, 1 December 2015
(this page is hugely WIP)
Overview
GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.
Types
There are three main types of registers :
- configuration registers, which directly map to various rendering properties (for example : GPUREG_FACECULLING_CONFIG)
- data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example : GPUREG_GSH_CODETRANSFER_DATA)
- action triggering registers, which tell the GPU to do something, like draw a primitive (for example : GPUREG_DRAWARRAYS)
Aliases
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU Commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to GPUREG_VSH_FLOATUNIFORM_DATA so that a consecutively writing command based at 02C0 will write its first parameter to GPUREG_VSH_FLOATUNIFORM_CONFIG and ever subsequent ones to GPUREG_VSH_FLOATUNIFORM_DATA
Register list
Miscellaneous registers (0x000-0x03F)
Rasterizer registers (0x040-0x07F)
| Register ID | Register name | Notes | Official Name |
|---|---|---|---|
| 0040 | GPUREG_FACECULLING_CONFIG | PICA_REG_CULL_FACE | |
| 0041 | GPUREG_VIEWPORT_WIDTH | PICA_REG_VIEWPORT_WIDTH1 | |
| 0042 | GPUREG_VIEWPORT_INVW | PICA_REG_VIEWPORT_WIDTH2 | |
| 0043 | GPUREG_VIEWPORT_HEIGHT | PICA_REG_VIEWPORT_HEIGHT1 | |
| 0044 | GPUREG_VIEWPORT_INVH | PICA_REG_VIEWPORT_HEIGHT2 | |
| 0045 | GPUREG_0045 | ||
| 0046 | GPUREG_0046 | ||
| 0047 | GPUREG_FRAGOP_CLIP | ? | PICA_REG_FRAGOP_CLIP |
| 0048 | GPUREG_FRAGOP_CLIP_DATA1 | ? | PICA_REG_FRAGOP_CLIP_DATA1 |
| 0049 | GPUREG_FRAGOP_CLIP_DATA2 | ? | PICA_REG_FRAGOP_CLIP_DATA2 |
| 004A | GPUREG_FRAGOP_CLIP_DATA3 | ? | PICA_REG_FRAGOP_CLIP_DATA3 |
| 004B | GPUREG_FRAGOP_CLIP_DATA4 | ? | PICA_REG_FRAGOP_CLIP_DATA4 |
| 004C | GPUREG_004C | ||
| 004D | GPUREG_DEPTHMAP_SCALE | As f24 | PICA_REG_FRAGOP_WSCALE_DATA1 |
| 004E | GPUREG_DEPTHMAP_OFFSET | As f24 | PICA_REG_FRAGOP_WSCALE_DATA2 |
| 004F | GPUREG_SH_OUTMAP_TOTAL | PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0 | |
| 0050 | GPUREG_SH_OUTMAP_O0 | PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0 | |
| 0051 | GPUREG_SH_OUTMAP_O1 | PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1 | |
| 0052 | GPUREG_SH_OUTMAP_O2 | PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2 | |
| 0053 | GPUREG_SH_OUTMAP_O3 | PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3 | |
| 0054 | GPUREG_SH_OUTMAP_O4 | PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4 | |
| 0055 | GPUREG_SH_OUTMAP_O5 | PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5 | |
| 0056 | GPUREG_SH_OUTMAP_O6 | PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6 | |
| 0057 | GPUREG_0057 | ||
| 0058 | GPUREG_0058 | ||
| 0059 | GPUREG_0059 | ||
| 005A | GPUREG_005A | ||
| 005B | GPUREG_005B | ||
| 005C | GPUREG_005C | ||
| 005D | GPUREG_005D | ||
| 005E | GPUREG_005E | ||
| 005F | GPUREG_005F | ||
| 0060 | GPUREG_0060 | ||
| 0061 | GPUREG_EARLY_DEPTH_FUNC | ? | PICA_REG_EARLY_DEPTH_FUNC |
| 0062 | GPUREG_EARLY_DEPTH_TEST1 | ? | PICA_REG_EARLY_DEPTH_TEST1 |
| 0063 | GPUREG_EARLY_DEPTH_CLEAR | PICA_REG_EARLY_DEPTH_CLEAR | |
| 0064 | GPUREG_SH_OUT_ATTR_MODE | ? | PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE |
| 0065 | GPUREG_SCISSORTEST_MODE | PICA_REG_SCISSOR | |
| 0066 | GPUREG_SCISSORTEST_POS | PICA_REG_SCISSOR_XY | |
| 0067 | GPUREG_SCISSORTEST_DIM | PICA_REG_SCISSOR_SIZE | |
| 0068 | GPUREG_VIEWPORT_XY | PICA_REG_VIEWPORT_XY | |
| 0069 | GPUREG_0069 | ||
| 006A | GPUREG_EARLY_DEPTH_DATA | PICA_REG_EARLY_DEPTH_DATA | |
| 006B | GPUREG_006B | ||
| 006C | GPUREG_006C | ||
| 006D | GPUREG_FRAGOP_WSCALE | ? | PICA_REG_FRAGOP_WSCALE |
| 006E | GPUREG_RENDER_BUF_RESOLUTION1 | ? | PICA_REG_RENDER_BUF_RESOLUTION1 |
| 006F | GPUREG_SH_OUT_ATTR_CLK | ? | PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK |
| 0070 | GPUREG_0070 | ||
| 0071 | GPUREG_0071 | ||
| 0072 | GPUREG_0072 | ||
| 0073 | GPUREG_0073 | ||
| 0074 | GPUREG_0074 | ||
| 0075 | GPUREG_0075 | ||
| 0076 | GPUREG_0076 | ||
| 0077 | GPUREG_0077 | ||
| 0078 | GPUREG_0078 | ||
| 0079 | GPUREG_0079 | ||
| 007A | GPUREG_007A | ||
| 007B | GPUREG_007B | ||
| 007C | GPUREG_007C | ||
| 007D | GPUREG_007D | ||
| 007E | GPUREG_007E | ||
| 007F | GPUREG_007F |
Texturing registers (0x080-0x0FF)
| Register ID | Register name | Notes | Official Name |
|---|---|---|---|
| 0080 | GPUREG_TEXTURE_FUNC | PICA_REG_TEXTURE_FUNC | |
| 0081 | GPUREG_TEXUNIT0_BORDER_COLOR | PICA_REG_TEXTURE0_BORDER_COLOR | |
| 0082 | GPUREG_TEXUNIT0_DIM | PICA_REG_TEXTURE0_SIZE | |
| 0083 | GPUREG_TEXUNIT0_PARAM | PICA_REG_TEXTURE0_WRAP_FILTER | |
| 0084 | GPUREG_TEXUNIT0_LOD | ? | PICA_REG_TEXTURE0_LOD |
| 0085 | GPUREG_TEXUNIT0_ADDR1 | PICA_REG_TEXTURE0_ADDR1 | |
| 0086 | GPUREG_TEXUNIT0_ADDR2 | PICA_REG_TEXTURE0_ADDR2 | |
| 0087 | GPUREG_TEXUNIT0_ADDR3 | PICA_REG_TEXTURE0_ADDR3 | |
| 0088 | GPUREG_TEXUNIT0_ADDR4 | PICA_REG_TEXTURE0_ADDR4 | |
| 0089 | GPUREG_TEXUNIT0_ADDR5 | PICA_REG_TEXTURE0_ADDR5 | |
| 008A | GPUREG_TEXUNIT0_ADDR6 | PICA_REG_TEXTURE0_ADDR6 | |
| 008B | GPUREG_TEXUNIT0_SHADOW | ? | PICA_REG_TEXTURE0_SHADOW |
| 008C | GPUREG_008C | ||
| 008D | GPUREG_008D | ||
| 008E | GPUREG_TEXUNIT0_TYPE | ? | PICA_REG_TEXTURE0_FORMAT |
| 008F | GPUREG_LIGHTING_ENABLE0 | ? | PICA_REG_FRAG_LIGHT_EN0 |
| 0090 | GPUREG_0090 | ||
| 0091 | GPUREG_TEXUNIT1_BORDER_COLOR | PICA_REG_TEXTURE1_BORDER_COLOR | |
| 0092 | GPUREG_TEXUNIT1_DIM | PICA_REG_TEXTURE1_SIZE | |
| 0093 | GPUREG_TEXUNIT1_PARAM | PICA_REG_TEXTURE1_WRAP_FILTER | |
| 0094 | GPUREG_TEXUNIT1_LOD | ? | PICA_REG_TEXTURE1_LOD |
| 0095 | GPUREG_TEXUNIT1_ADDR | PICA_REG_TEXTURE1_ADDR | |
| 0096 | GPUREG_TEXUNIT1_TYPE | PICA_REG_TEXTURE1_FORMAT | |
| 0097 | GPUREG_0097 | ||
| 0098 | GPUREG_0098 | ||
| 0099 | GPUREG_TEXUNIT2_BORDER_COLOR | PICA_REG_TEXTURE2_BORDER_COLOR | |
| 009A | GPUREG_TEXUNIT2_DIM | PICA_REG_TEXTURE2_SIZE | |
| 009B | GPUREG_TEXUNIT2_PARAM | PICA_REG_TEXTURE2_WRAP_FILTER | |
| 009C | GPUREG_TEXUNIT2_LOD | ? | PICA_REG_TEXTURE2_LOD |
| 009D | GPUREG_TEXUNIT2_ADDR | PICA_REG_TEXTURE2_ADDR | |
| 009E | GPUREG_TEXUNIT2_TYPE | PICA_REG_TEXTURE2_FORMAT | |
| 009F | GPUREG_009F | ||
| 00A0 | GPUREG_00A0 | ||
| 00A1 | GPUREG_00A1 | ||
| 00A2 | GPUREG_00A2 | ||
| 00A3 | GPUREG_00A3 | ||
| 00A4 | GPUREG_00A4 | ||
| 00A5 | GPUREG_00A5 | ||
| 00A6 | GPUREG_00A6 | ||
| 00A7 | GPUREG_00A7 | ||
| 00A8 | GPUREG_TEXUNIT3_PROTEX0 | ? | PICA_REG_TEXTURE3_PROTEX0 |
| 00A9 | GPUREG_TEXUNIT3_PROTEX1 | ? | PICA_REG_TEXTURE3_PROTEX1 |
| 00AA | GPUREG_TEXUNIT3_PROTEX2 | ? | PICA_REG_TEXTURE3_PROTEX2 |
| 00AB | GPUREG_TEXUNIT3_PROTEX3 | ? | PICA_REG_TEXTURE3_PROTEX3 |
| 00AC | GPUREG_TEXUNIT3_PROTEX4 | ? | PICA_REG_TEXTURE3_PROTEX4 |
| 00AD | GPUREG_TEXUNIT3_PROTEX5 | ? | PICA_REG_TEXTURE3_PROTEX5 |
| 00AE | GPUREG_00AE | ||
| 00AF | GPUREG_PROTEX_LUT | ? | PICA_REG_PROTEX_LUT |
| 00B0 | GPUREG_PROTEX_LUT_DATA0 | ? | PICA_REG_PROTEX_LUT_DATA0 |
| 00B1 | GPUREG_PROTEX_LUT_DATA1 | ? | PICA_REG_PROTEX_LUT_DATA1 |
| 00B2 | GPUREG_PROTEX_LUT_DATA2 | ? | PICA_REG_PROTEX_LUT_DATA2 |
| 00B3 | GPUREG_PROTEX_LUT_DATA3 | ? | PICA_REG_PROTEX_LUT_DATA3 |
| 00B4 | GPUREG_PROTEX_LUT_DATA4 | ? | PICA_REG_PROTEX_LUT_DATA4 |
| 00B5 | GPUREG_PROTEX_LUT_DATA5 | ? | PICA_REG_PROTEX_LUT_DATA5 |
| 00B6 | GPUREG_PROTEX_LUT_DATA6 | ? | PICA_REG_PROTEX_LUT_DATA6 |
| 00B7 | GPUREG_PROTEX_LUT_DATA7 | ? | PICA_REG_PROTEX_LUT_DATA7 |
| 00B8 | GPUREG_00B8 | ||
| 00B9 | GPUREG_00B9 | ||
| 00BA | GPUREG_00BA | ||
| 00BB | GPUREG_00BB | ||
| 00BC | GPUREG_00BC | ||
| 00BD | GPUREG_00BD | ||
| 00BE | GPUREG_00BE | ||
| 00BF | GPUREG_00BF | ||
| 00C0 | GPUREG_TEXENV0_SOURCE | PICA_REG_TEX_ENV_0 | |
| 00C1 | GPUREG_TEXENV0_OPERAND | PICA_REG_TEX_ENV_0_OPERAND | |
| 00C2 | GPUREG_TEXENV0_COMBINER | PICA_REG_TEX_ENV_0_COMBINE | |
| 00C3 | GPUREG_TEXENV0_COLOR | PICA_REG_TEX_ENV_0_COLOR | |
| 00C4 | GPUREG_TEXENV0_SCALE | PICA_REG_TEX_ENV_0_SCALE | |
| 00C5 | GPUREG_00C5 | ||
| 00C6 | GPUREG_00C6 | ||
| 00C7 | GPUREG_00C7 | ||
| 00C8 | GPUREG_TEXENV1_SOURCE | PICA_REG_TEX_ENV_1 | |
| 00C9 | GPUREG_TEXENV1_OPERAND | PICA_REG_TEX_ENV_1_OPERAND | |
| 00CA | GPUREG_TEXENV1_COMBINER | PICA_REG_TEX_ENV_1_COMBINE | |
| 00CB | GPUREG_TEXENV1_COLOR | PICA_REG_TEX_ENV_1_COLOR | |
| 00CC | GPUREG_TEXENV1_SCALE | PICA_REG_TEX_ENV_1_SCALE | |
| 00CD | GPUREG_00CD | ||
| 00CE | GPUREG_00CE | ||
| 00CF | GPUREG_00CF | ||
| 00D0 | GPUREG_TEXENV2_SOURCE | PICA_REG_TEX_ENV_2 | |
| 00D1 | GPUREG_TEXENV2_OPERAND | PICA_REG_TEX_ENV_2_OPERAND | |
| 00D2 | GPUREG_TEXENV2_COMBINER | PICA_REG_TEX_ENV_2_COMBINE | |
| 00D3 | GPUREG_TEXENV2_COLOR | PICA_REG_TEX_ENV_2_COLOR | |
| 00D4 | GPUREG_TEXENV2_SCALE | PICA_REG_TEX_ENV_2_SCALE | |
| 00D5 | GPUREG_00D5 | ||
| 00D6 | GPUREG_00D6 | ||
| 00D7 | GPUREG_00D7 | ||
| 00D8 | GPUREG_TEXENV3_SOURCE | PICA_REG_TEX_ENV_3 | |
| 00D9 | GPUREG_TEXENV3_OPERAND | PICA_REG_TEX_ENV_3_OPERAND | |
| 00DA | GPUREG_TEXENV3_COMBINER | PICA_REG_TEX_ENV_3_COMBINE | |
| 00DB | GPUREG_TEXENV3_COLOR | PICA_REG_TEX_ENV_3_COLOR | |
| 00DC | GPUREG_TEXENV3_SCALE | PICA_REG_TEX_ENV_3_SCALE | |
| 00DD | GPUREG_00DD | ||
| 00DE | GPUREG_00DE | ||
| 00DF | GPUREG_00DF | ||
| 00E0 | GPUREG_TEXENV_UPDATE_BUFFER | ? | PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT |
| 00E1 | GPUREG_FOG_COLOR | ? | PICA_REG_FOG_COLOR |
| 00E2 | GPUREG_00E2 | ||
| 00E3 | GPUREG_00E3 | ||
| 00E4 | GPUREG_GAS_ATTENUATION | ? | PICA_REG_GAS_ATTENUATION |
| 00E5 | GPUREG_GAS_ACCMAX | ? | PICA_REG_GAS_ACCMAX |
| 00E6 | GPUREG_FOG_LUT_INDEX | ? | PICA_REG_FOG_LUT_INDEX |
| 00E7 | GPUREG_00E7 | ||
| 00E8 | GPUREG_FOG_LUT_DATA0 | ? | PICA_REG_FOG_LUT_DATA0 |
| 00E9 | GPUREG_FOG_LUT_DATA1 | ? | PICA_REG_FOG_LUT_DATA1 |
| 00EA | GPUREG_FOG_LUT_DATA2 | ? | PICA_REG_FOG_LUT_DATA2 |
| 00EB | GPUREG_FOG_LUT_DATA3 | ? | PICA_REG_FOG_LUT_DATA3 |
| 00EC | GPUREG_FOG_LUT_DATA4 | ? | PICA_REG_FOG_LUT_DATA4 |
| 00ED | GPUREG_FOG_LUT_DATA5 | ? | PICA_REG_FOG_LUT_DATA5 |
| 00EE | GPUREG_FOG_LUT_DATA6 | ? | PICA_REG_FOG_LUT_DATA6 |
| 00EF | GPUREG_FOG_LUT_DATA7 | ? | PICA_REG_FOG_LUT_DATA7 |
| 00F0 | GPUREG_TEXENV4_SOURCE | PICA_REG_TEX_ENV_4 | |
| 00F1 | GPUREG_TEXENV4_OPERAND | PICA_REG_TEX_ENV_4_OPERAND | |
| 00F2 | GPUREG_TEXENV4_COMBINER | PICA_REG_TEX_ENV_4_COMBINE | |
| 00F3 | GPUREG_TEXENV4_COLOR | PICA_REG_TEX_ENV_4_COLOR | |
| 00F4 | GPUREG_TEXENV4_SCALE | PICA_REG_TEX_ENV_4_SCALE | |
| 00F5 | GPUREG_00F5 | ||
| 00F6 | GPUREG_00F6 | ||
| 00F7 | GPUREG_00F7 | ||
| 00F8 | GPUREG_TEXENV5_SOURCE | PICA_REG_TEX_ENV_5 | |
| 00F9 | GPUREG_TEXENV5_OPERAND | PICA_REG_TEX_ENV_5_OPERAND | |
| 00FA | GPUREG_TEXENV5_COMBINER | PICA_REG_TEX_ENV_5_COMBINE | |
| 00FB | GPUREG_TEXENV5_COLOR | PICA_REG_TEX_ENV_5_COLOR | |
| 00FC | GPUREG_TEXENV5_SCALE | PICA_REG_TEX_ENV_5_SCALE | |
| 00FD | GPUREG_TEXENV_BUFFER_COLOR | ? | PICA_REG_TEX_ENV_BUF_COLOR |
| 00FE | GPUREG_00FE | ||
| 00FF | GPUREG_00FF |
Framebuffer registers (0x100-0x13F)
| Register ID | Register name | Notes | Official Name |
|---|---|---|---|
| 0100 | GPUREG_BLEND_ENABLE | PICA_REG_COLOR_OPERATION | |
| 0101 | GPUREG_BLEND_CONFIG | PICA_REG_BLEND_FUNC | |
| 0102 | GPUREG_LOGICOP_CONFIG | PICA_REG_LOGIC_OP | |
| 0103 | GPUREG_BLEND_COLOR | PICA_REG_BLEND_COLOR | |
| 0104 | GPUREG_ALPHATEST_CONFIG | PICA_REG_FRAGOP_ALPHA_TEST | |
| 0105 | GPUREG_STENCIL_TEST | PICA_REG_STENCIL_TEST | |
| 0106 | GPUREG_STENCIL_ACTION | PICA_REG_STENCIL_OP | |
| 0107 | GPUREG_DEPTHTEST_CONFIG | PICA_REG_DEPTH_COLOR_MASK | |
| 0108 | GPUREG_0108 | ||
| 0109 | GPUREG_0109 | ||
| 010A | GPUREG_010A | ||
| 010B | GPUREG_010B | ||
| 010C | GPUREG_010C | ||
| 010D | GPUREG_010D | ||
| 010E | GPUREG_010E | ||
| 010F | GPUREG_010F | ||
| 0110 | GPUREG_FRAMEBUFFER_INVALIDATE | PICA_REG_COLOR_BUFFER_CLEAR0 | |
| 0111 | GPUREG_FRAMEBUFFER_FLUSH | PICA_REG_COLOR_BUFFER_CLEAR1 | |
| 0112 | GPUREG_COLORBUFFER_READ | PICA_REG_COLOR_BUFFER_READ | |
| 0113 | GPUREG_COLORBUFFER_WRITE | PICA_REG_COLOR_BUFFER_WRITE | |
| 0114 | GPUREG_DEPTHBUFFER_READ | PICA_REG_DEPTH_STENCIL_READ | |
| 0115 | GPUREG_DEPTHBUFFER_WRITE | PICA_REG_DEPTH_STENCIL_WRITE | |
| 0116 | GPUREG_DEPTHBUFFER_FORMAT | PICA_REG_RENDER_BUF_DEPTH_MODE | |
| 0117 | GPUREG_COLORBUFFER_FORMAT | PICA_REG_RENDER_BUF_COLOR_MODE | |
| 0118 | GPUREG_EARLY_DEPTH_TEST2 | ? | PICA_REG_EARLY_DEPTH_TEST2 |
| 0119 | GPUREG_0119 | ||
| 011A | GPUREG_011A | ||
| 011B | GPUREG_FRAMEBUFFER_BLOCK32 | PICA_REG_RENDER_BLOCK_FORMAT | |
| 011C | GPUREG_DEPTHBUFFER_LOC | PICA_REG_RENDER_BUF_DEPTH_ADDR | |
| 011D | GPUREG_COLORBUFFER_LOC | PICA_REG_RENDER_BUF_COLOR_ADDR | |
| 011E | GPUREG_FRAMEBUFFER_DIM | PICA_REG_RENDER_BUF_RESOLUTION0 | |
| 011F | GPUREG_011F | ||
| 0120 | GPUREGGAS_LIGHT_XY | ? | PICA_REG_GAS_LIGHT_XY |
| 0121 | GPUREG_GAS_LIGHT_Z | ? | PICA_REG_GAS_LIGHT_Z |
| 0122 | GPUREG_GAS_LIGHT_Z_COLOR | ? | PICA_REG_GAS_LIGHT_Z_COLOR |
| 0123 | GPUREG_GAS_LUT_INDEX | ? | PICA_REG_GAS_LUT_INDEX |
| 0124 | GPUREG_GAS_LUT_DATA | ? | PICA_REG_GAS_LUT_DATA |
| 0125 | GPUREG_0125 | ||
| 0126 | GPUREG_GAS_DELTAZ_DEPTH | ? | PICA_REG_GAS_DELTAZ_DEPTH |
| 0127 | GPUREG_0127 | ||
| 0128 | GPUREG_0128 | ||
| 0129 | GPUREG_0129 | ||
| 012A | GPUREG_012A | ||
| 012B | GPUREG_012B | ||
| 012C | GPUREG_012C | ||
| 012D | GPUREG_012D | ||
| 012E | GPUREG_012E | ||
| 012F | GPUREG_012F | ||
| 0130 | GPUREG_FRAGOP_SHADOW | ? | PICA_REG_FRAGOP_SHADOW |
| 0131 | GPUREG_0131 | ||
| 0132 | GPUREG_0132 | ||
| 0133 | GPUREG_0133 | ||
| 0134 | GPUREG_0134 | ||
| 0135 | GPUREG_0135 | ||
| 0136 | GPUREG_0136 | ||
| 0137 | GPUREG_0137 | ||
| 0138 | GPUREG_0138 | ||
| 0139 | GPUREG_0139 | ||
| 013A | GPUREG_013A | ||
| 013B | GPUREG_013B | ||
| 013C | GPUREG_013C | ||
| 013D | GPUREG_013D | ||
| 013E | GPUREG_013E | ||
| 013F | GPUREG_013F |
Fragment lighting registers (0x140-0x1FF)
| Register ID | Register name | Notes | Official Name |
|---|---|---|---|
| 0140 | GPUREG_LIGHT0_SPECULAR0 | ? | PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START |
| 0141 | GPUREG_LIGHT0_SPECULAR1 | ? | PICA_REG_FRAG_LIGHT0_SPECULAR1 |
| 0142 | GPUREG_LIGHT0_DIFFUSE | ? | PICA_REG_FRAG_LIGHT0_DIFFUSE |
| 0143 | GPUREG_LIGHT0_AMBIENT | ? | PICA_REG_FRAG_LIGHT0_AMBIENT |
| 0144 | GPUREG_LIGHT0_XY | ? | PICA_REG_FRAG_LIGHT0_POSITION_XY |
| 0145 | GPUREG_LIGHT0_Z | ? | PICA_REG_FRAG_LIGHT0_POSITION_Z |
| 0146 | GPUREG_LIGHT0_SPOTDIR_XY | ? | PICA_REG_FRAG_LIGHT0_SPOT_XY |
| 0147 | GPUREG_LIGHT0_SPOTDIR_Z | ? | PICA_REG_FRAG_LIGHT0_SPOT_Z |
| 0148 | GPUREG_0148 | ||
| 0149 | GPUREG_LIGHT0_CONFIG | PICA_REG_FRAG_LIGHT0_TYPE | |
| 014A | GPUREG_LIGHT0_ATTENUATION_BIAS | ? | PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS |
| 014B | GPUREG_LIGHT0_ATTENUATION_SCALE | ? | PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE |
| 014C | GPUREG_014C | ||
| 014D | GPUREG_014D | ||
| 014E | GPUREG_014E | ||
| 014F | GPUREG_014F | ||
| 0150 | GPUREG_LIGHT1_SPECULAR0 | ? | PICA_REG_FRAG_LIGHT1_SPECULAR0 |
| 0151 | GPUREG_LIGHT1_SPECULAR1 | ? | PICA_REG_FRAG_LIGHT1_SPECULAR1 |
| 0152 | GPUREG_LIGHT1_DIFFUSE | ? | PICA_REG_FRAG_LIGHT1_DIFFUSE |
| 0153 | GPUREG_LIGHT1_AMBIENT | ? | PICA_REG_FRAG_LIGHT1_AMBIENT |
| 0154 | GPUREG_LIGHT1_XY | ? | PICA_REG_FRAG_LIGHT1_POSITION_XY |
| 0155 | GPUREG_LIGHT1_Z | ? | PICA_REG_FRAG_LIGHT1_POSITION_Z |
| 0156 | GPUREG_LIGHT1_SPOTDIR_XY | ? | PICA_REG_FRAG_LIGHT1_SPOT_XY |
| 0157 | GPUREG_LIGHT1_SPOTDIR_Z | ? | PICA_REG_FRAG_LIGHT1_SPOT_Z |
| 0158 | GPUREG_0158 | ||
| 0159 | GPUREG_LIGHT1_CONFIG | ? | PICA_REG_FRAG_LIGHT1_TYPE |
| 015A | GPUREG_LIGHT1_ATTENUATION_BIAS | ? | PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS |
| 015B | GPUREG_LIGHT1_ATTENUATION_SCALE | ? | PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE |
| 015C | GPUREG_015C | ||
| 015D | GPUREG_015D | ||
| 015E | GPUREG_015E | ||
| 015F | GPUREG_015F | ||
| 0160 | GPUREG_LIGHT2_SPECULAR0 | ? | PICA_REG_FRAG_LIGHT2_SPECULAR0 |
| 0161 | GPUREG_LIGHT2_SPECULAR1 | ? | PICA_REG_FRAG_LIGHT2_SPECULAR1 |
| 0162 | GPUREG_LIGHT2_DIFFUSE | ? | PICA_REG_FRAG_LIGHT2_DIFFUSE |
| 0163 | GPUREG_LIGHT2_AMBIENT | ? | PICA_REG_FRAG_LIGHT2_AMBIENT |
| 0164 | GPUREG_LIGHT2_XY | ? | PICA_REG_FRAG_LIGHT2_POSITION_XY |
| 0165 | GPUREG_LIGHT2_Z | ? | PICA_REG_FRAG_LIGHT2_POSITION_Z |
| 0166 | GPUREG_LIGHT2_SPOTDIR_XY | ? | PICA_REG_FRAG_LIGHT2_SPOT_XY |
| 0167 | GPUREG_LIGHT2_SPOTDIR_Z | ? | PICA_REG_FRAG_LIGHT2_SPOT_Z |
| 0168 | GPUREG_0168 | ||
| 0169 | GPUREG_LIGHT2_CONFIG | ? | PICA_REG_FRAG_LIGHT2_TYPE |
| 016A | GPUREG_LIGHT2_ATTENUATION_BIAS | ? | PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS |
| 016B | GPUREG_LIGHT2_ATTENUATION_SCALE | ? | PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE |
| 016C | GPUREG_016C | ||
| 016D | GPUREG_016D | ||
| 016E | GPUREG_016E | ||
| 016F | GPUREG_016F | ||
| 0170 | GPUREG_LIGHT3_SPECULAR0 | ? | PICA_REG_FRAG_LIGHT3_SPECULAR0 |
| 0171 | GPUREG_LIGHT3_SPECULAR1 | ? | PICA_REG_FRAG_LIGHT3_SPECULAR1 |
| 0172 | GPUREG_LIGHT3_DIFFUSE | ? | PICA_REG_FRAG_LIGHT3_DIFFUSE |
| 0173 | GPUREG_LIGHT3_AMBIENT | ? | PICA_REG_FRAG_LIGHT3_AMBIENT |
| 0174 | GPUREG_LIGHT3_XY | ? | PICA_REG_FRAG_LIGHT3_POSITION_XY |
| 0175 | GPUREG_LIGHT3_Z | ? | PICA_REG_FRAG_LIGHT3_POSITION_Z |
| 0176 | GPUREG_LIGHT3_SPOTDIR_XY | ? | PICA_REG_FRAG_LIGHT3_SPOT_XY |
| 0177 | GPUREG_LIGHT3_SPOTDIR_Z | ? | PICA_REG_FRAG_LIGHT3_SPOT_Z |
| 0178 | GPUREG_0178 | ||
| 0179 | GPUREG_LIGHT3_CONFIG | ? | PICA_REG_FRAG_LIGHT3_TYPE |
| 017A | GPUREG_LIGHT3_ATTENUATION_BIAS | ? | PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS |
| 017B | GPUREG_LIGHT3_ATTENUATION_SCALE | ? | PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE |
| 017C | GPUREG_017C | ||
| 017D | GPUREG_017D | ||
| 017E | GPUREG_017E | ||
| 017F | GPUREG_017F | ||
| 0180 | GPUREG_LIGHT4_SPECULAR0 | ? | PICA_REG_FRAG_LIGHT4_SPECULAR0 |
| 0181 | GPUREG_LIGHT4_SPECULAR1 | ? | PICA_REG_FRAG_LIGHT4_SPECULAR1 |
| 0182 | GPUREG_LIGHT4_DIFFUSE | ? | PICA_REG_FRAG_LIGHT4_DIFFUSE |
| 0183 | GPUREG_LIGHT4_AMBIENT | ? | PICA_REG_FRAG_LIGHT4_AMBIENT |
| 0184 | GPUREG_LIGHT4_XY | ? | PICA_REG_FRAG_LIGHT4_POSITION_XY |
| 0185 | GPUREG_LIGHT4_Z | ? | PICA_REG_FRAG_LIGHT4_POSITION_Z |
| 0186 | GPUREG_LIGHT4_SPOTDIR_XY | ? | PICA_REG_FRAG_LIGHT4_SPOT_XY |
| 0187 | GPUREG_LIGHT4_SPOTDIR_Z | ? | PICA_REG_FRAG_LIGHT4_SPOT_Z |
| 0188 | GPUREG_0188 | ||
| 0189 | GPUREG_LIGHT4_CONFIG | ? | PICA_REG_FRAG_LIGHT4_TYPE |
| 018A | GPUREG_LIGHT4_ATTENUATION_BIAS | ? | PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS |
| 018B | GPUREG_LIGHT4_ATTENUATION_SCALE | ? | PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE |
| 018C | GPUREG_018C | ||
| 018D | GPUREG_018D | ||
| 018E | GPUREG_018E | ||
| 018F | GPUREG_018F | ||
| 0190 | GPUREG_LIGHT5_SPECULAR0 | ? | PICA_REG_FRAG_LIGHT5_SPECULAR0 |
| 0191 | GPUREG_LIGHT5_SPECULAR1 | ? | PICA_REG_FRAG_LIGHT5_SPECULAR1 |
| 0192 | GPUREG_LIGHT5_DIFFUSE | ? | PICA_REG_FRAG_LIGHT5_DIFFUSE |
| 0193 | GPUREG_LIGHT5_AMBIENT | ? | PICA_REG_FRAG_LIGHT5_AMBIENT |
| 0194 | GPUREG_LIGHT5_XY | ? | PICA_REG_FRAG_LIGHT5_POSITION_XY |
| 0195 | GPUREG_LIGHT5_Z | ? | PICA_REG_FRAG_LIGHT5_POSITION_Z |
| 0196 | GPUREG_LIGHT5_SPOTDIR_XY | ? | PICA_REG_FRAG_LIGHT5_SPOT_XY |
| 0197 | GPUREG_LIGHT5_SPOTDIR_Z | ? | PICA_REG_FRAG_LIGHT5_SPOT_Z |
| 0198 | GPUREG_0198 | ||
| 0199 | GPUREG_LIGHT5_CONFIG | ? | PICA_REG_FRAG_LIGHT5_TYPE |
| 019A | GPUREG_LIGHT5_ATTENUATION_BIAS | PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS | |
| 019B | GPUREG_LIGHT5_ATTENUATION_SCALE | PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE | |
| 019C | GPUREG_019C | ||
| 019D | GPUREG_019D | ||
| 019E | GPUREG_019E | ||
| 019F | GPUREG_019F | ||
| 01A0 | GPUREG_LIGHT6_SPECULAR0 | ? | PICA_REG_FRAG_LIGHT6_SPECULAR0 |
| 01A1 | GPUREG_LIGHT6_SPECULAR1 | ? | PICA_REG_FRAG_LIGHT6_SPECULAR1 |
| 01A2 | GPUREG_LIGHT6_DIFFUSE | PICA_REG_FRAG_LIGHT6_DIFFUSE | |
| 01A3 | GPUREG_LIGHT6_AMBIENT | PICA_REG_FRAG_LIGHT6_AMBIENT | |
| 01A4 | GPUREG_LIGHT6_XY | PICA_REG_FRAG_LIGHT6_POSITION_XY | |
| 01A5 | GPUREG_LIGHT6_Z | PICA_REG_FRAG_LIGHT6_POSITION_Z | |
| 01A6 | GPUREG_LIGHT6_SPOTDIR_XY | ? | PICA_REG_FRAG_LIGHT6_SPOT_XY |
| 01A7 | GPUREG_LIGHT6_SPOTDIR_Z | ? | PICA_REG_FRAG_LIGHT6_SPOT_Z |
| 01A8 | GPUREG_01A8 | ||
| 01A9 | GPUREG_LIGHT6_CONFIG | ? | PICA_REG_FRAG_LIGHT6_TYPE |
| 01AA | GPUREG_LIGHT6_ATTENUATION_BIAS | PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS | |
| 01AB | GPUREG_LIGHT6_ATTENUATION_SCALE | PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE | |
| 01AC | GPUREG_01AC | ||
| 01AD | GPUREG_01AD | ||
| 01AE | GPUREG_01AE | ||
| 01AF | GPUREG_01AF | ||
| 01B0 | GPUREG_LIGHT7_SPECULAR0 | ? | PICA_REG_FRAG_LIGHT7_SPECULAR0 |
| 01B1 | GPUREG_LIGHT7_SPECULAR1 | ? | PICA_REG_FRAG_LIGHT7_SPECULAR1 |
| 01B2 | GPUREG_LIGHT7_DIFFUSE | ? | PICA_REG_FRAG_LIGHT7_DIFFUSE |
| 01B3 | GPUREG_LIGHT7_AMBIENT | ? | PICA_REG_FRAG_LIGHT7_AMBIENT |
| 01B4 | GPUREG_LIGHT7_XY | ? | PICA_REG_FRAG_LIGHT7_POSITION_XY |
| 01B5 | GPUREG_LIGHT7_Z | ? | PICA_REG_FRAG_LIGHT7_POSITION_Z |
| 01B6 | GPUREG_LIGHT7_SPOTDIR_XY | ? | PICA_REG_FRAG_LIGHT7_SPOT_XY |
| 01B7 | GPUREG_LIGHT7_SPOTDIR_Z | ? | PICA_REG_FRAG_LIGHT7_SPOT_Z |
| 01B8 | GPUREG_01B8 | ||
| 01B9 | GPUREG_LIGHT7_CONFIG | ? | PICA_REG_FRAG_LIGHT7_TYPE |
| 01BA | GPUREG_LIGHT7_ATTENUATION_BIAS | PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS | |
| 01BB | GPUREG_LIGHT7_ATTENUATION_SCALE | PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE | |
| 01BC | GPUREG_01BC | ||
| 01BD | GPUREG_01BD | ||
| 01BE | GPUREG_01BE | ||
| 01BF | GPUREG_01BF | ||
| 01C0 | GPUREG_LIGHTING_AMBIENT | ? | PICA_REG_FRAG_LIGHT_AMBIENT |
| 01C1 | GPUREG_01C1 | ||
| 01C2 | GPUREG_LIGHTING_NUM_LIGHTS | ? | PICA_REG_FRAG_LIGHT_SRC_NUM |
| 01C3 | GPUREG_LIGHTING_CONFIG0 | ? | PICA_REG_FRAG_LIGHT_FUNC_MODE0 |
| 01C4 | GPUREG_LIGHTING_CONFIG1 | ? | PICA_REG_FRAG_LIGHT_FUNC_MODE1 |
| 01C5 | GPUREG_LIGHTING_LUT_INDEX | ? | PICA_REG_FRAG_LIGHT_LUT |
| 01C6 | GPUREG_LIGHTING_ENABLE1 | ? | PICA_REG_FRAG_LIGHT_EN1 |
| 01C7 | GPUREG_01C7 | ||
| 01C8 | GPUREG_LIGHTING_LUT_DATA | ? | PICA_REG_FRAG_LIGHT_LUT_DATA0 |
| 01C9 | GPUREG_LIGHTING_LUT_DATA | ? | PICA_REG_FRAG_LIGHT_LUT_DATA1 |
| 01CA | GPUREG_LIGHTING_LUT_DATA | ? | PICA_REG_FRAG_LIGHT_LUT_DATA2 |
| 01CB | GPUREG_LIGHTING_LUT_DATA | ? | PICA_REG_FRAG_LIGHT_LUT_DATA3 |
| 01CC | GPUREG_LIGHTING_LUT_DATA | ? | PICA_REG_FRAG_LIGHT_LUT_DATA4 |
| 01CD | GPUREG_LIGHTING_LUT_DATA | ? | PICA_REG_FRAG_LIGHT_LUT_DATA5 |
| 01CE | GPUREG_LIGHTING_LUT_DATA | ? | PICA_REG_FRAG_LIGHT_LUT_DATA6 |
| 01CF | GPUREG_LIGHTING_LUT_DATA | ? | PICA_REG_FRAG_LIGHT_LUT_DATA7 |
| 01D0 | GPUREG_LIGHTING_LUTINPUT_ABS | ? | PICA_REG_FRAG_LIGHT_ABSLUTINPUT |
| 01D1 | GPUREG_LIGHTING_LUTINPUT_SELECT | ? | PICA_REG_FRAG_LIGHT_LUTINPUT |
| 01D2 | GPUREG_LIGHTING_LUTINPUT_SCALE | ? | PICA_REG_FRAG_LIGHT_LUTSCALE |
| 01D3 | GPUREG_01D3 | ||
| 01D4 | GPUREG_01D4 | ||
| 01D5 | GPUREG_01D5 | ||
| 01D6 | GPUREG_01D6 | ||
| 01D7 | GPUREG_01D7 | ||
| 01D8 | GPUREG_01D8 | ||
| 01D9 | GPUREG_LIGHTING_LIGHT_PERMUTATION | ? | PICA_REG_FRAG_LIGHT_SRC_EN_ID |
| 01DA | GPUREG_01DA | ||
| 01DB | GPUREG_01DB | ||
| 01DC | GPUREG_01DC | ||
| 01DD | GPUREG_01DD | ||
| 01DE | GPUREG_01DE | ||
| 01DF | GPUREG_01DF | ||
| 01E0 | GPUREG_01E0 | ||
| 01E1 | GPUREG_01E1 | ||
| 01E2 | GPUREG_01E2 | ||
| 01E3 | GPUREG_01E3 | ||
| 01E4 | GPUREG_01E4 | ||
| 01E5 | GPUREG_01E5 | ||
| 01E6 | GPUREG_01E6 | ||
| 01E7 | GPUREG_01E7 | ||
| 01E8 | GPUREG_01E8 | ||
| 01E9 | GPUREG_01E9 | ||
| 01EA | GPUREG_01EA | ||
| 01EB | GPUREG_01EB | ||
| 01EC | GPUREG_01EC | ||
| 01ED | GPUREG_01ED | ||
| 01EE | GPUREG_01EE | ||
| 01EF | GPUREG_01EF | ||
| 01F0 | GPUREG_01F0 | ||
| 01F1 | GPUREG_01F1 | ||
| 01F2 | GPUREG_01F2 | ||
| 01F3 | GPUREG_01F3 | ||
| 01F4 | GPUREG_01F4 | ||
| 01F5 | GPUREG_01F5 | ||
| 01F6 | GPUREG_01F6 | ||
| 01F7 | GPUREG_01F7 | ||
| 01F8 | GPUREG_01F8 | ||
| 01F9 | GPUREG_01F9 | ||
| 01FA | GPUREG_01FA | ||
| 01FB | GPUREG_01FB | ||
| 01FC | GPUREG_01FC | ||
| 01FD | GPUREG_01FD | ||
| 01FE | GPUREG_01FE | ||
| 01FF | GPUREG_01FF |
Geometry pipeline registers (0x200-0x27F)
Shader registers (0x280-0x2DF)
| Register ID | Register name | Notes | Official Name |
|---|---|---|---|
| Geometry shader | |||
| 0280 | GPUREG_GSH_BOOLUNIFORM | PICA_REG_GS_BOOL | |
| 0281 | GPUREG_GSH_INTUNIFORM_I0 | PICA_REG_GS_INT0 | |
| 0282 | GPUREG_GSH_INTUNIFORM_I1 | PICA_REG_GS_INT1 | |
| 0283 | GPUREG_GSH_INTUNIFORM_I2 | PICA_REG_GS_INT2 | |
| 0284 | GPUREG_GSH_INTUNIFORM_I3 | PICA_REG_GS_INT3 | |
| 0285 | GPUREG_0285 | ||
| 0286 | GPUREG_0286 | ||
| 0287 | GPUREG_0287 | ||
| 0288 | GPUREG_0288 | ||
| 0289 | GPUREG_GSH_INPUTBUFFER_CONFIG | PICA_REG_GS_ATTR_NUM | |
| 028A | GPUREG_GSH_ENTRYPOINT | PICA_REG_GS_START_ADDR | |
| 028B | GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW | PICA_REG_GS_ATTR_IN_REG_MAP0 | |
| 028C | GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH | PICA_REG_GS_ATTR_IN_REG_MAP1 | |
| 028D | GPUREG_GSH_OUTMAP_MASK | PICA_REG_GS_OUT_REG_MASK | |
| 028E | GPUREG_028E | ||
| 028F | GPUREG_GSH_CODETRANSFER_END | PICA_REG_GS_PROG_RENEWAL_END | |
| 0290 | GPUREG_GSH_FLOATUNIFORM_CONFIG | PICA_REG_GS_FLOAT_ADDR | |
| 0291 | GPUREG_GSH_FLOATUNIFORM_INDEX | PICA_REG_GS_FLOAT_DATA1 | |
| 0292 | GPUREG_GSH_FLOATUNIFORM_DATA | PICA_REG_GS_FLOAT_DATA2 | |
| 0293 | GPUREG_GSH_FLOATUNIFORM_DATA | PICA_REG_GS_FLOAT_DATA3 | |
| 0294 | GPUREG_GSH_FLOATUNIFORM_DATA | PICA_REG_GS_FLOAT_DATA4 | |
| 0295 | GPUREG_GSH_FLOATUNIFORM_DATA | PICA_REG_GS_FLOAT_DATA5 | |
| 0296 | GPUREG_GSH_FLOATUNIFORM_DATA | PICA_REG_GS_FLOAT_DATA6 | |
| 0297 | GPUREG_GSH_FLOATUNIFORM_DATA | PICA_REG_GS_FLOAT_DATA7 | |
| 0298 | GPUREG_GSH_FLOATUNIFORM_DATA | PICA_REG_GS_FLOAT_DATA8 | |
| 0299 | GPUREG_0299 | ||
| 029A | GPUREG_029A | ||
| 029B | GPUREG_GSH_CODETRANSFER_INDEX | ? | PICA_REG_GS_PROG_ADDR |
| 029C | GPUREG_GSH_CODETRANSFER_DATA | PICA_REG_GS_PROG_DATA0 | |
| 029D | GPUREG_GSH_CODETRANSFER_DATA | PICA_REG_GS_PROG_DATA1 | |
| 029E | GPUREG_GSH_CODETRANSFER_DATA | PICA_REG_GS_PROG_DATA2 | |
| 029F | GPUREG_GSH_CODETRANSFER_DATA | PICA_REG_GS_PROG_DATA3 | |
| 02A0 | GPUREG_GSH_CODETRANSFER_DATA | PICA_REG_GS_PROG_DATA4 | |
| 02A1 | GPUREG_GSH_CODETRANSFER_DATA | PICA_REG_GS_PROG_DATA5 | |
| 02A2 | GPUREG_GSH_CODETRANSFER_DATA | PICA_REG_GS_PROG_DATA6 | |
| 02A3 | GPUREG_GSH_CODETRANSFER_DATA | PICA_REG_GS_PROG_DATA7 | |
| 02A4 | GPUREG_02A4 | ||
| 02A5 | GPUREG_GSH_OPDESCS_INDEX | PICA_REG_GS_PROG_SWIZZLE_ADDR | |
| 02A6 | GPUREG_GSH_OPDESCS_DATA | PICA_REG_GS_PROG_SWIZZLE_DATA0 | |
| 02A7 | GPUREG_GSH_OPDESCS_DATA | PICA_REG_GS_PROG_SWIZZLE_DATA1 | |
| 02A8 | GPUREG_GSH_OPDESCS_DATA | PICA_REG_GS_PROG_SWIZZLE_DATA2 | |
| 02A9 | GPUREG_GSH_OPDESCS_DATA | PICA_REG_GS_PROG_SWIZZLE_DATA3 | |
| 02AA | GPUREG_GSH_OPDESCS_DATA | PICA_REG_GS_PROG_SWIZZLE_DATA4 | |
| 02AB | GPUREG_GSH_OPDESCS_DATA | PICA_REG_GS_PROG_SWIZZLE_DATA5 | |
| 02AC | GPUREG_GSH_OPDESCS_DATA | PICA_REG_GS_PROG_SWIZZLE_DATA6 | |
| 02AD | GPUREG_GSH_OPDESCS_DATA | PICA_REG_GS_PROG_SWIZZLE_DATA7 | |
| 02AE | GPUREG_02AE | ||
| 02AF | GPUREG_02AF | ||
| Vertex shader | |||
| 02B0 | GPUREG_VSH_BOOLUNIFORM | PICA_REG_VS_BOOL | |
| 02B1 | GPUREG_VSH_INTUNIFORM_I0 | PICA_REG_VS_INT0 | |
| 02B2 | GPUREG_VSH_INTUNIFORM_I1 | PICA_REG_VS_INT1 | |
| 02B3 | GPUREG_VSH_INTUNIFORM_I2 | PICA_REG_VS_INT2 | |
| 02B4 | GPUREG_VSH_INTUNIFORM_I3 | PICA_REG_VS_INT3 | |
| 02B5 | GPUREG_02B5 | ||
| 02B6 | GPUREG_02B6 | ||
| 02B7 | GPUREG_02B7 | ||
| 02B8 | GPUREG_02B8 | ||
| 02B9 | GPUREG_VSH_INPUTBUFFER_CONFIG | PICA_REG_VS_ATTR_NUM0 | |
| 02BA | GPUREG_VSH_ENTRYPOINT | PICA_REG_VS_START_ADDR | |
| 02BB | GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW | PICA_REG_VS_ATTR_IN_REG_MAP0 | |
| 02BC | GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH | PICA_REG_VS_ATTR_IN_REG_MAP1 | |
| 02BD | GPUREG_VSH_OUTMAP_MASK | PICA_REG_VS_OUT_REG_MASK | |
| 02BE | GPUREG_02BE | ||
| 02BF | GPUREG_VSH_CODETRANSFER_END | PICA_REG_VS_PROG_RENEWAL_END | |
| 02C0 | GPUREG_VSH_FLOATUNIFORM_INDEX | PICA_REG_VS_FLOAT_ADDR | |
| 02C1 | GPUREG_VSH_FLOATUNIFORM_DATA | PICA_REG_VS_FLOAT_DATA1 | |
| 02C2 | GPUREG_VSH_FLOATUNIFORM_DATA | PICA_REG_VS_FLOAT_DATA2 | |
| 02C3 | GPUREG_VSH_FLOATUNIFORM_DATA | PICA_REG_VS_FLOAT_DATA3 | |
| 02C4 | GPUREG_VSH_FLOATUNIFORM_DATA | PICA_REG_VS_FLOAT_DATA4 | |
| 02C5 | GPUREG_VSH_FLOATUNIFORM_DATA | PICA_REG_VS_FLOAT_DATA5 | |
| 02C6 | GPUREG_VSH_FLOATUNIFORM_DATA | PICA_REG_VS_FLOAT_DATA6 | |
| 02C7 | GPUREG_VSH_FLOATUNIFORM_DATA | PICA_REG_VS_FLOAT_DATA7 | |
| 02C8 | GPUREG_VSH_FLOATUNIFORM_DATA | PICA_REG_VS_FLOAT_DATA8 | |
| 02C9 | GPUREG_02C9 | ||
| 02CA | GPUREG_02CA | ||
| 02CB | GPUREG_VSH_CODETRANSFER_INDEX | ? | PICA_REG_VS_PROG_ADDR |
| 02CC | GPUREG_VSH_CODETRANSFER_DATA | PICA_REG_VS_PROG_DATA0 | |
| 02CD | GPUREG_VSH_CODETRANSFER_DATA | PICA_REG_VS_PROG_DATA1 | |
| 02CE | GPUREG_VSH_CODETRANSFER_DATA | PICA_REG_VS_PROG_DATA2 | |
| 02CF | GPUREG_VSH_CODETRANSFER_DATA | PICA_REG_VS_PROG_DATA3 | |
| 02D0 | GPUREG_VSH_CODETRANSFER_DATA | PICA_REG_VS_PROG_DATA4 | |
| 02D1 | GPUREG_VSH_CODETRANSFER_DATA | PICA_REG_VS_PROG_DATA5 | |
| 02D2 | GPUREG_VSH_CODETRANSFER_DATA | PICA_REG_VS_PROG_DATA6 | |
| 02D3 | GPUREG_VSH_CODETRANSFER_DATA | PICA_REG_VS_PROG_DATA7 | |
| 02D4 | GPUREG_02D4 | ||
| 02D5 | GPUREG_VSH_OPDESCS_INDEX | ? | PICA_REG_VS_PROG_SWIZZLE_ADDR |
| 02D6 | GPUREG_VSH_OPDESCS_DATA | PICA_REG_VS_PROG_SWIZZLE_DATA0 | |
| 02D7 | GPUREG_VSH_OPDESCS_DATA | PICA_REG_VS_PROG_SWIZZLE_DATA1 | |
| 02D8 | GPUREG_VSH_OPDESCS_DATA | PICA_REG_VS_PROG_SWIZZLE_DATA2 | |
| 02D9 | GPUREG_VSH_OPDESCS_DATA | PICA_REG_VS_PROG_SWIZZLE_DATA3 | |
| 02DA | GPUREG_VSH_OPDESCS_DATA | PICA_REG_VS_PROG_SWIZZLE_DATA4 | |
| 02DB | GPUREG_VSH_OPDESCS_DATA | PICA_REG_VS_PROG_SWIZZLE_DATA5 | |
| 02DC | GPUREG_VSH_OPDESCS_DATA | PICA_REG_VS_PROG_SWIZZLE_DATA6 | |
| 02DD | GPUREG_VSH_OPDESCS_DATA | PICA_REG_VS_PROG_SWIZZLE_DATA7 | |
| 02DE | GPUREG_02DE | ||
| 02DF | GPUREG_02DF | ||
Unknown registers (0x2E0-0x2FF)
| Register ID | Register name | Notes | Official Name |
|---|---|---|---|
| 02E0 | GPUREG_02E0 | ||
| 02E1 | GPUREG_02E1 | ||
| 02E2 | GPUREG_02E2 | ||
| 02E3 | GPUREG_02E3 | ||
| 02E4 | GPUREG_02E4 | ||
| 02E5 | GPUREG_02E5 | ||
| 02E6 | GPUREG_02E6 | ||
| 02E7 | GPUREG_02E7 | ||
| 02E8 | GPUREG_02E8 | ||
| 02E9 | GPUREG_02E9 | ||
| 02EA | GPUREG_02EA | ||
| 02EB | GPUREG_02EB | ||
| 02EC | GPUREG_02EC | ||
| 02ED | GPUREG_02ED | ||
| 02EE | GPUREG_02EE | ||
| 02EF | GPUREG_02EF | ||
| 02F0 | GPUREG_02F0 | ||
| 02F1 | GPUREG_02F1 | ||
| 02F2 | GPUREG_02F2 | ||
| 02F3 | GPUREG_02F3 | ||
| 02F4 | GPUREG_02F4 | ||
| 02F5 | GPUREG_02F5 | ||
| 02F6 | GPUREG_02F6 | ||
| 02F7 | GPUREG_02F7 | ||
| 02F8 | GPUREG_02F8 | ||
| 02F9 | GPUREG_02F9 | ||
| 02FA | GPUREG_02FA | ||
| 02FB | GPUREG_02FB | ||
| 02FC | GPUREG_02FC | ||
| 02FD | GPUREG_02FD | ||
| 02FE | GPUREG_02FE | ||
| 02FF | GPUREG_02FF |
Miscellaneous registers
GPUREG_FINALIZE
Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software. Failure to write to this register in any command buffer will result in the GPU hanging.
Rasterizer registers
GPUREG_FACECULLING_CONFIG
| Bits | Description |
|---|---|
| 0-1 | Culling mode |
Culling mode values:
| Value | Description |
|---|---|
| 0 | None |
| 1 | Front Face (Counter Clockwise) |
| 2 | Back Face (Counter Clockwise) |
GPUREG_VIEWPORT_WIDTH
| Bits | Description |
|---|---|
| 0-23 | float24, width / 2 |
GPUREG_VIEWPORT_INVW
| Bits | Description |
|---|---|
| 1-31 | float31, 2 / width |
GPUREG_VIEWPORT_HEIGHT
| Bits | Description |
|---|---|
| 0-23 | float24, height / 2 |
GPUREG_VIEWPORT_INVH
| Bits | Description |
|---|---|
| 1-31 | float31, 2 / height |
GPUREG_FRAGOP_CLIP
| Bits | Description |
|---|---|
| 0-1 | Enabled (0 = disabled, 1 = enabled) |
GPUREG_FRAGOP_CLIP_DATAi
| Bits | Description |
|---|---|
| 0-23 | float24, Clipping plane coefficient |
GPUREG_DEPTHMAP_SCALE
| Bits | Description |
|---|---|
| 0-23 | float24, Near - Far |
GPUREG_DEPTHMAP_OFFSET
| Bits | Description |
|---|---|
| 0-23 | float24, Near |
GPUREG_SH_OUTMAP_TOTAL
| Bits | Description |
|---|---|
| 0-31 | Number of following attributes |
GPUREG_SH_OUTMAP_Oi
These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.
| Bits | Description |
|---|---|
| 0-7 | Semantic for the x component of the register. |
| 8-15 | Semantic for the y component of the register. |
| 16-23 | Semantic for the z component of the register. |
| 24-31 | Semantic for the w component of the register. |
The semantic ids are:
| Value | Semantic | Description |
|---|---|---|
| 0x00 | position.x | Vertex Position |
| 0x01 | position.y | |
| 0x02 | position.z | |
| 0x03 | position.w | |
| 0x04 | normquat.x | Quaternion specifying the normal/tangent frame (for fragment lighting) |
| 0x05 | normquat.y | |
| 0x06 | normquat.z | |
| 0x07 | normquat.w | |
| 0x08 | color.r | Vertex color |
| 0x09 | color.g | |
| 0x0A | color.b | |
| 0x0B | color.a | |
| 0x0C | texcoord0.u | Texture coordinates for texture 0 |
| 0x0D | texcoord0.v | |
| 0x0E | texcoord1.u | Texture coordinates for texture 1 |
| 0x0F | texcoord1.v | |
| 0x10 | texcoord0.w | |
| 0x12 | view.x | View vector (for fragment lighting) |
| 0x13 | view.y | |
| 0x14 | view.z | |
| 0x16 | texcoord2.u | Texture coordinates for texture 2 |
| 0x17 | texcoord2.v | |
| 0x1F | Unused component | Should be set for unused components of the output register |
GPUREG_EARLY_DEPTH_FUNC
| Bits | Description |
|---|---|
| 0-1 | Early depth function |
Early depth function values:
| Value | Description |
|---|---|
| 0 | >= |
| 1 | > |
| 2 | <= |
| 3 | < |
GPUREG_EARLY_DEPTH_TEST1
| Bits | Description |
|---|---|
| 0-1 | Enabled (0 = disabled, 1 = enabled) |
GPUREG_EARLY_DEPTH_CLEAR
| Bits | Description |
|---|---|
| 0-1 | Trigger (0 = idle, 1 = clear) |
GPUREG_SH_OUT_ATTR_MODE
| Bits | Description |
|---|---|
| 0-1 | Use texture coordinates (0 = don't use, 1 = use) |
GPUREG_SCISSORTEST_MODE
| Bits | Description |
|---|---|
| 0-1 | Enabled (0 = disabled, 1 = enabled) |
GPUREG_SCISSORTEST_POS
| Bits | Description |
|---|---|
| 0-15 | X1 |
| 16-31 | Y1 |
GPUREG_SCISSORTEST_DIM
| Bits | Description |
|---|---|
| 0-15 | X2 |
| 16-31 | Y2 |
GPUREG_VIEWPORT_XY
| Bits | Description |
|---|---|
| 0-15 | X |
| 16-31 | Y |
GPUREG_EARLY_DEPTH_DATA
| Bits | Description |
|---|---|
| 0-31 | Clear value |
GPUREG_FRAGOP_WSCALE
| Bits | Description |
|---|---|
| 0-1 | Enabled (0 = disabled, 1 = enabled) |
GPUREG_RENDER_BUF_RESOLUTION1
| Bits | Description |
|---|---|
| 0-11 | Width |
| 12-23 | Height |
| 24 | 0x1 |
GPUREG_SH_OUT_ATTR_CLK
| Bits | Description |
|---|---|
| 0 | 'position.z' present |
| 1 | 'color' component present |
| 8 | 'texcoord0' component present |
| 9 | 'texcoord1' component present |
| 10 | 'texcoord2' component present |
| 16 | 'texcoord0.w' present |
| 24 | 'normquat' or 'view' component present |
Texturing registers
GPUREG_TEXTURE_FUNC
| Bits | Description |
|---|---|
| 0 | Texture 0 enabled |
| 1 | Texture 1 enabled |
| 2 | Texture 2 enabled |
| 3 | 0x0 |
| 8-9 | Texture 3 coordinates (0 = texture 0, 1 = texture 1, 2 = texture 2) |
| 10 | Texture 3 enabled |
| 12 | 0x1 |
| 13 | Texture 2 coordinates (0 = texture 2, 1 = texture 1) |
| 16 | Clear texture cache (0 = don't clear, 1 = clear) |
Framebuffer registers
GPUREG_FRAMEBUFFER_INVALIDATE
Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does not flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.
GPUREG_FRAMEBUFFER_FLUSH
Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.
GPUREG_DEPTHBUFFER_FORMAT
The format the current depth buffer should be written into. Following values are possible:
| Value | Description |
|---|---|
| 0 | 16-bit depth |
| 1 | ?? seems to freeze the GPU |
| 2 | 24-bit depth |
| 3 | 24-bit depth + 8-bit stencil (stencil is within bit 24-31) |
GPUREG_COLORBUFFER_FORMAT
Describes the format of the current color buffer used for 3D rendering.
| Bits | Description |
|---|---|
| 0-7 | Pixel size (0=16-bit, 1=24-bit, 2=32-bit, 3=64-bit?) |
| 16-23 | Framebuffer Format (0=GL_RGBA8, 1=GL_RGB8, 2=GL_RGB5_A1, 3=GL_R5_G6_B5, 4=GL_RGBA4).
Note that these values are slightly different from those in GPU#Framebuffer_color_formats. Color components are laid out in reverse byte order, with the most significant bits used first. |
GPUREG_FRAMEBUFFER_BLOCK32
When set to 0, use regular 8x8 tiling format for the framebuffer, compatible with textures. When set to 1, use a 32x32 tiling format. To untile the color buffer when using this format, use bit 16 of the display transfer flags. It is unknown if there are any advantages to using the 32x32 format.
Fragment lighting registers
GPUREG_LIGHTING_ENABLE0
This register is set to 0 when fragment lighting is disabled, and to 1 when it is enabled.
GPUREG_LIGHTING_ENABLE1
This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.
GPUREG_LIGHTING_CONFIG0
| Bits | Description |
|---|---|
| 0 | Shadow factor enable, usually set to bit16 OR bit18 OR bit19 |
| 1 | Unknown, set to 0 |
| 2-3 | "Fresnel selector" (see below) |
| 4-7 | "Config", "Light env config" (see below) |
| 8-15 | Unknown, set to 4 |
| 16 | "Shadow primary", 0=disabled, 1=enabled |
| 17 | "Shadow secondary", 0=disabled, 1=enabled |
| 18 | "Invert shadow", 0=disabled, 1=enabled |
| 19 | "Shadow alpha", 0=disabled, 1=enabled |
| 20-21 | Unknown, set to 0 |
| 22-23 | "Bump selector", texture unit for bumpmapping |
| 24-25 | "Shadow selector", texture unit for shadow mapping |
| 26 | Unknown, set to 0 |
| 27 | "Clamp highlights", 0=disabled, 1=enabled |
| 28-29 | "Bump mode", "Light env texy usage" (see below) |
| 30 | "Bump renorm", 0=enabled, 1=disabled |
| 31 | Unknown, set to 1 |
Fresnel selector constants:
| Value | Description |
|---|---|
| 0 | NO_FRESNEL |
| 1 | PRI_ALPHA_FRESNEL |
| 2 | SEC_ALPHA_FRESNEL |
| 3 | PRI_SEC_ALPHA_FRESNEL |
The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If lut_RR is enabled but not lut_RG or lut_RB, the output of lut_RR is used for the three components; Red, Green and Blue.
Light env config constants:
| Value | Description | Available LUTs |
|---|---|---|
| 0 | LIGHT_ENV_LAYER_CONFIG0 | lut_D0, lut_RR, lut_SP, lut_DA |
| 1 | LIGHT_ENV_LAYER_CONFIG1 | lut_FR, lut_RR, lut_SP, lut_DA |
| 2 | LIGHT_ENV_LAYER_CONFIG2 | lut_D0, lut_D1, lut_RR, lut_DA |
| 3 | LIGHT_ENV_LAYER_CONFIG3 | lut_D0, lut_D1, lut_FR, lut_DA |
| 4 | LIGHT_ENV_LAYER_CONFIG4 | All except for lut_FR |
| 5 | LIGHT_ENV_LAYER_CONFIG5 | All except for lut_D1 |
| 6 | LIGHT_ENV_LAYER_CONFIG6 | All except for lut_RB and lut_RG |
| 8 (sic) | LIGHT_ENV_LAYER_CONFIG7 | All |
Bump mode constants:
| Value | Description |
|---|---|
| 0 | BUMP_NOT_USED |
| 1 | BUMP_AS_BUMP |
| 2 | BUMP_AS_TANG |
Bit 30 is set when bump mode is not zero.
GPUREG_LIGHTING_CONFIG1
| Bits | Description |
|---|---|
| 0 | Disable bit for frag light source 0 shadows |
| 1 | Disable bit for frag light source 1 shadows |
| 2 | Disable bit for frag light source 2 shadows |
| 3 | Disable bit for frag light source 3 shadows |
| 4 | Disable bit for frag light source 4 shadows |
| 5 | Disable bit for frag light source 5 shadows |
| 6 | Disable bit for frag light source 6 shadows |
| 7 | Disable bit for frag light source 7 shadows |
| 8 | Disable bit for frag light source 0 spot |
| 9 | Disable bit for frag light source 1 spot |
| 10 | Disable bit for frag light source 2 spot |
| 11 | Disable bit for frag light source 3 spot |
| 12 | Disable bit for frag light source 4 spot |
| 13 | Disable bit for frag light source 5 spot |
| 14 | Disable bit for frag light source 6 spot |
| 15 | Disable bit for frag light source 7 spot |
| 16 | Disable bit for lut_D0 |
| 17 | Disable bit for lut_D1 |
| 18 | Unknown, set to 1 |
| 19 | Disable bit for lut_FR |
| 20 | Disable bit for lut_RB |
| 21 | Disable bit for lut_RG |
| 22 | Disable bit for lut_RR |
| 23 | Unknown, set to 1 |
| 24 | Disable bit for frag light source 0 distance attenuation |
| 25 | Disable bit for frag light source 1 distance attenuation |
| 26 | Disable bit for frag light source 2 distance attenuation |
| 27 | Disable bit for frag light source 3 distance attenuation |
| 28 | Disable bit for frag light source 4 distance attenuation |
| 29 | Disable bit for frag light source 5 distance attenuation |
| 30 | Disable bit for frag light source 6 distance attenuation |
| 31 | Disable bit for frag light source 7 distance attenuation |
GPUREG_LIGHTING_NUM_LIGHTS
The number of active lights minus one (0..7) is written to this register.
GPUREG_LIGHTING_LIGHT_PERMUTATION
| Bits | Description |
|---|---|
| 0-2 | ID of the 1st enabled light (0..7) |
| 4-6 | ID of the 2nd enabled light (0..7) |
| 8-10 | ID of the 3rd enabled light (0..7) |
| 12-14 | ID of the 4th enabled light (0..7) |
| 16-18 | ID of the 5th enabled light (0..7) |
| 20-22 | ID of the 6th enabled light (0..7) |
| 24-26 | ID of the 7th enabled light (0..7) |
| 28-30 | ID of the 8th enabled light (0..7) |
GPUREG_LIGHTING_LUTINPUT_SELECT
| Bits | Description |
|---|---|
| 0-3 | Input selector for lut_D0 |
| 4-7 | Input selector for lut_D1 |
| 8-11 | Input selector for lut_SP |
| 12-15 | Input selector for lut_FR |
| 16-19 | Input selector for lut_RB |
| 20-23 | Input selector for lut_RG |
| 24-27 | Input selector for lut_RR |
Input selector values:
| Value | Description |
|---|---|
| 0 | N·H |
| 1 | V·H |
| 2 | N·V |
| 3 | L·N |
| 4 | -L·P (aka Spotlight aka SP) |
| 5 | cos φ (aka CP) |
GPUREG_LIGHTING_LUTINPUT_ABS
| Bits | Description |
|---|---|
| 1 | abs() flag for the input of lut_D0 (0=enabled, 1=disabled) |
| 5 | abs() flag for the input of lut_D1 (0=enabled, 1=disabled) |
| 9 | abs() flag for the input of lut_SP (0=enabled, 1=disabled) |
| 13 | abs() flag for the input of lut_FR (0=enabled, 1=disabled) |
| 17 | abs() flag for the input of lut_RB (0=enabled, 1=disabled) |
| 21 | abs() flag for the input of lut_RG (0=enabled, 1=disabled) |
| 25 | abs() flag for the input of lut_RR (0=enabled, 1=disabled) |
This register controls whether the absolute value of the input is taken before using a LUT.
GPUREG_LIGHTING_LUTINPUT_SCALE
| Bits | Description |
|---|---|
| 0-3 | Scaler selector for lut_D0 |
| 4-7 | Scaler selector for lut_D1 |
| 8-11 | Scaler selector for lut_SP |
| 12-15 | Scaler selector for lut_FR |
| 16-19 | Scaler selector for lut_RB |
| 20-23 | Scaler selector for lut_RG |
| 24-27 | Scaler selector for lut_RR |
Scaler selector values:
| Value | Description |
|---|---|
| 0 | 1x |
| 1 | 2x |
| 2 | 4x |
| 3 | 8x |
| 6 | 0.25x |
| 7 | 0.5x |
This register controls the scaling that is applied to the output of a LUT.
GPUREG_LIGHTING_LUT_INDEX
This register controls which LUT and what offset into it the LUT_DATA register writes to.
| Bits | Description |
|---|---|
| 0-7 | Starting entry offset (0...255) |
| 8-10 | LUT ID (context=0) or Light ID (context=1,2) |
| 11-12 | Context ID |
LUT ID values:
| Value | Description |
|---|---|
| 0 | lut_D0 |
| 1 | lut_D1 |
| 3 | lut_FR |
| 4 | lut_RB |
| 5 | lut_RG |
| 6 | lut_RR |
Context ID values:
| Value | Description |
|---|---|
| 0 | LUTs common to all lights - writes to the LUT selected by the ID |
| 1 | lut_SP - writes to the LUT specific to the selected light |
| 2 | lut_DA - writes to the LUT specific to the selected light |
GPUREG_LIGHTING_LUT_DATA
Lighting LUT data is written here.
A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.
lut_DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.
Format of an entry:
| Bits | Description |
|---|---|
| 0-11 | Entry value (12bit fractional number; floatval = x / 4096; however 0xFFF is treated as 1.0) |
| 12-22 | Absolute value of the difference between the next entry and this entry, used to implement linear interpolation (11bit fractional number; floatval = x / 2048; however 0x7FF is treated as 1.0) |
| 23 | Sign bit of the difference (0=positive, 1=negative) |
GPUREG_LIGHTING_AMBIENT
| Bits | Description |
|---|---|
| 0-7 | Blue component (0..255) |
| 10-17 | Green component (0..255) |
| 20-27 | Red component (0..255) |
This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.
GPUREG_LIGHTx_CONFIG
| Bits | Description |
|---|---|
| 0 | Light type (0 = positional light, 1 = directional light) |
| 1 | Two side diffuse (0=disable, 1=enable) |
| 2 | Geometric factor 0 (0=disable, 1=enable) |
| 3 | Geometric factor 1 (0=disable, 1=enable) |
GPUREG_LIGHTx_XY
| Bits | Description |
|---|---|
| 0-15 | X coordinate (float16 = 1.5.10) |
| 16-31 | Y coordinate (float16 = 1.5.10) |
These registers (along with _Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.
GPUREG_LIGHTx_Z
| Bits | Description |
|---|---|
| 0-15 | Z coordinate (float16 = 1.5.10) |
These registers (along with _XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.
GPUREG_LIGHTx_SPOTDIR_XY
| Bits | Description |
|---|---|
| 0-12 | X coordinate (2.11 signed fixed point) (Usually the input value is negated) |
| 16-28 | Y coordinate (2.11 signed fixed point) (Usually the input value is negated) |
These registers (along with _Z) represent the spot direction (unitary) vector of the corresponding light.
GPUREG_LIGHTx_SPOTDIR_Z
| Bits | Description |
|---|---|
| 0-12 | Z coordinate (2.11 signed fixed point) (Usually the input value is negated) |
These registers (along with _XY) represent the spot direction (unitary) vector of the corresponding light.
GPUREG_LIGHTx_ATTENUATION_BIAS
These registers contain the distance attenuation bias value (float20 = 1.7.12) of the corresponding light. The attenuation factor is lut_DA(clip(bias + scale*distance, 0.0, 1.0)).
GPUREG_LIGHTx_ATTENUATION_SCALE
These registers contain the distance attenuation scale value (float20 = 1.7.12) of the corresponding light. The attenuation factor is lut_DA(clip(bias + scale*distance, 0.0, 1.0)).
GPUREG_LIGHTx_AMBIENT
These registers contain the ambient color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_ambient*lightX_ambient.
GPUREG_LIGHTx_DIFFUSE
These registers contain the diffuse color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_diffuse*lightX_diffuse.
GPUREG_LIGHTx_SPECULAR0
These registers contain the specular0 color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_specular0*lightX_specular0.
GPUREG_LIGHTx_SPECULAR1
These registers contain the specular1 color (same format as GPUREG_LIGHTING_AMBIENT) of the corresponding light. Usually set to material_specular1*lightX_specular1.
Geometry pipeline registers
GPUREG_GEOSTAGE_CONFIG
| Bits | Description |
|---|---|
| 0-7 | Geometry stage mode. (0=Vertex shader only, 2=Vertex shader + geometry shader) |
| 8 | Unknown. Seems to skip every other triangle when used with indexed rendering and without geoshaders. Has no effect with non-indexed rendering without geoshaders. If this is 0, you don't need to use GPU_UNKPRIM with DrawElements. |
| 9-15 | No effect. |
| 16-23 | Unknown. |
| 24-31 | Unknown. Often set to 0. |
This register configures the geometry stage of the GPU pipeline.
GPUREG_FIXEDATTRIB_INDEX
See GPU/Fixed Vertex Attributes and GPU/Immediate-Mode Vertex Submission for usage info.
| Bits | Description |
|---|---|
| 0-31 | Sets the active fixed attribute index. This is the fixed attribute which will be set when writing to GPUREG_FIXEDATTRIB_DATA. Valid values are 0-11. If the special value 0xF is written here, this sets up immediate-mode vertex submission instead, and writes to the data register will input vertex data directly into the pipeline. |
GPUREG_FIXEDATTRIB_DATA
Accepts a packed 4-tuple of float24 values (in the same format used for specifying shader uniforms). This is stored as the fixed attribute value for the attribute currently specified in the index register. Attributes are always specified as a 4-tuple of floats, regardless of the format configured in GPUREG_ATTRIBBUFFERS_FORMAT_HIGH.
If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly. The index register does not need to be re-set after each write.
GPUREG_RESTART_PRIMITIVE
| Bits | Description |
|---|---|
| 0-7 | Writing 0x01 to this field ends the current triangle strip or fan. This is necessary before using these kinds of primitives with immediate-mode, but most games seem to write to it before every draw call. |
Geometry shader registers
GPUREG_GSH_BOOLUNIFORM
| Bits | Description |
|---|---|
| 0 | Value of geometry shader unit's b0 boolean register. (0=true, 1=false) |
| 1 | Value of geometry shader unit's b1 boolean register. (0=true, 1=false) |
| 2 | Value of geometry shader unit's b2 boolean register. (0=true, 1=false) |
| 3 | Value of geometry shader unit's b3 boolean register. (0=true, 1=false) |
| 4 | Value of geometry shader unit's b4 boolean register. (0=true, 1=false) |
| 5 | Value of geometry shader unit's b5 boolean register. (0=true, 1=false) |
| 6 | Value of geometry shader unit's b6 boolean register. (0=true, 1=false) |
| 7 | Value of geometry shader unit's b7 boolean register. (0=true, 1=false) |
| 8 | Value of geometry shader unit's b8 boolean register. (0=true, 1=false) |
| 9 | Value of geometry shader unit's b9 boolean register. (0=true, 1=false) |
| 10 | Value of geometry shader unit's b10 boolean register. (0=true, 1=false) |
| 11 | Value of geometry shader unit's b11 boolean register. (0=true, 1=false) |
| 12 | Value of geometry shader unit's b12 boolean register. (0=true, 1=false) |
| 13 | Value of geometry shader unit's b13 boolean register. (0=true, 1=false) |
| 14 | Value of geometry shader unit's b14 boolean register. (0=true, 1=false) |
| 15 | Value of geometry shader unit's b15 boolean register. (0=true, 1=false) |
| 16-31 | Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang |
This register is used to set the geometry shader unit's boolean registers.
GPUREG_GSH_INTUNIFORM_I0
| Bits | Description |
|---|---|
| 0-7 | Value for geometry shader's i0.x (u8, 0-255) |
| 8-15 | Value for geometry shader's i0.y (u8, 0-255) |
| 16-23 | Value for geometry shader's i0.z (u8, 0-255) |
| 24-31 | Value for geometry shader's i0.w (u8, 0-255) |
This register is used to set the geometry shader's i0 integer register.
GPUREG_GSH_INTUNIFORM_I1
| Bits | Description |
|---|---|
| 0-7 | Value for geometry shader's i1.x (u8, 0-255) |
| 8-15 | Value for geometry shader's i1.y (u8, 0-255) |
| 16-23 | Value for geometry shader's i1.z (u8, 0-255) |
| 24-31 | Value for geometry shader's i1.w (u8, 0-255) |
This register is used to set the geometry shader's i1 integer register.
GPUREG_GSH_INTUNIFORM_I2
| Bits | Description |
|---|---|
| 0-7 | Value for geometry shader's i2.x (u8, 0-255) |
| 8-15 | Value for geometry shader's i2.y (u8, 0-255) |
| 16-23 | Value for geometry shader's i2.z (u8, 0-255) |
| 24-31 | Value for geometry shader's i2.w (u8, 0-255) |
This register is used to set the geometry shader's i2 integer register.
GPUREG_GSH_INTUNIFORM_I3
| Bits | Description |
|---|---|
| 0-7 | Value for geometry shader's i3.x (u8, 0-255) |
| 8-15 | Value for geometry shader's i3.y (u8, 0-255) |
| 16-23 | Value for geometry shader's i3.z (u8, 0-255) |
| 24-31 | Value for geometry shader's i3.w (u8, 0-255) |
This register is used to set the geometry shader's i3 integer register.
GPUREG_GSH_INPUTBUFFER_CONFIG
| Bits | Description |
|---|---|
| 0-7 | Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register) |
| 8-23 | Unknown. These bits typically aren't updated by games. |
| 24-31 | Unknown. This is typically set to 8 for geometry shaders. |
This register is used to configure the geometry shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the input primitive size in registers, though it is not a limit on the number of input registers which can be accessed from the geometry shader.
GPUREG_GSH_ENTRYPOINT
| Bits | Description |
|---|---|
| 0-15 | Geometry shader unit entrypoint, in words. |
| 16-31 | Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang |
This sets the entrypoint for the program running on the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entrypoint, it can also be used to set this single shader unit to run from a different entrypoint than the other three even when running a vertex shader.
GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW
| Bits | Description |
|---|---|
| 0-3 | Index of geometry shader input register which the 1st attribute will be stored in. |
| 4-7 | Index of geometry shader input register which the 2nd attribute will be stored in. |
| 8-11 | Index of geometry shader input register which the 3rd attribute will be stored in. |
| 12-15 | Index of geometry shader input register which the 4th attribute will be stored in. |
| 16-19 | Index of geometry shader input register which the 5th attribute will be stored in. |
| 20-23 | Index of geometry shader input register which the 6th attribute will be stored in. |
| 24-27 | Index of geometry shader input register which the 7th attribute will be stored in. |
| 28-31 | Index of geometry shader input register which the 8th attribute will be stored in. |
This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 1st attribute.
GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH
| Bits | Description |
|---|---|
| 0-3 | Index of geometry shader input register which the 9th attribute will be stored in. |
| 4-7 | Index of geometry shader input register which the 10th attribute will be stored in. |
| 8-11 | Index of geometry shader input register which the 11th attribute will be stored in. |
| 12-15 | Index of geometry shader input register which the 12th attribute will be stored in. |
| 16-19 | Index of geometry shader input register which the 13th attribute will be stored in. |
| 20-23 | Index of geometry shader input register which the 14th attribute will be stored in. |
| 24-27 | Index of geometry shader input register which the 15th attribute will be stored in. |
| 28-31 | Index of geometry shader input register which the 16th attribute will be stored in. |
This register sets the geometry shader input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the geometry shader program, v5 will contain the input buffer's 9th attribute.
GPUREG_GSH_OUTMAP_MASK
| Bits | Description |
|---|---|
| 0 | Enable bit for geometry shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled) |
| 1 | Enable bit for geometry shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled) |
| 2 | Enable bit for geometry shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled) |
| 3 | Enable bit for geometry shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled) |
| 4 | Enable bit for geometry shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled) |
| 5 | Enable bit for geometry shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled) |
| 6 | Enable bit for geometry shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled) |
This register toggles the geometry shader unit's output registers.
GPUREG_GSH_CODETRANSFER_END
| Bits | Description |
|---|---|
| 0 | Code data transfer end signal bit. |
This register's value should be set to 1 in order to finalize the transfer of geometry shader code. It is unknown whether this register is used for other functions.
GPUREG_GSH_FLOATUNIFORM_CONFIG
| Bits | Description |
|---|---|
| 0-6 | Target float vec4 geometry shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95) |
| 31 | Float vec4 geometry shader uniform data transfer mode. (0 = float24, 1 = float32) |
This register sets the target float vec4 geometry shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before GPUREG_GSH_FLOATUNIFORM_DATA, though writing to one register does not make writing to the other mandatory.
GPUREG_GSH_FLOATUNIFORM_DATA
| Bits | Description |
|---|---|
| 0-31 | Float vec4 geometry shader uniform data. (format depends on transfer mode, see below for details) |
This register is used to set the value of float vec4 geometry shader uniform registers. The data format which should be written to it depends on the transfer mode set with GPUREG_GSH_FLOATUNIFORM_CONFIG. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to GPUREG_GSH_FLOATUNIFORM_CONFIG.
- In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
- first word : ZZWWWWWW
- second word : YYYYZZZZ
- third word : XXXXXXYY
- In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
GPUREG_GSH_CODETRANSFER_CONFIG
| Bits | Description |
|---|---|
| 0-11 | Target geometry shader code offset for data transfer. |
This register is used to set the offset at which upcoming geometry shader code data transferred through GPUREG_GSH_CODETRANSFER_DATA should be written.
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The shader control flow instructions only have room to address 12 bits though, so it's likely that the maximum is 4095.
GPUREG_GSH_CODETRANSFER_DATA
| Bits | Description |
|---|---|
| 0-31 | Geometry shader instruction data. |
This register is used to transfer geometry shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader code memory bank at the offset initially set by GPUREG_GSH_CODETRANSFER_CONFIG. The offset in question is incremented after each write to this register.
GPUREG_GSH_OPDESCS_CONFIG
| Bits | Description |
|---|---|
| 0-6 | Target geometry shader operand descriptor offset for data transfer. |
This register is used to set the offset at which upcoming geometry shader operand descriptor data transferred through GPUREG_GSH_OPDESCS_DATA should be written.
GPUREG_GSH_OPDESCS_DATA
| Bits | Description |
|---|---|
| 0-31 | Geometry shader operand descriptor data. |
This register is used to transfer geometry shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU geometry shader operand descriptor memory bank at the offset initially set by GPUREG_GSH_OPDESCS_CONFIG. The offset in question is incremented after each write to this register.
Vertex shader registers
GPUREG_VSH_BOOLUNIFORM
| Bits | Description |
|---|---|
| 0 | Value of vertex shader unit's b0 boolean register. (0=true, 1=false) |
| 1 | Value of vertex shader unit's b1 boolean register. (0=true, 1=false) |
| 2 | Value of vertex shader unit's b2 boolean register. (0=true, 1=false) |
| 3 | Value of vertex shader unit's b3 boolean register. (0=true, 1=false) |
| 4 | Value of vertex shader unit's b4 boolean register. (0=true, 1=false) |
| 5 | Value of vertex shader unit's b5 boolean register. (0=true, 1=false) |
| 6 | Value of vertex shader unit's b6 boolean register. (0=true, 1=false) |
| 7 | Value of vertex shader unit's b7 boolean register. (0=true, 1=false) |
| 8 | Value of vertex shader unit's b8 boolean register. (0=true, 1=false) |
| 9 | Value of vertex shader unit's b9 boolean register. (0=true, 1=false) |
| 10 | Value of vertex shader unit's b10 boolean register. (0=true, 1=false) |
| 11 | Value of vertex shader unit's b11 boolean register. (0=true, 1=false) |
| 12 | Value of vertex shader unit's b12 boolean register. (0=true, 1=false) |
| 13 | Value of vertex shader unit's b13 boolean register. (0=true, 1=false) |
| 14 | Value of vertex shader unit's b14 boolean register. (0=true, 1=false) |
| 15 | Value of vertex shader unit's b15 boolean register. (0=true, 1=false) |
| 16-31 | Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang |
This register is used to set the vertex shader unit's boolean registers.
GPUREG_VSH_INTUNIFORM_I0
| Bits | Description |
|---|---|
| 0-7 | Value for vertex shader's i0.x (u8, 0-255) |
| 8-15 | Value for vertex shader's i0.y (u8, 0-255) |
| 16-23 | Value for vertex shader's i0.z (u8, 0-255) |
| 24-31 | Value for vertex shader's i0.w (u8, 0-255) |
This register is used to set the vertex shader's i0 integer register.
GPUREG_VSH_INTUNIFORM_I1
| Bits | Description |
|---|---|
| 0-7 | Value for vertex shader's i1.x (u8, 0-255) |
| 8-15 | Value for vertex shader's i1.y (u8, 0-255) |
| 16-23 | Value for vertex shader's i1.z (u8, 0-255) |
| 24-31 | Value for vertex shader's i1.w (u8, 0-255) |
This register is used to set the vertex shader's i1 integer register.
GPUREG_VSH_INTUNIFORM_I2
| Bits | Description |
|---|---|
| 0-7 | Value for vertex shader's i2.x (u8, 0-255) |
| 8-15 | Value for vertex shader's i2.y (u8, 0-255) |
| 16-23 | Value for vertex shader's i2.z (u8, 0-255) |
| 24-31 | Value for vertex shader's i2.w (u8, 0-255) |
This register is used to set the vertex shader's i2 integer register.
GPUREG_VSH_INTUNIFORM_I3
| Bits | Description |
|---|---|
| 0-7 | Value for vertex shader's i3.x (u8, 0-255) |
| 8-15 | Value for vertex shader's i3.y (u8, 0-255) |
| 16-23 | Value for vertex shader's i3.z (u8, 0-255) |
| 24-31 | Value for vertex shader's i3.w (u8, 0-255) |
This register is used to set the vertex shader's i3 integer register.
GPUREG_VSH_INPUTBUFFER_CONFIG
| Bits | Description |
|---|---|
| 0-7 | Input buffer stride minus 1, in float vec4 registers. (value 0 means a stride of 1 float vec4 register) |
| 8-23 | Unknown. These bits typically aren't updated by games. |
| 24-31 | Unknown. This is typically set to 0xA for vertex shaders. |
This register is used to configure the vertex shader's input buffer. In the context of a geometry shader, the stride parameter can be interpreted as the number of attributes per vertex.
GPUREG_VSH_ENTRYPOINT
| Bits | Description |
|---|---|
| 0-15 | Vertex shader entrypoint, in words. |
| 16-31 | Unknown. This seems to always be set to 0x7FFF, and other values may cause the GPU to hang |
This sets the entrypoint for the program running on shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.
GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW
| Bits | Description |
|---|---|
| 0-3 | Index of vertex shader input register which the 1st attribute will be stored in. |
| 4-7 | Index of vertex shader input register which the 2nd attribute will be stored in. |
| 8-11 | Index of vertex shader input register which the 3rd attribute will be stored in. |
| 12-15 | Index of vertex shader input register which the 4th attribute will be stored in. |
| 16-19 | Index of vertex shader input register which the 5th attribute will be stored in. |
| 20-23 | Index of vertex shader input register which the 6th attribute will be stored in. |
| 24-27 | Index of vertex shader input register which the 7th attribute will be stored in. |
| 28-31 | Index of vertex shader input register which the 8th attribute will be stored in. |
This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 1st attribute.
GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH
| Bits | Description |
|---|---|
| 0-3 | Index of vertex shader input register which the 9th attribute will be stored in. |
| 4-7 | Index of vertex shader input register which the 10th attribute will be stored in. |
| 8-11 | Index of vertex shader input register which the 11th attribute will be stored in. |
| 12-15 | Index of vertex shader input register which the 12th attribute will be stored in. |
| 16-19 | Index of vertex shader input register which the 13th attribute will be stored in. |
| 20-23 | Index of vertex shader input register which the 14th attribute will be stored in. |
| 24-27 | Index of vertex shader input register which the 15th attribute will be stored in. |
| 28-31 | Index of vertex shader input register which the 16th attribute will be stored in. |
This register sets the vertex shader input register index which will correspond to each attribute contained by the input buffer for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the vertex shader program, v5 will contain the input buffer's 9th attribute.
GPUREG_VSH_OUTMAP_MASK
| Bits | Description |
|---|---|
| 0 | Enable bit for vertex shader's o0 output register. (1 = o0 enabled, 0 = o0 disabled) |
| 1 | Enable bit for vertex shader's o1 output register. (1 = o1 enabled, 0 = o1 disabled) |
| 2 | Enable bit for vertex shader's o2 output register. (1 = o2 enabled, 0 = o2 disabled) |
| 3 | Enable bit for vertex shader's o3 output register. (1 = o3 enabled, 0 = o3 disabled) |
| 4 | Enable bit for vertex shader's o4 output register. (1 = o4 enabled, 0 = o4 disabled) |
| 5 | Enable bit for vertex shader's o5 output register. (1 = o5 enabled, 0 = o5 disabled) |
| 6 | Enable bit for vertex shader's o6 output register. (1 = o6 enabled, 0 = o6 disabled) |
| 7 | Enable bit for vertex shader's o7 output register. (1 = o7 enabled, 0 = o7 disabled) |
| 8 | Enable bit for vertex shader's o8 output register. (1 = o8 enabled, 0 = o8 disabled) |
| 9 | Enable bit for vertex shader's o9 output register. (1 = o9 enabled, 0 = o9 disabled) |
| 10 | Enable bit for vertex shader's o10 output register. (1 = o10 enabled, 0 = o10 disabled) |
| 11 | Enable bit for vertex shader's o11 output register. (1 = o11 enabled, 0 = o11 disabled) |
| 12 | Enable bit for vertex shader's o12 output register. (1 = o12 enabled, 0 = o12 disabled) |
| 13 | Enable bit for vertex shader's o13 output register. (1 = o13 enabled, 0 = o13 disabled) |
| 14 | Enable bit for vertex shader's o14 output register. (1 = o14 enabled, 0 = o14 disabled) |
| 15 | Enable bit for vertex shader's o15 output register. (1 = o15 enabled, 0 = o15 disabled) |
This register toggles the vertex shader units' output registers.
GPUREG_VSH_CODETRANSFER_END
| Bits | Description |
|---|---|
| 0 | Code data transfer end signal bit. |
This register's value should be set to 1 in order to finalize the transfer of vertex shader code. It is unknown whether this register is used for other functions.
GPUREG_VSH_FLOATUNIFORM_CONFIG
| Bits | Description |
|---|---|
| 0-6 | Target float vec4 vertex shader uniform ID for transfer. (range 0-95, where 0 = c0 and 95 = c95) |
| 31 | Float vec4 vertex shader uniform data transfer mode. (0 = float24, 1 = float32) |
This register sets the target float vec4 vertex shader uniform ID and transfer mode for the data transfer system. As such it is typically used right before GPUREG_VSH_FLOATUNIFORM_DATA, though writing to one register does not make writing to the other mandatory.
GPUREG_VSH_FLOATUNIFORM_DATA
| Bits | Description |
|---|---|
| 0-31 | Float vec4 vertex shader uniform data. (format depends on transfer mode, see below for details) |
This register is used to set the value of float vec4 vertex shader uniform registers. The data format which should be written to it depends on the transfer mode set with GPUREG_VSH_FLOATUNIFORM_CONFIG. This register functions as a FIFO queue : after each time a uniform register is successfully set, the target uniform ID value is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to GPUREG_VSH_FLOATUNIFORM_CONFIG.
- In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes :
- first word : ZZWWWWWW
- second word : YYYYZZZZ
- third word : XXXXXXYY
- In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.
GPUREG_VSH_CODETRANSFER_CONFIG
| Bits | Description |
|---|---|
| 0-11 | Target vertex shader code offset for data transfer. |
This register is used to set the offset at which upcoming vertex shader code data transferred through GPUREG_VSH_CODETRANSFER_DATA should be written.
NOTE : as we do not yet know what a shader program's maximum size is yet, we also do not know how many bits the code offset parameter holds. The biggest shader binary observed so far was 2422 instructions long. The shader control flow instructions only have room to address 12 bits though, so it's likely that the maximum is 4095.
GPUREG_VSH_CODETRANSFER_DATA
| Bits | Description |
|---|---|
| 0-31 | Vertex shader instruction data. |
This register is used to transfer vertex shader code data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader code memory bank at the offset initially set by GPUREG_VSH_CODETRANSFER_CONFIG. The offset in question is incremented after each write to this register.
GPUREG_VSH_OPDESCS_CONFIG
| Bits | Description |
|---|---|
| 0-6 | Target vertex shader operand descriptor offset for data transfer. |
This register is used to set the offset at which upcoming vertex shader operand descriptor data transferred through GPUREG_VSH_OPDESCS_DATA should be written.
GPUREG_VSH_OPDESCS_DATA
| Bits | Description |
|---|---|
| 0-31 | Vertex shader operand descriptor data. |
This register is used to transfer vertex shader operand descriptor data. This register behaves as a FIFO queue : each write to this register writes the provided value to the GPU vertex shader operand descriptor memory bank at the offset initially set by GPUREG_VSH_OPDESCS_CONFIG. The offset in question is incremented after each write to this register.