SHA Registers - Revision history

Profi200: /* SHA_CNT */

2019-05-15T16:44:40Z

SHA_CNT

← Older revision		Revision as of 20:44, 15 May 2019
Line 44:		Line 44:
	\|-		\|-
	\| 2		\| 2
	\| ~~Enable IRQ~~ 0		\| Input DMA enable (1= enable, 0=disable)
	\|-		\|-
	\| 3		\| 3
Line 65:		Line 65:
	\|-		\|-
	\| 10		\| 10
	\| ~~Enable IRQ~~ 1		\| Output DMA enable (1= enable, 0=disable)
	\|-		\|-
	\| 16		\| 16
Line 73:		Line 73:
	\| ?		\| ?
	\|}		\|}

			Bit 8 is used when boot9 chains eMMC reads with AES and SHA to to load, decrypt and verify FIRM partitions.

	== SHA_BLKCNT ==		== SHA_BLKCNT ==

2017-01-06T01:03:44Z

Registers

← Older revision		Revision as of 04:03, 6 January 2017
Line 26:		Line 26:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SHA_INFIFO~~\|~~SHA_INFIFO~~]]		\| [[#SHA_FIFO\|SHA_FIFO]]
	\| 0x1000A080		\| 0x1000A080
	\| 0x40		\| 0x40
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	\|-		\|-
	\| 1		\| 1
	\| ~~Pad input~~/~~final round~~		\| Final round (1=enable/busy, 0=normal)
	\|-		\|-
	\| 2		\| 2
	\| ?		\| Enable IRQ 0
	\|-		\|-
	\| 3		\| 3
	\| Output Endianess (0=~~Little endian~~, 1=~~Big endian~~)		\| Output Endianess (0=little, 1=big)
	\|-		\|-
	\| 4-5		\| 4-5
Line 59:		Line 59:
	\|-		\|-
	\| 8		\| 8
	\| ~~Unknown.~~ When set, the entire ARM9 hangs/crashes when attempting to read SHA_INFIFO.		\| Clear FIFO? When set, the entire ARM9 hangs/crashes when attempting to read SHA_INFIFO.
	\|-		\|-
	\| 9		\| 9
	\| ~~Unknown. This bit seems to be cleared by reading from SHA_INFIFO.~~		\| Enable FIFO (1=fifo, 0=write-only)
	\|-		\|-
	\| 10		\| 10
	\| ?		\| Enable IRQ 1
	\|-		\|-
	\| 16		\| 16
Line 71:		Line 71:
	\|-		\|-
	\| 17		\| 17
	\| ~~1 when FIFO expects read/write~~		\| ?
	\|}		\|}

Line 80:		Line 80:
	This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register.		This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register.

	== ~~SHA_INFIFO~~ ==		== SHA_FIFO ==
	The data to be hashed must be written here. It does not matter what offset is written to.		The data to be hashed must be written here. It does not matter what offset is written to.

2016-03-09T00:35:57Z

SHA_CNT

2016-03-09T00:24:21Z

SHA_CNT

← Older revision		Revision as of 03:24, 9 March 2016
Line 37:		Line 37:
	! Description		! Description
	\|-		\|-
	\| 0-1		\| 0
	\| ~~0=Hash ready,~~ 1=~~Normal~~, 2=~~Final Round~~		\| Start (1=enable/busy, 0=idle)
			\|-
			\| 1
			\| Pad input
	\|-		\|-
	\| 2		\| 2
Line 65:		Line 68:
	\|-		\|-
	\| 16		\| 16
	\| ~~Enable~~		\| ?
	\|-		\|-
	\| 17		\| 17

2015-04-18T08:08:49Z

SHA_CNT

← Older revision		Revision as of 12:08, 18 April 2015
Line 56:		Line 56:
	\|-		\|-
	\| 8		\| 8
	\| Unknown. When set, the entire ARM9 hangs/crashes when attempting to read ~~REG_SHA_IN~~.		\| Unknown. When set, the entire ARM9 hangs/crashes when attempting to read SHA_INFIFO.
	\|-		\|-
	\| 9		\| 9
	\| ?		\| Unknown. This bit seems to be cleared by reading from SHA_INFIFO.
	\|-		\|-
	\| 10		\| 10

2015-03-19T23:41:30Z

← Older revision		Revision as of 02:41, 20 March 2015
Line 78:		Line 78:

	== SHA_INFIFO ==		== SHA_INFIFO ==
	The data to be hashed must be written here. ~~The data must be padded with 0x00s~~ to ~~align with the register size (if needed)~~.		The data to be hashed must be written here. It does not matter what offset is written to.

2015-03-19T23:37:56Z

← Older revision		Revision as of 02:37, 20 March 2015
Line 14:		Line 14:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SHA_INPUTSZ~~\|~~SHA_INPUTSZ~~]]		\| [[#SHA_BLKCNT\|SHA_BLKCNT]]
	\| 0x1000A004		\| 0x1000A004
	\| 4		\| 4
Line 26:		Line 26:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SHA_IN~~\|~~SHA_IN~~]]		\| [[#SHA_INFIFO\|SHA_INFIFO]]
	\| 0x1000A080		\| 0x1000A080
	\| 0x40		\| 0x40
Line 71:		Line 71:
	\|}		\|}

	== ~~SHA_INPUTSZ~~ ==		== SHA_BLKCNT ==
	This reg contains the total size of the data written to REG_SHA_IN.		This reg contains the total size of the data written to REG_SHA_IN, this field is updated when performing hash-function final-round.

	== SHA_HASH ==		== SHA_HASH ==
	This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register.		This reg contains the SHA* hash after the final round, and the internal state during normal rounds. It is possible to write the internal state using this register.

	== ~~SHA_IN~~ ==		== SHA_INFIFO ==
	The data to be hashed must be written here. The data must be padded with 0x00s to align with the register size (if needed).		The data to be hashed must be written here. The data must be padded with 0x00s to align with the register size (if needed).

2015-03-19T23:26:09Z

← Older revision		Revision as of 02:26, 20 March 2015
Line 39:		Line 39:
	\| 0-1		\| 0-1
	\| 0=Hash ready, 1=Normal, 2=Final Round		\| 0=Hash ready, 1=Normal, 2=Final Round
			\|-
			\| 2
			\| ?
	\|-		\|-
	\| 3		\| 3
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	\| 4-5		\| 4-5
	\| Mode (0=SHA256, 1=SHA224, 2=3=SHA1)		\| Mode (0=SHA256, 1=SHA224, 2=3=SHA1)
			\|-
			\| 6
			\| ?
			\|-
			\| 7
			\| ?
	\|-		\|-
	\| 8		\| 8
	\| Unknown. When set, the entire ARM9 hangs/crashes when attempting to read REG_SHA_IN.		\| Unknown. When set, the entire ARM9 hangs/crashes when attempting to read REG_SHA_IN.
			\|-
			\| 9
			\| ?
			\|-
			\| 10
			\| ?
	\|-		\|-
	\| 16		\| 16

2015-03-19T23:10:21Z

2015-03-19T23:08:22Z

← Older revision		Revision as of 02:08, 20 March 2015
Line 49:		Line 49:
	\| Unknown. When set, the entire ARM9 hangs/crashes when attempting to read REG_SHA_IN.		\| Unknown. When set, the entire ARM9 hangs/crashes when attempting to read REG_SHA_IN.
	\|-		\|-
	\| 24		\| 16
	\| Enable		\| Enable
	\|-		\|-
	\| 25		\| 17
	\| 1 when FIFO expects read/write		\| 1 when FIFO expects read/write
	\|}		\|}