GPU/Internal Registers - Revision history

Kynex7510: Texunit addresses order

2025-08-03T08:58:13Z

Texunit addresses order

← Older revision		Revision as of 12:58, 3 August 2025
Line 4,713:		Line 4,713:
	\|}		\|}

	Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.		Otherwise, ADDR(1) points to a 2D texture, and the rest are empty. Addresses shall be ordered from lowest to highest, otherwise some faces might not render correctly.

	=== GPUREG_TEXUNIT''i''_SHADOW ===		=== GPUREG_TEXUNIT''i''_SHADOW ===

2025-03-17T11:32:27Z

← Older revision		Revision as of 14:32, 17 March 2025
Line 6,332:		Line 6,332:
	\|-		\|-
	\| 24		\| 24
	\| ~~0x1~~		\| unsigned, Vertical flip? (0 = enable, 1 = disable)
	\|}		\|}

2024-10-06T11:27:25Z

← Older revision		Revision as of 15:27, 6 October 2024
Line 5,254:		Line 5,254:
	\|}		\|}

	Using ~~previous~~ source in the first TEV stage returns the ~~primary color, while previous~~ buffer returns zero.		Using Previous (15) as a source in the first TEV stage returns the value of source 3. If source 3 has Previous it returns zero. Previous buffer (13) always returns zero.

	=== GPUREG_TEXENV''i''_OPERAND ===		=== GPUREG_TEXENV''i''_OPERAND ===

2024-01-24T15:36:55Z

Update GPUREG_VSH_COM_MODE from hardware findings

← Older revision		Revision as of 18:36, 24 January 2024
Line 7,731:		Line 7,731:

	This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.		This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.
			When disabled and the geometry unit is not in use, as configured by GPUREG_GEOSTAGE_CONFIG, uniforms, outmap mask, program code and swizzle data are propagated to the geometry shader unit.

	=== GPUREG_START_DRAW_FUNC0 ===		=== GPUREG_START_DRAW_FUNC0 ===

2023-09-13T16:22:59Z

GPUREG_SH_OUTMAP_Oi

← Older revision		Revision as of 20:22, 13 September 2023
Line 4,161:		Line 4,161:

	These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.		These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.

	Semantics that have not been mapped to a component of an output register have a value of 1		Semantics that have not been mapped to a component of an output register have a value of 1

2023-09-13T16:21:29Z

GPUREG_SH_OUTMAP_Oi

← Older revision		Revision as of 20:21, 13 September 2023
Line 4,161:		Line 4,161:

	These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.		These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.
			Semantics that have not been mapped to a component of an output register have a value of 1

	Semantic values:		Semantic values:

2023-08-25T19:38:02Z

Document previous usage in the first TEV stage

← Older revision		Revision as of 23:38, 25 August 2023
Line 5,251:		Line 5,251:
	\| Previous		\| Previous
	\|}		\|}

			Using previous source in the first TEV stage returns the primary color, while previous buffer returns zero.

	=== GPUREG_TEXENV''i''_OPERAND ===		=== GPUREG_TEXENV''i''_OPERAND ===

2023-08-19T02:50:26Z

GPUREG_LIGHTING_CONFIG1

← Older revision		Revision as of 06:50, 19 August 2023
Line 6,902:		Line 6,902:
	\| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)		\| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
	\|-		\|-
	\| 20~~-22~~		\| 20
	\| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)		\| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 1 = disabled)
	\|-		\|-
	\| 21		\| 21
	\| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)		\| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 1 = disabled)
	\|-		\|-
	\| 22		\| 22
	\| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)		\| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 1 = disabled)
	\|-		\|-
	\| 24		\| 24

2019-01-18T02:11:15Z

Command Header: Size field is 8-bit, not 11-bit (tested on hardware)

← Older revision		Revision as of 05:11, 18 January 2019
Line 26:		Line 26:
	\| Parameter mask		\| Parameter mask
	\|-		\|-
	\| 20-30		\| 20-27
	\| Number of extra parameters (may be zero)		\| Number of extra parameters (may be zero)
			\|-
			\| 28-30
			\| Unused
	\|-		\|-
	\| 31		\| 31

2018-07-04T10:15:00Z

GPUREG_TEXUNIT3_PROCTEX5

← Older revision		Revision as of 14:15, 4 July 2018
Line 5,050:		Line 5,050:
	\| 24-31		\| 24-31
	\| unsigned, mipmap level 3 offset (usually 0xE0)		\| unsigned, mipmap level 3 offset (usually 0xE0)
	\|-
	\|
	~~\| Note: mipmap level 4-7 seems to be hardcoded at offset 0xF0, 0xF8, 0xFC and 0xFE~~
	\|}		\|}

	This register is used to set the procedural texture unit's offset.		This register is used to set the procedural texture unit's offset. Mipmap level 4-7 seems to be hardcoded at offset 0xF0, 0xF8, 0xFC and 0xFE .

	=== GPUREG_PROCTEX_LUT ===		=== GPUREG_PROCTEX_LUT ===