GPU/External Registers - Revision history

Made: /* Hotspot Profiling */

2025-12-02T13:42:58Z

Hotspot Profiling

← Older revision		Revision as of 16:42, 2 December 2025
Line 171:		Line 171:
	\| 0x1EF0006C		\| 0x1EF0006C
	\| 0xFFFFFFFF		\| 0xFFFFFFFF
	\| Result FIFO ~~(4 * u32)~~		\| Result FIFO
	\|}		\|}

Made: Add hotspot profiling registers

2025-11-09T19:28:26Z

Add hotspot profiling registers

@@ Line 57: / Line 57: @@
 | ?
 | Writes 0xFF2 on GPU init.
 |-
 | 0x1EF000C0
@@ Line 144: / Line 149: @@
 These registers are used by [[GSP Shared Memory#GX SetMemoryFill|GX SetMemoryFill]].
 == LCD Source Framebuffer Setup ==

Kynex7510: Update T2T constraints

2025-07-22T18:53:23Z

Update T2T constraints

@@ Line 658: / Line 658: @@
 * Width dimensions must be >= 64.
 * Height dimensions must be >= 32.
-Format conversion results:
+Format conversion results: same as tiled->linear.
 === TextureCopy ===

Kynex7510: T2T

2025-07-22T10:40:53Z

T2T

@@ Line 647: / Line 647: @@
 | RGBA4 -> RGBA4
 | style="background: lightgreen" | Has interrupt, correct output
 |}

Kynex7510 at 21:28, 5 July 2025

2025-07-05T19:28:57Z

← Older revision		Revision as of 23:28, 5 July 2025
Line 565:		Line 565:
	* Width dimensions are required to be aligned to 16 bytes when doing RGB8 transfers.		* Width dimensions are required to be aligned to 16 bytes when doing RGB8 transfers.
	** Otherwise they are required to be aligned to 8 bytes.		** Otherwise they are required to be aligned to 8 bytes.
	* If downscale is used, input and output dimensions should be the same, and width/2 must also follow alignment constraints.		* If downscale is used, input and output dimensions should be the same (otherwise the output is glitched), and width/2 must also follow alignment constraints.

	Format conversion results:		Format conversion results:
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	\|-		\|-
	\| RGB565 -> RGB565		\| RGB565 -> RGB565
	\| style="background: ~~yellow~~" \| Has interrupt, output ~~not tested~~		\| style="background: lightgreen" \| Has interrupt, correct output
	\|-		\|-
	\| RGB565 -> RGB5A1		\| RGB565 -> RGB5A1
	\| style="background: ~~yellow~~" \| Has interrupt, output ~~not tested~~		\| style="background: lightgreen" \| Has interrupt, correct output
	\|-		\|-
	\| RGB565 -> RGBA4		\| RGB565 -> RGBA4
	\| style="background: ~~yellow~~" \| Has interrupt, output ~~not tested~~		\| style="background: lightgreen" \| Has interrupt, correct output
	\|-		\|-
	\| RGB5A1 -> RGBA8		\| RGB5A1 -> RGBA8
Line 625:		Line 625:
	\|-		\|-
	\| RGB5A1 -> RGB565		\| RGB5A1 -> RGB565
	\| style="background: ~~yellow~~" \| Has interrupt, output ~~not tested~~		\| style="background: lightgreen" \| Has interrupt, correct output
	\|-		\|-
	\| RGB5A1 -> RGB5A1		\| RGB5A1 -> RGB5A1
	\| style="background: ~~yellow~~" \| Has interrupt, output ~~not tested~~		\| style="background: lightgreen" \| Has interrupt, correct output
	\|-		\|-
	\| RGB5A1 -> RGBA4		\| RGB5A1 -> RGBA4
	\| style="background: ~~yellow~~" \| Has interrupt, output ~~not tested~~		\| style="background: lightgreen" \| Has interrupt, correct output
	\|-		\|-
	\| RGBA4 -> RGBA8		\| RGBA4 -> RGBA8
Line 640:		Line 640:
	\|-		\|-
	\| RGBA4 -> RGB565		\| RGBA4 -> RGB565
	\| style="background: ~~yellow~~" \| Has interrupt, output ~~not tested~~		\| style="background: lightgreen" \| Has interrupt, correct output
	\|-		\|-
	\| RGBA4 -> RGB5A1		\| RGBA4 -> RGB5A1
	\| style="background: ~~yellow~~" \| Has interrupt, output ~~not tested~~		\| style="background: lightgreen" \| Has interrupt, correct output
	\|-		\|-
	\| RGBA4 -> RGBA4		\| RGBA4 -> RGBA4
	\| style="background: ~~yellow~~" \| Has interrupt, output ~~not tested~~		\| style="background: lightgreen" \| Has interrupt, correct output
	\|}		\|}

Kynex7510: PPF rewrites + add T2L stuff

2025-06-19T17:09:11Z

PPF rewrites + add T2L stuff

Show changes

Kynex7510 at 18:45, 1 June 2025

2025-06-01T16:45:13Z

← Older revision		Revision as of 20:45, 1 June 2025
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	Memory fills are used to initialize buffers in memory with a given value, similar to memset. A memory fill is triggered by setting bit0 in the control register. Doing so aborts any running memory fills on that filling unit. Upon completion, the hardware unsets bit0 and sets bit1 and fires interrupt PSC0.		Memory fills are used to initialize buffers in memory with a given value, similar to memset. A memory fill is triggered by setting bit0 in the control register. Doing so aborts any running memory fills on that filling unit. Upon completion, the hardware unsets bit0 and sets bit1 and fires interrupt PSC0.

	The addresses must ~~not~~ be part of ~~FCRAM~~.		The addresses must be part of VRAM.

	These registers are used by [[GSP Shared Memory#GX SetMemoryFill\|GX SetMemoryFill]].		These registers are used by [[GSP Shared Memory#GX SetMemoryFill\|GX SetMemoryFill]].

Kynex7510 at 21:57, 17 May 2025

2025-05-17T19:57:10Z

← Older revision		Revision as of 23:57, 17 May 2025
Line 140:		Line 140:

	Memory fills are used to initialize buffers in memory with a given value, similar to memset. A memory fill is triggered by setting bit0 in the control register. Doing so aborts any running memory fills on that filling unit. Upon completion, the hardware unsets bit0 and sets bit1 and fires interrupt PSC0.		Memory fills are used to initialize buffers in memory with a given value, similar to memset. A memory fill is triggered by setting bit0 in the control register. Doing so aborts any running memory fills on that filling unit. Upon completion, the hardware unsets bit0 and sets bit1 and fires interrupt PSC0.

			The addresses must not be part of FCRAM.

	These registers are used by [[GSP Shared Memory#GX SetMemoryFill\|GX SetMemoryFill]].		These registers are used by [[GSP Shared Memory#GX SetMemoryFill\|GX SetMemoryFill]].

Kynex7510: moved

2025-05-12T13:07:08Z

moved

← Older revision		Revision as of 17:07, 12 May 2025
Line 501:		Line 501:

	These registers are used by [[GSP_Shared_Memory\|GX command]] 3 and 4. For cmd4, *0x1EF00C18 \|= 1 is used instead of just writing value 1. The DisplayTransfer registers are only used if bit 3 of the flags is unset and ignored otherwise. The TextureCopy registers are likewise only used if bit 3 is set, and ignored otherwise.		These registers are used by [[GSP_Shared_Memory\|GX command]] 3 and 4. For cmd4, *0x1EF00C18 \|= 1 is used instead of just writing value 1. The DisplayTransfer registers are only used if bit 3 of the flags is unset and ignored otherwise. The TextureCopy registers are likewise only used if bit 3 is set, and ignored otherwise.

			The minimum supported dimension for output is 64x64, anything lower will hang the engine.

	==== Flags Register - 0x1EF00C10 ====		==== Flags Register - 0x1EF00C10 ====

Kynex7510: Miss Information

2025-04-13T09:35:42Z

Miss Information

← Older revision		Revision as of 13:35, 13 April 2025
Line 562:		Line 562:
	line width = (16 * 24) >> 4 = 24		line width = (16 * 24) >> 4 = 24
	gap = line width		gap = line width
	size = (16 * 32 * ~~24) >> 4~~ = ~~768~~		size = 16 * 32 * 3 = 1536

	By correctly calculating the input and output gap sizes it is possible to use this functionality to copy arbitrary sub-rectangles between differently-sized framebuffers or textures, which is one of its main uses over a regular no-conversion DisplayTransfer. When copying tiled textures/framebuffers it's important to remember that the contents of a tile are laid out sequentially in memory, and so this should be taken into account when calculating the transfer parameters.		By correctly calculating the input and output gap sizes it is possible to use this functionality to copy arbitrary sub-rectangles between differently-sized framebuffers or textures, which is one of its main uses over a regular no-conversion DisplayTransfer. When copying tiled textures/framebuffers it's important to remember that the contents of a tile are laid out sequentially in memory, and so this should be taken into account when calculating the transfer parameters.