Corelink DMA Engines - Revision history

Profi200: /* XDMA Peripheral IDs */

2021-01-29T11:51:36Z

XDMA Peripheral IDs

@@ Line 138: / Line 138: @@
 | 0
 | Process9
-| CTRCARD
+| CTRCARD1 (0x10004000?)
 |-
 | 7
 | Process9
-| SHA
+| SHA out
 |-
 |}

Unknown: /* CDMA Peripheral IDs */

2018-06-29T08:13:30Z

CDMA Peripheral IDs

← Older revision		Revision as of 12:13, 29 June 2018
Line 93:		Line 93:
	\|-		\|-
	\| 0x12		\| 0x12
	\| mvd		\| mvd (y2r2)
	\| ~~Related to y2r2~~		\| SetSendingY
	\|-		\|-
	\| 0x13		\| 0x13
	\| mvd		\| mvd (y2r2)
	\| ~~Related to y2r2~~		\| SetSendingU
	\|-		\|-
	\| 0x14		\| 0x14
	\| mvd		\| mvd (y2r2)
	\| ~~Related to y2r2~~		\| SetSendingV
	\|-		\|-
	\| 0x15		\| 0x15
	\| mvd		\| mvd (y2r2)
	\| ~~Related to y2r2~~		\| SetSendingYUV
	\|-		\|-
	\| 0x16		\| 0x16
	\| mvd		\| mvd (y2r2)
	\| ~~Related to y2r2~~		\| SetReceiving
	\|-		\|-
	\| 0x17		\| 0x17

Unknown: /* CDMA Peripheral IDs */ 0x14 is related to y2r2

2018-06-29T01:37:30Z

CDMA Peripheral IDs: 0x14 is related to y2r2

← Older revision		Revision as of 05:37, 29 June 2018
Line 102:		Line 102:
	\| 0x14		\| 0x14
	\| mvd		\| mvd
	\| ?		\| Related to y2r2
	\|-		\|-
	\| 0x15		\| 0x15

Unknown: /* CDMA Peripheral IDs */

2018-06-29T01:09:00Z

CDMA Peripheral IDs

← Older revision		Revision as of 05:09, 29 June 2018
Line 94:		Line 94:
	\| 0x12		\| 0x12
	\| mvd		\| mvd
	\| ?		\| Related to y2r2
	\|-		\|-
	\| 0x13		\| 0x13
	\| mvd		\| mvd
	\| ?		\| Related to y2r2
	\|-		\|-
	\| 0x14		\| 0x14
Line 106:		Line 106:
	\| 0x15		\| 0x15
	\| mvd		\| mvd
	\| ?		\| Related to y2r2
	\|-		\|-
	\| 0x16		\| 0x16
	\| mvd		\| mvd
	\| ?		\| Related to y2r2
	\|-		\|-
	\| 0x17		\| 0x17
	\| mvd		\| mvd
	\| ?		\| Related to l2b
	\|-		\|-
	\| 0x18		\| 0x18
	\| mvd		\| mvd
	\| ?		\| Related to l2b
	\|-		\|-
	\| 0x19		\| 0x19
	\| mvd		\| mvd
	\| ?		\| Related to l2b
	\|-		\|-
	\| 0x1A		\| 0x1A
	\| mvd		\| mvd
	\| ?		\| Related to l2b
	\|}		\|}

TuxSH: /* DmaConfig */

2017-08-09T19:24:12Z

DmaConfig

← Older revision		Revision as of 23:24, 9 August 2017
Line 7:		Line 7:
	sint8_t channel_sel; // @0 Selects which DMA channel to use: 0-7, -1 = don't care.		sint8_t channel_sel; // @0 Selects which DMA channel to use: 0-7, -1 = don't care.
	uint8_t endian_swap_size; // @1 Accepted values: 0=none, 2=16bit, 4=32bit, 8=64bit.		uint8_t endian_swap_size; // @1 Accepted values: 0=none, 2=16bit, 4=32bit, 8=64bit.
	uint8_t flags; // @2 bit0: ~~DST_IS_PERIPHERAL~~, bit1: ~~SRC_IS_PERIPHERAL~~, bit2: SHALL_BLOCK, bit3: KEEP_ALIVE, bit6: ~~DST_IS_RAM~~, bit7: ~~SRC_IS_RAM~~		uint8_t flags; // @2 bit0: SRC_IS_PERIPHERAL, bit1: DST_IS_PERIPHERAL, bit2: SHALL_BLOCK, bit3: KEEP_ALIVE, bit6: SRC_IS_RAM, bit7: DST_IS_RAM
	uint8_t padding;		uint8_t padding;
	DmaSubConfig dst_cfg;		DmaSubConfig dst_cfg;

TuxSH: /* DmaConfig */

2017-08-09T13:11:24Z

DmaConfig

← Older revision		Revision as of 17:11, 9 August 2017
Line 16:		Line 16:
	sint8_t peripheral_id; // @0 If not *_IS_RAM set, this must be < 0x1E.		sint8_t peripheral_id; // @0 If not *_IS_RAM set, this must be < 0x1E.
	uint8_t allowed_burst_sizes; // @1 Accepted values: 4, 8, 4\|8 = 12, 1\|2\|4\|8 = 15		uint8_t allowed_burst_sizes; // @1 Accepted values: 4, 8, 4\|8 = 12, 1\|2\|4\|8 = 15
	sint16_t ~~max_burst_total~~; // @2 ~~Burst length * burst size~~		sint16_t gather_granule_size; // @2
	sint16_t ~~transfer_size?~~; // @4 ~~Must~~ not be 0 if peripheral_id == 0xFF.		sint16_t gather_stride; // @4 Has to be >= 0, must not be 0 if peripheral_id == 0xFF.
	sint16_t ~~unk4~~; // @6		sint16_t scatter_granule_size; // @6
	sint16_t ~~transfer_stride?~~; // @8		sint16_t scatter_stride; // @8 Can be negative.
	}		}

Line 28:		Line 28:
	.peripheral_id = 0xFF,		.peripheral_id = 0xFF,
	.allowed_burst_sizes = 1 \| 2 \| 4 \| 8,		.allowed_burst_sizes = 1 \| 2 \| 4 \| 8,
	.~~max_burst_total~~ = 0x80,		.gather_granule_size = 0x80,
	.~~transfer_size?~~ = 0,		.gather_stride = 0,
	.~~unk4~~ = 0x80,		.scatter_granule_size = 0x80,
	.~~transfer_stride?~~ = 0,		.scatter_stride = 0,

	If SHALL_BLOCK is set, the thread will sleep until the DMA engine is ready. If not set, the SVC will return 0xD04007F0 if the DMA channel is busy.		If SHALL_BLOCK is set, the thread will sleep until the DMA engine is ready. If not set, the SVC will return 0xD04007F0 if the DMA channel is busy.

TuxSH at 20:43, 7 August 2017

2017-08-07T18:43:52Z

← Older revision		Revision as of 22:43, 7 August 2017
Line 7:		Line 7:
	sint8_t channel_sel; // @0 Selects which DMA channel to use: 0-7, -1 = don't care.		sint8_t channel_sel; // @0 Selects which DMA channel to use: 0-7, -1 = don't care.
	uint8_t endian_swap_size; // @1 Accepted values: 0=none, 2=16bit, 4=32bit, 8=64bit.		uint8_t endian_swap_size; // @1 Accepted values: 0=none, 2=16bit, 4=32bit, 8=64bit.
	uint8_t flags; // @2 bit0: ~~DST_CFG~~, bit1: ~~SRC_CFG~~, bit2: SHALL_BLOCK, bit3: KEEP_ALIVE, bit6: ~~DST_ALT_CFG~~, bit7: ~~SRC_ALT_CFG~~		uint8_t flags; // @2 bit0: DST_IS_PERIPHERAL, bit1: SRC_IS_PERIPHERAL, bit2: SHALL_BLOCK, bit3: KEEP_ALIVE, bit6: DST_IS_RAM, bit7: SRC_IS_RAM
	uint8_t padding;		uint8_t padding;
	DmaSubConfig dst_cfg;		DmaSubConfig dst_cfg;
Line 14:		Line 14:

	struct DmaSubConfig {		struct DmaSubConfig {
	sint8_t peripheral_id; // @0 If not *~~_ALT_CFG~~ set, this must be < 0x1E.		sint8_t peripheral_id; // @0 If not *_IS_RAM set, this must be < 0x1E.
	uint8_t ~~burst_size_raw~~; ~~// (1 << raw size) bytes, bit4 is ignored?~~ // @1 Accepted values: 4~~=fixed_addr??~~, 8=~~increment_addr??~~, 12=~~lgy_fb_copy?,~~ 15~~=userspace_copy? (??)~~		uint8_t allowed_burst_sizes; // @1 Accepted values: 4, 8, 4\|8 = 12, 1\|2\|4\|8 = 15
	sint16_t ~~max_burst_size_bits~~; // @2 ~~Must be 0 or multiple of 4?~~		sint16_t max_burst_total; // @2 Burst length * burst size
	sint16_t transfer_size?; // @4 Must not be 0 if peripheral_id == 0xFF.		sint16_t transfer_size?; // @4 Must not be 0 if peripheral_id == 0xFF.
	sint16_t unk4; // @6		sint16_t unk4; // @6
Line 22:		Line 22:
	}		}

	If ~~SRC_CFG~~/~~DST_CFG~~ is set in the flags field, the configuration for src/dst is loaded from src_cfg/dst_cfg respectively. If the *~~_ALT_CFG~~ flag is set same thing goes, except byte0 of each cfg is forced to 0xFF. ~~ALT_CFG~~ has priority over ~~CFG~~.		If SRC_IS_PERIPHERAL/SRC_IS_PERIPHERAL is set in the flags field, the configuration for src/dst is loaded from src_cfg/dst_cfg respectively and the transfer will be done from/to a fixed address. If the _IS_RAM flag is set same thing goes, except byte0 of each cfg is forced to 0xFF (RAM) and the transfer will be done from/to an incrementing address. _IS_RAM has priority over _IS_PERIPHERAL.

	If ~~CFG~~ or ~~ALT_CFG~~ is ~~not~~ set, default configuration is loaded:		If neither _IS_PERIPHERAL or _IS_RAM is set, default configuration is loaded:

	.peripheral_id = 0xFF,		.peripheral_id = 0xFF,
	.~~unk2~~ = ~~0xF~~,		.allowed_burst_sizes = 1 \| 2 \| 4 \| 8,
	.~~unk3~~ = 0x80,		.max_burst_total = 0x80,
	.transfer_size = 0,		.transfer_size? = 0,
	.unk4 = 0x80,		.unk4 = 0x80,
	.~~unk5~~ = 0,		.transfer_stride? = 0,

	~~Checks suggest that unk2 of DmaSubConfig equalling 4 means NO_INCREMENT (don't increment after read/write).~~

	If SHALL_BLOCK is set, the thread will sleep until the DMA engine is ready. If not set, the SVC will return 0xD04007F0 if the DMA channel is busy.		If SHALL_BLOCK is set, the thread will sleep until the DMA engine is ready. If not set, the SVC will return 0xD04007F0 if the DMA channel is busy.
Line 138:		Line 136:
	! Description		! Description
	\|-		\|-
	\| 0 ~~(?)~~		\| 0
	\| Process9		\| Process9
	\| CTRCARD		\| CTRCARD

TuxSH: /* XDMA Peripheral IDs */

2017-08-07T07:55:03Z

XDMA Peripheral IDs

← Older revision		Revision as of 11:55, 7 August 2017
Line 137:		Line 137:
	! Module		! Module
	! Description		! Description
			\|-
			\| 0 (?)
			\| Process9
			\| CTRCARD
	\|-		\|-
	\| 7		\| 7

TuxSH: /* XDMA Peripheral IDs */

2017-08-07T07:53:23Z

XDMA Peripheral IDs

← Older revision		Revision as of 11:53, 7 August 2017
Line 137:		Line 137:
	! Module		! Module
	! Description		! Description
			\|-
			\| 7
			\| Process9
			\| SHA
	\|-		\|-
	\|}		\|}

TuxSH at 22:35, 6 August 2017

2017-08-06T20:35:52Z

← Older revision		Revision as of 00:35, 7 August 2017
Line 7:		Line 7:
	sint8_t channel_sel; // @0 Selects which DMA channel to use: 0-7, -1 = don't care.		sint8_t channel_sel; // @0 Selects which DMA channel to use: 0-7, -1 = don't care.
	uint8_t endian_swap_size; // @1 Accepted values: 0=none, 2=16bit, 4=32bit, 8=64bit.		uint8_t endian_swap_size; // @1 Accepted values: 0=none, 2=16bit, 4=32bit, 8=64bit.
	uint8_t flags; // @2 bit0: DST_CFG, bit1: SRC_CFG, bit2: SHALL_BLOCK, bit3: ~~???~~, bit6: DST_ALT_CFG, bit7: SRC_ALT_CFG		uint8_t flags; // @2 bit0: DST_CFG, bit1: SRC_CFG, bit2: SHALL_BLOCK, bit3: KEEP_ALIVE, bit6: DST_ALT_CFG, bit7: SRC_ALT_CFG
	uint8_t padding;		uint8_t padding;
	DmaSubConfig dst_cfg;		DmaSubConfig dst_cfg;
Line 15:		Line 15:
	struct DmaSubConfig {		struct DmaSubConfig {
	sint8_t peripheral_id; // @0 If not *_ALT_CFG set, this must be < 0x1E.		sint8_t peripheral_id; // @0 If not *_ALT_CFG set, this must be < 0x1E.
	uint8_t ~~type~~; // @1 Accepted values: 4=fixed_addr??, 8=increment_addr??, 12=lgy_fb_copy?, 15=userspace_copy?		uint8_t burst_size_raw; // (1 << raw size) bytes, bit4 is ignored? // @1 Accepted values: 4=fixed_addr??, 8=increment_addr??, 12=lgy_fb_copy?, 15=userspace_copy? (??)
	sint16_t ~~unk3~~; // @2 Must be 0 or multiple of 4?		sint16_t max_burst_size_bits; // @2 Must be 0 or multiple of 4?
	sint16_t transfer_size?; // @4 Must not be 0 if peripheral_id == 0xFF.		sint16_t transfer_size?; // @4 Must not be 0 if peripheral_id == 0xFF.
	sint16_t unk4; // @6		sint16_t unk4; // @6