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2026-05-12T22:45:10Z
User contributions
MediaWiki 1.43.1
https://www.3dbrew.org/w/index.php?title=Bootloader&diff=20185
Bootloader
2017-07-23T13:24:02Z
<p>Plutooo: </p>
<hr />
<div>The bootloader is the binary code stored in the ARM9 and ARM11 boot ROMs and hence is ran when the 3DS is powered on. It's purpose is initializing hardware and loading the [[FIRM|system firmware]] from the internal [[Flash_Filesystem|NAND memory]]..<br />
<br />
Besides NATIVE_FIRM, the bootloader is also capable of booting other firmwares (such as TWL_FIRM and AGB_FIRM). However, this will result either in a japanese error-screen or a system shutdown, directly after FIRM-Launching.<br />
<br />
== Boot ROM ==<br />
Upon boot, parts of the ARM9 and ARM11 boot ROMs are protected by writing to [[CONFIG#CFG_SYSPROT9|CFG_SYSPROT9]] and [[CONFIG#CFG_SYSPROT11|CFG_SYSPROT11]], respectively. The ARM9 and ARM11 boot ROMs are identical for all 3DS consoles (3DS, 3DS XL, 2DS, New 3DS, New 3DS XL, New 2DS XL)<br />
<br />
== NAND FIRM boot ==<br />
Boot9 is not hard-coded to only handle 2 FIRM partitions: it parses all 8 NCSD partitions for this. Boot9 will attempt to use every partition listed in the NCSD which is an actual FIRM partition, in the same order listed in the NCSD, until booting one of them succeeds. Among the not-yet-processed partitions, the FIRM which has the highest value at u32 firmhdr+4 will have a FIRM-boot attempted first. Since that value is normally 0x0, the order of FIRM-partition processing is normally identical to the order of the NCSD partitions.<br />
<br />
Boot9 is hard-coded for using [[AES_Registers|AES]] keyslot 0x6 for NAND crypto.<br />
<br />
== Non-NAND FIRM boot ==<br />
Boot9 can also boot from non-NAND. For this a different set of RSA pubks are used(separate pubks for retail/devunit like NAND). The spiflash FIRM image for this is also encrypted with AES-CBC using a normalkey stored in prot_boot9(separate for retail/devunit). This encryption is basically used instead of what is used for NAND-firm-partitions. This encryption is only used for the FIRM sections, the FIRM header is used raw. The AES keyslot for this is only overwritten afterwards when booting from non-NAND fails. AES keyslot 0x3F is used for this.<br />
<br />
CTR_word[0] = firmimageoffset;//FIRM section offset from FIRM header<br />
CTR_word[1] = outbufaddr;//FIRM section load addr<br />
CTR_word[2] = readsize;//FIRM section size<br />
CTR_word[3] = readsize;//FIRM section size<br />
<br />
When booting from NAND fails, boot9 will then attempt to boot from Wifi SPI-flash(this only triggers when the wifi module hw is properly accessible/connected, which is normally the case). The base offset for spiflash FIRM is 0x400. Note that this region(all data prior to offset 0x1F300) is write-protected by the spiflash(not writable from 3DS-mode / DS-mode).<br />
<br />
Additionally, if the shell is closed and a special key combination (Start + Select + X) is held, boot9 will attempt to boot from an inserted NTR cartridge before booting from NAND. Note: While normally on O3DS/2DS the console will not turn on if the shell is closed (or this is faked by holding a magnet to the console), when this special key combination is held holding down the power button will cause boot to occur anyway.<br />
<br />
For non-NAND booting, NCSD / FIRM-backup is not used.<br />
<br />
== SDMMC ==<br />
<br />
Boot9 has code implemented for using SD(HC) cards, but the input deviceids used by boot9 for those functions are hard-coded for NAND. However, it is possible to use an SD(HC) card in place of the NAND if the NAND chip is first disconnected, and a SD card connected to the bus. Due to the CID being different, partitions will need to be re-encrypted and TWL mode will not work, due to the MBR being in the NCSD header. Using sighax, it may be possible to replace the NCSD header.<br />
<br />
== Boot9 RSA keyslots ==<br />
<br />
The following are initialized during main() startup, by initialize_rsakeyslots_pubk(). Each of these, for the ones which are actually set, have different keydata for retail/devunit.<br />
* 0: Not set.<br />
* 1: Used for the NAND FIRM signature.<br />
* 2: Used for the non-NAND-FIRM signature.<br />
* 3: Used for the NAND-NCSD FIRM signature.<br />
<br />
When FIRM loading is successful, initialize_x07ffbd00_x07ffc100_rsakeyslotsprivk() is called, right before calling the final function in main(). Besides ITCM writing, this overwrites all 4 RSA keyslots with modulus + private-exponents loaded from boot9 data.<br />
<br />
initialize_x07ffbd00_x07ffc100_rsakeyslotsprivk():<br />
This initializes the 4 0x100-byte/0x200-byte chunks at 0x07ffb800+0x500(0x07ffbd00)/0x07ffb800+0x900(0x07ffc100). End address of the first section is 0x07ffc100(start addr of the second section), end address of the second section is 0x07ffc900. Hence, the first section total size is 0x400-bytes, while the second section total size is 0x800-bytes.<br />
<br />
These are initialized using via the boot9 data image, with ptrs from DTCM. Seperate keydata is used for retail/devunit.<br />
<br />
When initializing the first ITCM area: rsa_setkeyslot_privk() is called for all 4 RSA keyslots. The modulo for each one is also copied to (index*0x100) + 0x07ffb800 + 0x500. The private exponent is not copied into ITCM.<br />
<br />
The second ITCM area is initialized by copying 4 0x200-byte entries in a loop. These are RSA pubks+privks, which Boot9 doesn't use itself at all besides this copy loop.<br />
<br />
== Boot9 image data memory layout ==<br />
0xffffb088 is the beginning of the boot9 image data section.<br />
<br />
* 0xffffb088 size 0x38-bytes: This is the array used during FIRM-section-loading for the memory-range blacklist for FIRM sections.<br />
* 0xffffb0c0(end-addr of the above area) size 0x20-bytes: Unknown.<br />
* 0xffffb0e0(end-addr of the above area) size 0x2f80-bytes: This is *all* of the keys stored in the image.<br />
* 0xffffe060(end addr of the above key-area) size 0x230-bytes: This is the initial DTCM image @ 0xFFF00000, see below.<br />
* 0xffffe290(DTCM_image_end) - {boot9 image end}: All-zero.<br />
<br />
Layout of the 0x2f80-byte key-area at 0xffffb0e0:<br />
* 0xffffb0e0 size 0x2600-bytes: This is the RSA key-data, see below.<br />
* 0xffffd6e0(end-addr of the above area) size 0x40-bytes: This is the keydata used for crypting the entire OTP with keyslot 0x3f, used by main(). The first 0x20-bytes is for retail, the remaining 0x20-bytes starting at 0xffffd700 is for devunit. Chunk+0(retail=0xffffd6e0 devunit=0xffffd700) is the normalkey, chunk+0x10(retail=0xffffd6f0 devunit=0xffffd710) is the AES-IV.<br />
* ...<br />
* 0xffffd760: size 0x100-bytes: First 0x80-bytes is for retail, the remaining 0x80-bytes at 0xffffd7e0 is for devunit. This 0x80-byte block is copied to 0x07ffcd00 by a Boot9 function, however that code actually does the copy in two 0x40-bytes chunks.<br />
* 0xffffd860(end-addr of the above area) size 0x400-bytes: This is the bootrom_dataptr passed to the aes-keyinit function for retail. See the below Tools section for how this is processed.<br />
* 0xffffdc60(end-addr of the above area) size 0x400-bytes: This is the devunit version of the above the 0x400-byte chunk. This is very last chunk of data in the boot9 data-section key-area: end addr for this area is 0xffffe060.<br />
<br />
Layout of the 0x2600-byte RSA key-data at 0xffffb0e0: <br />
First 0x1300-bytes is for retail, the remaining 0x1300-bytes starting at 0xffffc3e0 is for devunit.<br />
* +0x0 retail=0xffffb0e0 devunit=0xffffc3e0: RSA modulo for keyslot3, initialized by initialize_rsakeyslots_pubk().<br />
* +0x100 retail=0xffffb1e0 devunit=0xffffc4e0: RSA modulo for keyslot1, initialized by initialize_rsakeyslots_pubk().<br />
* +0x200 retail=0xffffb2e0 devunit=0xffffc5e0: RSA modulo for keyslot2, initialized by initialize_rsakeyslots_pubk().<br />
* +0x300 size 0x200, retail=0xffffb3e0 devunit=0xffffc6e0: First 0x100-bytes is the RSA modulo, then the following 0x100-bytes is the RSA privk(private-exponent). This is for RSA-engine keyslot0 with initialize_x07ffbd00_x07ffc100_rsakeyslotsprivk(), which also copies this modulo to the array starting at 0x07ffbd00.<br />
* +0x500 size 0x200, retail=0xffffb5e0 devunit=0xffffc8e0: Used the same as the above block except for slot1.<br />
* +0x700 size 0x200, retail=0xffffb7e0 devunit=0xffffcae0: Used the same as the above block except for slot2.<br />
* +0x900 size 0x200, retail=0xffffb9e0 devunit=0xffffcce0: Used the same as the above block except for slot3.<br />
* +0xb00 size 0x200, retail=0xffffbbe0 devunit=0xffffcee0: First 0x100-bytes is the RSA modulo, then the following 0x100-bytes is the RSA privk(private-exponent). The 0x200-bytes here is copied to slot0 in the array at 0x07ffc100 by initialize_x07ffbd00_x07ffc100_rsakeyslotsprivk().<br />
* +0xd00 size 0x200, retail=0xffffbde0 devunit=0xffffd0e0: Used the same as the above block except for slot1.<br />
* +0xf00 size 0x200, retail=0xffffbfe0 devunit=0xffffd2e0: Used the same as the above block except for slot2.<br />
* +0x1100 size 0x200, retail=0xffffc1e0 devunit=0xffffd4e0: Used the same as the above block except for slot3.<br />
<br />
== Boot9 DTCM layout ==<br />
Most of this is just ptrs / other unknown data, not actual keys. However, there is an unknown 0x10-byte block @ +0x124(there's a ptr initialized for this block elsewhere).<br />
<br />
== Boot11 image data memory layout ==<br />
0x0001817c..0x000181f4 size 0x78-bytes: This seems to be the bootrom error screen font gfx data. This begins at the exact end-address of the crt0 code, the rest of the protected boot11 code begins at this end-address(0x000181f4). <br />
<br />
0x00019400 is the beginning of the boot11 data area, the first 8-bytes here are unknown.<br />
* 0x00019408..0x0001b498 size 0x2090-bytes: This is the blowfish keydata which gets copied to arm9itcm_twlkeydata+0x3e0 later.<br />
* ...<br />
* 0x0001c498..0x0001c4f8 size 0x60-bytes: This is the data which eventually gets copied to arm9itcm_twlkeydata+0x380.<br />
* 0x0001c4f8..0x0001c538 size 0x40-bytes: This is the data which eventually gets copied to arm9itcm_twlkeydata+0x340.<br />
* 0x0001c538..0x0001c578 size 0x40-bytes: This is the data which eventually gets copied to arm9itcm_twlkeydata+0x300.<br />
* 0x0001c578..0x0001c5f8 size 0x80-bytes: This is the data which eventually gets copied to arm9itcm_twlkeydata+0x280.<br />
* 0x0001c5f8..0x0001c678 size 0x80-bytes: This is the data which eventually gets copied to arm9itcm_twlkeydata+0x0.<br />
* 0x0001c678..0x0001c878 size 0x200-bytes: This is the data which eventually gets copied to arm9itcm_twlkeydata+0x80.<br />
* 0x0001c878..0x0001d078 size 0x800-bytes: These are the 3DS RSA-2048 modulus which are eventually copied to arm9_itcm+0x4900: on retail the first 4 are copied there by boot9, on devunit the last 4 are copied to itcm.<br />
* 0x0001d078 size 0x120-bytes is the initial data for the .data section @ 0x1ffe8000, this is the very end of the protected arm11-bootrom.<br />
<br />
== AES keys ==<br />
See the Tools section for how Boot9 initializes the keyslots.<br />
<br />
See also [[AES_Registers|here]].<br />
<br />
For an issue with console-unique key-init, see [[OTP_Registers|here]].<br />
<br />
== BootROM Errors ==<br />
Sample error-screen(where firm0+firm1 RSA signatures were corrupted):<br />
<br />
BOOTROM 8046<br />
ERRCODE: 00F800FF<br />
DEDEFFFF FFFFFFFF<br />
00000000 00000000<br />
<br />
* 1st line is: <code>print_string(..., "BOOTROM %X", 0x8046);//This last param comes from the .pool.</code><br />
* 2nd line is: <code>print_string(..., "ERRCODE: %08X", *((unsigned int*)(0x1FFFE000+0xC)));//See below memory notes.</code><br />
* 3rd line is: <code>print_string(..., "%08X %08X", *((unsigned int*)(0x1FFFE000+0x10))`, `*((unsigned int*)(0x1fffe000+0x14)));//See below memory notes.</code><br />
* 4th line is: <code>print_string(..., "%08X %08X",*((unsigned int*)(0x1FFFE000+0x18))`, `*((unsigned int*)(0x1fffe000+0x1C)));//See below memory notes.</code><br />
<br />
== 0x1FFFE000 memory ==<br />
This memory is used by boot9 mainly for sending info to the arm11 for the error-screen. The data in this region is still stored in memory by the time the ARM9+ARM11 jumps to FIRM.<br />
<br />
Among boot9/boot11, the 3 words at 0x1FFFE000 seem to be ''only'' accessed by the boot11 function initializing those words.<br />
<br />
* u32 0x1FFFE000+0: ARM11 MPCore "Cycle Counter Register (CCNT)".<br />
* u32 0x1FFFE000+4: ARM11 MPCore "Count Register 0 (PMN0)".<br />
* u32 0x1FFFE000+8: ARM11 MPCore "Count Register 1 (PMN0)".<br />
* 8bit-entry-array 0x1FFFE000+0xC: 8bit status-codes initialized by boot9 main(), for the FIRM-boot devices. +0 is NAND and +2 is wifi-spiflash.<br />
* ...<br />
* 8bit-entry-array 0x1FFFE000+0x10: Status-codes originally from nand_findfirmpartition_loadfirm(), for each of the 8 NCSD partitions.<br />
<br />
== BootROM Status Codes ==<br />
{| class="wikitable" border="1"<br />
|-<br />
! Value<br />
! Description<br />
|-<br />
| 0x00<br />
| Success<br />
|-<br />
| 0xEE(~17)<br />
| NCSD header validation function failed: NCSD magicnum is invalid or RSA verification failed.<br />
|-<br />
| 0xDE(~33)<br />
| FIRM header validation function failed: FIRM magicnum is invalid or RSA verification failed.<br />
|-<br />
| 0xDF(~32)<br />
| Failed to read sector data from the device.<br />
|-<br />
| 0xCF(~48)<br />
| FIRM section validation function failed: FIRM section is invalid.<br />
|-<br />
| 0xF7(~8)<br />
| A NAND FIRM from another partition was already found with a priority(firmhdr+4) >= to the value for the current partition's FIRM priority.<br />
|-<br />
| 0xF8(~7)<br />
| The FIRM magicnum(firmhdr+0) is invalid.<br />
|-<br />
| 0xFF(~0)<br />
| Initial value for each entry in the 8-entry array of status-codes for the NAND NCSD partitions. Indicates that the partition is not a FIRM partition(partition fs type isn't 0x3 or partition fs crypt-type isn't 0x2).<br />
|}<br />
<br />
== Boot9 startup ==<br />
<br />
0xffff0000 jumps to 0xffff8000. 0xffff8000 is crt0:<br />
* Very first thing this does is clear u8 register 0x10000002 ([[CONFIG_Registers#CFG_RST11|CFG_RST11]]) bit 0 to zero.<br />
* Then sp is initialized for each cpumode, IRQs/FIQs are disabled during the first mode-switch.<br />
* Order of mode-switches + sp initialization: svc-mode = 0xfff04000, irq-mode = 0xfff03f00, system-mode = 0xfff03b00. Hence, the rest of the code following this runs in system-mode.<br />
* Then L_ffff80cc/mpu_init() is called.<br />
* Then L_ffff0038() is called, which initializes the exception-handler addresses @ 0x08000000.<br />
* Then L_ffff81b8() is called(r4 + lr are saved on the DTCM stack), which after calling a memclear function which doesn't do anything, it then clears 0x08000030 size 0x10. Here the DTCM at 0xfff00000 size 0x4000 is cleared.<br />
* Then L_ffff81b4() is called, which branches to DTCM_init(). This copies the initial DTCM data from the Boot9 data image into boot9, then it clears 0xFFF00230 - 0xFFF01AC0.<br />
* Then LT_ffff8228/main is jumped to, with LR set to the address of an infinite-branch-loop instruction.<br />
<br />
mpu_init():<br />
* Bitmask 0x000f9005 is cleared in the cp15 control register. MCR instructions which do then following are then executed: flush entire instruction cache, flush entire data cache, and drain write buffer.<br />
* Then the 8 [[Memory_layout|MPU]] memregions are initialized.<br />
* ITCM memregion reg = 0x24: baseaddr=0x0, size = 128MB(0x08000000).<br />
* DTCM memregion reg = 0xfff0000a: baseaddr=0xfff00000, size=16KB(0x00004000).<br />
* Then instruction cachable and data cachable/bufferable bits for the MPU regions are setup.<br />
* Then the instruction/data access permissions for the MPU regions are setup.<br />
* Lastly bitmask 0x0005707d is orred in the cp15 control register.<br />
<br />
== Boot9 main() ==<br />
<br />
The following functions are called: LT_ffff2024(), LT_ffff1ff8(), pxi_init(), rsa_init(), initialize_rsakeyslots_pubk(), crypto_initialize(), and aesengine_reset().<br />
Then AES keyslot 0x3F is setup: aesengine_setnormalkey(0x3f, 5, ptr) is called. ptr on retail(CFG_UNITINFO check) is 0xffffd6e0, 0xffffd700 for devunit. Then essentially, aesengine_setctr(5, ptr+0x10) is executed.<br />
Then AES keyslot 0x3f is selected.<br />
When calling the following functions, if any of them return zero, it will immediately jump to setting ptr to 0x10012000(otp), otherwise when all of them return non-zero ptr = sp+0x94. otp_decrypt(sp+4), otp_verify(sp+4), initialize_consoleunique_itcm(sp+4, 0x07ffb800).<br />
Then the following is executed: initialize_aeskeys_wrap(ptr, 0x70);<br />
Then sp+4 size 0x100 is cleared to zero.<br />
<br />
...<br />
<br />
NAND firm-boot code-block, is described below. Note that boot9 is basically hard-coded to use deviceid NAND, not SD.<br />
{<br />
timer_updatestoredstate() is called, then the AES keyslot for NAND-FIRM is selected(0x6).<br />
Then LT_ffff56c8() is called, if that returns non-zero the statuscode variable is set to ~2 then it jumps to NAND_BOOTEND.<br />
Then LT_ffff5774(0x201) is called, if that returns non-zero the statuscode variable is set to ~1 then it jumps to NAND_BOOTEND.<br />
Then fsdriver_setup_mmc() is called. Then nand_findfirmpartition_loadfirm(0) is called, with the statuscode variable set to the retval.<br />
Executes a loop which runs 8 times: write the output from get_errorcode_arrayentry_xfff005e8(loopindex) to u8 0x1fffe000+0x10+loopindex(copy the array of 32bit error-codes for all 8 NCSD partitions initialized by nand_findfirmpartition_loadfirm() to the array of 8bit entries at 0x1fffe000+0x10).<br />
<br />
NAND_BOOTEND:<br />
Then the statuscode variable is written to u8 0x1fffe000+0xc.<br />
Then LT_ffff5690(0x201, 0x1fffe018, 0x1fffe01c) is called.<br />
Then LT_ffff5644() is called.<br />
Then timer_updatestoredstate() is called.<br />
When statuscode==0 for success, it jumps to FIRMLOAD_END. Otherwise, it continues to the next code-block.<br />
}<br />
<br />
Wifi spi-flash firm-boot code-block, executed when no FIRM was loaded successfully so far.<br />
{<br />
timer_updatestoredstate() is called.<br />
<br />
Then spi_wififlash_cmdgetstatusreg(sp+0x100) is executed. When bit0 of the output u8 at sp+0x100 is clear, it will continue this code-block, otherwise it will set the statuscode variable to ~1 then jump to SPIFLASH_BOOTEND.<br />
Then fsdriver_setup_wififlash() is called.<br />
Here read_firmhdr_validate_loadfirm(0, 2) is called, with the statuscode variable set to the retval.<br />
<br />
SPIFLASH_BOOTEND:<br />
Then the statuscode variable is written to u8 0x1fffe000+0xe.<br />
Then timer_updatestoredstate() is called.<br />
When statuscode==0 for success, it jumps to FIRMLOAD_END. Otherwise, it executes writenormalkey_keyslot3f(), then jumps to FIRMLOAD_FAILURE.<br />
}<br />
<br />
FIRMLOAD_END:<br />
Here it calls firmhdr_getarm11_entrypoint() and firmhdr_getarm9_entrypoint(). Immediately after calling each function it checks if the retval is 0, if so it then jumps to FIRMLOAD_FAILURE.<br />
After calling initialize_x07ffbd00_x07ffc100_rsakeyslotsprivk(), it jumps to FIRMLOAD_EXIT.<br />
<br />
FIRMLOAD_FAILURE:<br />
Here it clears 0x07ffb800 size 0x3c70 to zero, endaddr = 0x07fff470.<br />
Then it continues to FIRMLOAD_EXIT.<br />
<br />
FIRMLOAD_EXIT:<br />
Here firmboot() is called, which should never return. The instruction after this bl is a call for panic().<br />
<br />
== Boot11 ==<br />
<br />
* ...<br />
<br />
main():<br />
LT_1263c();<br />
...<br />
LT_13944()<br />
...<br />
pxi_init();<br />
initializefuncptr_firmboot_start(firmbootbegin_funcptr);<br />
firmboot();<br />
return;<br />
<br />
LT_12220/initializefuncptr_firmboot_start<br />
inr0=funcptr<br />
This writes inr0 to address 0x1ffe8028, then returns.<br />
This initializes the funcptr which firmboot() can call after the very first func-call.<br />
<br />
LT_13944<br />
if([[I2C_Registers|i2cmcu_readregf]](sp+0)==0)<br />
{<br />
return (*((u8*)0x10147000) >> 4) & 1;//Reads [[GPIO_Registers|GPIO]] when reading I2C fails.<br />
}<br />
Here it basically does "return <byte loaded from sp+0> ^ 0x2". Hence in this case, it will return 0x2 when the system shell is closed(sleep-mode), otherwise 0x0 is returned.<br />
<br />
LT_12454/firmboot<br />
This is the arm11 version of the boot9 firmboot() function, like boot9 this is the final function called from main(). The functionality for these two functions are identical, minus addresses.<br />
ptr = firmboot_loadentrypoint11();<br />
funcptr = *(0x1ffe8028);<br />
if(funcptr)funcptr(ptr);<br />
LT_11ffc(ptr);<br />
return;<br />
<br />
== Boot Procedure ==<br />
<br />
* 0 seconds - unit is powered on. The ARM9 and ARM11 [[Memory_layout|bootroms]] begin execution.<br />
* <= ~1 second - BootROMs fully run, load FIRM, etc. The loaded FIRM begins running.<br />
**The ARM11 sysmodules included with FIRM are launched by ARM11-kernel, etc.<br />
**The [[Process_Manager_Services|PM]] module launches [[NS]].<br />
**If [[Home_Menu#Auto-Boot_Function|auto-booting]] is needed, NS will [[NS#Auto-boot|auto-boot]] titles.<br />
**Otherwise, NS will instead launch [[ErrDisp]] and the [[Configuration Memory#ACTIVEMENUTID|current active menu]] via the PM module. For retail units, this menu is usually the [[Home Menu]]. Note that the PM module first launches the module dependencies when launching a process, prior to actually launching the process.<br />
**The further Home Menu startup process is described [[Home_Menu#Home_Menu_startup|here]]. This includes Home Menu manually launching various sysmodules.<br />
<br />
* 4 seconds - the LCD screens are initialized.<br />
<br />
* 7 seconds - [[Home Menu]] is fully initialized/loaded.<br />
<br />
== NAND Reads during Boot ==<br />
During a successful boot on 6.x, the bootloader (and firm) reads the following sectors from NAND (in this order):<br />
00000000 (NCSD Partition Table)<br />
<br />
Only verify 'FIRM' magic? (A second Header-read will be attempted even if everything except the magic is 0xFF...)<br />
0B130000 (FIRM Partition)<br />
0B530000 (Secondary FIRM Partition)<br />
<br />
Verify RSA signature and parse Header:<br />
0B130000 (FIRM: Header)<br />
0B130200 (FIRM: Section 1)<br />
0B163E00 (FIRM: Section 2)<br />
0B193E00 (FIRM: Section 3)<br />
<br />
00013000 .. Below is probably NATIVE_FIRM booting ..<br />
00014000<br />
00015000<br />
00016000<br />
00017000<br />
<br />
09011A00<br />
09011C00<br />
09012000<br />
09012400<br />
...<br />
<br />
== Error Codes ==<br />
When the 3DS does not find the NAND chip, the following error is displayed:<br />
<br />
[[Image:CTR_Bootrom_Error.jpg|240px]]<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Error<br />
! Description<br />
|-<br />
| <tt>00F800FE 00000000 00000000 00000200 00000000</tt><br />
| Error when having SD-card reader connected to NAND during boot.<br />
|-<br />
| <tt>00F800FE 00000000 00000000 00000400 00000000</tt><br />
| NAND not found error (?)<br />
|-<br />
| <tt>00F800FE FFFFFFFF FFFFFFFF 00000080 00800000</tt><br />
| NAND error when DAT1 was used as DAT0.<br />
|-<br />
| <tt>00F800FE FFFFFFFF FFFFFFFF 00000005 00800000</tt><br />
| NAND error when DAT2 was used as DAT0.<br />
|-<br />
| <tt>00F800FE FFFFFFFF FFFFFFFF 00000005 00000000</tt><br />
| NAND error when DAT3 was used as DAT0.<br />
|-<br />
| <tt>00F800FF F8F8FFFF FFFFFFFF 00000000 00000000</tt><br />
| Both the firm0 and firm1 partitions are corrupt (failed signature checks).<br />
|-<br />
| <tt>00F800EE FFFFFFFF FFFFFFFF 00000000 00000000</tt><br />
| [[NCSD]] header in sector 0 is corrupt (failed signature check).<br />
|}<br />
<br />
== Tools ==<br />
* [https://github.com/yellows8/boot9_tools boot9_tools]</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=SVC&diff=19829
SVC
2017-04-10T23:39:40Z
<p>Plutooo: </p>
<hr />
<div>= System calls =<br />
'''Note: The argument-lists here apply to the official syscall wrapper-functions that are found in userland processes. The actual ordering passed to the kernel via the SVC instruction is documented in [[Kernel_ABI|Kernel ABI]].'''<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Id<br />
! NF ARM11<br />
! NF ARM9<br />
! TF ARM11<br />
! Description<br />
! scope="col" width="200" | Notes<br />
|-<br />
| 0x01 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|ControlMemory]](u32* outaddr, u32 addr0, u32 addr1, u32 size, [[Memory Management#enum_MemoryOperation|MemoryOperation]] operation, [[Memory Management#enum_MemoryPermission|MemoryPermission]] permissions)<br />
| Outaddr is usually the same as the input addr0.<br />
|-<br />
| 0x02 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|QueryMemory]]([[Memory Management#struct MemoryInfo|MemoryInfo]]* info, [[Memory Management#struct PageInfo|PageInfo]]* out, u32 Addr)<br />
|<br />
|-<br />
| 0x03 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| void ExitProcess(void)<br />
|<br />
|-<br />
| 0x04 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetProcessAffinityMask(u8* affinitymask, Handle process, s32 processorcount)<br />
|<br />
|-<br />
| 0x05 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetProcessAffinityMask(Handle process, u8* affinitymask, s32 processorcount)<br />
|<br />
|-<br />
| 0x06 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetProcessIdealProcessor(s32 *idealprocessor, Handle process)<br />
|<br />
|-<br />
| 0x07 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetProcessIdealProcessor(Handle process, s32 idealprocessor)<br />
|<br />
|-<br />
| 0x08 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#CreateThread|CreateThread]](Handle* thread, func entrypoint, u32 arg, u32 stacktop, s32 threadpriority, s32 processorid)<br />
|<br />
|-<br />
| 0x09 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| void [[Multi-threading#ExitThread|ExitThread]](void)<br />
|<br />
|-<br />
| 0x0A <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| void [[Multi-threading#SleepThread|SleepThread]](s64 nanoseconds)<br />
|<br />
|-<br />
| 0x0B <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#GetThreadPriority|GetThreadPriority]](s32* priority, Handle thread)<br />
|<br />
|-<br />
| 0x0C <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#SetThreadPriority|SetThreadPriority]](Handle thread, s32 priority)<br />
|<br />
|-<br />
| 0x0D <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#GetThreadAffinityMask|GetThreadAffinityMask]](u8* affinitymask, Handle thread, s32 processorcount)<br />
|<br />
|-<br />
| 0x0E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#SetThreadAffinityMask|SetThreadAffinityMask]](Handle thread, u8* affinitymask, s32 processorcount)<br />
| Replaced with a stub in ARM11 NATIVE_FIRM kernel beginning with [[8.0.0-18]].<br />
|-<br />
| 0x0F <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#GetThreadIdealProcessor|GetThreadIdealProcessor]](s32* processorid, Handle thread)<br />
|<br />
|-<br />
| 0x10 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#SetThreadIdealProcessor|SetThreadIdealProcessor]](Handle thread, s32 processorid)<br />
| Replaced with a stub in ARM11 NATIVE_FIRM kernel beginning with [[8.0.0-18]].<br />
|-<br />
| 0x11 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| s32 GetCurrentProcessorNumber(void)<br />
|<br />
|-<br />
| 0x12 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#Run|Run]](Handle process, StartupInfo* info)<br />
| This starts the main() thread. Buf+0 is main-thread priority, Buf+4 is main-thread stack-size.<br />
|-<br />
| 0x13 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#CreateMutex|CreateMutex]](Handle* mutex, bool initialLocked)<br />
|<br />
|-<br />
| 0x14 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#ReleaseMutex|ReleaseMutex]](Handle mutex)<br />
|<br />
|-<br />
| 0x15 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#CreateSemaphore|CreateSemaphore]](Handle* semaphore, s32 initialCount, s32 maxCount)<br />
|<br />
|-<br />
| 0x16 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#ReleaseSemaphore|ReleaseSemaphore]](s32* count, Handle semaphore, s32 releaseCount)<br />
|<br />
|-<br />
| 0x17 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#CreateEvent|CreateEvent]](Handle* event, ResetType resettype)<br />
|<br />
|-<br />
| 0x18 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#SignalEvent|SignalEvent]](Handle event)<br />
|<br />
|-<br />
| 0x19 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#ClearEvent|ClearEvent]](Handle event)<br />
|<br />
|-<br />
| 0x1A <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result CreateTimer(Handle* timer, ResetType resettype)<br />
|<br />
|-<br />
| 0x1B <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result SetTimer(Handle timer, s64 initial_nanoseconds, s64 interval)<br />
|<br />
|-<br />
| 0x1C <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result CancelTimer(Handle timer)<br />
|<br />
|-<br />
| 0x1D <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result ClearTimer(Handle timer)<br />
|<br />
|-<br />
| 0x1E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|CreateMemoryBlock]](Handle* memblock, u32 addr, u32 size, [[Memory Management#enum_MemoryPermission|MemoryPermission]] mypermission, [[Memory Management#enum_MemoryPermission|MemoryPermission]] otherpermission)<br />
|<br />
|-<br />
| 0x1F <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|MapMemoryBlock]](Handle memblock, u32 addr, [[Memory Management#enum_MemoryPermission|MemoryPermission]] mypermissions, [[Memory Management#enum_MemoryPermission|MemoryPermission]] otherpermission)<br />
|<br />
|-<br />
| 0x20 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|UnmapMemoryBlock]](Handle memblock, u32 addr)<br />
|<br />
|-<br />
| 0x21 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#Address_Arbiters|CreateAddressArbiter]](Handle* arbiter)<br />
|<br />
|-<br />
| 0x22 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#Address_Arbiters|ArbitrateAddress]](Handle arbiter, u32 addr, ArbitrationType type, s32 value, s64 nanoseconds)<br />
|<br />
|-<br />
| 0x23 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result CloseHandle(Handle handle)<br />
|<br />
|-<br />
| 0x24 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result WaitSynchronization1(Handle handle, s64 timeout_nanoseconds)<br />
|<br />
|-<br />
| 0x25 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result WaitSynchronizationN(s32* out, Handle* handles, s32 handlecount, bool waitAll, s64 timeout_nanoseconds)<br />
|<br />
|-<br />
| 0x26 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SignalAndWait(s32* out, Handle signal, Handle* handles, s32 handleCount, bool waitAll, s64 nanoseconds)<br />
| Stubbed<br />
|-<br />
| 0x27 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result DuplicateHandle(Handle* out, Handle original)<br />
|<br />
|-<br />
| 0x28 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| s64 GetSystemTick(void) (This returns the total CPU ticks elapsed since the CPU was powered-on)<br />
|<br />
|-<br />
| 0x29 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetHandleInfo(s64* out, Handle handle, HandleInfoType type)<br />
|<br />
|-<br />
| 0x2A <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result GetSystemInfo(s64* out, SystemInfoType type, s32 param)<br />
|<br />
|-<br />
| 0x2B <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result GetProcessInfo(s64* out, Handle process, ProcessInfoType type)<br />
|<br />
|-<br />
| 0x2C <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#GetThreadInfo|GetThreadInfo]](s64* out, Handle thread, ThreadInfoType type)<br />
|<br />
|-<br />
| 0x2D <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|ConnectToPort]](Handle* out, const char* portName)<br />
|<br />
|-<br />
| 0x2E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SendSyncRequest1(Handle session)<br />
| Stubbed<br />
|<br />
|-<br />
| 0x2F <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SendSyncRequest2(Handle session)<br />
| Stubbed<br />
|<br />
|-<br />
| 0x30 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SendSyncRequest3(Handle session)<br />
| Stubbed<br />
|<br />
|-<br />
| 0x31 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SendSyncRequest4(Handle session)<br />
| Stubbed<br />
|<br />
|-<br />
| 0x32 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|SendSyncRequest]](Handle session)<br />
|<br />
|-<br />
| 0x33 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result OpenProcess(Handle* process, u32 processId)<br />
|<br />
|-<br />
| 0x34 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#OpenThread|OpenThread]](Handle* thread, Handle process, u32 threadId)<br />
|<br />
|-<br />
| 0x35 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: green" | Yes<br />
| Result GetProcessId(u32* processId, Handle process)<br />
|<br />
|-<br />
| 0x36 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#GetProcessIdOfThread|GetProcessIdOfThread]](u32* processId, Handle thread)<br />
|<br />
|-<br />
| 0x37 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#GetThreadId|GetThreadId]](u32* threadId, Handle thread)<br />
|<br />
|-<br />
| 0x38 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetResourceLimit(Handle* resourceLimit, Handle process)<br />
|<br />
|-<br />
| 0x39 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetResourceLimitLimitValues(s64* values, Handle resourceLimit, LimitableResource* names, s32 nameCount)<br />
|<br />
|-<br />
| 0x3A <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetResourceLimitCurrentValues(s64* values, Handle resourceLimit, LimitableResource* names, s32 nameCount)<br />
|<br />
|-<br />
| 0x3B <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#GetThreadContext|GetThreadContext]](ThreadContext* context, Handle thread)<br />
| Stubbed<br />
|-<br />
| 0x3C <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Break(BreakReason reason)<br />
Break(BreakReason debugReason, const void* croInfo, u32 croInfoSize)<br />
|<br />
|-<br />
| 0x3D <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| OutputDebugString(void const, int)<br />
| Does nothing on non-debug units.<br />
|-<br />
| 0x3E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| ControlPerformanceCounter(unsigned long long, int, unsigned int, unsigned long long)<br />
|<br />
|- style="border-top: double"<br />
| 0x47 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|CreatePort]](Handle* portServer, Handle* portClient, const char* name, s16 maxSessions)<br />
| Setting name=NULL creates a private port not accessible from svcConnectToPort.<br />
|-<br />
| 0x48 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|CreateSessionToPort]](Handle* session, Handle port)<br />
|<br />
|-<br />
| 0x49 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|CreateSession]](Handle* sessionServer, Handle* sessionClient)<br />
|<br />
|-<br />
| 0x4A <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|AcceptSession]](Handle* session, Handle port)<br />
|<br />
|-<br />
| 0x4B <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReplyAndReceive1(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
| Stubbed.<br />
|-<br />
| 0x4C <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReplyAndReceive2(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
| Stubbed.<br />
|-<br />
| 0x4D <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReplyAndReceive3(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
| Stubbed.<br />
|-<br />
| 0x4E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReplyAndReceive4(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
| Stubbed.<br />
|-<br />
| 0x4F <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|ReplyAndReceive]](s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
|<br />
|-<br />
| 0x50 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[#Interrupt Handling|BindInterrupt]](Interrupt name, Handle eventOrSemaphore, s32 priority, bool isLevelHighActive)<br />
|<br />
|-<br />
| 0x51 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result UnbindInterrupt(Interrupt name, Handle eventOrSemaphore)<br />
|<br />
|-<br />
| 0x52 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result InvalidateProcessDataCache(Handle process, void* addr, u32 size)<br />
|<br />
|-<br />
| 0x53 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result StoreProcessDataCache(Handle process, void const* addr, u32 size)<br />
|<br />
|-<br />
| 0x54 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result FlushProcessDataCache(Handle process, void const* addr, u32 size)<br />
|<br />
|-<br />
| 0x55 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Corelink DMA Engines|StartInterProcessDma]](Handle* dma, Handle dstProcess, void* dst, Handle srcProcess, const void* src, u32 size, const DmaConfig* config)<br />
|<br />
|-<br />
| 0x56 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result StopDma(Handle dma)<br />
|<br />
|-<br />
| 0x57 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result GetDmaState(DmaState* state, Handle dma)<br />
|<br />
|-<br />
| 0x58<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| RestartDma(Handle, void *, void const*, unsigned int, signed char)<br />
|<br />
|-<br />
| 0x59<br />
| style="background: green" | Yes<br />
| style="background: red" | No?<br />
| style="background: red" | No<br />
| SetGpuProt(s8 input_flag). Implemented with [[11.3.0-36|11.3.0-X]], see below.<br />
|-<br />
| 0x5A<br />
| style="background: green" | Yes<br />
| style="background: red" | No?<br />
| style="background: red" | No<br />
| SetWifiEnabled(s0 input_flag). Implemented with [[11.4.0-37|11.4.0-X]], see below.<br />
|- style="border-top: double"<br />
| 0x60 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result DebugActiveProcess(Handle* debug, u32 processID)<br />
|<br />
|-<br />
| 0x61 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result BreakDebugProcess(Handle debug)<br />
|<br />
|-<br />
| 0x62 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result TerminateDebugProcess(Handle debug)<br />
|<br />
|-<br />
| 0x63 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetProcessDebugEvent(DebugEventInfo* info, Handle debug)<br />
|<br />
|-<br />
| 0x64 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ContinueDebugEvent(Handle debug, u32 flags)<br />
|<br />
|-<br />
| 0x65 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetProcessList(s32* processCount, u32* processIds, s32 processIdMaxCount)<br />
|<br />
|-<br />
| 0x66 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetThreadList(s32* threadCount, u32* threadIds, s32 threadIdMaxCount, Handle domain)<br />
|<br />
|-<br />
| 0x67 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetDebugThreadContext(ThreadContext* context, Handle debug, u32 threadId, u32 controlFlags)<br />
|<br />
|-<br />
| 0x68 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetDebugThreadContext(Handle debug, u32 threadId, const ThreadContext* context, u32 controlFlags)<br />
|<br />
|-<br />
| 0x69 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result QueryDebugProcessMemory(MemoryInfo* blockInfo, PageInfo* pageInfo, Handle debug, u32 addr)<br />
|<br />
|-<br />
| 0x6A <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReadProcessMemory(void* buffer, Handle debug, u32 addr, u32 size)<br />
|<br />
|-<br />
| 0x6B <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result WriteProcessMemory(Handle debug, void const* buffer, u32 addr, u32 size)<br />
|<br />
|-<br />
| 0x6C <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetHardwareBreakPoint(s32 registerId, u32 control, u32 value)<br />
|<br />
|-<br />
| 0x6D<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| [[Multi-threading#GetDebugThreadParam|GetDebugThreadParam]](s64* unused, u32* out, Handle kdebug, u32 threadId, DebugThreadParameter param)<br />
| <br />
|- style="border-top: double"<br />
| 0x70<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ControlProcessMemory(Handle KProcess, unsigned int Addr0, unsigned int Addr1, unsigned int Size, unsigned int Type, unsigned int Permissions)<br />
|<br />
|-<br />
| 0x71<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management#Memory_Mapping|MapProcessMemory]](Handle process, u32 startAddr, u32 size)<br />
|<br />
|-<br />
| 0x72<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management#Memory_Mapping|UnmapProcessMemory]](Handle process, u32 startAddr, u32 size)<br />
|<br />
|-<br />
| 0x73<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#CreateCodeSet|CreateCodeSet]](Handle* handle_out, struct CodeSetInfo, u32 code_ptr, u32 ro_ptr, u32 data_ptr)<br />
|<br />
|-<br />
| 0x74<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result RandomStub()<br />
| Stubbed<br />
|-<br />
| 0x75<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#CreateProcess|CreateProcess]](Handle* handle_out, Handle codeset_handle, u32 [[NCCH/Extended_Header#ARM11_Kernel_Capabilities|arm11kernelcaps_ptr]], u32 arm11kernelcaps_num)<br />
|<br />
|-<br />
| 0x76<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| TerminateProcess(Handle)<br />
|<br />
|-<br />
| 0x77<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetProcessResourceLimits(Handle KProcess, Handle KResourceLimit)<br />
| <br />
|-<br />
| 0x78<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result CreateResourceLimit(Handle *KResourceLimit)<br />
|<br />
|-<br />
| 0x79<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetResourceLimitValues(Handle res_limit, LimitableResource* resource_type_list, s64* resource_list, u32 count)<br />
|<br />
|-<br />
| 0x7A<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: green" | Yes<br />
| AddCodeSegment (unsigned int Addr, unsigned int Size)<br />
| Stubbed on NATIVE_FIRM beginning with [[2.0.0-2]]. Used during TWL_FIRM boot.<br />
|-<br />
| 0x7B<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| Backdoor(unsigned int CodeAddress)<br />
| This is used on ARM9 NATIVE_FIRM. <br />
No ARM11 processes have access to it without some form of kernelhax, and this was removed on [[11.0.0-33]] (for ARM11).<br />
<br />
|-<br />
| 0x7C<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| KernelSetState(unsigned int Type, ...)<br />
| The type determines the args to be passed<br />
|-<br />
| 0x7D<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result QueryProcessMemory(MemInfo *Info, unsigned int *Out, Handle KProcess, unsigned int Addr)<br />
|<br />
|- style="border-top: double"<br />
| 0xFF<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Stop point<br />
| The svcaccesscontrol mask doesn't apply for this SVC. This svc doesn't check the "debug mode enabled" flag either. Does nothing if there is no [[KDebug]] object associated to the current process. Stubbed on ARM9 NATIVE_FIRM.<br />
|}<br />
NF: NATIVE_FIRM. TF: TWL_FIRM.<br />
<br />
Note that "stubbed" here means that the SVC only returns an error, as in the following snippet:<br />
<br />
<pre>ROM:FFF04D98 LDR R0, =0xF8C007F4<br />
ROM:FFF04D9C BX LR</pre><br />
<br />
= Types and structures =<br />
<br />
== enum ResetType ==<br />
<br />
{| class="wikitable" border="1"<br />
! Reset type<br />
! Id<br />
|-<br />
| ONESHOT<br />
| 0<br />
|-<br />
| STICKY<br />
| 1<br />
|-<br />
| PULSE<br />
| 2<br />
|}<br />
<br />
Timers/Events may be waited on by a thread using svcWaitSynchronization. Once the timer runs out/the event gets signaled, threads waiting on the respective handles until the timer/event is reset. STICKY timers/events wake up threads until they are explicitly reset by some thread. ONESHOT timers/events will wake up exactly one thread and then are reset automatically. PULSE timers will be reset after waking up one thread too, but will also be started again immediately. It's unknown whether PULSE is a valid reset type for events.<br />
<br />
== struct StartupInfo ==<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| s32<br />
| Priority<br />
|-<br />
| u32<br />
| Stack size<br />
|-<br />
| s32<br />
| argc<br />
|-<br />
| s16*<br />
| argv<br />
|-<br />
| s16*<br />
| envp<br />
|}<br />
<br />
== enum BreakReason ==<br />
{| class="wikitable" border="1"<br />
! Break Reason<br />
! Value<br />
|-<br />
| PANIC<br />
| 0<br />
|-<br />
| ASSERT<br />
| 1<br />
|-<br />
| USER<br />
| 2<br />
|}<br />
<br />
== struct DebugEventInfo ==<br />
Size: 0x28 bytes<br />
<br />
When using svcGetProcessDebugEvent, the kernel fetches the first [[KEventInfo]] instance of the process's [[KDebug]]. The debug event is handled and parsed into this structure.<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Event type<br />
|-<br />
| u32<br />
| Thread ID (not used in all events)<br />
|-<br />
| u32<br />
| Flags. Bit0 means that svcContinueDebugEvent needs to be called for this event (except for EXIT PROCESS events, for which you need to call svcContinueDebugEvent even if this bit is clear)<br />
|-<br />
| u8[4]<br />
| Remnants of the corresponding flags in [[KEventInfo]], always 0 here<br />
|-<br />
| u32[6]<br />
| Event-specific data (see below)<br />
|}<br />
<br />
{| class="wikitable" border="1"<br />
! Event type<br />
! Id<br />
|-<br />
| ATTACH PROCESS<br />
| 0<br />
|-<br />
| ATTACH THREAD<br />
| 1<br />
|-<br />
| EXIT THREAD<br />
| 2<br />
|-<br />
| EXIT PROCESS<br />
| 3<br />
|-<br />
| EXCEPTION<br />
| 4<br />
|-<br />
| DLL LOAD *<br />
| 5<br />
|-<br />
| DLL UNLOAD *<br />
| 6<br />
|-<br />
| SCHEDULE IN **<br />
| 7<br />
|-<br />
| SCHEDULE OUT *<br />
| 8<br />
|-<br />
| SYSCALL IN *<br />
| 9<br />
|-<br />
| SYSCALL OUT *<br />
| 10<br />
|-<br />
| OUTPUT STRING<br />
| 11<br />
|-<br />
| MAP *<br />
| 12<br />
|}<br />
<br />
<nowiki>*</nowiki> Unused<br />
<br />
<nowiki>**</nowiki> Referenced but never used in practise<br />
<br />
When calling svcDebugActiveProcess, an ATTACH PROCESS debug event is signaled, then ATTACH THREAD for each of its opened threads, then finally ATTACH BREAK.<br />
<br />
ATTACH THREAD events are also emitted when a thread is created from an attached process.<br />
<br />
=== ATTACH PROCESS event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u64<br />
| Program ID<br />
|-<br />
| char[8]<br />
| Process name<br />
|-<br />
| u32<br />
| Process ID<br />
|-<br />
| u32<br />
| "Other" flag. Always 0 in available kernel versions<br />
|}<br />
<br />
=== ATTACH THREAD event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Creator thread ID (0 if attached by svcDebugActiveProcess)<br />
|-<br />
| void *<br />
| Thread local storage<br />
|-<br />
| u32 *<br />
| Entrypoint = .text load address of the parent process<br />
|}<br />
<br />
=== EXIT THREAD/PROCESS events ===<br />
<br />
A single u32 reason field is used.<br />
<br />
Thread exit reasons:<br />
{| class="wikitable" border="1"<br />
! Reason<br />
! Id<br />
|-<br />
| (None)<br />
| 0<br />
|-<br />
| TERMINATE<br />
| 1<br />
|-<br />
| EXIT PROCESS<br />
| 2<br />
|-<br />
| TERMINATE PROCESS<br />
| 3<br />
|}<br />
<br />
Process exit reasons:<br />
{| class="wikitable" border="1"<br />
! Reason<br />
! Id<br />
|-<br />
| (None)<br />
| 0<br />
|-<br />
| TERMINATE<br />
| 1<br />
|-<br />
| UNHANDLED EXCEPTION<br />
| 2<br />
|}<br />
<br />
=== EXCEPTION event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Exception type<br />
|-<br />
| u32<br />
| Exception address<br />
|-<br />
| u32[4]<br />
| Type-specific data, see below<br />
|}<br />
<br />
Exception types:<br />
{| class="wikitable" border="1"<br />
! Exception type<br />
! Id<br />
|-<br />
| UNDEFINED INSTRUCTION<br />
| 0<br />
|-<br />
| PREFETCH ABORT<br />
| 1<br />
|-<br />
| DATA ABORT<br />
| 2<br />
|-<br />
| UNALIGNED DATA ACCESS<br />
| 3<br />
|-<br />
| ATTACH BREAK<br />
| 4<br />
|-<br />
| STOP POINT<br />
| 5<br />
|-<br />
| USER BREAK<br />
| 6<br />
|-<br />
| DEBUGGER BREAK<br />
| 7<br />
|-<br />
| UNDEFINED SYSCALL<br />
| 8<br />
|}<br />
<br />
==== UNDEFINED INSTRUCTION/PREFETCH ABORT/DATA ABORT/UNALIGNED DATA ACCESS/UNDEFINED SYSCALL events ====<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Fault information: Fault Address Register (for DATA ABORT and UNALIGNED DATA ACCESS),<br />
attempted SVC ID (for UNDEFINED SYSCALL), otherwise 0<br />
|}<br />
<br />
==== STOP POINT event ====<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Stop point type that caused the event: 0 = svc 0xFF, 1 = breakpoint, 2 = watchpoint<br />
|-<br />
| u32<br />
| Fault information: FAR for watchpoints, 0 otherwise<br />
|}<br />
<br />
==== USER BREAK event ====<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Break reason<br />
|-<br />
| u32[2]<br />
| Info for LOAD_RO and UNLOAD_RO<br />
|}<br />
<br />
User break types:<br />
{| class="wikitable" border="1"<br />
! Reason<br />
! Id<br />
|-<br />
| PANIC<br />
| 0<br />
|-<br />
| ASSERT<br />
| 1<br />
|-<br />
| USER<br />
| 2<br />
|-<br />
| LOAD_RO<br />
| 3<br />
|-<br />
| UNLOAD_RO<br />
| 4<br />
|}<br />
<br />
==== DEBUGGER BREAK event ====<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| s32[4]<br />
| IDs of the attached process's threads that were running on each core at the time of the @ref svcBreakDebugProcess call, or -1 (only the first 2 values are meaningful on O3DS).<br />
|}<br />
<br />
=== SCHEDULE/SYSCALL IN/OUT events ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u64<br />
| Clock tick<br />
|-<br />
| u32<br />
| CPU ID (SCHEDULE events) Syscall (SYSCALL events)<br />
|}<br />
<br />
=== OUTPUT STRING event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| String address<br />
|-<br />
| u32<br />
| String size<br />
|}<br />
<br />
=== MAP event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Mapped address<br />
|-<br />
| u32<br />
| Mapped size<br />
|-<br />
| u32<br />
| MemoryPermission<br />
|-<br />
| u32<br />
| MemoryState<br />
|}<br />
<br />
== struct ThreadContext ==<br />
<br />
Size: 0xCC bytes<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Offset<br />
! Type<br />
! Description<br />
|-<br />
| 0x0<br />
| CpuRegisters<br />
| Saved CPU registers (r0-r12, sp, lr, pc, cpsr)<br />
|-<br />
| 0x44<br />
| FpuRegisters<br />
| Saved FPU registers (d0-d15, fpscr, fpexc)<br />
|}<br />
<br />
The user needs to adjust pc for exceptions that occured while in Thumb mode.<br />
<br />
'''Flags for svcGetDebugThreadContext/svcSetDebugThreadContext''':<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Get/set CPU GPRs (r0-r12)<br />
|-<br />
| 1<br />
| Get/set CPU SPRs (sp, lr, pc, cpsr)<br />
|-<br />
| 2<br />
| Get/set FPU GPRs (d0-d15 aka. f0-f31)<br />
|-<br />
| 3<br />
| Get/set FPU SPRs (fpscr, fpexc)<br />
|}<br />
<br />
When setting CPSR, the following assignment is done: <code>ctx->cpsr = ctx->cpsr & 0x7F0FDFF | userCtx->cpuRegisters.cpsr & 0xF80F0200;</code>. This is to avoid obvious security issues.<br />
<br />
== enum DebugThreadParameter ==<br />
<br />
{| class="wikitable" border="1"<br />
! Parameter<br />
! Id<br />
|-<br />
| PRIORITY<br />
| 0<br />
|-<br />
| SCHEDULING_MASK_LOW<br />
| 1<br />
|-<br />
| CPU_IDEAL<br />
| 2<br />
|-<br />
| CPU_CREATOR<br />
| 3<br />
|}<br />
<br />
== typedef Handle ==<br />
<br />
User-visible references to internal objects are represented by 32-bit integers called handles. Handles are only valid in the process they have been created in; hence, they cannot be exchanged between processes directly (the [[IPC]] functions provide a mean to copy handles to other processes, though).<br />
<br />
There are a number of special-purpose handles, which provide easy access to information on objects in the current process:<br />
{| class="wikitable" border="1"<br />
! Handle<br />
! Description<br />
|-<br />
| 0xFFFF8000<br />
| Handle to the active thread<br />
|-<br />
| 0xFFFF8001<br />
| Handle to the active process<br />
|}<br />
<br />
=svcSetHardwareBreakPoint=<br />
This is essentially an interface for writing values to the debug-unit (B/W)RP registers. registerId range 0..5 = breakpoints(BRP0-5), 0x100..0x101 = watchpoints(WRP0-1), anything outside of these ranges will result in an error. This is used for both adding and removing/disabling breakpoints/watchpoints, hence the raw control value parameter.<br />
<br />
Here the kernel sets bit15 in the DSCR, to enable monitor-mode debugging.<br />
<br />
Regardless of whether this is for a BRP, when bit21 is set in the control input parameter(BRP type = contextID), the kernel will load the target process [[KProcess|contextID]] and use that internally for the value field. The target process is specified via a [[KDebug]] handle passed as the "value" parameter.<br />
<br />
Lastly, the kernel disables the specified (B/W)RP, then writes the value parameter / loaded contextID to the (B/W)VR, then writes the input control value to the (B/W)CR.<br />
<br />
= [[DMA]] =<br />
The CTRSDK code for using svcStartInterProcessDma will execute svcBreak when svcStartInterProcessDma returns an error(except for certain error value(s)). Therefore on retail, triggering a svcStartInterProcessDma via a system-module which results in an error from svcStartInterProcessDma will result in the system-module terminating.<br />
<br />
= Interrupt Handling =<br />
<br />
svcBindInterrupt registers the given event or semaphore corresponding to the handle to the global [[ARM11_Interrupts#Interrupt_Table_.28New3DS.29|"interrupt table"]] for the given interrupt ID. Interrupts 0-14 and 16-31 can never be mapped regardless of the [[NCCH/Extended_Header#ARM11_Kernel_Capabilities|interrupt flags of the process's exheader]], and the latter are not checked when mapping interrupt 15. The "is level high active"/"is manual clear" parameter must be false when binding a semaphore handle (otherwise 0xD8E007EE "invalid combination" is returned).<br />
<br />
If something was already registered for the given ID, svcBindInterrupt returns error 0xD8E007F0. See [[KBaseInterruptEvent]] for more information on what happens on receipt of an interrupt.<br />
<br />
Applications hence can wait for specific interrupts to happen by calling WaitSynchronization(N) on the event or semaphore handles.<br />
<br />
The set of existing ARM11 interrupts is listed on [[ARM11 Interrupts|this page]].<br />
<br />
= Debugging =<br />
DebugActiveProcess is used to attach to a process for debugging. This SVC can only be used when the target process' ARM11 descriptors stored in the exheader have the kernel flag for "Enable debug" set. Otherwise when that flag is clear, the kernel flags for the process using this SVC must have the "Force debug" flag set.<br />
<br />
This SVC can only be used when a certain kernel state debug flag is non-zero(it's set to zero for retail).<br />
<br />
= KernelSetState =<br />
KernelSetState uses the 6th [[ARM11_Interrupts#Private_Interrupts|software-generated interrupt]] for any operation involving synchronization between cores.<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Type<br />
! Enabled for the NATIVE_FIRM ARM11 kernel<br />
! Enabled for the TWL_FIRM ARM11 kernel<br />
! Description<br />
|-<br />
| 0<br />
| Yes<br />
| No<br />
| Arguments : <code>u64 firmTitleID</code> (the high 32-bits of that title ID (0 when using N3DS pm) have a special meaning on N3DS, they're otherwise ignored, see below).<br />
This initializes the programID for launching [[FIRM]], then triggers launching [[FIRM]]. With New3DS kernel, it forces the firm title ID to be the New3DS NATIVE_FIRM, when the input firm title ID is 2. The high firm title ID is always set to 0x40138. On New3DS, the kernel disables the additional New3DS cache hw prior to calling the firmlaunch function from the <handler for the KernelSetState-types called via funcptr>.<br />
|-<br />
| 1<br />
| Yes<br />
| Yes<br />
| Does nothing.<br />
|-<br />
| 2<br />
| Yes<br />
| Yes<br />
| Powers down the GPU and syncs with Process9 (waits for <code>*(vu8 *)PXI_SYNC11</code> to be 1) during the process.<br />
On New3DS, the kernel disables the additional New3DS cache hw, when it's actually enabled, prior to executing the rest of the code from the <handler for the KernelSetState-types called via funcptr>.<br />
|-<br />
| 3<br />
| Yes<br />
| No<br />
| Arguments: <code>0, void* address</code> or <code>1</code><br />
This used for initializing the 0x1000-byte buffer used by the launched [[FIRM]]. When the first parameter is 1, this buffer is copied to the beginning of FCRAM at 0xE0000000. When it is 0, this kernel buffer is mapped to the process address specified by the second argument.<br />
|-<br />
| 4<br />
| No<br />
| Yes<br />
| This unmaps(?) the following virtual memory by writing value physaddr (where physaddr base is 0x80000000) to the L1 MMU table entries: 0x00300000..0x04300000, 0x08000000..0x0FE00000, and 0x10000000..0xF8000000.<br />
|-<br />
| 5<br />
| Yes<br />
| Yes<br />
| Used by kernelpanic. This makes core0 enter a WFI/B infinite loop. Threads that were created on core1 or core2 have their priority set to 0x3F, except if the thread was created on core1 and whose parent process (if any) has the "Runnable on sleep" [[NCCH/Extended_Header#ARM11_Kernel_Flags|ARM11 kernel flag]] set. Core1 threads with a priority of 0x40 without a parent process have their priority set to 0x3E.<br />
<br />
Prior to first invoking this handler, the global variable holding <code>UNITINFO != 0</code> is true, and if there is no [[LCD_Registers#Fill_Color|LCD fill]] set at the time kernelpanic is called, kernelpanic fills the top screen with red and the bottom screen with either yellow (if the current process was running under the APPLICATION memregion) or red. <br />
<br />
Before invoking this handler a second time, kernelpanic wait for the user to hold L+R+Start+Select down.<br />
|-<br />
| 6<br />
| Yes<br />
| No<br />
| Arguments: <code>u32 what, u64 val</code><br />
UNITINFO needs to be non-zero. <br />
<br />
If <code>what</code> is 0 or any invalid value, nothing is done. <br />
<br />
If it is 1, <code>val != 0</code> is written to the global variable enabling ERR:F-format register dumps on user-mode CPU/VFP exceptions (the VFP exception handler acts as if this variable was always true and works on retail environments). The user handler, stack pointer to use for exception handling, and pointer to use for the exception info structure are contiguously located in either the thread's TLS, or if the handler is NULL, in the main thread's TLS, at offset 0x40. If the specified stack pointer is 1, sp_usr - 0x5c is used instead; if the specified exception info buffer is 1, sp_usr - 0x5c is used instead, and if it is 0, <specified stack> - 0x5c is used (0x5c is the size of the exception info structure that is being pushed). Configured by NS on startup on dev-units (default being 0 on non-debugger/jtag units).<br />
<br />
If 2, kernelpanic will be called when svcBreak is used by a non-attached process. Configured by NS on startup on dev-units (default being 0 on non-debugger/jtag units).<br />
<br />
If 3, this changes the scheduling/preemption mode (when no threads are being preempted, otherwise returns error 0xC8A01414), see [[KResourceLimit]] for more details.<br />
|-<br />
| 7<br />
| Yes<br />
| No<br />
| This triggers an MCU (hard) reboot. This reboot is triggered via device address 0x4A on the second [[I2C]] bus (the MCU). Register address 0x20 is written to with value 4. This code will not return.<br />
On New3DS, the kernel disables the additional New3DS cache hw prior to calling the reboot function from the <handler for the KernelSetState-types called via funcptr>.<br />
|-<br />
| 8<br />
| Yes<br />
| No<br />
| Alternate FIRM launch code-path, with different [[PXI]] FIFO word constants. Usually not used. PTM-sysmodule can use this but it's unknown what exactly triggers that in PTM-sysmodule.<br />
|-<br />
| 9<br />
| Yes, implemented at some point after system-version v4.5.<br />
| ?<br />
| Argumens: <code>u64 titleID</code>.<br />
When creating a process, if the process has a non-zero TID equal to the parameter above (which is stored in a global variable), then KProcessHwInfo+0x32 ("process is the currently running app") is set to <code>true</code>.<br />
Used by NS conditionally based on the contents of the [[NS CFA]].<br />
|-<br />
| 10<br />
| Yes<br />
| ?<br />
| Arguments: <code>u32 config</code><br />
ConfigureNew3DSCPU. Only available for the [[New_3DS]] kernel. The actual code for processing this runs under the <handler for the KernelSetState-types called via funcptr>, which runs on all ARM11 cores. Only bit0-1 of the argument are used here. Bit 0 enables higher core clock, and bit 1 enables additional (L2) cache. This configures the hardware [[PDN_Registers|register]] for the flags listed [[NCCH/Extended_Header#Flag1|here]], among other code which uses the MPCore private memory region registers.<br />
|}<br />
<br />
= GetSystemInfo =<br />
{| class="wikitable" border="1"<br />
! SystemInfoType value<br />
! s32 param<br />
! Description<br />
|-<br />
| 0<br />
| 0<br />
| This writes the total used memory size in the following memory regions to out: APPLICATION, SYSTEM, and BASE.<br />
|-<br />
| 0<br />
| 1<br />
| This writes the total used memory size in the APPLICATION memory region to out.<br />
|-<br />
| 0<br />
| 2<br />
| This writes the total used memory size in the SYSTEM memory region to out.<br />
|-<br />
| 0<br />
| 3<br />
| This writes the total used memory size in the BASE memory region to out.<br />
|-<br />
| 2<br />
| Unused<br />
| This writes the FCRAM memory [[Memory_Allocation#FCRAM_Region_Data|used by the kernel]] to out.<br />
|-<br />
| 25<br />
| Unused<br />
| This writes the total number of threads which were directly launched by the kernel, to out. No longer exists with some kernel version?<br />
|-<br />
| 26<br />
| Unused<br />
| This writes the total number of processes which were directly launched by the kernel, to out. For the NATIVE_FIRM/SAFE_MODE_FIRM ARM11 kernel, this is normally 5, for processes sm, fs, pm, loader, and pxi.<br />
|}<br />
<br />
= GetProcessInfo =<br />
Input:<br />
R0 = unused<br />
R1 = Handle process<br />
R2 = ProcessInfoType type<br />
<br />
Output:<br />
R0 = Result<br />
R1 = output value lower word<br />
R2 = output value upper word<br />
<br />
{| class="wikitable" border="1"<br />
! ProcessInfoType value<br />
! Available since system version<br />
! Description<br />
|-<br />
| 0<br />
| <br />
| Returns the amount of executable memory allocated to the process + thread context size + page-rounded size of the external handle table<br />
|-<br />
| 1<br />
| <br />
| Returns the amount of <unknown> memory allocated to the process + thread context size + page-rounded size of the external handle table<br />
|-<br />
| 2<br />
| <br />
| Returns the amount of DMA-able (code, data, IO pages, etc.) memory allocated to the process + thread context size + page-rounded size of the external handle table<br />
|-<br />
| 3<br />
| <br />
| Returns the amount of <unknown> memory allocated to the process + thread context size + page-rounded size of the external handle table<br />
|-<br />
| 4<br />
| <br />
| Returns the amount handles in use by the process.<br />
|-<br />
| 5<br />
| <br />
| Returns the highest count of handles that have been open at once by the process<br />
|-<br />
| 6<br />
| <br />
| Returns <code>*(u32*)(KProcess+0x234)</code> which is always 0<br />
|-<br />
| 7<br />
| <br />
| Returns 0<br />
|-<br />
| 8<br />
| <br />
| Returns the maximum number of threads which can be opened by this process (always 0)<br />
|-<br />
| 9-18<br />
| [[8.0.0-18]]<br />
| This only returns error 0xD8E007ED.<br />
|-<br />
| 19<br />
| Stub: [[8.0.0-18]]. Implementation: [[11.3.0-36|11.3.0-X]].<br />
| Originally this only returned 0xD8E007ED. Now with v11.3 this returns the memregion for the process: out low u32 = [[KProcess]] "Kernel flags from the exheader kernel descriptors" & 0xF00. High out u32 = 0.<br />
|-<br />
| 20<br />
| [[8.0.0-18]]<br />
| low u32 = (0x20000000 - <LINEAR virtual-memory base for this process>). That is, the output value is the value which can be added to LINEAR memory vaddrs for converting to physical-memory addrs.<br />
|-<br />
| 21<br />
| [[8.0.0-18]]. N3DS only.<br />
| Returns the maximum amount of VRAM memory allocatable by the process: 0x800000 bytes if the process has already allocated VRAM memory, otherwise 0 (+ error 0xE0E01BF4)<br />
|-<br />
| 22<br />
| [[8.0.0-18]]. N3DS only.<br />
| Returns the address of the first chunk of VRAM allocated by this process<br />
|-<br />
| 23<br />
| [[8.0.0-18]]. N3DS only.<br />
| Returns the amount of VRAM allocated by this process (?)<br />
|}<br />
<br />
= GetHandleInfo =<br />
<br />
{| class="wikitable" border="1"<br />
! HandleInfoType value<br />
! Description<br />
|-<br />
| 0<br />
| This returns the time in ticks the KProcess referenced by the handle was created. If a KProcess handle was not given, it will write whatever was in r5, r6 when the svc was called.<br />
|-<br />
| 1<br />
| Get internal refcount for kernel object (not counting the one this SVC adds internally to operate), and also a boolean if it is 0 (prior to substracting 1, as explained before).<br />
|-<br />
| 0x32107<br />
| Returns (u64) 0.<br />
|}<br />
<br />
= svc7B Backdoor =<br />
This saves SVC-mode SP+LR on the user-mode stack, then sets the SVC-mode SP to the user-mode SP. This then calls the specified code in SVC-mode. Once the called code returns, this pops the saved SP+LR off the stack for restoring the SVC-mode SP, then returns from the svc7b handler. Note that this svc7b handler does not disable IRQs, if any IRQs/context-switches occur while the SVC-mode SP is set to the user-mode one here, the ARM11-kernel will crash(which hangs the whole ARM11-side system).<br />
<br />
= svc 0x59 =<br />
Implemented with [[11.3.0-36|11.3.0-X]]. Used with GSP module starting with that version. This always returns 0.<br />
<br />
When input_flag is not 0x1, it will use value 0x0 internally. When a state field already matches input_flag, this will immediately return. Otherwise, after this SVC finishes running, it will write input_flag to this state field. GSP module uses 0x0 for APPLICATION-memregionid and 0x1 for non-APPLICATION-memregionid.<br />
<br />
This writes "<nowiki>0x100 | <val></nowiki>" to [[CONFIG11_Registers#CFG11_GPUPROT|pdnregbase+0x140]], where val depends on input_flag and a kernel state field for [[Configuration_Memory|APPMEMTYPE]].<br />
<br />
When input_flag is 0x1 val is fixed:<br />
* Old3DS: 0x3<br />
* New3DS: 0x460<br />
<br />
Otherwise, val depends on the kernel APPMEMTYPE state field:<br />
{| class="wikitable" border="1"<br />
|-<br />
! FIRM<br />
! [[Memory_layout|APPMEMTYPE]]<br />
! val<br />
|-<br />
| Old3DS<br />
| 2<br />
| 0x3<br />
|-<br />
| Old3DS<br />
| 3<br />
| 0x5<br />
|-<br />
| Old3DS<br />
| 4<br />
| 0x6<br />
|-<br />
| Old3DS<br />
| Non-value-{2/3/4}<br />
| 0x7<br />
|-<br />
| New3DS<br />
| 7<br />
| 0x490<br />
|-<br />
| New3DS<br />
| Non-value-7<br />
| 0x4F0<br />
|}<br />
<br />
This same register is also initialized during kernel boot starting with [[3.0.0-5]], with the following values:<br />
* Old3DS: 0x103<br />
* New3DS: 0x550<br />
<br />
= svc 0x5A =<br />
Based on what NWM did previously, it looks like this one does the following:<br />
<br />
if (in_flag == 1)<br />
*(u8*)0x10140180 |= 1;<br />
else<br />
*(u8*)0x10140180 &~ 1;<br />
<br />
= Kernel error-codes =<br />
See [[Error codes]].<br />
<br />
{| class="wikitable" border="1"<br />
! Error-code value<br />
! Description<br />
|-<br />
| 0x09401BFE<br />
| Timeout occurred with svcWaitSynchronization*, when timeout is not ~0.<br />
|-<br />
| 0xC8601801<br />
| No more unused/free synchronization objects left to use in a given object's linked list. (KEvent, KMutex, KTimer, KSemaphore, KAddressArbiter, KThread)<br />
|-<br />
| 0xC8601802<br />
| No more unused/free KSharedMemory objects left to use in the KSharedMemory linked list - out of blocks<br />
|-<br />
| 0xC8601809<br />
| No more unused/free KSessions left to use in the KSession linked list - out of sessions<br />
|-<br />
| 0xC860180A<br />
| Not enough free memory available for memory allocation.<br />
|-<br />
| 0xC920181A<br />
| The session was closed by the other process..<br />
|-<br />
| 0xD0401834<br />
| Max connections to port have been exceeded<br />
|-<br />
| 0xD8609013<br />
| Unknown, probably reslimit related?<br />
|-<br />
| 0xD88007FA<br />
| Returned if no KObjectName object in the linked list of such objects matches the port name provided to the svc. <br />
|-<br />
| 0xD8E007ED<br />
| This indicates that a value is outside of the enum being used.<br />
|-<br />
| 0xD8E007F1<br />
| This error indicates Misaligned address.<br />
|-<br />
| 0xD8E007F7<br />
| This error indicates that the input handle used with the SVC does not exist in the process handle-table, or that the handle kernel object type does not match the type used by the SVC.<br />
|-<br />
| 0xD9000402<br />
| Invalid memory permissions for input/output buffers, for svcStartInterProcessDma.<br />
|-<br />
| 0xD9001814<br />
| Failed unprivileged load or store - wrong permissions on memory<br />
|-<br />
| 0xD9001BF7<br />
| This error is returned when the kernel retrieves a pointer to a kernel object, but the object type doesn't match the desired one.<br />
|-<br />
| 0xD92007EA<br />
| This error is returned when a process attempts to use svcCreateMemoryBlock when the process memorytype is the application memorytype, and when addr=0.<br />
|-<br />
| 0xE0E01BF5<br />
| This indicates an invalid address was used.<br />
|-<br />
| 0xF8C007F4<br />
| Invalid type/param0-param3 input for svcKernelSetState. This is also returned for those syscalls marked as stubs.<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=SVC&diff=19828
SVC
2017-04-10T23:38:31Z
<p>Plutooo: </p>
<hr />
<div>= System calls =<br />
'''Note: The argument-lists here apply to the official syscall wrapper-functions that are found in userland processes. The actual ordering passed to the kernel via the SVC instruction is documented in [[Kernel_ABI|Kernel ABI]].'''<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Id<br />
! NF ARM11<br />
! NF ARM9<br />
! TF ARM11<br />
! Description<br />
! scope="col" width="200" | Notes<br />
|-<br />
| 0x01 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|ControlMemory]](u32* outaddr, u32 addr0, u32 addr1, u32 size, [[Memory Management#enum_MemoryOperation|MemoryOperation]] operation, [[Memory Management#enum_MemoryPermission|MemoryPermission]] permissions)<br />
| Outaddr is usually the same as the input addr0.<br />
|-<br />
| 0x02 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|QueryMemory]]([[Memory Management#struct MemoryInfo|MemoryInfo]]* info, [[Memory Management#struct PageInfo|PageInfo]]* out, u32 Addr)<br />
|<br />
|-<br />
| 0x03 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| void ExitProcess(void)<br />
|<br />
|-<br />
| 0x04 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetProcessAffinityMask(u8* affinitymask, Handle process, s32 processorcount)<br />
|<br />
|-<br />
| 0x05 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetProcessAffinityMask(Handle process, u8* affinitymask, s32 processorcount)<br />
|<br />
|-<br />
| 0x06 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetProcessIdealProcessor(s32 *idealprocessor, Handle process)<br />
|<br />
|-<br />
| 0x07 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetProcessIdealProcessor(Handle process, s32 idealprocessor)<br />
|<br />
|-<br />
| 0x08 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#CreateThread|CreateThread]](Handle* thread, func entrypoint, u32 arg, u32 stacktop, s32 threadpriority, s32 processorid)<br />
|<br />
|-<br />
| 0x09 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| void [[Multi-threading#ExitThread|ExitThread]](void)<br />
|<br />
|-<br />
| 0x0A <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| void [[Multi-threading#SleepThread|SleepThread]](s64 nanoseconds)<br />
|<br />
|-<br />
| 0x0B <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#GetThreadPriority|GetThreadPriority]](s32* priority, Handle thread)<br />
|<br />
|-<br />
| 0x0C <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#SetThreadPriority|SetThreadPriority]](Handle thread, s32 priority)<br />
|<br />
|-<br />
| 0x0D <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#GetThreadAffinityMask|GetThreadAffinityMask]](u8* affinitymask, Handle thread, s32 processorcount)<br />
|<br />
|-<br />
| 0x0E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#SetThreadAffinityMask|SetThreadAffinityMask]](Handle thread, u8* affinitymask, s32 processorcount)<br />
| Replaced with a stub in ARM11 NATIVE_FIRM kernel beginning with [[8.0.0-18]].<br />
|-<br />
| 0x0F <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#GetThreadIdealProcessor|GetThreadIdealProcessor]](s32* processorid, Handle thread)<br />
|<br />
|-<br />
| 0x10 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#SetThreadIdealProcessor|SetThreadIdealProcessor]](Handle thread, s32 processorid)<br />
| Replaced with a stub in ARM11 NATIVE_FIRM kernel beginning with [[8.0.0-18]].<br />
|-<br />
| 0x11 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| s32 GetCurrentProcessorNumber(void)<br />
|<br />
|-<br />
| 0x12 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#Run|Run]](Handle process, StartupInfo* info)<br />
| This starts the main() thread. Buf+0 is main-thread priority, Buf+4 is main-thread stack-size.<br />
|-<br />
| 0x13 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#CreateMutex|CreateMutex]](Handle* mutex, bool initialLocked)<br />
|<br />
|-<br />
| 0x14 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#ReleaseMutex|ReleaseMutex]](Handle mutex)<br />
|<br />
|-<br />
| 0x15 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#CreateSemaphore|CreateSemaphore]](Handle* semaphore, s32 initialCount, s32 maxCount)<br />
|<br />
|-<br />
| 0x16 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#ReleaseSemaphore|ReleaseSemaphore]](s32* count, Handle semaphore, s32 releaseCount)<br />
|<br />
|-<br />
| 0x17 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#CreateEvent|CreateEvent]](Handle* event, ResetType resettype)<br />
|<br />
|-<br />
| 0x18 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#SignalEvent|SignalEvent]](Handle event)<br />
|<br />
|-<br />
| 0x19 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#ClearEvent|ClearEvent]](Handle event)<br />
|<br />
|-<br />
| 0x1A <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result CreateTimer(Handle* timer, ResetType resettype)<br />
|<br />
|-<br />
| 0x1B <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result SetTimer(Handle timer, s64 initial_nanoseconds, s64 interval)<br />
|<br />
|-<br />
| 0x1C <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result CancelTimer(Handle timer)<br />
|<br />
|-<br />
| 0x1D <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result ClearTimer(Handle timer)<br />
|<br />
|-<br />
| 0x1E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|CreateMemoryBlock]](Handle* memblock, u32 addr, u32 size, [[Memory Management#enum_MemoryPermission|MemoryPermission]] mypermission, [[Memory Management#enum_MemoryPermission|MemoryPermission]] otherpermission)<br />
|<br />
|-<br />
| 0x1F <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|MapMemoryBlock]](Handle memblock, u32 addr, [[Memory Management#enum_MemoryPermission|MemoryPermission]] mypermissions, [[Memory Management#enum_MemoryPermission|MemoryPermission]] otherpermission)<br />
|<br />
|-<br />
| 0x20 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|UnmapMemoryBlock]](Handle memblock, u32 addr)<br />
|<br />
|-<br />
| 0x21 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#Address_Arbiters|CreateAddressArbiter]](Handle* arbiter)<br />
|<br />
|-<br />
| 0x22 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#Address_Arbiters|ArbitrateAddress]](Handle arbiter, u32 addr, ArbitrationType type, s32 value, s64 nanoseconds)<br />
|<br />
|-<br />
| 0x23 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result CloseHandle(Handle handle)<br />
|<br />
|-<br />
| 0x24 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result WaitSynchronization1(Handle handle, s64 timeout_nanoseconds)<br />
|<br />
|-<br />
| 0x25 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result WaitSynchronizationN(s32* out, Handle* handles, s32 handlecount, bool waitAll, s64 timeout_nanoseconds)<br />
|<br />
|-<br />
| 0x26 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SignalAndWait(s32* out, Handle signal, Handle* handles, s32 handleCount, bool waitAll, s64 nanoseconds)<br />
| Stubbed<br />
|-<br />
| 0x27 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result DuplicateHandle(Handle* out, Handle original)<br />
|<br />
|-<br />
| 0x28 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| s64 GetSystemTick(void) (This returns the total CPU ticks elapsed since the CPU was powered-on)<br />
|<br />
|-<br />
| 0x29 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetHandleInfo(s64* out, Handle handle, HandleInfoType type)<br />
|<br />
|-<br />
| 0x2A <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result GetSystemInfo(s64* out, SystemInfoType type, s32 param)<br />
|<br />
|-<br />
| 0x2B <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result GetProcessInfo(s64* out, Handle process, ProcessInfoType type)<br />
|<br />
|-<br />
| 0x2C <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#GetThreadInfo|GetThreadInfo]](s64* out, Handle thread, ThreadInfoType type)<br />
|<br />
|-<br />
| 0x2D <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|ConnectToPort]](Handle* out, const char* portName)<br />
|<br />
|-<br />
| 0x2E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SendSyncRequest1(Handle session)<br />
| Stubbed<br />
|<br />
|-<br />
| 0x2F <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SendSyncRequest2(Handle session)<br />
| Stubbed<br />
|<br />
|-<br />
| 0x30 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SendSyncRequest3(Handle session)<br />
| Stubbed<br />
|<br />
|-<br />
| 0x31 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SendSyncRequest4(Handle session)<br />
| Stubbed<br />
|<br />
|-<br />
| 0x32 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|SendSyncRequest]](Handle session)<br />
|<br />
|-<br />
| 0x33 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result OpenProcess(Handle* process, u32 processId)<br />
|<br />
|-<br />
| 0x34 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#OpenThread|OpenThread]](Handle* thread, Handle process, u32 threadId)<br />
|<br />
|-<br />
| 0x35 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: green" | Yes<br />
| Result GetProcessId(u32* processId, Handle process)<br />
|<br />
|-<br />
| 0x36 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#GetProcessIdOfThread|GetProcessIdOfThread]](u32* processId, Handle thread)<br />
|<br />
|-<br />
| 0x37 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#GetThreadId|GetThreadId]](u32* threadId, Handle thread)<br />
|<br />
|-<br />
| 0x38 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetResourceLimit(Handle* resourceLimit, Handle process)<br />
|<br />
|-<br />
| 0x39 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetResourceLimitLimitValues(s64* values, Handle resourceLimit, LimitableResource* names, s32 nameCount)<br />
|<br />
|-<br />
| 0x3A <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetResourceLimitCurrentValues(s64* values, Handle resourceLimit, LimitableResource* names, s32 nameCount)<br />
|<br />
|-<br />
| 0x3B <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#GetThreadContext|GetThreadContext]](ThreadContext* context, Handle thread)<br />
| Stubbed<br />
|-<br />
| 0x3C <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Break(BreakReason reason)<br />
Break(BreakReason debugReason, const void* croInfo, u32 croInfoSize)<br />
|<br />
|-<br />
| 0x3D <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| OutputDebugString(void const, int)<br />
| Does nothing on non-debug units.<br />
|-<br />
| 0x3E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| ControlPerformanceCounter(unsigned long long, int, unsigned int, unsigned long long)<br />
|<br />
|- style="border-top: double"<br />
| 0x47 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|CreatePort]](Handle* portServer, Handle* portClient, const char* name, s16 maxSessions)<br />
| Setting name=NULL creates a private port not accessible from svcConnectToPort.<br />
|-<br />
| 0x48 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|CreateSessionToPort]](Handle* session, Handle port)<br />
|<br />
|-<br />
| 0x49 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|CreateSession]](Handle* sessionServer, Handle* sessionClient)<br />
|<br />
|-<br />
| 0x4A <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|AcceptSession]](Handle* session, Handle port)<br />
|<br />
|-<br />
| 0x4B <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReplyAndReceive1(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
| Stubbed.<br />
|-<br />
| 0x4C <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReplyAndReceive2(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
| Stubbed.<br />
|-<br />
| 0x4D <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReplyAndReceive3(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
| Stubbed.<br />
|-<br />
| 0x4E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReplyAndReceive4(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
| Stubbed.<br />
|-<br />
| 0x4F <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|ReplyAndReceive]](s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
|<br />
|-<br />
| 0x50 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[#Interrupt Handling|BindInterrupt]](Interrupt name, Handle eventOrSemaphore, s32 priority, bool isLevelHighActive)<br />
|<br />
|-<br />
| 0x51 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result UnbindInterrupt(Interrupt name, Handle eventOrSemaphore)<br />
|<br />
|-<br />
| 0x52 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result InvalidateProcessDataCache(Handle process, void* addr, u32 size)<br />
|<br />
|-<br />
| 0x53 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result StoreProcessDataCache(Handle process, void const* addr, u32 size)<br />
|<br />
|-<br />
| 0x54 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result FlushProcessDataCache(Handle process, void const* addr, u32 size)<br />
|<br />
|-<br />
| 0x55 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Corelink DMA Engines|StartInterProcessDma]](Handle* dma, Handle dstProcess, void* dst, Handle srcProcess, const void* src, u32 size, const DmaConfig* config)<br />
|<br />
|-<br />
| 0x56 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result StopDma(Handle dma)<br />
|<br />
|-<br />
| 0x57 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result GetDmaState(DmaState* state, Handle dma)<br />
|<br />
|-<br />
| 0x58<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| RestartDma(Handle, void *, void const*, unsigned int, signed char)<br />
|<br />
|-<br />
| 0x59<br />
| style="background: green" | Yes<br />
| style="background: red" | No?<br />
| style="background: red" | No<br />
| SetGpuProt(s8 input_flag). Implemented with [[11.3.0-36|11.3.0-X]], see below.<br />
|-<br />
| 0x5A<br />
| style="background: green" | Yes<br />
| style="background: red" | No?<br />
| style="background: red" | No<br />
| PokeWifiPdnReg(s0 input_flag). Implemented with [[11.4.0-37|11.4.0-X]], see below.<br />
|- style="border-top: double"<br />
| 0x60 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result DebugActiveProcess(Handle* debug, u32 processID)<br />
|<br />
|-<br />
| 0x61 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result BreakDebugProcess(Handle debug)<br />
|<br />
|-<br />
| 0x62 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result TerminateDebugProcess(Handle debug)<br />
|<br />
|-<br />
| 0x63 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetProcessDebugEvent(DebugEventInfo* info, Handle debug)<br />
|<br />
|-<br />
| 0x64 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ContinueDebugEvent(Handle debug, u32 flags)<br />
|<br />
|-<br />
| 0x65 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetProcessList(s32* processCount, u32* processIds, s32 processIdMaxCount)<br />
|<br />
|-<br />
| 0x66 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetThreadList(s32* threadCount, u32* threadIds, s32 threadIdMaxCount, Handle domain)<br />
|<br />
|-<br />
| 0x67 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetDebugThreadContext(ThreadContext* context, Handle debug, u32 threadId, u32 controlFlags)<br />
|<br />
|-<br />
| 0x68 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetDebugThreadContext(Handle debug, u32 threadId, const ThreadContext* context, u32 controlFlags)<br />
|<br />
|-<br />
| 0x69 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result QueryDebugProcessMemory(MemoryInfo* blockInfo, PageInfo* pageInfo, Handle debug, u32 addr)<br />
|<br />
|-<br />
| 0x6A <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReadProcessMemory(void* buffer, Handle debug, u32 addr, u32 size)<br />
|<br />
|-<br />
| 0x6B <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result WriteProcessMemory(Handle debug, void const* buffer, u32 addr, u32 size)<br />
|<br />
|-<br />
| 0x6C <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetHardwareBreakPoint(s32 registerId, u32 control, u32 value)<br />
|<br />
|-<br />
| 0x6D<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| [[Multi-threading#GetDebugThreadParam|GetDebugThreadParam]](s64* unused, u32* out, Handle kdebug, u32 threadId, DebugThreadParameter param)<br />
| <br />
|- style="border-top: double"<br />
| 0x70<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ControlProcessMemory(Handle KProcess, unsigned int Addr0, unsigned int Addr1, unsigned int Size, unsigned int Type, unsigned int Permissions)<br />
|<br />
|-<br />
| 0x71<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management#Memory_Mapping|MapProcessMemory]](Handle process, u32 startAddr, u32 size)<br />
|<br />
|-<br />
| 0x72<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management#Memory_Mapping|UnmapProcessMemory]](Handle process, u32 startAddr, u32 size)<br />
|<br />
|-<br />
| 0x73<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#CreateCodeSet|CreateCodeSet]](Handle* handle_out, struct CodeSetInfo, u32 code_ptr, u32 ro_ptr, u32 data_ptr)<br />
|<br />
|-<br />
| 0x74<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result RandomStub()<br />
| Stubbed<br />
|-<br />
| 0x75<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#CreateProcess|CreateProcess]](Handle* handle_out, Handle codeset_handle, u32 [[NCCH/Extended_Header#ARM11_Kernel_Capabilities|arm11kernelcaps_ptr]], u32 arm11kernelcaps_num)<br />
|<br />
|-<br />
| 0x76<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| TerminateProcess(Handle)<br />
|<br />
|-<br />
| 0x77<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetProcessResourceLimits(Handle KProcess, Handle KResourceLimit)<br />
| <br />
|-<br />
| 0x78<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result CreateResourceLimit(Handle *KResourceLimit)<br />
|<br />
|-<br />
| 0x79<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetResourceLimitValues(Handle res_limit, LimitableResource* resource_type_list, s64* resource_list, u32 count)<br />
|<br />
|-<br />
| 0x7A<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: green" | Yes<br />
| AddCodeSegment (unsigned int Addr, unsigned int Size)<br />
| Stubbed on NATIVE_FIRM beginning with [[2.0.0-2]]. Used during TWL_FIRM boot.<br />
|-<br />
| 0x7B<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| Backdoor(unsigned int CodeAddress)<br />
| This is used on ARM9 NATIVE_FIRM. <br />
No ARM11 processes have access to it without some form of kernelhax, and this was removed on [[11.0.0-33]] (for ARM11).<br />
<br />
|-<br />
| 0x7C<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| KernelSetState(unsigned int Type, ...)<br />
| The type determines the args to be passed<br />
|-<br />
| 0x7D<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result QueryProcessMemory(MemInfo *Info, unsigned int *Out, Handle KProcess, unsigned int Addr)<br />
|<br />
|- style="border-top: double"<br />
| 0xFF<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Stop point<br />
| The svcaccesscontrol mask doesn't apply for this SVC. This svc doesn't check the "debug mode enabled" flag either. Does nothing if there is no [[KDebug]] object associated to the current process. Stubbed on ARM9 NATIVE_FIRM.<br />
|}<br />
NF: NATIVE_FIRM. TF: TWL_FIRM.<br />
<br />
Note that "stubbed" here means that the SVC only returns an error, as in the following snippet:<br />
<br />
<pre>ROM:FFF04D98 LDR R0, =0xF8C007F4<br />
ROM:FFF04D9C BX LR</pre><br />
<br />
= Types and structures =<br />
<br />
== enum ResetType ==<br />
<br />
{| class="wikitable" border="1"<br />
! Reset type<br />
! Id<br />
|-<br />
| ONESHOT<br />
| 0<br />
|-<br />
| STICKY<br />
| 1<br />
|-<br />
| PULSE<br />
| 2<br />
|}<br />
<br />
Timers/Events may be waited on by a thread using svcWaitSynchronization. Once the timer runs out/the event gets signaled, threads waiting on the respective handles until the timer/event is reset. STICKY timers/events wake up threads until they are explicitly reset by some thread. ONESHOT timers/events will wake up exactly one thread and then are reset automatically. PULSE timers will be reset after waking up one thread too, but will also be started again immediately. It's unknown whether PULSE is a valid reset type for events.<br />
<br />
== struct StartupInfo ==<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| s32<br />
| Priority<br />
|-<br />
| u32<br />
| Stack size<br />
|-<br />
| s32<br />
| argc<br />
|-<br />
| s16*<br />
| argv<br />
|-<br />
| s16*<br />
| envp<br />
|}<br />
<br />
== enum BreakReason ==<br />
{| class="wikitable" border="1"<br />
! Break Reason<br />
! Value<br />
|-<br />
| PANIC<br />
| 0<br />
|-<br />
| ASSERT<br />
| 1<br />
|-<br />
| USER<br />
| 2<br />
|}<br />
<br />
== struct DebugEventInfo ==<br />
Size: 0x28 bytes<br />
<br />
When using svcGetProcessDebugEvent, the kernel fetches the first [[KEventInfo]] instance of the process's [[KDebug]]. The debug event is handled and parsed into this structure.<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Event type<br />
|-<br />
| u32<br />
| Thread ID (not used in all events)<br />
|-<br />
| u32<br />
| Flags. Bit0 means that svcContinueDebugEvent needs to be called for this event (except for EXIT PROCESS events, for which you need to call svcContinueDebugEvent even if this bit is clear)<br />
|-<br />
| u8[4]<br />
| Remnants of the corresponding flags in [[KEventInfo]], always 0 here<br />
|-<br />
| u32[6]<br />
| Event-specific data (see below)<br />
|}<br />
<br />
{| class="wikitable" border="1"<br />
! Event type<br />
! Id<br />
|-<br />
| ATTACH PROCESS<br />
| 0<br />
|-<br />
| ATTACH THREAD<br />
| 1<br />
|-<br />
| EXIT THREAD<br />
| 2<br />
|-<br />
| EXIT PROCESS<br />
| 3<br />
|-<br />
| EXCEPTION<br />
| 4<br />
|-<br />
| DLL LOAD *<br />
| 5<br />
|-<br />
| DLL UNLOAD *<br />
| 6<br />
|-<br />
| SCHEDULE IN **<br />
| 7<br />
|-<br />
| SCHEDULE OUT *<br />
| 8<br />
|-<br />
| SYSCALL IN *<br />
| 9<br />
|-<br />
| SYSCALL OUT *<br />
| 10<br />
|-<br />
| OUTPUT STRING<br />
| 11<br />
|-<br />
| MAP *<br />
| 12<br />
|}<br />
<br />
<nowiki>*</nowiki> Unused<br />
<br />
<nowiki>**</nowiki> Referenced but never used in practise<br />
<br />
When calling svcDebugActiveProcess, an ATTACH PROCESS debug event is signaled, then ATTACH THREAD for each of its opened threads, then finally ATTACH BREAK.<br />
<br />
ATTACH THREAD events are also emitted when a thread is created from an attached process.<br />
<br />
=== ATTACH PROCESS event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u64<br />
| Program ID<br />
|-<br />
| char[8]<br />
| Process name<br />
|-<br />
| u32<br />
| Process ID<br />
|-<br />
| u32<br />
| "Other" flag. Always 0 in available kernel versions<br />
|}<br />
<br />
=== ATTACH THREAD event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Creator thread ID (0 if attached by svcDebugActiveProcess)<br />
|-<br />
| void *<br />
| Thread local storage<br />
|-<br />
| u32 *<br />
| Entrypoint = .text load address of the parent process<br />
|}<br />
<br />
=== EXIT THREAD/PROCESS events ===<br />
<br />
A single u32 reason field is used.<br />
<br />
Thread exit reasons:<br />
{| class="wikitable" border="1"<br />
! Reason<br />
! Id<br />
|-<br />
| (None)<br />
| 0<br />
|-<br />
| TERMINATE<br />
| 1<br />
|-<br />
| EXIT PROCESS<br />
| 2<br />
|-<br />
| TERMINATE PROCESS<br />
| 3<br />
|}<br />
<br />
Process exit reasons:<br />
{| class="wikitable" border="1"<br />
! Reason<br />
! Id<br />
|-<br />
| (None)<br />
| 0<br />
|-<br />
| TERMINATE<br />
| 1<br />
|-<br />
| UNHANDLED EXCEPTION<br />
| 2<br />
|}<br />
<br />
=== EXCEPTION event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Exception type<br />
|-<br />
| u32<br />
| Exception address<br />
|-<br />
| u32[4]<br />
| Type-specific data, see below<br />
|}<br />
<br />
Exception types:<br />
{| class="wikitable" border="1"<br />
! Exception type<br />
! Id<br />
|-<br />
| UNDEFINED INSTRUCTION<br />
| 0<br />
|-<br />
| PREFETCH ABORT<br />
| 1<br />
|-<br />
| DATA ABORT<br />
| 2<br />
|-<br />
| UNALIGNED DATA ACCESS<br />
| 3<br />
|-<br />
| ATTACH BREAK<br />
| 4<br />
|-<br />
| STOP POINT<br />
| 5<br />
|-<br />
| USER BREAK<br />
| 6<br />
|-<br />
| DEBUGGER BREAK<br />
| 7<br />
|-<br />
| UNDEFINED SYSCALL<br />
| 8<br />
|}<br />
<br />
==== UNDEFINED INSTRUCTION/PREFETCH ABORT/DATA ABORT/UNALIGNED DATA ACCESS/UNDEFINED SYSCALL events ====<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Fault information: Fault Address Register (for DATA ABORT and UNALIGNED DATA ACCESS),<br />
attempted SVC ID (for UNDEFINED SYSCALL), otherwise 0<br />
|}<br />
<br />
==== STOP POINT event ====<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Stop point type that caused the event: 0 = svc 0xFF, 1 = breakpoint, 2 = watchpoint<br />
|-<br />
| u32<br />
| Fault information: FAR for watchpoints, 0 otherwise<br />
|}<br />
<br />
==== USER BREAK event ====<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Break reason<br />
|-<br />
| u32[2]<br />
| Info for LOAD_RO and UNLOAD_RO<br />
|}<br />
<br />
User break types:<br />
{| class="wikitable" border="1"<br />
! Reason<br />
! Id<br />
|-<br />
| PANIC<br />
| 0<br />
|-<br />
| ASSERT<br />
| 1<br />
|-<br />
| USER<br />
| 2<br />
|-<br />
| LOAD_RO<br />
| 3<br />
|-<br />
| UNLOAD_RO<br />
| 4<br />
|}<br />
<br />
==== DEBUGGER BREAK event ====<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| s32[4]<br />
| IDs of the attached process's threads that were running on each core at the time of the @ref svcBreakDebugProcess call, or -1 (only the first 2 values are meaningful on O3DS).<br />
|}<br />
<br />
=== SCHEDULE/SYSCALL IN/OUT events ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u64<br />
| Clock tick<br />
|-<br />
| u32<br />
| CPU ID (SCHEDULE events) Syscall (SYSCALL events)<br />
|}<br />
<br />
=== OUTPUT STRING event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| String address<br />
|-<br />
| u32<br />
| String size<br />
|}<br />
<br />
=== MAP event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Mapped address<br />
|-<br />
| u32<br />
| Mapped size<br />
|-<br />
| u32<br />
| MemoryPermission<br />
|-<br />
| u32<br />
| MemoryState<br />
|}<br />
<br />
== struct ThreadContext ==<br />
<br />
Size: 0xCC bytes<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Offset<br />
! Type<br />
! Description<br />
|-<br />
| 0x0<br />
| CpuRegisters<br />
| Saved CPU registers (r0-r12, sp, lr, pc, cpsr)<br />
|-<br />
| 0x44<br />
| FpuRegisters<br />
| Saved FPU registers (d0-d15, fpscr, fpexc)<br />
|}<br />
<br />
The user needs to adjust pc for exceptions that occured while in Thumb mode.<br />
<br />
'''Flags for svcGetDebugThreadContext/svcSetDebugThreadContext''':<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Get/set CPU GPRs (r0-r12)<br />
|-<br />
| 1<br />
| Get/set CPU SPRs (sp, lr, pc, cpsr)<br />
|-<br />
| 2<br />
| Get/set FPU GPRs (d0-d15 aka. f0-f31)<br />
|-<br />
| 3<br />
| Get/set FPU SPRs (fpscr, fpexc)<br />
|}<br />
<br />
When setting CPSR, the following assignment is done: <code>ctx->cpsr = ctx->cpsr & 0x7F0FDFF | userCtx->cpuRegisters.cpsr & 0xF80F0200;</code>. This is to avoid obvious security issues.<br />
<br />
== enum DebugThreadParameter ==<br />
<br />
{| class="wikitable" border="1"<br />
! Parameter<br />
! Id<br />
|-<br />
| PRIORITY<br />
| 0<br />
|-<br />
| SCHEDULING_MASK_LOW<br />
| 1<br />
|-<br />
| CPU_IDEAL<br />
| 2<br />
|-<br />
| CPU_CREATOR<br />
| 3<br />
|}<br />
<br />
== typedef Handle ==<br />
<br />
User-visible references to internal objects are represented by 32-bit integers called handles. Handles are only valid in the process they have been created in; hence, they cannot be exchanged between processes directly (the [[IPC]] functions provide a mean to copy handles to other processes, though).<br />
<br />
There are a number of special-purpose handles, which provide easy access to information on objects in the current process:<br />
{| class="wikitable" border="1"<br />
! Handle<br />
! Description<br />
|-<br />
| 0xFFFF8000<br />
| Handle to the active thread<br />
|-<br />
| 0xFFFF8001<br />
| Handle to the active process<br />
|}<br />
<br />
=svcSetHardwareBreakPoint=<br />
This is essentially an interface for writing values to the debug-unit (B/W)RP registers. registerId range 0..5 = breakpoints(BRP0-5), 0x100..0x101 = watchpoints(WRP0-1), anything outside of these ranges will result in an error. This is used for both adding and removing/disabling breakpoints/watchpoints, hence the raw control value parameter.<br />
<br />
Here the kernel sets bit15 in the DSCR, to enable monitor-mode debugging.<br />
<br />
Regardless of whether this is for a BRP, when bit21 is set in the control input parameter(BRP type = contextID), the kernel will load the target process [[KProcess|contextID]] and use that internally for the value field. The target process is specified via a [[KDebug]] handle passed as the "value" parameter.<br />
<br />
Lastly, the kernel disables the specified (B/W)RP, then writes the value parameter / loaded contextID to the (B/W)VR, then writes the input control value to the (B/W)CR.<br />
<br />
= [[DMA]] =<br />
The CTRSDK code for using svcStartInterProcessDma will execute svcBreak when svcStartInterProcessDma returns an error(except for certain error value(s)). Therefore on retail, triggering a svcStartInterProcessDma via a system-module which results in an error from svcStartInterProcessDma will result in the system-module terminating.<br />
<br />
= Interrupt Handling =<br />
<br />
svcBindInterrupt registers the given event or semaphore corresponding to the handle to the global [[ARM11_Interrupts#Interrupt_Table_.28New3DS.29|"interrupt table"]] for the given interrupt ID. Interrupts 0-14 and 16-31 can never be mapped regardless of the [[NCCH/Extended_Header#ARM11_Kernel_Capabilities|interrupt flags of the process's exheader]], and the latter are not checked when mapping interrupt 15. The "is level high active"/"is manual clear" parameter must be false when binding a semaphore handle (otherwise 0xD8E007EE "invalid combination" is returned).<br />
<br />
If something was already registered for the given ID, svcBindInterrupt returns error 0xD8E007F0. See [[KBaseInterruptEvent]] for more information on what happens on receipt of an interrupt.<br />
<br />
Applications hence can wait for specific interrupts to happen by calling WaitSynchronization(N) on the event or semaphore handles.<br />
<br />
The set of existing ARM11 interrupts is listed on [[ARM11 Interrupts|this page]].<br />
<br />
= Debugging =<br />
DebugActiveProcess is used to attach to a process for debugging. This SVC can only be used when the target process' ARM11 descriptors stored in the exheader have the kernel flag for "Enable debug" set. Otherwise when that flag is clear, the kernel flags for the process using this SVC must have the "Force debug" flag set.<br />
<br />
This SVC can only be used when a certain kernel state debug flag is non-zero(it's set to zero for retail).<br />
<br />
= KernelSetState =<br />
KernelSetState uses the 6th [[ARM11_Interrupts#Private_Interrupts|software-generated interrupt]] for any operation involving synchronization between cores.<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Type<br />
! Enabled for the NATIVE_FIRM ARM11 kernel<br />
! Enabled for the TWL_FIRM ARM11 kernel<br />
! Description<br />
|-<br />
| 0<br />
| Yes<br />
| No<br />
| Arguments : <code>u64 firmTitleID</code> (the high 32-bits of that title ID (0 when using N3DS pm) have a special meaning on N3DS, they're otherwise ignored, see below).<br />
This initializes the programID for launching [[FIRM]], then triggers launching [[FIRM]]. With New3DS kernel, it forces the firm title ID to be the New3DS NATIVE_FIRM, when the input firm title ID is 2. The high firm title ID is always set to 0x40138. On New3DS, the kernel disables the additional New3DS cache hw prior to calling the firmlaunch function from the <handler for the KernelSetState-types called via funcptr>.<br />
|-<br />
| 1<br />
| Yes<br />
| Yes<br />
| Does nothing.<br />
|-<br />
| 2<br />
| Yes<br />
| Yes<br />
| Powers down the GPU and syncs with Process9 (waits for <code>*(vu8 *)PXI_SYNC11</code> to be 1) during the process.<br />
On New3DS, the kernel disables the additional New3DS cache hw, when it's actually enabled, prior to executing the rest of the code from the <handler for the KernelSetState-types called via funcptr>.<br />
|-<br />
| 3<br />
| Yes<br />
| No<br />
| Arguments: <code>0, void* address</code> or <code>1</code><br />
This used for initializing the 0x1000-byte buffer used by the launched [[FIRM]]. When the first parameter is 1, this buffer is copied to the beginning of FCRAM at 0xE0000000. When it is 0, this kernel buffer is mapped to the process address specified by the second argument.<br />
|-<br />
| 4<br />
| No<br />
| Yes<br />
| This unmaps(?) the following virtual memory by writing value physaddr (where physaddr base is 0x80000000) to the L1 MMU table entries: 0x00300000..0x04300000, 0x08000000..0x0FE00000, and 0x10000000..0xF8000000.<br />
|-<br />
| 5<br />
| Yes<br />
| Yes<br />
| Used by kernelpanic. This makes core0 enter a WFI/B infinite loop. Threads that were created on core1 or core2 have their priority set to 0x3F, except if the thread was created on core1 and whose parent process (if any) has the "Runnable on sleep" [[NCCH/Extended_Header#ARM11_Kernel_Flags|ARM11 kernel flag]] set. Core1 threads with a priority of 0x40 without a parent process have their priority set to 0x3E.<br />
<br />
Prior to first invoking this handler, the global variable holding <code>UNITINFO != 0</code> is true, and if there is no [[LCD_Registers#Fill_Color|LCD fill]] set at the time kernelpanic is called, kernelpanic fills the top screen with red and the bottom screen with either yellow (if the current process was running under the APPLICATION memregion) or red. <br />
<br />
Before invoking this handler a second time, kernelpanic wait for the user to hold L+R+Start+Select down.<br />
|-<br />
| 6<br />
| Yes<br />
| No<br />
| Arguments: <code>u32 what, u64 val</code><br />
UNITINFO needs to be non-zero. <br />
<br />
If <code>what</code> is 0 or any invalid value, nothing is done. <br />
<br />
If it is 1, <code>val != 0</code> is written to the global variable enabling ERR:F-format register dumps on user-mode CPU/VFP exceptions (the VFP exception handler acts as if this variable was always true and works on retail environments). The user handler, stack pointer to use for exception handling, and pointer to use for the exception info structure are contiguously located in either the thread's TLS, or if the handler is NULL, in the main thread's TLS, at offset 0x40. If the specified stack pointer is 1, sp_usr - 0x5c is used instead; if the specified exception info buffer is 1, sp_usr - 0x5c is used instead, and if it is 0, <specified stack> - 0x5c is used (0x5c is the size of the exception info structure that is being pushed). Configured by NS on startup on dev-units (default being 0 on non-debugger/jtag units).<br />
<br />
If 2, kernelpanic will be called when svcBreak is used by a non-attached process. Configured by NS on startup on dev-units (default being 0 on non-debugger/jtag units).<br />
<br />
If 3, this changes the scheduling/preemption mode (when no threads are being preempted, otherwise returns error 0xC8A01414), see [[KResourceLimit]] for more details.<br />
|-<br />
| 7<br />
| Yes<br />
| No<br />
| This triggers an MCU (hard) reboot. This reboot is triggered via device address 0x4A on the second [[I2C]] bus (the MCU). Register address 0x20 is written to with value 4. This code will not return.<br />
On New3DS, the kernel disables the additional New3DS cache hw prior to calling the reboot function from the <handler for the KernelSetState-types called via funcptr>.<br />
|-<br />
| 8<br />
| Yes<br />
| No<br />
| Alternate FIRM launch code-path, with different [[PXI]] FIFO word constants. Usually not used. PTM-sysmodule can use this but it's unknown what exactly triggers that in PTM-sysmodule.<br />
|-<br />
| 9<br />
| Yes, implemented at some point after system-version v4.5.<br />
| ?<br />
| Argumens: <code>u64 titleID</code>.<br />
When creating a process, if the process has a non-zero TID equal to the parameter above (which is stored in a global variable), then KProcessHwInfo+0x32 ("process is the currently running app") is set to <code>true</code>.<br />
Used by NS conditionally based on the contents of the [[NS CFA]].<br />
|-<br />
| 10<br />
| Yes<br />
| ?<br />
| Arguments: <code>u32 config</code><br />
ConfigureNew3DSCPU. Only available for the [[New_3DS]] kernel. The actual code for processing this runs under the <handler for the KernelSetState-types called via funcptr>, which runs on all ARM11 cores. Only bit0-1 of the argument are used here. Bit 0 enables higher core clock, and bit 1 enables additional (L2) cache. This configures the hardware [[PDN_Registers|register]] for the flags listed [[NCCH/Extended_Header#Flag1|here]], among other code which uses the MPCore private memory region registers.<br />
|}<br />
<br />
= GetSystemInfo =<br />
{| class="wikitable" border="1"<br />
! SystemInfoType value<br />
! s32 param<br />
! Description<br />
|-<br />
| 0<br />
| 0<br />
| This writes the total used memory size in the following memory regions to out: APPLICATION, SYSTEM, and BASE.<br />
|-<br />
| 0<br />
| 1<br />
| This writes the total used memory size in the APPLICATION memory region to out.<br />
|-<br />
| 0<br />
| 2<br />
| This writes the total used memory size in the SYSTEM memory region to out.<br />
|-<br />
| 0<br />
| 3<br />
| This writes the total used memory size in the BASE memory region to out.<br />
|-<br />
| 2<br />
| Unused<br />
| This writes the FCRAM memory [[Memory_Allocation#FCRAM_Region_Data|used by the kernel]] to out.<br />
|-<br />
| 25<br />
| Unused<br />
| This writes the total number of threads which were directly launched by the kernel, to out. No longer exists with some kernel version?<br />
|-<br />
| 26<br />
| Unused<br />
| This writes the total number of processes which were directly launched by the kernel, to out. For the NATIVE_FIRM/SAFE_MODE_FIRM ARM11 kernel, this is normally 5, for processes sm, fs, pm, loader, and pxi.<br />
|}<br />
<br />
= GetProcessInfo =<br />
Input:<br />
R0 = unused<br />
R1 = Handle process<br />
R2 = ProcessInfoType type<br />
<br />
Output:<br />
R0 = Result<br />
R1 = output value lower word<br />
R2 = output value upper word<br />
<br />
{| class="wikitable" border="1"<br />
! ProcessInfoType value<br />
! Available since system version<br />
! Description<br />
|-<br />
| 0<br />
| <br />
| Returns the amount of executable memory allocated to the process + thread context size + page-rounded size of the external handle table<br />
|-<br />
| 1<br />
| <br />
| Returns the amount of <unknown> memory allocated to the process + thread context size + page-rounded size of the external handle table<br />
|-<br />
| 2<br />
| <br />
| Returns the amount of DMA-able (code, data, IO pages, etc.) memory allocated to the process + thread context size + page-rounded size of the external handle table<br />
|-<br />
| 3<br />
| <br />
| Returns the amount of <unknown> memory allocated to the process + thread context size + page-rounded size of the external handle table<br />
|-<br />
| 4<br />
| <br />
| Returns the amount handles in use by the process.<br />
|-<br />
| 5<br />
| <br />
| Returns the highest count of handles that have been open at once by the process<br />
|-<br />
| 6<br />
| <br />
| Returns <code>*(u32*)(KProcess+0x234)</code> which is always 0<br />
|-<br />
| 7<br />
| <br />
| Returns 0<br />
|-<br />
| 8<br />
| <br />
| Returns the maximum number of threads which can be opened by this process (always 0)<br />
|-<br />
| 9-18<br />
| [[8.0.0-18]]<br />
| This only returns error 0xD8E007ED.<br />
|-<br />
| 19<br />
| Stub: [[8.0.0-18]]. Implementation: [[11.3.0-36|11.3.0-X]].<br />
| Originally this only returned 0xD8E007ED. Now with v11.3 this returns the memregion for the process: out low u32 = [[KProcess]] "Kernel flags from the exheader kernel descriptors" & 0xF00. High out u32 = 0.<br />
|-<br />
| 20<br />
| [[8.0.0-18]]<br />
| low u32 = (0x20000000 - <LINEAR virtual-memory base for this process>). That is, the output value is the value which can be added to LINEAR memory vaddrs for converting to physical-memory addrs.<br />
|-<br />
| 21<br />
| [[8.0.0-18]]. N3DS only.<br />
| Returns the maximum amount of VRAM memory allocatable by the process: 0x800000 bytes if the process has already allocated VRAM memory, otherwise 0 (+ error 0xE0E01BF4)<br />
|-<br />
| 22<br />
| [[8.0.0-18]]. N3DS only.<br />
| Returns the address of the first chunk of VRAM allocated by this process<br />
|-<br />
| 23<br />
| [[8.0.0-18]]. N3DS only.<br />
| Returns the amount of VRAM allocated by this process (?)<br />
|}<br />
<br />
= GetHandleInfo =<br />
<br />
{| class="wikitable" border="1"<br />
! HandleInfoType value<br />
! Description<br />
|-<br />
| 0<br />
| This returns the time in ticks the KProcess referenced by the handle was created. If a KProcess handle was not given, it will write whatever was in r5, r6 when the svc was called.<br />
|-<br />
| 1<br />
| Get internal refcount for kernel object (not counting the one this SVC adds internally to operate), and also a boolean if it is 0 (prior to substracting 1, as explained before).<br />
|-<br />
| 0x32107<br />
| Returns (u64) 0.<br />
|}<br />
<br />
= svc7B Backdoor =<br />
This saves SVC-mode SP+LR on the user-mode stack, then sets the SVC-mode SP to the user-mode SP. This then calls the specified code in SVC-mode. Once the called code returns, this pops the saved SP+LR off the stack for restoring the SVC-mode SP, then returns from the svc7b handler. Note that this svc7b handler does not disable IRQs, if any IRQs/context-switches occur while the SVC-mode SP is set to the user-mode one here, the ARM11-kernel will crash(which hangs the whole ARM11-side system).<br />
<br />
= svc 0x59 =<br />
Implemented with [[11.3.0-36|11.3.0-X]]. Used with GSP module starting with that version. This always returns 0.<br />
<br />
When input_flag is not 0x1, it will use value 0x0 internally. When a state field already matches input_flag, this will immediately return. Otherwise, after this SVC finishes running, it will write input_flag to this state field. GSP module uses 0x0 for APPLICATION-memregionid and 0x1 for non-APPLICATION-memregionid.<br />
<br />
This writes "<nowiki>0x100 | <val></nowiki>" to [[CONFIG11_Registers#CFG11_GPUPROT|pdnregbase+0x140]], where val depends on input_flag and a kernel state field for [[Configuration_Memory|APPMEMTYPE]].<br />
<br />
When input_flag is 0x1 val is fixed:<br />
* Old3DS: 0x3<br />
* New3DS: 0x460<br />
<br />
Otherwise, val depends on the kernel APPMEMTYPE state field:<br />
{| class="wikitable" border="1"<br />
|-<br />
! FIRM<br />
! [[Memory_layout|APPMEMTYPE]]<br />
! val<br />
|-<br />
| Old3DS<br />
| 2<br />
| 0x3<br />
|-<br />
| Old3DS<br />
| 3<br />
| 0x5<br />
|-<br />
| Old3DS<br />
| 4<br />
| 0x6<br />
|-<br />
| Old3DS<br />
| Non-value-{2/3/4}<br />
| 0x7<br />
|-<br />
| New3DS<br />
| 7<br />
| 0x490<br />
|-<br />
| New3DS<br />
| Non-value-7<br />
| 0x4F0<br />
|}<br />
<br />
This same register is also initialized during kernel boot starting with [[3.0.0-5]], with the following values:<br />
* Old3DS: 0x103<br />
* New3DS: 0x550<br />
<br />
= svc 0x5A =<br />
Based on what NWM did previously, it looks like this one does the following:<br />
<br />
if (in_flag == 1)<br />
*(u8*)0x10140180 |= 1;<br />
else<br />
*(u8*)0x10140180 &~ 1;<br />
<br />
= Kernel error-codes =<br />
See [[Error codes]].<br />
<br />
{| class="wikitable" border="1"<br />
! Error-code value<br />
! Description<br />
|-<br />
| 0x09401BFE<br />
| Timeout occurred with svcWaitSynchronization*, when timeout is not ~0.<br />
|-<br />
| 0xC8601801<br />
| No more unused/free synchronization objects left to use in a given object's linked list. (KEvent, KMutex, KTimer, KSemaphore, KAddressArbiter, KThread)<br />
|-<br />
| 0xC8601802<br />
| No more unused/free KSharedMemory objects left to use in the KSharedMemory linked list - out of blocks<br />
|-<br />
| 0xC8601809<br />
| No more unused/free KSessions left to use in the KSession linked list - out of sessions<br />
|-<br />
| 0xC860180A<br />
| Not enough free memory available for memory allocation.<br />
|-<br />
| 0xC920181A<br />
| The session was closed by the other process..<br />
|-<br />
| 0xD0401834<br />
| Max connections to port have been exceeded<br />
|-<br />
| 0xD8609013<br />
| Unknown, probably reslimit related?<br />
|-<br />
| 0xD88007FA<br />
| Returned if no KObjectName object in the linked list of such objects matches the port name provided to the svc. <br />
|-<br />
| 0xD8E007ED<br />
| This indicates that a value is outside of the enum being used.<br />
|-<br />
| 0xD8E007F1<br />
| This error indicates Misaligned address.<br />
|-<br />
| 0xD8E007F7<br />
| This error indicates that the input handle used with the SVC does not exist in the process handle-table, or that the handle kernel object type does not match the type used by the SVC.<br />
|-<br />
| 0xD9000402<br />
| Invalid memory permissions for input/output buffers, for svcStartInterProcessDma.<br />
|-<br />
| 0xD9001814<br />
| Failed unprivileged load or store - wrong permissions on memory<br />
|-<br />
| 0xD9001BF7<br />
| This error is returned when the kernel retrieves a pointer to a kernel object, but the object type doesn't match the desired one.<br />
|-<br />
| 0xD92007EA<br />
| This error is returned when a process attempts to use svcCreateMemoryBlock when the process memorytype is the application memorytype, and when addr=0.<br />
|-<br />
| 0xE0E01BF5<br />
| This indicates an invalid address was used.<br />
|-<br />
| 0xF8C007F4<br />
| Invalid type/param0-param3 input for svcKernelSetState. This is also returned for those syscalls marked as stubs.<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=11.4.0-37&diff=19827
11.4.0-37
2017-04-10T23:22:03Z
<p>Plutooo: </p>
<hr />
<div>The Old3DS+New3DS 11.4.0-37 system update was released on April 10, 2017. This Old3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN. This New3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN.<br />
<br />
Security flaws fixed: yes.<br />
<br />
==Change-log==<br />
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/667/p/430/c/267 Official] USA change-log:<br />
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience<br />
<br />
==System Titles==<br />
<fill this in (manually) later><br />
<br />
===[[NWM_Services|NWM-sysmodule]]===<br />
The [[CONFIG11_Registers]] are no longer directly mapped under userland for NWM-sysmodule.<br />
This prevents anything under NWM-module from modifying the GPUPROT register.<br />
<br />
The crt0-poke in PDN that NWM previously did:<br />
0x1EC4010C |= 0x10<br />
<br />
.. has been removed from NWM. This one has presumably moved into kernel bootup.<br />
<br />
Reads from 0x1EC40180 have been replaced by a new syscall, [[SVC|0x5A]].<br />
<br />
==See Also==<br />
System update report(s):<br />
* [https://yls8.mtheall.com/ninupdates/reports.php?date=04-10-17_08-00-38&sys=ctr]<br />
* [https://yls8.mtheall.com/ninupdates/reports.php?date=04-10-17_08-00-47&sys=ktr]</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=SVC&diff=19826
SVC
2017-04-10T23:19:11Z
<p>Plutooo: /* System calls */</p>
<hr />
<div>= System calls =<br />
'''Note: The argument-lists here apply to the official syscall wrapper-functions that are found in userland processes. The actual ordering passed to the kernel via the SVC instruction is documented in [[Kernel_ABI|Kernel ABI]].'''<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Id<br />
! NF ARM11<br />
! NF ARM9<br />
! TF ARM11<br />
! Description<br />
! scope="col" width="200" | Notes<br />
|-<br />
| 0x01 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|ControlMemory]](u32* outaddr, u32 addr0, u32 addr1, u32 size, [[Memory Management#enum_MemoryOperation|MemoryOperation]] operation, [[Memory Management#enum_MemoryPermission|MemoryPermission]] permissions)<br />
| Outaddr is usually the same as the input addr0.<br />
|-<br />
| 0x02 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|QueryMemory]]([[Memory Management#struct MemoryInfo|MemoryInfo]]* info, [[Memory Management#struct PageInfo|PageInfo]]* out, u32 Addr)<br />
|<br />
|-<br />
| 0x03 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| void ExitProcess(void)<br />
|<br />
|-<br />
| 0x04 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetProcessAffinityMask(u8* affinitymask, Handle process, s32 processorcount)<br />
|<br />
|-<br />
| 0x05 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetProcessAffinityMask(Handle process, u8* affinitymask, s32 processorcount)<br />
|<br />
|-<br />
| 0x06 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetProcessIdealProcessor(s32 *idealprocessor, Handle process)<br />
|<br />
|-<br />
| 0x07 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetProcessIdealProcessor(Handle process, s32 idealprocessor)<br />
|<br />
|-<br />
| 0x08 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#CreateThread|CreateThread]](Handle* thread, func entrypoint, u32 arg, u32 stacktop, s32 threadpriority, s32 processorid)<br />
|<br />
|-<br />
| 0x09 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| void [[Multi-threading#ExitThread|ExitThread]](void)<br />
|<br />
|-<br />
| 0x0A <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| void [[Multi-threading#SleepThread|SleepThread]](s64 nanoseconds)<br />
|<br />
|-<br />
| 0x0B <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#GetThreadPriority|GetThreadPriority]](s32* priority, Handle thread)<br />
|<br />
|-<br />
| 0x0C <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#SetThreadPriority|SetThreadPriority]](Handle thread, s32 priority)<br />
|<br />
|-<br />
| 0x0D <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#GetThreadAffinityMask|GetThreadAffinityMask]](u8* affinitymask, Handle thread, s32 processorcount)<br />
|<br />
|-<br />
| 0x0E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#SetThreadAffinityMask|SetThreadAffinityMask]](Handle thread, u8* affinitymask, s32 processorcount)<br />
| Replaced with a stub in ARM11 NATIVE_FIRM kernel beginning with [[8.0.0-18]].<br />
|-<br />
| 0x0F <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#GetThreadIdealProcessor|GetThreadIdealProcessor]](s32* processorid, Handle thread)<br />
|<br />
|-<br />
| 0x10 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#SetThreadIdealProcessor|SetThreadIdealProcessor]](Handle thread, s32 processorid)<br />
| Replaced with a stub in ARM11 NATIVE_FIRM kernel beginning with [[8.0.0-18]].<br />
|-<br />
| 0x11 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| s32 GetCurrentProcessorNumber(void)<br />
|<br />
|-<br />
| 0x12 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#Run|Run]](Handle process, StartupInfo* info)<br />
| This starts the main() thread. Buf+0 is main-thread priority, Buf+4 is main-thread stack-size.<br />
|-<br />
| 0x13 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#CreateMutex|CreateMutex]](Handle* mutex, bool initialLocked)<br />
|<br />
|-<br />
| 0x14 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#ReleaseMutex|ReleaseMutex]](Handle mutex)<br />
|<br />
|-<br />
| 0x15 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#CreateSemaphore|CreateSemaphore]](Handle* semaphore, s32 initialCount, s32 maxCount)<br />
|<br />
|-<br />
| 0x16 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#ReleaseSemaphore|ReleaseSemaphore]](s32* count, Handle semaphore, s32 releaseCount)<br />
|<br />
|-<br />
| 0x17 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#CreateEvent|CreateEvent]](Handle* event, ResetType resettype)<br />
|<br />
|-<br />
| 0x18 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#SignalEvent|SignalEvent]](Handle event)<br />
|<br />
|-<br />
| 0x19 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#ClearEvent|ClearEvent]](Handle event)<br />
|<br />
|-<br />
| 0x1A <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result CreateTimer(Handle* timer, ResetType resettype)<br />
|<br />
|-<br />
| 0x1B <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result SetTimer(Handle timer, s64 initial_nanoseconds, s64 interval)<br />
|<br />
|-<br />
| 0x1C <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result CancelTimer(Handle timer)<br />
|<br />
|-<br />
| 0x1D <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result ClearTimer(Handle timer)<br />
|<br />
|-<br />
| 0x1E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|CreateMemoryBlock]](Handle* memblock, u32 addr, u32 size, [[Memory Management#enum_MemoryPermission|MemoryPermission]] mypermission, [[Memory Management#enum_MemoryPermission|MemoryPermission]] otherpermission)<br />
|<br />
|-<br />
| 0x1F <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|MapMemoryBlock]](Handle memblock, u32 addr, [[Memory Management#enum_MemoryPermission|MemoryPermission]] mypermissions, [[Memory Management#enum_MemoryPermission|MemoryPermission]] otherpermission)<br />
|<br />
|-<br />
| 0x20 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management|UnmapMemoryBlock]](Handle memblock, u32 addr)<br />
|<br />
|-<br />
| 0x21 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#Address_Arbiters|CreateAddressArbiter]](Handle* arbiter)<br />
|<br />
|-<br />
| 0x22 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#Address_Arbiters|ArbitrateAddress]](Handle arbiter, u32 addr, ArbitrationType type, s32 value, s64 nanoseconds)<br />
|<br />
|-<br />
| 0x23 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result CloseHandle(Handle handle)<br />
|<br />
|-<br />
| 0x24 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result WaitSynchronization1(Handle handle, s64 timeout_nanoseconds)<br />
|<br />
|-<br />
| 0x25 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result WaitSynchronizationN(s32* out, Handle* handles, s32 handlecount, bool waitAll, s64 timeout_nanoseconds)<br />
|<br />
|-<br />
| 0x26 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SignalAndWait(s32* out, Handle signal, Handle* handles, s32 handleCount, bool waitAll, s64 nanoseconds)<br />
| Stubbed<br />
|-<br />
| 0x27 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result DuplicateHandle(Handle* out, Handle original)<br />
|<br />
|-<br />
| 0x28 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| s64 GetSystemTick(void) (This returns the total CPU ticks elapsed since the CPU was powered-on)<br />
|<br />
|-<br />
| 0x29 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetHandleInfo(s64* out, Handle handle, HandleInfoType type)<br />
|<br />
|-<br />
| 0x2A <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result GetSystemInfo(s64* out, SystemInfoType type, s32 param)<br />
|<br />
|-<br />
| 0x2B <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result GetProcessInfo(s64* out, Handle process, ProcessInfoType type)<br />
|<br />
|-<br />
| 0x2C <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#GetThreadInfo|GetThreadInfo]](s64* out, Handle thread, ThreadInfoType type)<br />
|<br />
|-<br />
| 0x2D <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|ConnectToPort]](Handle* out, const char* portName)<br />
|<br />
|-<br />
| 0x2E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SendSyncRequest1(Handle session)<br />
| Stubbed<br />
|<br />
|-<br />
| 0x2F <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SendSyncRequest2(Handle session)<br />
| Stubbed<br />
|<br />
|-<br />
| 0x30 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SendSyncRequest3(Handle session)<br />
| Stubbed<br />
|<br />
|-<br />
| 0x31 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SendSyncRequest4(Handle session)<br />
| Stubbed<br />
|<br />
|-<br />
| 0x32 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|SendSyncRequest]](Handle session)<br />
|<br />
|-<br />
| 0x33 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result OpenProcess(Handle* process, u32 processId)<br />
|<br />
|-<br />
| 0x34 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#OpenThread|OpenThread]](Handle* thread, Handle process, u32 threadId)<br />
|<br />
|-<br />
| 0x35 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: green" | Yes<br />
| Result GetProcessId(u32* processId, Handle process)<br />
|<br />
|-<br />
| 0x36 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#GetProcessIdOfThread|GetProcessIdOfThread]](u32* processId, Handle thread)<br />
|<br />
|-<br />
| 0x37 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Multi-threading#GetThreadId|GetThreadId]](u32* threadId, Handle thread)<br />
|<br />
|-<br />
| 0x38 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetResourceLimit(Handle* resourceLimit, Handle process)<br />
|<br />
|-<br />
| 0x39 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetResourceLimitLimitValues(s64* values, Handle resourceLimit, LimitableResource* names, s32 nameCount)<br />
|<br />
|-<br />
| 0x3A <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetResourceLimitCurrentValues(s64* values, Handle resourceLimit, LimitableResource* names, s32 nameCount)<br />
|<br />
|-<br />
| 0x3B <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#GetThreadContext|GetThreadContext]](ThreadContext* context, Handle thread)<br />
| Stubbed<br />
|-<br />
| 0x3C <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Break(BreakReason reason)<br />
Break(BreakReason debugReason, const void* croInfo, u32 croInfoSize)<br />
|<br />
|-<br />
| 0x3D <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| OutputDebugString(void const, int)<br />
| Does nothing on non-debug units.<br />
|-<br />
| 0x3E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| ControlPerformanceCounter(unsigned long long, int, unsigned int, unsigned long long)<br />
|<br />
|- style="border-top: double"<br />
| 0x47 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|CreatePort]](Handle* portServer, Handle* portClient, const char* name, s16 maxSessions)<br />
| Setting name=NULL creates a private port not accessible from svcConnectToPort.<br />
|-<br />
| 0x48 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|CreateSessionToPort]](Handle* session, Handle port)<br />
|<br />
|-<br />
| 0x49 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|CreateSession]](Handle* sessionServer, Handle* sessionClient)<br />
|<br />
|-<br />
| 0x4A <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|AcceptSession]](Handle* session, Handle port)<br />
|<br />
|-<br />
| 0x4B <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReplyAndReceive1(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
| Stubbed.<br />
|-<br />
| 0x4C <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReplyAndReceive2(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
| Stubbed.<br />
|-<br />
| 0x4D <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReplyAndReceive3(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
| Stubbed.<br />
|-<br />
| 0x4E <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReplyAndReceive4(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
| Stubbed.<br />
|-<br />
| 0x4F <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[IPC|ReplyAndReceive]](s32* index, Handle* handles, s32 handleCount, Handle replyTarget)<br />
|<br />
|-<br />
| 0x50 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[#Interrupt Handling|BindInterrupt]](Interrupt name, Handle eventOrSemaphore, s32 priority, bool isLevelHighActive)<br />
|<br />
|-<br />
| 0x51 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result UnbindInterrupt(Interrupt name, Handle eventOrSemaphore)<br />
|<br />
|-<br />
| 0x52 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result InvalidateProcessDataCache(Handle process, void* addr, u32 size)<br />
|<br />
|-<br />
| 0x53 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result StoreProcessDataCache(Handle process, void const* addr, u32 size)<br />
|<br />
|-<br />
| 0x54 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result FlushProcessDataCache(Handle process, void const* addr, u32 size)<br />
|<br />
|-<br />
| 0x55 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result [[Corelink DMA Engines|StartInterProcessDma]](Handle* dma, Handle dstProcess, void* dst, Handle srcProcess, const void* src, u32 size, const DmaConfig* config)<br />
|<br />
|-<br />
| 0x56 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result StopDma(Handle dma)<br />
|<br />
|-<br />
| 0x57 <br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Result GetDmaState(DmaState* state, Handle dma)<br />
|<br />
|-<br />
| 0x58<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| RestartDma(Handle, void *, void const*, unsigned int, signed char)<br />
|<br />
|-<br />
| 0x59<br />
| style="background: green" | Yes<br />
| style="background: red" | No?<br />
| style="background: red" | No<br />
| SetGpuProt(s8 input_flag). Implemented with [[11.3.0-36|11.3.0-X]], see below.<br />
|-<br />
| 0x5A<br />
| style="background: green" | Yes<br />
| style="background: red" | No?<br />
| style="background: red" | No<br />
| GetWifiPdnReg<br />
|- style="border-top: double"<br />
| 0x60 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result DebugActiveProcess(Handle* debug, u32 processID)<br />
|<br />
|-<br />
| 0x61 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result BreakDebugProcess(Handle debug)<br />
|<br />
|-<br />
| 0x62 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result TerminateDebugProcess(Handle debug)<br />
|<br />
|-<br />
| 0x63 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetProcessDebugEvent(DebugEventInfo* info, Handle debug)<br />
|<br />
|-<br />
| 0x64 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ContinueDebugEvent(Handle debug, u32 flags)<br />
|<br />
|-<br />
| 0x65 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetProcessList(s32* processCount, u32* processIds, s32 processIdMaxCount)<br />
|<br />
|-<br />
| 0x66 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetThreadList(s32* threadCount, u32* threadIds, s32 threadIdMaxCount, Handle domain)<br />
|<br />
|-<br />
| 0x67 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result GetDebugThreadContext(ThreadContext* context, Handle debug, u32 threadId, u32 controlFlags)<br />
|<br />
|-<br />
| 0x68 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetDebugThreadContext(Handle debug, u32 threadId, const ThreadContext* context, u32 controlFlags)<br />
|<br />
|-<br />
| 0x69 <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result QueryDebugProcessMemory(MemoryInfo* blockInfo, PageInfo* pageInfo, Handle debug, u32 addr)<br />
|<br />
|-<br />
| 0x6A <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ReadProcessMemory(void* buffer, Handle debug, u32 addr, u32 size)<br />
|<br />
|-<br />
| 0x6B <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result WriteProcessMemory(Handle debug, void const* buffer, u32 addr, u32 size)<br />
|<br />
|-<br />
| 0x6C <br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetHardwareBreakPoint(s32 registerId, u32 control, u32 value)<br />
|<br />
|-<br />
| 0x6D<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| [[Multi-threading#GetDebugThreadParam|GetDebugThreadParam]](s64* unused, u32* out, Handle kdebug, u32 threadId, DebugThreadParameter param)<br />
| <br />
|- style="border-top: double"<br />
| 0x70<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result ControlProcessMemory(Handle KProcess, unsigned int Addr0, unsigned int Addr1, unsigned int Size, unsigned int Type, unsigned int Permissions)<br />
|<br />
|-<br />
| 0x71<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management#Memory_Mapping|MapProcessMemory]](Handle process, u32 startAddr, u32 size)<br />
|<br />
|-<br />
| 0x72<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Memory Management#Memory_Mapping|UnmapProcessMemory]](Handle process, u32 startAddr, u32 size)<br />
|<br />
|-<br />
| 0x73<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#CreateCodeSet|CreateCodeSet]](Handle* handle_out, struct CodeSetInfo, u32 code_ptr, u32 ro_ptr, u32 data_ptr)<br />
|<br />
|-<br />
| 0x74<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result RandomStub()<br />
| Stubbed<br />
|-<br />
| 0x75<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result [[Multi-threading#CreateProcess|CreateProcess]](Handle* handle_out, Handle codeset_handle, u32 [[NCCH/Extended_Header#ARM11_Kernel_Capabilities|arm11kernelcaps_ptr]], u32 arm11kernelcaps_num)<br />
|<br />
|-<br />
| 0x76<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| TerminateProcess(Handle)<br />
|<br />
|-<br />
| 0x77<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetProcessResourceLimits(Handle KProcess, Handle KResourceLimit)<br />
| <br />
|-<br />
| 0x78<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result CreateResourceLimit(Handle *KResourceLimit)<br />
|<br />
|-<br />
| 0x79<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result SetResourceLimitValues(Handle res_limit, LimitableResource* resource_type_list, s64* resource_list, u32 count)<br />
|<br />
|-<br />
| 0x7A<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: green" | Yes<br />
| AddCodeSegment (unsigned int Addr, unsigned int Size)<br />
| Stubbed on NATIVE_FIRM beginning with [[2.0.0-2]]. Used during TWL_FIRM boot.<br />
|-<br />
| 0x7B<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| Backdoor(unsigned int CodeAddress)<br />
| This is used on ARM9 NATIVE_FIRM. <br />
No ARM11 processes have access to it without some form of kernelhax, and this was removed on [[11.0.0-33]] (for ARM11).<br />
<br />
|-<br />
| 0x7C<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| KernelSetState(unsigned int Type, ...)<br />
| The type determines the args to be passed<br />
|-<br />
| 0x7D<br />
| style="background: green" | Yes<br />
| style="background: red" | No<br />
| style="background: red" | No<br />
| Result QueryProcessMemory(MemInfo *Info, unsigned int *Out, Handle KProcess, unsigned int Addr)<br />
|<br />
|- style="border-top: double"<br />
| 0xFF<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| style="background: green" | Yes<br />
| Stop point<br />
| The svcaccesscontrol mask doesn't apply for this SVC. This svc doesn't check the "debug mode enabled" flag either. Does nothing if there is no [[KDebug]] object associated to the current process. Stubbed on ARM9 NATIVE_FIRM.<br />
|}<br />
NF: NATIVE_FIRM. TF: TWL_FIRM.<br />
<br />
Note that "stubbed" here means that the SVC only returns an error, as in the following snippet:<br />
<br />
<pre>ROM:FFF04D98 LDR R0, =0xF8C007F4<br />
ROM:FFF04D9C BX LR</pre><br />
<br />
= Types and structures =<br />
<br />
== enum ResetType ==<br />
<br />
{| class="wikitable" border="1"<br />
! Reset type<br />
! Id<br />
|-<br />
| ONESHOT<br />
| 0<br />
|-<br />
| STICKY<br />
| 1<br />
|-<br />
| PULSE<br />
| 2<br />
|}<br />
<br />
Timers/Events may be waited on by a thread using svcWaitSynchronization. Once the timer runs out/the event gets signaled, threads waiting on the respective handles until the timer/event is reset. STICKY timers/events wake up threads until they are explicitly reset by some thread. ONESHOT timers/events will wake up exactly one thread and then are reset automatically. PULSE timers will be reset after waking up one thread too, but will also be started again immediately. It's unknown whether PULSE is a valid reset type for events.<br />
<br />
== struct StartupInfo ==<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| s32<br />
| Priority<br />
|-<br />
| u32<br />
| Stack size<br />
|-<br />
| s32<br />
| argc<br />
|-<br />
| s16*<br />
| argv<br />
|-<br />
| s16*<br />
| envp<br />
|}<br />
<br />
== enum BreakReason ==<br />
{| class="wikitable" border="1"<br />
! Break Reason<br />
! Value<br />
|-<br />
| PANIC<br />
| 0<br />
|-<br />
| ASSERT<br />
| 1<br />
|-<br />
| USER<br />
| 2<br />
|}<br />
<br />
== struct DebugEventInfo ==<br />
Size: 0x28 bytes<br />
<br />
When using svcGetProcessDebugEvent, the kernel fetches the first [[KEventInfo]] instance of the process's [[KDebug]]. The debug event is handled and parsed into this structure.<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Event type<br />
|-<br />
| u32<br />
| Thread ID (not used in all events)<br />
|-<br />
| u32<br />
| Flags. Bit0 means that svcContinueDebugEvent needs to be called for this event (except for EXIT PROCESS events, for which you need to call svcContinueDebugEvent even if this bit is clear)<br />
|-<br />
| u8[4]<br />
| Remnants of the corresponding flags in [[KEventInfo]], always 0 here<br />
|-<br />
| u32[6]<br />
| Event-specific data (see below)<br />
|}<br />
<br />
{| class="wikitable" border="1"<br />
! Event type<br />
! Id<br />
|-<br />
| ATTACH PROCESS<br />
| 0<br />
|-<br />
| ATTACH THREAD<br />
| 1<br />
|-<br />
| EXIT THREAD<br />
| 2<br />
|-<br />
| EXIT PROCESS<br />
| 3<br />
|-<br />
| EXCEPTION<br />
| 4<br />
|-<br />
| DLL LOAD *<br />
| 5<br />
|-<br />
| DLL UNLOAD *<br />
| 6<br />
|-<br />
| SCHEDULE IN **<br />
| 7<br />
|-<br />
| SCHEDULE OUT *<br />
| 8<br />
|-<br />
| SYSCALL IN *<br />
| 9<br />
|-<br />
| SYSCALL OUT *<br />
| 10<br />
|-<br />
| OUTPUT STRING<br />
| 11<br />
|-<br />
| MAP *<br />
| 12<br />
|}<br />
<br />
<nowiki>*</nowiki> Unused<br />
<br />
<nowiki>**</nowiki> Referenced but never used in practise<br />
<br />
When calling svcDebugActiveProcess, an ATTACH PROCESS debug event is signaled, then ATTACH THREAD for each of its opened threads, then finally ATTACH BREAK.<br />
<br />
ATTACH THREAD events are also emitted when a thread is created from an attached process.<br />
<br />
=== ATTACH PROCESS event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u64<br />
| Program ID<br />
|-<br />
| char[8]<br />
| Process name<br />
|-<br />
| u32<br />
| Process ID<br />
|-<br />
| u32<br />
| "Other" flag. Always 0 in available kernel versions<br />
|}<br />
<br />
=== ATTACH THREAD event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Creator thread ID (0 if attached by svcDebugActiveProcess)<br />
|-<br />
| void *<br />
| Thread local storage<br />
|-<br />
| u32 *<br />
| Entrypoint = .text load address of the parent process<br />
|}<br />
<br />
=== EXIT THREAD/PROCESS events ===<br />
<br />
A single u32 reason field is used.<br />
<br />
Thread exit reasons:<br />
{| class="wikitable" border="1"<br />
! Reason<br />
! Id<br />
|-<br />
| (None)<br />
| 0<br />
|-<br />
| TERMINATE<br />
| 1<br />
|-<br />
| EXIT PROCESS<br />
| 2<br />
|-<br />
| TERMINATE PROCESS<br />
| 3<br />
|}<br />
<br />
Process exit reasons:<br />
{| class="wikitable" border="1"<br />
! Reason<br />
! Id<br />
|-<br />
| (None)<br />
| 0<br />
|-<br />
| TERMINATE<br />
| 1<br />
|-<br />
| UNHANDLED EXCEPTION<br />
| 2<br />
|}<br />
<br />
=== EXCEPTION event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Exception type<br />
|-<br />
| u32<br />
| Exception address<br />
|-<br />
| u32[4]<br />
| Type-specific data, see below<br />
|}<br />
<br />
Exception types:<br />
{| class="wikitable" border="1"<br />
! Exception type<br />
! Id<br />
|-<br />
| UNDEFINED INSTRUCTION<br />
| 0<br />
|-<br />
| PREFETCH ABORT<br />
| 1<br />
|-<br />
| DATA ABORT<br />
| 2<br />
|-<br />
| UNALIGNED DATA ACCESS<br />
| 3<br />
|-<br />
| ATTACH BREAK<br />
| 4<br />
|-<br />
| STOP POINT<br />
| 5<br />
|-<br />
| USER BREAK<br />
| 6<br />
|-<br />
| DEBUGGER BREAK<br />
| 7<br />
|-<br />
| UNDEFINED SYSCALL<br />
| 8<br />
|}<br />
<br />
==== UNDEFINED INSTRUCTION/PREFETCH ABORT/DATA ABORT/UNALIGNED DATA ACCESS/UNDEFINED SYSCALL events ====<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Fault information: Fault Address Register (for DATA ABORT and UNALIGNED DATA ACCESS),<br />
attempted SVC ID (for UNDEFINED SYSCALL), otherwise 0<br />
|}<br />
<br />
==== STOP POINT event ====<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Stop point type that caused the event: 0 = svc 0xFF, 1 = breakpoint, 2 = watchpoint<br />
|-<br />
| u32<br />
| Fault information: FAR for watchpoints, 0 otherwise<br />
|}<br />
<br />
==== USER BREAK event ====<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Break reason<br />
|-<br />
| u32[2]<br />
| Info for LOAD_RO and UNLOAD_RO<br />
|}<br />
<br />
User break types:<br />
{| class="wikitable" border="1"<br />
! Reason<br />
! Id<br />
|-<br />
| PANIC<br />
| 0<br />
|-<br />
| ASSERT<br />
| 1<br />
|-<br />
| USER<br />
| 2<br />
|-<br />
| LOAD_RO<br />
| 3<br />
|-<br />
| UNLOAD_RO<br />
| 4<br />
|}<br />
<br />
==== DEBUGGER BREAK event ====<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| s32[4]<br />
| IDs of the attached process's threads that were running on each core at the time of the @ref svcBreakDebugProcess call, or -1 (only the first 2 values are meaningful on O3DS).<br />
|}<br />
<br />
=== SCHEDULE/SYSCALL IN/OUT events ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u64<br />
| Clock tick<br />
|-<br />
| u32<br />
| CPU ID (SCHEDULE events) Syscall (SYSCALL events)<br />
|}<br />
<br />
=== OUTPUT STRING event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| String address<br />
|-<br />
| u32<br />
| String size<br />
|}<br />
<br />
=== MAP event ===<br />
<br />
{| class="wikitable" border="1"<br />
! Type<br />
! Field<br />
|-<br />
| u32<br />
| Mapped address<br />
|-<br />
| u32<br />
| Mapped size<br />
|-<br />
| u32<br />
| MemoryPermission<br />
|-<br />
| u32<br />
| MemoryState<br />
|}<br />
<br />
== struct ThreadContext ==<br />
<br />
Size: 0xCC bytes<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Offset<br />
! Type<br />
! Description<br />
|-<br />
| 0x0<br />
| CpuRegisters<br />
| Saved CPU registers (r0-r12, sp, lr, pc, cpsr)<br />
|-<br />
| 0x44<br />
| FpuRegisters<br />
| Saved FPU registers (d0-d15, fpscr, fpexc)<br />
|}<br />
<br />
The user needs to adjust pc for exceptions that occured while in Thumb mode.<br />
<br />
'''Flags for svcGetDebugThreadContext/svcSetDebugThreadContext''':<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Get/set CPU GPRs (r0-r12)<br />
|-<br />
| 1<br />
| Get/set CPU SPRs (sp, lr, pc, cpsr)<br />
|-<br />
| 2<br />
| Get/set FPU GPRs (d0-d15 aka. f0-f31)<br />
|-<br />
| 3<br />
| Get/set FPU SPRs (fpscr, fpexc)<br />
|}<br />
<br />
When setting CPSR, the following assignment is done: <code>ctx->cpsr = ctx->cpsr & 0x7F0FDFF | userCtx->cpuRegisters.cpsr & 0xF80F0200;</code>. This is to avoid obvious security issues.<br />
<br />
== enum DebugThreadParameter ==<br />
<br />
{| class="wikitable" border="1"<br />
! Parameter<br />
! Id<br />
|-<br />
| PRIORITY<br />
| 0<br />
|-<br />
| SCHEDULING_MASK_LOW<br />
| 1<br />
|-<br />
| CPU_IDEAL<br />
| 2<br />
|-<br />
| CPU_CREATOR<br />
| 3<br />
|}<br />
<br />
== typedef Handle ==<br />
<br />
User-visible references to internal objects are represented by 32-bit integers called handles. Handles are only valid in the process they have been created in; hence, they cannot be exchanged between processes directly (the [[IPC]] functions provide a mean to copy handles to other processes, though).<br />
<br />
There are a number of special-purpose handles, which provide easy access to information on objects in the current process:<br />
{| class="wikitable" border="1"<br />
! Handle<br />
! Description<br />
|-<br />
| 0xFFFF8000<br />
| Handle to the active thread<br />
|-<br />
| 0xFFFF8001<br />
| Handle to the active process<br />
|}<br />
<br />
=svcSetHardwareBreakPoint=<br />
This is essentially an interface for writing values to the debug-unit (B/W)RP registers. registerId range 0..5 = breakpoints(BRP0-5), 0x100..0x101 = watchpoints(WRP0-1), anything outside of these ranges will result in an error. This is used for both adding and removing/disabling breakpoints/watchpoints, hence the raw control value parameter.<br />
<br />
Here the kernel sets bit15 in the DSCR, to enable monitor-mode debugging.<br />
<br />
Regardless of whether this is for a BRP, when bit21 is set in the control input parameter(BRP type = contextID), the kernel will load the target process [[KProcess|contextID]] and use that internally for the value field. The target process is specified via a [[KDebug]] handle passed as the "value" parameter.<br />
<br />
Lastly, the kernel disables the specified (B/W)RP, then writes the value parameter / loaded contextID to the (B/W)VR, then writes the input control value to the (B/W)CR.<br />
<br />
= [[DMA]] =<br />
The CTRSDK code for using svcStartInterProcessDma will execute svcBreak when svcStartInterProcessDma returns an error(except for certain error value(s)). Therefore on retail, triggering a svcStartInterProcessDma via a system-module which results in an error from svcStartInterProcessDma will result in the system-module terminating.<br />
<br />
= Interrupt Handling =<br />
<br />
svcBindInterrupt registers the given event or semaphore corresponding to the handle to the global [[ARM11_Interrupts#Interrupt_Table_.28New3DS.29|"interrupt table"]] for the given interrupt ID. Interrupts 0-14 and 16-31 can never be mapped regardless of the [[NCCH/Extended_Header#ARM11_Kernel_Capabilities|interrupt flags of the process's exheader]], and the latter are not checked when mapping interrupt 15. The "is level high active"/"is manual clear" parameter must be false when binding a semaphore handle (otherwise 0xD8E007EE "invalid combination" is returned).<br />
<br />
If something was already registered for the given ID, svcBindInterrupt returns error 0xD8E007F0. See [[KBaseInterruptEvent]] for more information on what happens on receipt of an interrupt.<br />
<br />
Applications hence can wait for specific interrupts to happen by calling WaitSynchronization(N) on the event or semaphore handles.<br />
<br />
The set of existing ARM11 interrupts is listed on [[ARM11 Interrupts|this page]].<br />
<br />
= Debugging =<br />
DebugActiveProcess is used to attach to a process for debugging. This SVC can only be used when the target process' ARM11 descriptors stored in the exheader have the kernel flag for "Enable debug" set. Otherwise when that flag is clear, the kernel flags for the process using this SVC must have the "Force debug" flag set.<br />
<br />
This SVC can only be used when a certain kernel state debug flag is non-zero(it's set to zero for retail).<br />
<br />
= KernelSetState =<br />
KernelSetState uses the 6th [[ARM11_Interrupts#Private_Interrupts|software-generated interrupt]] for any operation involving synchronization between cores.<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Type<br />
! Enabled for the NATIVE_FIRM ARM11 kernel<br />
! Enabled for the TWL_FIRM ARM11 kernel<br />
! Description<br />
|-<br />
| 0<br />
| Yes<br />
| No<br />
| Arguments : <code>u64 firmTitleID</code> (the high 32-bits of that title ID (0 when using N3DS pm) have a special meaning on N3DS, they're otherwise ignored, see below).<br />
This initializes the programID for launching [[FIRM]], then triggers launching [[FIRM]]. With New3DS kernel, it forces the firm title ID to be the New3DS NATIVE_FIRM, when the input firm title ID is 2. The high firm title ID is always set to 0x40138. On New3DS, the kernel disables the additional New3DS cache hw prior to calling the firmlaunch function from the <handler for the KernelSetState-types called via funcptr>.<br />
|-<br />
| 1<br />
| Yes<br />
| Yes<br />
| Does nothing.<br />
|-<br />
| 2<br />
| Yes<br />
| Yes<br />
| Powers down the GPU and syncs with Process9 (waits for <code>*(vu8 *)PXI_SYNC11</code> to be 1) during the process.<br />
On New3DS, the kernel disables the additional New3DS cache hw, when it's actually enabled, prior to executing the rest of the code from the <handler for the KernelSetState-types called via funcptr>.<br />
|-<br />
| 3<br />
| Yes<br />
| No<br />
| Arguments: <code>0, void* address</code> or <code>1</code><br />
This used for initializing the 0x1000-byte buffer used by the launched [[FIRM]]. When the first parameter is 1, this buffer is copied to the beginning of FCRAM at 0xE0000000. When it is 0, this kernel buffer is mapped to the process address specified by the second argument.<br />
|-<br />
| 4<br />
| No<br />
| Yes<br />
| This unmaps(?) the following virtual memory by writing value physaddr (where physaddr base is 0x80000000) to the L1 MMU table entries: 0x00300000..0x04300000, 0x08000000..0x0FE00000, and 0x10000000..0xF8000000.<br />
|-<br />
| 5<br />
| Yes<br />
| Yes<br />
| Used by kernelpanic. This makes core0 enter a WFI/B infinite loop. Threads that were created on core1 or core2 have their priority set to 0x3F, except if the thread was created on core1 and whose parent process (if any) has the "Runnable on sleep" [[NCCH/Extended_Header#ARM11_Kernel_Flags|ARM11 kernel flag]] set. Core1 threads with a priority of 0x40 without a parent process have their priority set to 0x3E.<br />
<br />
Prior to first invoking this handler, the global variable holding <code>UNITINFO != 0</code> is true, and if there is no [[LCD_Registers#Fill_Color|LCD fill]] set at the time kernelpanic is called, kernelpanic fills the top screen with red and the bottom screen with either yellow (if the current process was running under the APPLICATION memregion) or red. <br />
<br />
Before invoking this handler a second time, kernelpanic wait for the user to hold L+R+Start+Select down.<br />
|-<br />
| 6<br />
| Yes<br />
| No<br />
| Arguments: <code>u32 what, u64 val</code><br />
UNITINFO needs to be non-zero. <br />
<br />
If <code>what</code> is 0 or any invalid value, nothing is done. <br />
<br />
If it is 1, <code>val != 0</code> is written to the global variable enabling ERR:F-format register dumps on user-mode CPU/VFP exceptions (the VFP exception handler acts as if this variable was always true and works on retail environments). The user handler, stack pointer to use for exception handling, and pointer to use for the exception info structure are contiguously located in either the thread's TLS, or if the handler is NULL, in the main thread's TLS, at offset 0x40. If the specified stack pointer is 1, sp_usr - 0x5c is used instead; if the specified exception info buffer is 1, sp_usr - 0x5c is used instead, and if it is 0, <specified stack> - 0x5c is used (0x5c is the size of the exception info structure that is being pushed). Configured by NS on startup on dev-units (default being 0 on non-debugger/jtag units).<br />
<br />
If 2, kernelpanic will be called when svcBreak is used by a non-attached process. Configured by NS on startup on dev-units (default being 0 on non-debugger/jtag units).<br />
<br />
If 3, this changes the scheduling/preemption mode (when no threads are being preempted, otherwise returns error 0xC8A01414), see [[KResourceLimit]] for more details.<br />
|-<br />
| 7<br />
| Yes<br />
| No<br />
| This triggers an MCU (hard) reboot. This reboot is triggered via device address 0x4A on the second [[I2C]] bus (the MCU). Register address 0x20 is written to with value 4. This code will not return.<br />
On New3DS, the kernel disables the additional New3DS cache hw prior to calling the reboot function from the <handler for the KernelSetState-types called via funcptr>.<br />
|-<br />
| 8<br />
| Yes<br />
| No<br />
| Alternate FIRM launch code-path, with different [[PXI]] FIFO word constants. Usually not used. PTM-sysmodule can use this but it's unknown what exactly triggers that in PTM-sysmodule.<br />
|-<br />
| 9<br />
| Yes, implemented at some point after system-version v4.5.<br />
| ?<br />
| Argumens: <code>u64 titleID</code>.<br />
When creating a process, if the process has a non-zero TID equal to the parameter above (which is stored in a global variable), then KProcessHwInfo+0x32 ("process is the currently running app") is set to <code>true</code>.<br />
Used by NS conditionally based on the contents of the [[NS CFA]].<br />
|-<br />
| 10<br />
| Yes<br />
| ?<br />
| Arguments: <code>u32 config</code><br />
ConfigureNew3DSCPU. Only available for the [[New_3DS]] kernel. The actual code for processing this runs under the <handler for the KernelSetState-types called via funcptr>, which runs on all ARM11 cores. Only bit0-1 of the argument are used here. Bit 0 enables higher core clock, and bit 1 enables additional (L2) cache. This configures the hardware [[PDN_Registers|register]] for the flags listed [[NCCH/Extended_Header#Flag1|here]], among other code which uses the MPCore private memory region registers.<br />
|}<br />
<br />
= GetSystemInfo =<br />
{| class="wikitable" border="1"<br />
! SystemInfoType value<br />
! s32 param<br />
! Description<br />
|-<br />
| 0<br />
| 0<br />
| This writes the total used memory size in the following memory regions to out: APPLICATION, SYSTEM, and BASE.<br />
|-<br />
| 0<br />
| 1<br />
| This writes the total used memory size in the APPLICATION memory region to out.<br />
|-<br />
| 0<br />
| 2<br />
| This writes the total used memory size in the SYSTEM memory region to out.<br />
|-<br />
| 0<br />
| 3<br />
| This writes the total used memory size in the BASE memory region to out.<br />
|-<br />
| 2<br />
| Unused<br />
| This writes the FCRAM memory [[Memory_Allocation#FCRAM_Region_Data|used by the kernel]] to out.<br />
|-<br />
| 25<br />
| Unused<br />
| This writes the total number of threads which were directly launched by the kernel, to out. No longer exists with some kernel version?<br />
|-<br />
| 26<br />
| Unused<br />
| This writes the total number of processes which were directly launched by the kernel, to out. For the NATIVE_FIRM/SAFE_MODE_FIRM ARM11 kernel, this is normally 5, for processes sm, fs, pm, loader, and pxi.<br />
|}<br />
<br />
= GetProcessInfo =<br />
Input:<br />
R0 = unused<br />
R1 = Handle process<br />
R2 = ProcessInfoType type<br />
<br />
Output:<br />
R0 = Result<br />
R1 = output value lower word<br />
R2 = output value upper word<br />
<br />
{| class="wikitable" border="1"<br />
! ProcessInfoType value<br />
! Available since system version<br />
! Description<br />
|-<br />
| 0<br />
| <br />
| Returns the amount of executable memory allocated to the process + thread context size + page-rounded size of the external handle table<br />
|-<br />
| 1<br />
| <br />
| Returns the amount of <unknown> memory allocated to the process + thread context size + page-rounded size of the external handle table<br />
|-<br />
| 2<br />
| <br />
| Returns the amount of DMA-able (code, data, IO pages, etc.) memory allocated to the process + thread context size + page-rounded size of the external handle table<br />
|-<br />
| 3<br />
| <br />
| Returns the amount of <unknown> memory allocated to the process + thread context size + page-rounded size of the external handle table<br />
|-<br />
| 4<br />
| <br />
| Returns the amount handles in use by the process.<br />
|-<br />
| 5<br />
| <br />
| Returns the highest count of handles that have been open at once by the process<br />
|-<br />
| 6<br />
| <br />
| Returns <code>*(u32*)(KProcess+0x234)</code> which is always 0<br />
|-<br />
| 7<br />
| <br />
| Returns 0<br />
|-<br />
| 8<br />
| <br />
| Returns the maximum number of threads which can be opened by this process (always 0)<br />
|-<br />
| 9-18<br />
| [[8.0.0-18]]<br />
| This only returns error 0xD8E007ED.<br />
|-<br />
| 19<br />
| Stub: [[8.0.0-18]]. Implementation: [[11.3.0-36|11.3.0-X]].<br />
| Originally this only returned 0xD8E007ED. Now with v11.3 this returns the memregion for the process: out low u32 = [[KProcess]] "Kernel flags from the exheader kernel descriptors" & 0xF00. High out u32 = 0.<br />
|-<br />
| 20<br />
| [[8.0.0-18]]<br />
| low u32 = (0x20000000 - <LINEAR virtual-memory base for this process>). That is, the output value is the value which can be added to LINEAR memory vaddrs for converting to physical-memory addrs.<br />
|-<br />
| 21<br />
| [[8.0.0-18]]. N3DS only.<br />
| Returns the maximum amount of VRAM memory allocatable by the process: 0x800000 bytes if the process has already allocated VRAM memory, otherwise 0 (+ error 0xE0E01BF4)<br />
|-<br />
| 22<br />
| [[8.0.0-18]]. N3DS only.<br />
| Returns the address of the first chunk of VRAM allocated by this process<br />
|-<br />
| 23<br />
| [[8.0.0-18]]. N3DS only.<br />
| Returns the amount of VRAM allocated by this process (?)<br />
|}<br />
<br />
= GetHandleInfo =<br />
<br />
{| class="wikitable" border="1"<br />
! HandleInfoType value<br />
! Description<br />
|-<br />
| 0<br />
| This returns the time in ticks the KProcess referenced by the handle was created. If a KProcess handle was not given, it will write whatever was in r5, r6 when the svc was called.<br />
|-<br />
| 1<br />
| Get internal refcount for kernel object (not counting the one this SVC adds internally to operate), and also a boolean if it is 0 (prior to substracting 1, as explained before).<br />
|-<br />
| 0x32107<br />
| Returns (u64) 0.<br />
|}<br />
<br />
= svc7B Backdoor =<br />
This saves SVC-mode SP+LR on the user-mode stack, then sets the SVC-mode SP to the user-mode SP. This then calls the specified code in SVC-mode. Once the called code returns, this pops the saved SP+LR off the stack for restoring the SVC-mode SP, then returns from the svc7b handler. Note that this svc7b handler does not disable IRQs, if any IRQs/context-switches occur while the SVC-mode SP is set to the user-mode one here, the ARM11-kernel will crash(which hangs the whole ARM11-side system).<br />
<br />
= svc 0x59 =<br />
Implemented with [[11.3.0-36|11.3.0-X]]. Used with GSP module starting with that version. This always returns 0.<br />
<br />
When input_flag is not 0x1, it will use value 0x0 internally. When a state field already matches input_flag, this will immediately return. Otherwise, after this SVC finishes running, it will write input_flag to this state field. GSP module uses 0x0 for APPLICATION-memregionid and 0x1 for non-APPLICATION-memregionid.<br />
<br />
This writes "<nowiki>0x100 | <val></nowiki>" to [[CONFIG11_Registers#CFG11_GPUPROT|pdnregbase+0x140]], where val depends on input_flag and a kernel state field for [[Configuration_Memory|APPMEMTYPE]].<br />
<br />
When input_flag is 0x1 val is fixed:<br />
* Old3DS: 0x3<br />
* New3DS: 0x460<br />
<br />
Otherwise, val depends on the kernel APPMEMTYPE state field:<br />
{| class="wikitable" border="1"<br />
|-<br />
! FIRM<br />
! [[Memory_layout|APPMEMTYPE]]<br />
! val<br />
|-<br />
| Old3DS<br />
| 2<br />
| 0x3<br />
|-<br />
| Old3DS<br />
| 3<br />
| 0x5<br />
|-<br />
| Old3DS<br />
| 4<br />
| 0x6<br />
|-<br />
| Old3DS<br />
| Non-value-{2/3/4}<br />
| 0x7<br />
|-<br />
| New3DS<br />
| 7<br />
| 0x490<br />
|-<br />
| New3DS<br />
| Non-value-7<br />
| 0x4F0<br />
|}<br />
<br />
This same register is also initialized during kernel boot starting with [[3.0.0-5]], with the following values:<br />
* Old3DS: 0x103<br />
* New3DS: 0x550<br />
<br />
= Kernel error-codes =<br />
See [[Error codes]].<br />
<br />
{| class="wikitable" border="1"<br />
! Error-code value<br />
! Description<br />
|-<br />
| 0x09401BFE<br />
| Timeout occurred with svcWaitSynchronization*, when timeout is not ~0.<br />
|-<br />
| 0xC8601801<br />
| No more unused/free synchronization objects left to use in a given object's linked list. (KEvent, KMutex, KTimer, KSemaphore, KAddressArbiter, KThread)<br />
|-<br />
| 0xC8601802<br />
| No more unused/free KSharedMemory objects left to use in the KSharedMemory linked list - out of blocks<br />
|-<br />
| 0xC8601809<br />
| No more unused/free KSessions left to use in the KSession linked list - out of sessions<br />
|-<br />
| 0xC860180A<br />
| Not enough free memory available for memory allocation.<br />
|-<br />
| 0xC920181A<br />
| The session was closed by the other process..<br />
|-<br />
| 0xD0401834<br />
| Max connections to port have been exceeded<br />
|-<br />
| 0xD8609013<br />
| Unknown, probably reslimit related?<br />
|-<br />
| 0xD88007FA<br />
| Returned if no KObjectName object in the linked list of such objects matches the port name provided to the svc. <br />
|-<br />
| 0xD8E007ED<br />
| This indicates that a value is outside of the enum being used.<br />
|-<br />
| 0xD8E007F1<br />
| This error indicates Misaligned address.<br />
|-<br />
| 0xD8E007F7<br />
| This error indicates that the input handle used with the SVC does not exist in the process handle-table, or that the handle kernel object type does not match the type used by the SVC.<br />
|-<br />
| 0xD9000402<br />
| Invalid memory permissions for input/output buffers, for svcStartInterProcessDma.<br />
|-<br />
| 0xD9001814<br />
| Failed unprivileged load or store - wrong permissions on memory<br />
|-<br />
| 0xD9001BF7<br />
| This error is returned when the kernel retrieves a pointer to a kernel object, but the object type doesn't match the desired one.<br />
|-<br />
| 0xD92007EA<br />
| This error is returned when a process attempts to use svcCreateMemoryBlock when the process memorytype is the application memorytype, and when addr=0.<br />
|-<br />
| 0xE0E01BF5<br />
| This indicates an invalid address was used.<br />
|-<br />
| 0xF8C007F4<br />
| Invalid type/param0-param3 input for svcKernelSetState. This is also returned for those syscalls marked as stubs.<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=GPU/Internal_Registers&diff=19813
GPU/Internal Registers
2017-04-08T10:58:34Z
<p>Plutooo: </p>
<hr />
<div>[[Category:GPU]]<br />
<br />
== Overview ==<br />
<br />
GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.<br />
<br />
Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).<br />
<br />
In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.<br />
<br />
For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).<br />
<br />
Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.<br />
<br />
The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.<br />
<br />
=== Command Header ===<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0-15<br />
| Command ID<br />
|-<br />
| 16-19<br />
| Parameter mask<br />
|-<br />
| 20-30<br />
| Number of extra parameters (may be zero)<br />
|-<br />
| 31<br />
| Consecutive writing mode<br />
|}<br />
<br />
=== Parameter masking ===<br />
<br />
Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.<br />
<br />
=== Types ===<br />
<br />
There are three main types of registers :<br />
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])<br />
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])<br />
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])<br />
<br />
=== Aliases ===<br />
<br />
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]<br />
<br />
=== Data Types ===<br />
<br />
{| class="wikitable" border="1"<br />
! Name<br />
! Description<br />
|-<br />
| signed<br />
| Signed integer<br />
|-<br />
| unsigned<br />
| Unsigned integer<br />
|-<br />
| floatX.Y.Z<br />
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits<br />
|-<br />
| fixedX.Y.Z<br />
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits<br />
|}<br />
<br />
== Register list ==<br />
<br />
=== Miscellaneous registers (0x000-0x03F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0000<br />
| [[#GPUREG_0000|GPUREG_0000]]<br />
| <br />
|<br />
|-<br />
| 0001<br />
| [[#GPUREG_0001|GPUREG_0001]]<br />
| <br />
|<br />
|-<br />
| 0002<br />
| [[#GPUREG_0002|GPUREG_0002]]<br />
| <br />
|<br />
|-<br />
| 0003<br />
| [[#GPUREG_0003|GPUREG_0003]]<br />
| <br />
|<br />
|-<br />
| 0004<br />
| [[#GPUREG_0004|GPUREG_0004]]<br />
| <br />
|<br />
|-<br />
| 0005<br />
| [[#GPUREG_0005|GPUREG_0005]]<br />
| <br />
|<br />
|-<br />
| 0006<br />
| [[#GPUREG_0006|GPUREG_0006]]<br />
| <br />
|<br />
|-<br />
| 0007<br />
| [[#GPUREG_0007|GPUREG_0007]]<br />
| <br />
|<br />
|-<br />
| 0008<br />
| [[#GPUREG_0008|GPUREG_0008]]<br />
| <br />
|<br />
|-<br />
| 0009<br />
| [[#GPUREG_0009|GPUREG_0009]]<br />
| <br />
|<br />
|-<br />
| 000A<br />
| [[#GPUREG_000A|GPUREG_000A]]<br />
| <br />
|<br />
|-<br />
| 000B<br />
| [[#GPUREG_000B|GPUREG_000B]]<br />
| <br />
|<br />
|-<br />
| 000C<br />
| [[#GPUREG_000C|GPUREG_000C]]<br />
| <br />
|<br />
|-<br />
| 000D<br />
| [[#GPUREG_000D|GPUREG_000D]]<br />
| <br />
|<br />
|-<br />
| 000E<br />
| [[#GPUREG_000E|GPUREG_000E]]<br />
| <br />
|<br />
|-<br />
| 000F<br />
| [[#GPUREG_000F|GPUREG_000F]]<br />
| <br />
|<br />
|-<br />
| 0010<br />
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]<br />
| <br />
|PICA_REG_INTERRUPT<br />
|-<br />
| 0011<br />
| [[#GPUREG_0011|GPUREG_0011]]<br />
| <br />
|<br />
|-<br />
| 0012<br />
| [[#GPUREG_0012|GPUREG_0012]]<br />
| <br />
|<br />
|-<br />
| 0013<br />
| [[#GPUREG_0013|GPUREG_0013]]<br />
| <br />
|<br />
|-<br />
| 0014<br />
| [[#GPUREG_0014|GPUREG_0014]]<br />
| <br />
|<br />
|-<br />
| 0015<br />
| [[#GPUREG_0015|GPUREG_0015]]<br />
| <br />
|<br />
|-<br />
| 0016<br />
| [[#GPUREG_0016|GPUREG_0016]]<br />
| <br />
|<br />
|-<br />
| 0017<br />
| [[#GPUREG_0017|GPUREG_0017]]<br />
| <br />
|<br />
|-<br />
| 0018<br />
| [[#GPUREG_0018|GPUREG_0018]]<br />
| <br />
|<br />
|-<br />
| 0019<br />
| [[#GPUREG_0019|GPUREG_0019]]<br />
| <br />
|<br />
|-<br />
| 001A<br />
| [[#GPUREG_001A|GPUREG_001A]]<br />
| <br />
|<br />
|-<br />
| 001B<br />
| [[#GPUREG_001B|GPUREG_001B]]<br />
| <br />
|<br />
|-<br />
| 001C<br />
| [[#GPUREG_001C|GPUREG_001C]]<br />
| <br />
|<br />
|-<br />
| 001D<br />
| [[#GPUREG_001D|GPUREG_001D]]<br />
| <br />
|<br />
|-<br />
| 001E<br />
| [[#GPUREG_001E|GPUREG_001E]]<br />
| <br />
|<br />
|-<br />
| 001F<br />
| [[#GPUREG_001F|GPUREG_001F]]<br />
| <br />
|<br />
|-<br />
| 0020<br />
| [[#GPUREG_0020|GPUREG_0020]]<br />
| <br />
|<br />
|-<br />
| 0021<br />
| [[#GPUREG_0021|GPUREG_0021]]<br />
| <br />
|<br />
|-<br />
| 0022<br />
| [[#GPUREG_0022|GPUREG_0022]]<br />
| <br />
|<br />
|-<br />
| 0023<br />
| [[#GPUREG_0023|GPUREG_0023]]<br />
| <br />
|<br />
|-<br />
| 0024<br />
| [[#GPUREG_0024|GPUREG_0024]]<br />
| <br />
|<br />
|-<br />
| 0025<br />
| [[#GPUREG_0025|GPUREG_0025]]<br />
| <br />
|<br />
|-<br />
| 0026<br />
| [[#GPUREG_0026|GPUREG_0026]]<br />
| <br />
|<br />
|-<br />
| 0027<br />
| [[#GPUREG_0027|GPUREG_0027]]<br />
| <br />
|<br />
|-<br />
| 0028<br />
| [[#GPUREG_0028|GPUREG_0028]]<br />
| <br />
|<br />
|-<br />
| 0029<br />
| [[#GPUREG_0029|GPUREG_0029]]<br />
| <br />
|<br />
|-<br />
| 002A<br />
| [[#GPUREG_002A|GPUREG_002A]]<br />
| <br />
|<br />
|-<br />
| 002B<br />
| [[#GPUREG_002B|GPUREG_002B]]<br />
| <br />
|<br />
|-<br />
| 002C<br />
| [[#GPUREG_002C|GPUREG_002C]]<br />
| <br />
|<br />
|-<br />
| 002D<br />
| [[#GPUREG_002D|GPUREG_002D]]<br />
| <br />
|<br />
|-<br />
| 002E<br />
| [[#GPUREG_002E|GPUREG_002E]]<br />
| <br />
|<br />
|-<br />
| 002F<br />
| [[#GPUREG_002F|GPUREG_002F]]<br />
| <br />
|<br />
|-<br />
| 0030<br />
| [[#GPUREG_0030|GPUREG_0030]]<br />
| <br />
|<br />
|-<br />
| 0031<br />
| [[#GPUREG_0031|GPUREG_0031]]<br />
| <br />
|<br />
|-<br />
| 0032<br />
| [[#GPUREG_0032|GPUREG_0032]]<br />
| <br />
|<br />
|-<br />
| 0033<br />
| [[#GPUREG_0033|GPUREG_0033]]<br />
| <br />
|<br />
|-<br />
| 0034<br />
| [[#GPUREG_0034|GPUREG_0034]]<br />
| <br />
|<br />
|-<br />
| 0035<br />
| [[#GPUREG_0035|GPUREG_0035]]<br />
| <br />
|<br />
|-<br />
| 0036<br />
| [[#GPUREG_0036|GPUREG_0036]]<br />
| <br />
|<br />
|-<br />
| 0037<br />
| [[#GPUREG_0037|GPUREG_0037]]<br />
| <br />
|<br />
|-<br />
| 0038<br />
| [[#GPUREG_0038|GPUREG_0038]]<br />
| <br />
|<br />
|-<br />
| 0039<br />
| [[#GPUREG_0039|GPUREG_0039]]<br />
| <br />
|<br />
|-<br />
| 003A<br />
| [[#GPUREG_003A|GPUREG_003A]]<br />
| <br />
|<br />
|-<br />
| 003B<br />
| [[#GPUREG_003B|GPUREG_003B]]<br />
| <br />
|<br />
|-<br />
| 003C<br />
| [[#GPUREG_003C|GPUREG_003C]]<br />
| <br />
|<br />
|-<br />
| 003D<br />
| [[#GPUREG_003D|GPUREG_003D]]<br />
| <br />
|<br />
|-<br />
| 003E<br />
| [[#GPUREG_003E|GPUREG_003E]]<br />
| <br />
|<br />
|-<br />
| 003F<br />
| [[#GPUREG_003F|GPUREG_003F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Rasterizer registers (0x040-0x07F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0040<br />
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]<br />
| <br />
|PICA_REG_CULL_FACE<br />
|-<br />
| 0041<br />
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH1<br />
|-<br />
| 0042<br />
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH2<br />
|-<br />
| 0043<br />
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT1<br />
|-<br />
| 0044<br />
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT2<br />
|-<br />
| 0045<br />
| [[#GPUREG_0045|GPUREG_0045]]<br />
| <br />
|<br />
|-<br />
| 0046<br />
| [[#GPUREG_0046|GPUREG_0046]]<br />
| <br />
|<br />
|-<br />
| 0047<br />
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP<br />
|-<br />
| 0048<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]<br />
|? <br />
|PICA_REG_FRAGOP_CLIP_DATA1<br />
|-<br />
| 0049<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA2<br />
|-<br />
| 004A<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA3<br />
|-<br />
| 004B<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA4<br />
|-<br />
| 004C<br />
| [[#GPUREG_004C|GPUREG_004C]]<br />
| <br />
|<br />
|-<br />
| 004D<br />
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA1<br />
|-<br />
| 004E<br />
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA2<br />
|-<br />
| 004F<br />
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]<br />
| <br />
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0<br />
|-<br />
| 0050<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0<br />
|-<br />
| 0051<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1<br />
|-<br />
| 0052<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2<br />
|-<br />
| 0053<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3<br />
|-<br />
| 0054<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4<br />
|-<br />
| 0055<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5<br />
|-<br />
| 0056<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6<br />
|-<br />
| 0057<br />
| [[#GPUREG_0057|GPUREG_0057]]<br />
| <br />
|<br />
|-<br />
| 0058<br />
| [[#GPUREG_0058|GPUREG_0058]]<br />
| <br />
|<br />
|-<br />
| 0059<br />
| [[#GPUREG_0059|GPUREG_0059]]<br />
| <br />
|<br />
|-<br />
| 005A<br />
| [[#GPUREG_005A|GPUREG_005A]]<br />
| <br />
|<br />
|-<br />
| 005B<br />
| [[#GPUREG_005B|GPUREG_005B]]<br />
| <br />
|<br />
|-<br />
| 005C<br />
| [[#GPUREG_005C|GPUREG_005C]]<br />
| <br />
|<br />
|-<br />
| 005D<br />
| [[#GPUREG_005D|GPUREG_005D]]<br />
| <br />
|<br />
|-<br />
| 005E<br />
| [[#GPUREG_005E|GPUREG_005E]]<br />
| <br />
|<br />
|-<br />
| 005F<br />
| [[#GPUREG_005F|GPUREG_005F]]<br />
| <br />
|<br />
|-<br />
| 0060<br />
| [[#GPUREG_0060|GPUREG_0060]]<br />
| <br />
|<br />
|-<br />
| 0061<br />
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_FUNC<br />
|-<br />
| 0062<br />
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST1<br />
|-<br />
| 0063<br />
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]<br />
| <br />
|PICA_REG_EARLY_DEPTH_CLEAR<br />
|-<br />
| 0064<br />
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE<br />
|-<br />
| 0065<br />
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]<br />
| <br />
|PICA_REG_SCISSOR<br />
|-<br />
| 0066<br />
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]<br />
| <br />
|PICA_REG_SCISSOR_XY<br />
|-<br />
| 0067<br />
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]<br />
| <br />
|PICA_REG_SCISSOR_SIZE<br />
|-<br />
| 0068<br />
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]<br />
|<br />
|PICA_REG_VIEWPORT_XY<br />
|-<br />
| 0069<br />
| [[#GPUREG_0069|GPUREG_0069]]<br />
| <br />
|<br />
|-<br />
| 006A<br />
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]<br />
|<br />
|PICA_REG_EARLY_DEPTH_DATA<br />
|-<br />
| 006B<br />
| [[#GPUREG_006B|GPUREG_006B]]<br />
| <br />
|<br />
|-<br />
| 006C<br />
| [[#GPUREG_006C|GPUREG_006C]]<br />
| <br />
|<br />
|-<br />
| 006D<br />
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]<br />
|?<br />
|PICA_REG_FRAGOP_WSCALE<br />
|-<br />
| 006E<br />
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]<br />
|?<br />
|PICA_REG_RENDER_BUF_RESOLUTION1<br />
|-<br />
| 006F<br />
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK<br />
|-<br />
| 0070<br />
| [[#GPUREG_0070|GPUREG_0070]]<br />
| <br />
|<br />
|-<br />
| 0071<br />
| [[#GPUREG_0071|GPUREG_0071]]<br />
| <br />
|<br />
|-<br />
| 0072<br />
| [[#GPUREG_0072|GPUREG_0072]]<br />
| <br />
|<br />
|-<br />
| 0073<br />
| [[#GPUREG_0073|GPUREG_0073]]<br />
| <br />
|<br />
|-<br />
| 0074<br />
| [[#GPUREG_0074|GPUREG_0074]]<br />
| <br />
|<br />
|-<br />
| 0075<br />
| [[#GPUREG_0075|GPUREG_0075]]<br />
| <br />
|<br />
|-<br />
| 0076<br />
| [[#GPUREG_0076|GPUREG_0076]]<br />
| <br />
|<br />
|-<br />
| 0077<br />
| [[#GPUREG_0077|GPUREG_0077]]<br />
| <br />
|<br />
|-<br />
| 0078<br />
| [[#GPUREG_0078|GPUREG_0078]]<br />
| <br />
|<br />
|-<br />
| 0079<br />
| [[#GPUREG_0079|GPUREG_0079]]<br />
| <br />
|<br />
|-<br />
| 007A<br />
| [[#GPUREG_007A|GPUREG_007A]]<br />
| <br />
|<br />
|-<br />
| 007B<br />
| [[#GPUREG_007B|GPUREG_007B]]<br />
| <br />
|<br />
|-<br />
| 007C<br />
| [[#GPUREG_007C|GPUREG_007C]]<br />
| <br />
|<br />
|-<br />
| 007D<br />
| [[#GPUREG_007D|GPUREG_007D]]<br />
| <br />
|<br />
|-<br />
| 007E<br />
| [[#GPUREG_007E|GPUREG_007E]]<br />
| <br />
|<br />
|-<br />
| 007F<br />
| [[#GPUREG_007F|GPUREG_007F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Texturing registers (0x080-0x0FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0080<br />
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]<br />
|<br />
|PICA_REG_TEXTURE_FUNC<br />
|-<br />
| 0081<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE0_BORDER_COLOR<br />
|-<br />
| 0082<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]<br />
|<br />
|PICA_REG_TEXTURE0_SIZE<br />
|-<br />
| 0083<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE0_WRAP_FILTER<br />
|-<br />
| 0084<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE0_LOD<br />
|-<br />
| 0085<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR1<br />
|-<br />
| 0086<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR2<br />
|-<br />
| 0087<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR3<br />
|-<br />
| 0088<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR4<br />
|-<br />
| 0089<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR5<br />
|-<br />
| 008A<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR6<br />
|-<br />
| 008B<br />
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]<br />
|?<br />
|PICA_REG_TEXTURE0_SHADOW<br />
|-<br />
| 008C<br />
| [[#GPUREG_008C|GPUREG_008C]]<br />
|<br />
|<br />
|-<br />
| 008D<br />
| [[#GPUREG_008D|GPUREG_008D]]<br />
|<br />
|<br />
|-<br />
| 008E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]<br />
|?<br />
|PICA_REG_TEXTURE0_FORMAT<br />
|-<br />
| 008F<br />
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN0<br />
|-<br />
| 0090<br />
| [[#GPUREG_0090|GPUREG_0090]]<br />
| <br />
|<br />
|-<br />
| 0091<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE1_BORDER_COLOR<br />
|-<br />
| 0092<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]<br />
| <br />
|PICA_REG_TEXTURE1_SIZE<br />
|-<br />
| 0093<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE1_WRAP_FILTER<br />
|-<br />
| 0094<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE1_LOD<br />
|-<br />
| 0095<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]<br />
| <br />
|PICA_REG_TEXTURE1_ADDR<br />
|-<br />
| 0096<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE1_FORMAT<br />
|-<br />
| 0097<br />
| [[#GPUREG_0097|GPUREG_0097]]<br />
| <br />
|<br />
|-<br />
| 0098<br />
| [[#GPUREG_0098|GPUREG_0098]]<br />
| <br />
|<br />
|-<br />
| 0099<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE2_BORDER_COLOR<br />
|-<br />
| 009A<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]<br />
| <br />
|PICA_REG_TEXTURE2_SIZE<br />
|-<br />
| 009B<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE2_WRAP_FILTER<br />
|-<br />
| 009C<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE2_LOD<br />
|-<br />
| 009D<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]<br />
|<br />
|PICA_REG_TEXTURE2_ADDR<br />
|-<br />
| 009E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE2_FORMAT<br />
|-<br />
| 009F<br />
| [[#GPUREG_009F|GPUREG_009F]]<br />
| <br />
|<br />
|-<br />
| 00A0<br />
| [[#GPUREG_00A0|GPUREG_00A0]]<br />
| <br />
|<br />
|-<br />
| 00A1<br />
| [[#GPUREG_00A1|GPUREG_00A1]]<br />
| <br />
|<br />
|-<br />
| 00A2<br />
| [[#GPUREG_00A2|GPUREG_00A2]]<br />
| <br />
|<br />
|-<br />
| 00A3<br />
| [[#GPUREG_00A3|GPUREG_00A3]]<br />
| <br />
|<br />
|-<br />
| 00A4<br />
| [[#GPUREG_00A4|GPUREG_00A4]]<br />
| <br />
|<br />
|-<br />
| 00A5<br />
| [[#GPUREG_00A5|GPUREG_00A5]]<br />
| <br />
|<br />
|-<br />
| 00A6<br />
| [[#GPUREG_00A6|GPUREG_00A6]]<br />
| <br />
|<br />
|-<br />
| 00A7<br />
| [[#GPUREG_00A7|GPUREG_00A7]]<br />
| <br />
|<br />
|-<br />
| 00A8<br />
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX0<br />
|-<br />
| 00A9<br />
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX1<br />
|-<br />
| 00AA<br />
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]<br />
|? <br />
|PICA_REG_TEXTURE3_PROCTEX2<br />
|-<br />
| 00AB<br />
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX3<br />
|-<br />
| 00AC<br />
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX4<br />
|-<br />
| 00AD<br />
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX5<br />
|-<br />
| 00AE<br />
| [[#GPUREG_00AE|GPUREG_00AE]]<br />
| <br />
|<br />
|-<br />
| 00AF<br />
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]<br />
|?<br />
|PICA_REG_PROCTEX_LUT<br />
|-<br />
| 00B0<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA0<br />
|-<br />
| 00B1<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA1<br />
|-<br />
| 00B2<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA2<br />
|-<br />
| 00B3<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA3<br />
|-<br />
| 00B4<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA4<br />
|-<br />
| 00B5<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA5<br />
|-<br />
| 00B6<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA6<br />
|-<br />
| 00B7<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA7<br />
|-<br />
| 00B8<br />
| [[#GPUREG_00B8|GPUREG_00B8]]<br />
| <br />
|<br />
|-<br />
| 00B9<br />
| [[#GPUREG_00B9|GPUREG_00B9]]<br />
| <br />
|<br />
|-<br />
| 00BA<br />
| [[#GPUREG_00BA|GPUREG_00BA]]<br />
| <br />
|<br />
|-<br />
| 00BB<br />
| [[#GPUREG_00BB|GPUREG_00BB]]<br />
| <br />
|<br />
|-<br />
| 00BC<br />
| [[#GPUREG_00BC|GPUREG_00BC]]<br />
| <br />
|<br />
|-<br />
| 00BD<br />
| [[#GPUREG_00BD|GPUREG_00BD]]<br />
| <br />
|<br />
|-<br />
| 00BE<br />
| [[#GPUREG_00BE|GPUREG_00BE]]<br />
| <br />
|<br />
|-<br />
| 00BF<br />
| [[#GPUREG_00BF|GPUREG_00BF]]<br />
| <br />
|<br />
|-<br />
| 00C0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_0<br />
|-<br />
| 00C1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_0_OPERAND<br />
|-<br />
| 00C2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COMBINE<br />
|-<br />
| 00C3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COLOR<br />
|-<br />
| 00C4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_0_SCALE<br />
|-<br />
| 00C5<br />
| [[#GPUREG_00C5|GPUREG_00C5]]<br />
| <br />
|<br />
|-<br />
| 00C6<br />
| [[#GPUREG_00C6|GPUREG_00C6]]<br />
| <br />
|<br />
|-<br />
| 00C7<br />
| [[#GPUREG_00C7|GPUREG_00C7]]<br />
| <br />
|<br />
|-<br />
| 00C8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_1<br />
|-<br />
| 00C9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_1_OPERAND<br />
|-<br />
| 00CA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COMBINE<br />
|-<br />
| 00CB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COLOR<br />
|-<br />
| 00CC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_1_SCALE<br />
|-<br />
| 00CD<br />
| [[#GPUREG_00CD|GPUREG_00CD]]<br />
| <br />
|<br />
|-<br />
| 00CE<br />
| [[#GPUREG_00CE|GPUREG_00CE]]<br />
| <br />
|<br />
|-<br />
| 00CF<br />
| [[#GPUREG_00CF|GPUREG_00CF]]<br />
| <br />
|<br />
|-<br />
| 00D0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_2<br />
|-<br />
| 00D1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_2_OPERAND<br />
|-<br />
| 00D2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COMBINE<br />
|-<br />
| 00D3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COLOR<br />
|-<br />
| 00D4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_2_SCALE<br />
|-<br />
| 00D5<br />
| [[#GPUREG_00D5|GPUREG_00D5]]<br />
| <br />
|<br />
|-<br />
| 00D6<br />
| [[#GPUREG_00D6|GPUREG_00D6]]<br />
| <br />
|<br />
|-<br />
| 00D7<br />
| [[#GPUREG_00D7|GPUREG_00D7]]<br />
| <br />
|<br />
|-<br />
| 00D8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_3<br />
|-<br />
| 00D9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_3_OPERAND<br />
|-<br />
| 00DA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COMBINE<br />
|-<br />
| 00DB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COLOR<br />
|-<br />
| 00DC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_3_SCALE<br />
|-<br />
| 00DD<br />
| [[#GPUREG_00DD|GPUREG_00DD]]<br />
| <br />
|<br />
|-<br />
| 00DE<br />
| [[#GPUREG_00DE|GPUREG_00DE]]<br />
| <br />
|<br />
|-<br />
| 00DF<br />
| [[#GPUREG_00DF|GPUREG_00DF]]<br />
| <br />
|<br />
|-<br />
| 00E0<br />
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]<br />
|?<br />
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT<br />
|-<br />
| 00E1<br />
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]<br />
|?<br />
|PICA_REG_FOG_COLOR<br />
|-<br />
| 00E2<br />
| [[#GPUREG_00E2|GPUREG_00E2]]<br />
| <br />
|<br />
|-<br />
| 00E3<br />
| [[#GPUREG_00E3|GPUREG_00E3]]<br />
| <br />
|<br />
|-<br />
| 00E4<br />
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]<br />
|?<br />
|PICA_REG_GAS_ATTENUATION<br />
|-<br />
| 00E5<br />
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]<br />
|?<br />
|PICA_REG_GAS_ACCMAX<br />
|-<br />
| 00E6<br />
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FOG_LUT_INDEX<br />
|-<br />
| 00E7<br />
| [[#GPUREG_00E7|GPUREG_00E7]]<br />
| <br />
|<br />
|-<br />
| 00E8<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA0<br />
|-<br />
| 00E9<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]<br />
|? <br />
|PICA_REG_FOG_LUT_DATA1<br />
|-<br />
| 00EA<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA2<br />
|-<br />
| 00EB<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA3<br />
|-<br />
| 00EC<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA4<br />
|-<br />
| 00ED<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA5<br />
|-<br />
| 00EE<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA6<br />
|-<br />
| 00EF<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA7<br />
|-<br />
| 00F0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_4<br />
|-<br />
| 00F1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_4_OPERAND<br />
|-<br />
| 00F2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COMBINE<br />
|-<br />
| 00F3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COLOR<br />
|-<br />
| 00F4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_4_SCALE<br />
|-<br />
| 00F5<br />
| [[#GPUREG_00F5|GPUREG_00F5]]<br />
| <br />
|<br />
|-<br />
| 00F6<br />
| [[#GPUREG_00F6|GPUREG_00F6]]<br />
| <br />
|<br />
|-<br />
| 00F7<br />
| [[#GPUREG_00F7|GPUREG_00F7]]<br />
| <br />
|<br />
|-<br />
| 00F8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_5<br />
|-<br />
| 00F9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_5_OPERAND<br />
|-<br />
| 00FA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COMBINE<br />
|-<br />
| 00FB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COLOR<br />
|-<br />
| 00FC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_5_SCALE<br />
|-<br />
| 00FD<br />
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]<br />
|?<br />
|PICA_REG_TEX_ENV_BUF_COLOR<br />
|-<br />
| 00FE<br />
| [[#GPUREG_00FE|GPUREG_00FE]]<br />
| <br />
|<br />
|-<br />
| 00FF<br />
| [[#GPUREG_00FF|GPUREG_00FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Framebuffer registers (0x100-0x13F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0100<br />
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]<br />
|<br />
|PICA_REG_COLOR_OPERATION<br />
|-<br />
| 0101<br />
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]<br />
| <br />
|PICA_REG_BLEND_FUNC<br />
|-<br />
| 0102<br />
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]<br />
| <br />
|PICA_REG_LOGIC_OP<br />
|-<br />
| 0103<br />
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]<br />
| <br />
|PICA_REG_BLEND_COLOR<br />
|-<br />
| 0104<br />
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]<br />
| <br />
|PICA_REG_FRAGOP_ALPHA_TEST<br />
|-<br />
| 0105<br />
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]<br />
| <br />
|PICA_REG_STENCIL_TEST<br />
|-<br />
| 0106<br />
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]<br />
| <br />
|PICA_REG_STENCIL_OP<br />
|-<br />
| 0107<br />
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]<br />
| <br />
|PICA_REG_DEPTH_COLOR_MASK<br />
|-<br />
| 0108<br />
| [[#GPUREG_0108|GPUREG_0108]]<br />
| <br />
|<br />
|-<br />
| 0109<br />
| [[#GPUREG_0109|GPUREG_0109]]<br />
| <br />
|<br />
|-<br />
| 010A<br />
| [[#GPUREG_010A|GPUREG_010A]]<br />
| <br />
|<br />
|-<br />
| 010B<br />
| [[#GPUREG_010B|GPUREG_010B]]<br />
| <br />
|<br />
|-<br />
| 010C<br />
| [[#GPUREG_010C|GPUREG_010C]]<br />
| <br />
|<br />
|-<br />
| 010D<br />
| [[#GPUREG_010D|GPUREG_010D]]<br />
| <br />
|<br />
|-<br />
| 010E<br />
| [[#GPUREG_010E|GPUREG_010E]]<br />
| <br />
|<br />
|-<br />
| 010F<br />
| [[#GPUREG_010F|GPUREG_010F]]<br />
| <br />
|<br />
|-<br />
| 0110<br />
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR0<br />
|-<br />
| 0111<br />
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR1<br />
|-<br />
| 0112<br />
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_READ<br />
|-<br />
| 0113<br />
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_WRITE<br />
|-<br />
| 0114<br />
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_READ<br />
|-<br />
| 0115<br />
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_WRITE<br />
|-<br />
| 0116<br />
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_DEPTH_MODE<br />
|-<br />
| 0117<br />
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_MODE<br />
|-<br />
| 0118<br />
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST2<br />
|-<br />
| 0119<br />
| [[#GPUREG_0119|GPUREG_0119]]<br />
| <br />
|<br />
|-<br />
| 011A<br />
| [[#GPUREG_011A|GPUREG_011A]]<br />
| <br />
|<br />
|-<br />
| 011B<br />
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]<br />
|<br />
|PICA_REG_RENDER_BLOCK_FORMAT<br />
|-<br />
| 011C<br />
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]<br />
|<br />
|PICA_REG_RENDER_BUF_DEPTH_ADDR<br />
|-<br />
| 011D<br />
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_ADDR<br />
|-<br />
| 011E<br />
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]<br />
| <br />
|PICA_REG_RENDER_BUF_RESOLUTION0<br />
|-<br />
| 011F<br />
| [[#GPUREG_011F|GPUREG_011F]]<br />
| <br />
|<br />
|-<br />
| 0120<br />
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_XY<br />
|-<br />
| 0121<br />
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z<br />
|-<br />
| 0122<br />
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z_COLOR<br />
|-<br />
| 0123<br />
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]<br />
|?<br />
|PICA_REG_GAS_LUT_INDEX<br />
|-<br />
| 0124<br />
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]<br />
|?<br />
|PICA_REG_GAS_LUT_DATA<br />
|-<br />
| 0125<br />
| [[#GPUREG_0125|GPUREG_0125]]<br />
| <br />
|<br />
|-<br />
| 0126<br />
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]<br />
|?<br />
|PICA_REG_GAS_DELTAZ_DEPTH<br />
|-<br />
| 0127<br />
| [[#GPUREG_0127|GPUREG_0127]]<br />
| <br />
|<br />
|-<br />
| 0128<br />
| [[#GPUREG_0128|GPUREG_0128]]<br />
| <br />
|<br />
|-<br />
| 0129<br />
| [[#GPUREG_0129|GPUREG_0129]]<br />
| <br />
|<br />
|-<br />
| 012A<br />
| [[#GPUREG_012A|GPUREG_012A]]<br />
| <br />
|<br />
|-<br />
| 012B<br />
| [[#GPUREG_012B|GPUREG_012B]]<br />
| <br />
|<br />
|-<br />
| 012C<br />
| [[#GPUREG_012C|GPUREG_012C]]<br />
| <br />
|<br />
|-<br />
| 012D<br />
| [[#GPUREG_012D|GPUREG_012D]]<br />
| <br />
|<br />
|-<br />
| 012E<br />
| [[#GPUREG_012E|GPUREG_012E]]<br />
| <br />
|<br />
|-<br />
| 012F<br />
| [[#GPUREG_012F|GPUREG_012F]]<br />
| <br />
|<br />
|-<br />
| 0130<br />
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]<br />
|?<br />
|PICA_REG_FRAGOP_SHADOW<br />
|-<br />
| 0131<br />
| [[#GPUREG_0131|GPUREG_0131]]<br />
| <br />
|<br />
|-<br />
| 0132<br />
| [[#GPUREG_0132|GPUREG_0132]]<br />
| <br />
|<br />
|-<br />
| 0133<br />
| [[#GPUREG_0133|GPUREG_0133]]<br />
| <br />
|<br />
|-<br />
| 0134<br />
| [[#GPUREG_0134|GPUREG_0134]]<br />
| <br />
|<br />
|-<br />
| 0135<br />
| [[#GPUREG_0135|GPUREG_0135]]<br />
| <br />
|<br />
|-<br />
| 0136<br />
| [[#GPUREG_0136|GPUREG_0136]]<br />
| <br />
|<br />
|-<br />
| 0137<br />
| [[#GPUREG_0137|GPUREG_0137]]<br />
| <br />
|<br />
|-<br />
| 0138<br />
| [[#GPUREG_0138|GPUREG_0138]]<br />
| <br />
|<br />
|-<br />
| 0139<br />
| [[#GPUREG_0139|GPUREG_0139]]<br />
| <br />
|<br />
|-<br />
| 013A<br />
| [[#GPUREG_013A|GPUREG_013A]]<br />
| <br />
|<br />
|-<br />
| 013B<br />
| [[#GPUREG_013B|GPUREG_013B]]<br />
| <br />
|<br />
|-<br />
| 013C<br />
| [[#GPUREG_013C|GPUREG_013C]]<br />
| <br />
|<br />
|-<br />
| 013D<br />
| [[#GPUREG_013D|GPUREG_013D]]<br />
| <br />
|<br />
|-<br />
| 013E<br />
| [[#GPUREG_013E|GPUREG_013E]]<br />
| <br />
|<br />
|-<br />
| 013F<br />
| [[#GPUREG_013F|GPUREG_013F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Fragment lighting registers (0x140-0x1FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0140<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START<br />
|-<br />
| 0141<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR1<br />
|-<br />
| 0142<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIFFUSE<br />
|-<br />
| 0143<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_AMBIENT<br />
|-<br />
| 0144<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_XY<br />
|-<br />
| 0145<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_Z<br />
|-<br />
| 0146<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_XY<br />
|-<br />
| 0147<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_Z<br />
|-<br />
| 0148<br />
| [[#GPUREG_0148|GPUREG_0148]]<br />
| <br />
|<br />
|-<br />
| 0149<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]<br />
| <br />
|PICA_REG_FRAG_LIGHT0_TYPE<br />
|-<br />
| 014A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS<br />
|-<br />
| 014B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE<br />
|-<br />
| 014C<br />
| [[#GPUREG_014C|GPUREG_014C]]<br />
| <br />
|<br />
|-<br />
| 014D<br />
| [[#GPUREG_014D|GPUREG_014D]]<br />
| <br />
|<br />
|-<br />
| 014E<br />
| [[#GPUREG_014E|GPUREG_014E]]<br />
| <br />
|<br />
|-<br />
| 014F<br />
| [[#GPUREG_014F|GPUREG_014F]]<br />
| <br />
|<br />
|-<br />
| 0150<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR0<br />
|-<br />
| 0151<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR1<br />
|-<br />
| 0152<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIFFUSE<br />
|-<br />
| 0153<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_AMBIENT<br />
|-<br />
| 0154<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_XY<br />
|-<br />
| 0155<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_Z<br />
|-<br />
| 0156<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_XY<br />
|-<br />
| 0157<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_Z<br />
|-<br />
| 0158<br />
| [[#GPUREG_0158|GPUREG_0158]]<br />
| <br />
|<br />
|-<br />
| 0159<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_TYPE<br />
|-<br />
| 015A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS<br />
|-<br />
| 015B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE<br />
|-<br />
| 015C<br />
| [[#GPUREG_015C|GPUREG_015C]]<br />
| <br />
|<br />
|-<br />
| 015D<br />
| [[#GPUREG_015D|GPUREG_015D]]<br />
| <br />
|<br />
|-<br />
| 015E<br />
| [[#GPUREG_015E|GPUREG_015E]]<br />
| <br />
|<br />
|-<br />
| 015F<br />
| [[#GPUREG_015F|GPUREG_015F]]<br />
| <br />
|<br />
|-<br />
| 0160<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR0<br />
|-<br />
| 0161<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR1<br />
|-<br />
| 0162<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIFFUSE<br />
|-<br />
| 0163<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_AMBIENT<br />
|-<br />
| 0164<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_XY<br />
|-<br />
| 0165<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_Z<br />
|-<br />
| 0166<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_XY<br />
|-<br />
| 0167<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_Z<br />
|-<br />
| 0168<br />
| [[#GPUREG_0168|GPUREG_0168]]<br />
| <br />
|<br />
|-<br />
| 0169<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_TYPE<br />
|-<br />
| 016A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS<br />
|-<br />
| 016B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE<br />
|-<br />
| 016C<br />
| [[#GPUREG_016C|GPUREG_016C]]<br />
| <br />
|<br />
|-<br />
| 016D<br />
| [[#GPUREG_016D|GPUREG_016D]]<br />
| <br />
|<br />
|-<br />
| 016E<br />
| [[#GPUREG_016E|GPUREG_016E]]<br />
| <br />
|<br />
|-<br />
| 016F<br />
| [[#GPUREG_016F|GPUREG_016F]]<br />
| <br />
|<br />
|-<br />
| 0170<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR0<br />
|-<br />
| 0171<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR1<br />
|-<br />
| 0172<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIFFUSE<br />
|-<br />
| 0173<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_AMBIENT<br />
|-<br />
| 0174<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_XY<br />
|-<br />
| 0175<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_Z<br />
|-<br />
| 0176<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]<br />
|? <br />
|PICA_REG_FRAG_LIGHT3_SPOT_XY<br />
|-<br />
| 0177<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPOT_Z<br />
|-<br />
| 0178<br />
| [[#GPUREG_0178|GPUREG_0178]]<br />
| <br />
|<br />
|-<br />
| 0179<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_TYPE<br />
|-<br />
| 017A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS<br />
|-<br />
| 017B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE<br />
|-<br />
| 017C<br />
| [[#GPUREG_017C|GPUREG_017C]]<br />
| <br />
|<br />
|-<br />
| 017D<br />
| [[#GPUREG_017D|GPUREG_017D]]<br />
| <br />
|<br />
|-<br />
| 017E<br />
| [[#GPUREG_017E|GPUREG_017E]]<br />
| <br />
|<br />
|-<br />
| 017F<br />
| [[#GPUREG_017F|GPUREG_017F]]<br />
| <br />
|<br />
|-<br />
| 0180<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR0<br />
|-<br />
| 0181<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR1<br />
|-<br />
| 0182<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIFFUSE<br />
|-<br />
| 0183<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_AMBIENT<br />
|-<br />
| 0184<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_XY<br />
|-<br />
| 0185<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_Z<br />
|-<br />
| 0186<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_XY<br />
|-<br />
| 0187<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_Z<br />
|-<br />
| 0188<br />
| [[#GPUREG_0188|GPUREG_0188]]<br />
| <br />
|<br />
|-<br />
| 0189<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_TYPE<br />
|-<br />
| 018A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS<br />
|-<br />
| 018B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE<br />
|-<br />
| 018C<br />
| [[#GPUREG_018C|GPUREG_018C]]<br />
| <br />
|<br />
|-<br />
| 018D<br />
| [[#GPUREG_018D|GPUREG_018D]]<br />
| <br />
|<br />
|-<br />
| 018E<br />
| [[#GPUREG_018E|GPUREG_018E]]<br />
| <br />
|<br />
|-<br />
| 018F<br />
| [[#GPUREG_018F|GPUREG_018F]]<br />
| <br />
|<br />
|-<br />
| 0190<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR0<br />
|-<br />
| 0191<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR1<br />
|-<br />
| 0192<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_DIFFUSE<br />
|-<br />
| 0193<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_AMBIENT<br />
|-<br />
| 0194<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_XY<br />
|-<br />
| 0195<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_Z<br />
|-<br />
| 0196<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_XY<br />
|-<br />
| 0197<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_Z<br />
|-<br />
| 0198<br />
| [[#GPUREG_0198|GPUREG_0198]]<br />
| <br />
|<br />
|-<br />
| 0199<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_TYPE<br />
|-<br />
| 019A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS<br />
|-<br />
| 019B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE<br />
|-<br />
| 019C<br />
| [[#GPUREG_019C|GPUREG_019C]]<br />
| <br />
|<br />
|-<br />
| 019D<br />
| [[#GPUREG_019D|GPUREG_019D]]<br />
| <br />
|<br />
|-<br />
| 019E<br />
| [[#GPUREG_019E|GPUREG_019E]]<br />
| <br />
|<br />
|-<br />
| 019F<br />
| [[#GPUREG_019F|GPUREG_019F]]<br />
| <br />
|<br />
|-<br />
| 01A0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR0<br />
|-<br />
| 01A1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR1<br />
|-<br />
| 01A2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIFFUSE<br />
|-<br />
| 01A3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_AMBIENT<br />
|-<br />
| 01A4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_XY<br />
|-<br />
| 01A5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_Z<br />
|-<br />
| 01A6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_XY<br />
|-<br />
| 01A7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_Z<br />
|-<br />
| 01A8<br />
| [[#GPUREG_01A8|GPUREG_01A8]]<br />
| <br />
|<br />
|-<br />
| 01A9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_TYPE<br />
|-<br />
| 01AA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS<br />
|-<br />
| 01AB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE<br />
|-<br />
| 01AC<br />
| [[#GPUREG_01AC|GPUREG_01AC]]<br />
| <br />
|<br />
|-<br />
| 01AD<br />
| [[#GPUREG_01AD|GPUREG_01AD]]<br />
| <br />
|<br />
|-<br />
| 01AE<br />
| [[#GPUREG_01AE|GPUREG_01AE]]<br />
| <br />
|<br />
|-<br />
| 01AF<br />
| [[#GPUREG_01AF|GPUREG_01AF]]<br />
| <br />
|<br />
|-<br />
| 01B0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR0<br />
|-<br />
| 01B1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR1<br />
|-<br />
| 01B2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_DIFFUSE<br />
|-<br />
| 01B3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_AMBIENT<br />
|-<br />
| 01B4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_XY<br />
|-<br />
| 01B5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_Z<br />
|-<br />
| 01B6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_XY<br />
|-<br />
| 01B7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_Z<br />
|-<br />
| 01B8<br />
| [[#GPUREG_01B8|GPUREG_01B8]]<br />
| <br />
|<br />
|-<br />
| 01B9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_TYPE<br />
|-<br />
| 01BA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS<br />
|-<br />
| 01BB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE<br />
|-<br />
| 01BC<br />
| [[#GPUREG_01BC|GPUREG_01BC]]<br />
| <br />
|<br />
|-<br />
| 01BD<br />
| [[#GPUREG_01BD|GPUREG_01BD]]<br />
| <br />
|<br />
|-<br />
| 01BE<br />
| [[#GPUREG_01BE|GPUREG_01BE]]<br />
| <br />
|<br />
|-<br />
| 01BF<br />
| [[#GPUREG_01BF|GPUREG_01BF]]<br />
| <br />
|<br />
|-<br />
| 01C0<br />
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_AMBIENT<br />
|-<br />
| 01C1<br />
| [[#GPUREG_01C1|GPUREG_01C1]]<br />
| <br />
|<br />
|-<br />
| 01C2<br />
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_NUM<br />
|-<br />
| 01C3<br />
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE0<br />
|-<br />
| 01C4<br />
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE1<br />
|-<br />
| 01C5<br />
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT<br />
|-<br />
| 01C6<br />
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN1<br />
|-<br />
| 01C7<br />
| [[#GPUREG_01C7|GPUREG_01C7]]<br />
| <br />
|<br />
|-<br />
| 01C8<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA0<br />
|-<br />
| 01C9<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA1<br />
|-<br />
| 01CA<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA2<br />
|-<br />
| 01CB<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA3<br />
|-<br />
| 01CC<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA4<br />
|-<br />
| 01CD<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA5<br />
|-<br />
| 01CE<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA6<br />
|-<br />
| 01CF<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA7<br />
|-<br />
| 01D0<br />
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT<br />
|-<br />
| 01D1<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTINPUT<br />
|-<br />
| 01D2<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTSCALE<br />
|-<br />
| 01D3<br />
| [[#GPUREG_01D3|GPUREG_01D3]]<br />
| <br />
|<br />
|-<br />
| 01D4<br />
| [[#GPUREG_01D4|GPUREG_01D4]]<br />
| <br />
|<br />
|-<br />
| 01D5<br />
| [[#GPUREG_01D5|GPUREG_01D5]]<br />
| <br />
|<br />
|-<br />
| 01D6<br />
| [[#GPUREG_01D6|GPUREG_01D6]]<br />
| <br />
|<br />
|-<br />
| 01D7<br />
| [[#GPUREG_01D7|GPUREG_01D7]]<br />
| <br />
|<br />
|-<br />
| 01D8<br />
| [[#GPUREG_01D8|GPUREG_01D8]]<br />
| <br />
|<br />
|-<br />
| 01D9<br />
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_EN_ID<br />
|-<br />
| 01DA<br />
| [[#GPUREG_01DA|GPUREG_01DA]]<br />
| <br />
|<br />
|-<br />
| 01DB<br />
| [[#GPUREG_01DB|GPUREG_01DB]]<br />
| <br />
|<br />
|-<br />
| 01DC<br />
| [[#GPUREG_01DC|GPUREG_01DC]]<br />
| <br />
|<br />
|-<br />
| 01DD<br />
| [[#GPUREG_01DD|GPUREG_01DD]]<br />
| <br />
|<br />
|-<br />
| 01DE<br />
| [[#GPUREG_01DE|GPUREG_01DE]]<br />
| <br />
|<br />
|-<br />
| 01DF<br />
| [[#GPUREG_01DF|GPUREG_01DF]]<br />
| <br />
|<br />
|-<br />
| 01E0<br />
| [[#GPUREG_01E0|GPUREG_01E0]]<br />
| <br />
|<br />
|-<br />
| 01E1<br />
| [[#GPUREG_01E1|GPUREG_01E1]]<br />
| <br />
|<br />
|-<br />
| 01E2<br />
| [[#GPUREG_01E2|GPUREG_01E2]]<br />
| <br />
|<br />
|-<br />
| 01E3<br />
| [[#GPUREG_01E3|GPUREG_01E3]]<br />
| <br />
|<br />
|-<br />
| 01E4<br />
| [[#GPUREG_01E4|GPUREG_01E4]]<br />
| <br />
|<br />
|-<br />
| 01E5<br />
| [[#GPUREG_01E5|GPUREG_01E5]]<br />
| <br />
|<br />
|-<br />
| 01E6<br />
| [[#GPUREG_01E6|GPUREG_01E6]]<br />
| <br />
|<br />
|-<br />
| 01E7<br />
| [[#GPUREG_01E7|GPUREG_01E7]]<br />
| <br />
|<br />
|-<br />
| 01E8<br />
| [[#GPUREG_01E8|GPUREG_01E8]]<br />
| <br />
|<br />
|-<br />
| 01E9<br />
| [[#GPUREG_01E9|GPUREG_01E9]]<br />
| <br />
|<br />
|-<br />
| 01EA<br />
| [[#GPUREG_01EA|GPUREG_01EA]]<br />
| <br />
|<br />
|-<br />
| 01EB<br />
| [[#GPUREG_01EB|GPUREG_01EB]]<br />
| <br />
|<br />
|-<br />
| 01EC<br />
| [[#GPUREG_01EC|GPUREG_01EC]]<br />
| <br />
|<br />
|-<br />
| 01ED<br />
| [[#GPUREG_01ED|GPUREG_01ED]]<br />
| <br />
|<br />
|-<br />
| 01EE<br />
| [[#GPUREG_01EE|GPUREG_01EE]]<br />
| <br />
|<br />
|-<br />
| 01EF<br />
| [[#GPUREG_01EF|GPUREG_01EF]]<br />
| <br />
|<br />
|-<br />
| 01F0<br />
| [[#GPUREG_01F0|GPUREG_01F0]]<br />
| <br />
|<br />
|-<br />
| 01F1<br />
| [[#GPUREG_01F1|GPUREG_01F1]]<br />
| <br />
|<br />
|-<br />
| 01F2<br />
| [[#GPUREG_01F2|GPUREG_01F2]]<br />
| <br />
|<br />
|-<br />
| 01F3<br />
| [[#GPUREG_01F3|GPUREG_01F3]]<br />
| <br />
|<br />
|-<br />
| 01F4<br />
| [[#GPUREG_01F4|GPUREG_01F4]]<br />
| <br />
|<br />
|-<br />
| 01F5<br />
| [[#GPUREG_01F5|GPUREG_01F5]]<br />
| <br />
|<br />
|-<br />
| 01F6<br />
| [[#GPUREG_01F6|GPUREG_01F6]]<br />
| <br />
|<br />
|-<br />
| 01F7<br />
| [[#GPUREG_01F7|GPUREG_01F7]]<br />
| <br />
|<br />
|-<br />
| 01F8<br />
| [[#GPUREG_01F8|GPUREG_01F8]]<br />
| <br />
|<br />
|-<br />
| 01F9<br />
| [[#GPUREG_01F9|GPUREG_01F9]]<br />
| <br />
|<br />
|-<br />
| 01FA<br />
| [[#GPUREG_01FA|GPUREG_01FA]]<br />
| <br />
|<br />
|-<br />
| 01FB<br />
| [[#GPUREG_01FB|GPUREG_01FB]]<br />
| <br />
|<br />
|-<br />
| 01FC<br />
| [[#GPUREG_01FC|GPUREG_01FC]]<br />
| <br />
|<br />
|-<br />
| 01FD<br />
| [[#GPUREG_01FD|GPUREG_01FD]]<br />
| <br />
|<br />
|-<br />
| 01FE<br />
| [[#GPUREG_01FE|GPUREG_01FE]]<br />
| <br />
|<br />
|-<br />
| 01FF<br />
| [[#GPUREG_01FF|GPUREG_01FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Geometry pipeline registers (0x200-0x27F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0200<br />
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR<br />
|-<br />
| 0201<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS0<br />
|-<br />
| 0202<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS1<br />
|-<br />
| 0203<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET<br />
|-<br />
| 0204<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT0<br />
|-<br />
| 0205<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT1<br />
|-<br />
| 0206<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0207<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0208<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0209<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020B<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020C<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020E<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020F<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0210<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0211<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0212<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0213<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0214<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0215<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0216<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0217<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0218<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0219<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021B<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021C<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021E<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021F<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0220<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0221<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0222<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0223<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0224<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0225<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0226<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0227<br />
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET<br />
|-<br />
| 0228<br />
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]<br />
| <br />
|PICA_REG_DRAW_VERTEX_NUM<br />
|-<br />
| 0229<br />
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]<br />
| ?<br />
|PICA_REG_DRAW_MODE0<br />
|-<br />
| 022A<br />
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]<br />
|<br />
|PICA_REG_DRAW_VERTEX_OFFSET<br />
|-<br />
| 022B<br />
| [[#GPUREG_022B|GPUREG_022B]]<br />
| <br />
|<br />
|-<br />
| 022C<br />
| [[#GPUREG_022C|GPUREG_022C]]<br />
| <br />
|<br />
|-<br />
| 022D<br />
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]<br />
| <br />
|PICA_REG_POST_VERTEX_CACHE_NUM<br />
|-<br />
| 022E<br />
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]<br />
|<br />
|PICA_REG_START_DRAW_ARRAY<br />
|-<br />
| 022F<br />
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]<br />
|<br />
|PICA_REG_START_DRAW_ELEMENT<br />
|-<br />
| 0230<br />
| [[#GPUREG_0230|GPUREG_0230]]<br />
| <br />
|<br />
|-<br />
| 0231<br />
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]<br />
|?<br />
|PICA_REG_VTX_FUNC<br />
|-<br />
| 0232<br />
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR<br />
|-<br />
| 0233<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA0<br />
|-<br />
| 0234<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA1<br />
|-<br />
| 0235<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA2<br />
|-<br />
| 0236<br />
| [[#GPUREG_0236|GPUREG_0236]]<br />
| <br />
|<br />
|-<br />
| 0237<br />
| [[#GPUREG_0237|GPUREG_0237]]<br />
| <br />
|<br />
|-<br />
| 0238<br />
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH0<br />
|-<br />
| 0239<br />
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH1<br />
|-<br />
| 023A<br />
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH0<br />
|-<br />
| 023B<br />
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH1<br />
|-<br />
| 023C<br />
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH0<br />
|-<br />
| 023D<br />
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH1<br />
|-<br />
| 023E<br />
| [[#GPUREG_023E|GPUREG_023E]]<br />
| <br />
|<br />
|-<br />
| 023F<br />
| [[#GPUREG_023F|GPUREG_023F]]<br />
| <br />
|<br />
|-<br />
| 0240<br />
| [[#GPUREG_0240|GPUREG_0240]]<br />
| <br />
|<br />
|-<br />
| 0241<br />
| [[#GPUREG_0241|GPUREG_0241]]<br />
| <br />
|<br />
|-<br />
| 0242<br />
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]<br />
|?<br />
|PICA_REG_VS_ATTR_NUM1<br />
|-<br />
| 0243<br />
| [[#GPUREG_0243|GPUREG_0243]]<br />
| <br />
|<br />
|-<br />
| 0244<br />
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]<br />
|?<br />
|PICA_REG_VS_COM_MODE<br />
|-<br />
| 0245<br />
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC0<br />
|-<br />
| 0246<br />
| [[#GPUREG_0246|GPUREG_0246]]<br />
| <br />
|<br />
|-<br />
| 0247<br />
| [[#GPUREG_0247|GPUREG_0247]]<br />
| <br />
|<br />
|-<br />
| 0248<br />
| [[#GPUREG_0248|GPUREG_0248]]<br />
| <br />
|<br />
|-<br />
| 0249<br />
| [[#GPUREG_0249|GPUREG_0249]]<br />
| <br />
|<br />
|-<br />
| 024A<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM1<br />
|-<br />
| 024B<br />
| [[#GPUREG_024B|GPUREG_024B]]<br />
|<br />
|<br />
|-<br />
| 024C<br />
| [[#GPUREG_024C|GPUREG_024C]]<br />
| <br />
|<br />
|-<br />
| 024D<br />
| [[#GPUREG_024D|GPUREG_024D]]<br />
| <br />
|<br />
|-<br />
| 024E<br />
| [[#GPUREG_024E|GPUREG_024E]]<br />
| <br />
|<br />
|-<br />
| 024F<br />
| [[#GPUREG_024F|GPUREG_024F]]<br />
| <br />
|<br />
|-<br />
| 0250<br />
| [[#GPUREG_0250|GPUREG_0250]]<br />
| <br />
|<br />
|-<br />
| 0251<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM2<br />
|-<br />
| 0252<br />
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]<br />
|?<br />
|PICA_REG_GS_MISC_REG0<br />
|-<br />
| 0253<br />
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]<br />
|?<br />
|PICA_REG_DRAW_MODE1<br />
|-<br />
| 0254<br />
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]<br />
|?<br />
|PICA_REG_GS_MISC_REG1<br />
|-<br />
| 0255<br />
| [[#GPUREG_0255|GPUREG_0255]]<br />
| <br />
|<br />
|-<br />
| 0256<br />
| [[#GPUREG_0256|GPUREG_0256]]<br />
| <br />
|<br />
|-<br />
| 0257<br />
| [[#GPUREG_0257|GPUREG_0257]]<br />
| <br />
|<br />
|-<br />
| 0258<br />
| [[#GPUREG_0258|GPUREG_0258]]<br />
| <br />
|<br />
|-<br />
| 0259<br />
| [[#GPUREG_0259|GPUREG_0259]]<br />
| <br />
|<br />
|-<br />
| 025A<br />
| [[#GPUREG_025A|GPUREG_025A]]<br />
| <br />
|<br />
|-<br />
| 025B<br />
| [[#GPUREG_025B|GPUREG_025B]]<br />
| <br />
|<br />
|-<br />
| 025C<br />
| [[#GPUREG_025C|GPUREG_025C]]<br />
| <br />
|<br />
|-<br />
| 025D<br />
| [[#GPUREG_025D|GPUREG_025D]]<br />
| <br />
|<br />
|-<br />
| 025E<br />
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]<br />
| ?<br />
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3<br />
|-<br />
| 025F<br />
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC1<br />
|-<br />
| 0260<br />
| [[#GPUREG_0260|GPUREG_0260]]<br />
| <br />
|<br />
|-<br />
| 0261<br />
| [[#GPUREG_0261|GPUREG_0261]]<br />
| <br />
|<br />
|-<br />
| 0262<br />
| [[#GPUREG_0262|GPUREG_0262]]<br />
| <br />
|<br />
|-<br />
| 0263<br />
| [[#GPUREG_0263|GPUREG_0263]]<br />
| <br />
|<br />
|-<br />
| 0264<br />
| [[#GPUREG_0264|GPUREG_0264]]<br />
| <br />
|<br />
|-<br />
| 0265<br />
| [[#GPUREG_0265|GPUREG_0265]]<br />
| <br />
|<br />
|-<br />
| 0266<br />
| [[#GPUREG_0266|GPUREG_0266]]<br />
| <br />
|<br />
|-<br />
| 0267<br />
| [[#GPUREG_0267|GPUREG_0267]]<br />
| <br />
|<br />
|-<br />
| 0268<br />
| [[#GPUREG_0268|GPUREG_0268]]<br />
| <br />
|<br />
|-<br />
| 0269<br />
| [[#GPUREG_0269|GPUREG_0269]]<br />
| <br />
|<br />
|-<br />
| 026A<br />
| [[#GPUREG_026A|GPUREG_026A]]<br />
| <br />
|<br />
|-<br />
| 026B<br />
| [[#GPUREG_026B|GPUREG_026B]]<br />
| <br />
|<br />
|-<br />
| 026C<br />
| [[#GPUREG_026C|GPUREG_026C]]<br />
| <br />
|<br />
|-<br />
| 026D<br />
| [[#GPUREG_026D|GPUREG_026D]]<br />
| <br />
|<br />
|-<br />
| 026E<br />
| [[#GPUREG_026E|GPUREG_026E]]<br />
| <br />
|<br />
|-<br />
| 026F<br />
| [[#GPUREG_026F|GPUREG_026F]]<br />
| <br />
|<br />
|-<br />
| 0270<br />
| [[#GPUREG_0270|GPUREG_0270]]<br />
| <br />
|<br />
|-<br />
| 0271<br />
| [[#GPUREG_0271|GPUREG_0271]]<br />
| <br />
|<br />
|-<br />
| 0272<br />
| [[#GPUREG_0272|GPUREG_0272]]<br />
| <br />
|<br />
|-<br />
| 0273<br />
| [[#GPUREG_0273|GPUREG_0273]]<br />
| <br />
|<br />
|-<br />
| 0274<br />
| [[#GPUREG_0274|GPUREG_0274]]<br />
| <br />
|<br />
|-<br />
| 0275<br />
| [[#GPUREG_0275|GPUREG_0275]]<br />
| <br />
|<br />
|-<br />
| 0276<br />
| [[#GPUREG_0276|GPUREG_0276]]<br />
| <br />
|<br />
|-<br />
| 0277<br />
| [[#GPUREG_0277|GPUREG_0277]]<br />
| <br />
|<br />
|-<br />
| 0278<br />
| [[#GPUREG_0278|GPUREG_0278]]<br />
| <br />
|<br />
|-<br />
| 0279<br />
| [[#GPUREG_0279|GPUREG_0279]]<br />
| <br />
|<br />
|-<br />
| 027A<br />
| [[#GPUREG_027A|GPUREG_027A]]<br />
| <br />
|<br />
|-<br />
| 027B<br />
| [[#GPUREG_027B|GPUREG_027B]]<br />
| <br />
|<br />
|-<br />
| 027C<br />
| [[#GPUREG_027C|GPUREG_027C]]<br />
| <br />
|<br />
|-<br />
| 027D<br />
| [[#GPUREG_027D|GPUREG_027D]]<br />
| <br />
|<br />
|-<br />
| 027E<br />
| [[#GPUREG_027E|GPUREG_027E]]<br />
| <br />
|<br />
|-<br />
| 027F<br />
| [[#GPUREG_027F|GPUREG_027F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Shader registers (0x280-0x2DF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
! colspan=4 | Geometry shader<br />
|-<br />
| 0280<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_GS_BOOL<br />
|-<br />
| 0281<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_GS_INT0<br />
|-<br />
| 0282<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_GS_INT1<br />
|-<br />
| 0283<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_GS_INT2<br />
|-<br />
| 0284<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_GS_INT3<br />
|-<br />
| 0285<br />
| [[#GPUREG_0285|GPUREG_0285]]<br />
| <br />
|<br />
|-<br />
| 0286<br />
| [[#GPUREG_0286|GPUREG_0286]]<br />
| <br />
|<br />
|-<br />
| 0287<br />
| [[#GPUREG_0287|GPUREG_0287]]<br />
| <br />
|<br />
|-<br />
| 0288<br />
| [[#GPUREG_0288|GPUREG_0288]]<br />
| <br />
|<br />
|-<br />
| 0289<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_GS_ATTR_NUM<br />
|-<br />
| 028A<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_GS_START_ADDR<br />
|-<br />
| 028B<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP0<br />
|-<br />
| 028C<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP1<br />
|-<br />
| 028D<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_GS_OUT_REG_MASK<br />
|-<br />
| 028E<br />
| [[#GPUREG_028E|GPUREG_028E]]<br />
| <br />
|<br />
|-<br />
| 028F<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_GS_PROG_RENEWAL_END<br />
|-<br />
| 0290<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_GS_FLOAT_ADDR<br />
|-<br />
| 0291<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA0<br />
|-<br />
| 0292<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA1<br />
|-<br />
| 0293<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA2<br />
|-<br />
| 0294<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA3<br />
|-<br />
| 0295<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA4<br />
|-<br />
| 0296<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA5<br />
|-<br />
| 0297<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA6<br />
|-<br />
| 0298<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA7<br />
|-<br />
| 0299<br />
| [[#GPUREG_0299|GPUREG_0299]]<br />
| <br />
|<br />
|-<br />
| 029A<br />
| [[#GPUREG_029A|GPUREG_029A]]<br />
| <br />
|<br />
|-<br />
| 029B<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_GS_PROG_ADDR<br />
|-<br />
| 029C<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_DATA0<br />
|-<br />
| 029D<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_DATA1<br />
|-<br />
| 029E<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_DATA2<br />
|-<br />
| 029F<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_DATA3<br />
|-<br />
| 02A0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_DATA4<br />
|-<br />
| 02A1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_DATA5<br />
|-<br />
| 02A2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_DATA6<br />
|-<br />
| 02A3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_DATA7<br />
|-<br />
| 02A4<br />
| [[#GPUREG_02A4|GPUREG_02A4]]<br />
| <br />
|<br />
|-<br />
| 02A5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02A6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02A7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02A8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02A9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02AA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02AB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02AC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02AD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02AE<br />
| [[#GPUREG_02AE|GPUREG_02AE]]<br />
| <br />
|<br />
|-<br />
| 02AF<br />
| [[#GPUREG_02AF|GPUREG_02AF]]<br />
| <br />
|<br />
|-<br />
! colspan=4 | Vertex shader<br />
|-<br />
| 02B0<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_VS_BOOL<br />
|-<br />
| 02B1<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_VS_INT0<br />
|-<br />
| 02B2<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_VS_INT1<br />
|-<br />
| 02B3<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_VS_INT2<br />
|-<br />
| 02B4<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_VS_INT3<br />
|-<br />
| 02B5<br />
| [[#GPUREG_02B5|GPUREG_02B5]]<br />
| <br />
|<br />
|-<br />
| 02B6<br />
| [[#GPUREG_02B6|GPUREG_02B6]]<br />
| <br />
|<br />
|-<br />
| 02B7<br />
| [[#GPUREG_02B7|GPUREG_02B7]]<br />
| <br />
|<br />
|-<br />
| 02B8<br />
| [[#GPUREG_02B8|GPUREG_02B8]]<br />
| <br />
|<br />
|-<br />
| 02B9<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_VS_ATTR_NUM0<br />
|-<br />
| 02BA<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_VS_START_ADDR<br />
|-<br />
| 02BB<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP0<br />
|-<br />
| 02BC<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP1<br />
|-<br />
| 02BD<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_VS_OUT_REG_MASK<br />
|-<br />
| 02BE<br />
| [[#GPUREG_02BE|GPUREG_02BE]]<br />
| <br />
|<br />
|-<br />
| 02BF<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_VS_PROG_RENEWAL_END<br />
|-<br />
| 02C0<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_VS_FLOAT_ADDR<br />
|-<br />
| 02C1<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA0<br />
|-<br />
| 02C2<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA1<br />
|-<br />
| 02C3<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA2<br />
|-<br />
| 02C4<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA3<br />
|-<br />
| 02C5<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA4<br />
|-<br />
| 02C6<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA5<br />
|-<br />
| 02C7<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA6<br />
|-<br />
| 02C8<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA7<br />
|-<br />
| 02C9<br />
| [[#GPUREG_02C9|GPUREG_02C9]]<br />
| <br />
|<br />
|-<br />
| 02CA<br />
| [[#GPUREG_02CA|GPUREG_02CA]]<br />
| <br />
|<br />
|-<br />
| 02CB<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_ADDR<br />
|-<br />
| 02CC<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_DATA0<br />
|-<br />
| 02CD<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_DATA1<br />
|-<br />
| 02CE<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_DATA2<br />
|-<br />
| 02CF<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_DATA3<br />
|-<br />
| 02D0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_DATA4<br />
|-<br />
| 02D1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_DATA5<br />
|-<br />
| 02D2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_DATA6<br />
|-<br />
| 02D3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_DATA7<br />
|-<br />
| 02D4<br />
| [[#GPUREG_02D4|GPUREG_02D4]]<br />
| <br />
|<br />
|-<br />
| 02D5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02D6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02D7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02D8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02D9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02DA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02DB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02DC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02DD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02DE<br />
| [[#GPUREG_02DE|GPUREG_02DE]]<br />
| <br />
|<br />
|-<br />
| 02DF<br />
| [[#GPUREG_02DF|GPUREG_02DF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Unknown registers (0x2E0-0x2FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 02E0<br />
| [[#GPUREG_02E0|GPUREG_02E0]]<br />
| <br />
|<br />
|-<br />
| 02E1<br />
| [[#GPUREG_02E1|GPUREG_02E1]]<br />
| <br />
|<br />
|-<br />
| 02E2<br />
| [[#GPUREG_02E2|GPUREG_02E2]]<br />
| <br />
|<br />
|-<br />
| 02E3<br />
| [[#GPUREG_02E3|GPUREG_02E3]]<br />
| <br />
|<br />
|-<br />
| 02E4<br />
| [[#GPUREG_02E4|GPUREG_02E4]]<br />
| <br />
|<br />
|-<br />
| 02E5<br />
| [[#GPUREG_02E5|GPUREG_02E5]]<br />
| <br />
|<br />
|-<br />
| 02E6<br />
| [[#GPUREG_02E6|GPUREG_02E6]]<br />
| <br />
|<br />
|-<br />
| 02E7<br />
| [[#GPUREG_02E7|GPUREG_02E7]]<br />
| <br />
|<br />
|-<br />
| 02E8<br />
| [[#GPUREG_02E8|GPUREG_02E8]]<br />
| <br />
|<br />
|-<br />
| 02E9<br />
| [[#GPUREG_02E9|GPUREG_02E9]]<br />
| <br />
|<br />
|-<br />
| 02EA<br />
| [[#GPUREG_02EA|GPUREG_02EA]]<br />
| <br />
|<br />
|-<br />
| 02EB<br />
| [[#GPUREG_02EB|GPUREG_02EB]]<br />
| <br />
|<br />
|-<br />
| 02EC<br />
| [[#GPUREG_02EC|GPUREG_02EC]]<br />
| <br />
|<br />
|-<br />
| 02ED<br />
| [[#GPUREG_02ED|GPUREG_02ED]]<br />
| <br />
|<br />
|-<br />
| 02EE<br />
| [[#GPUREG_02EE|GPUREG_02EE]]<br />
| <br />
|<br />
|-<br />
| 02EF<br />
| [[#GPUREG_02EF|GPUREG_02EF]]<br />
| <br />
|<br />
|-<br />
| 02F0<br />
| [[#GPUREG_02F0|GPUREG_02F0]]<br />
| <br />
|<br />
|-<br />
| 02F1<br />
| [[#GPUREG_02F1|GPUREG_02F1]]<br />
| <br />
|<br />
|-<br />
| 02F2<br />
| [[#GPUREG_02F2|GPUREG_02F2]]<br />
| <br />
|<br />
|-<br />
| 02F3<br />
| [[#GPUREG_02F3|GPUREG_02F3]]<br />
| <br />
|<br />
|-<br />
| 02F4<br />
| [[#GPUREG_02F4|GPUREG_02F4]]<br />
| <br />
|<br />
|-<br />
| 02F5<br />
| [[#GPUREG_02F5|GPUREG_02F5]]<br />
| <br />
|<br />
|-<br />
| 02F6<br />
| [[#GPUREG_02F6|GPUREG_02F6]]<br />
| <br />
|<br />
|-<br />
| 02F7<br />
| [[#GPUREG_02F7|GPUREG_02F7]]<br />
| <br />
|<br />
|-<br />
| 02F8<br />
| [[#GPUREG_02F8|GPUREG_02F8]]<br />
| <br />
|<br />
|-<br />
| 02F9<br />
| [[#GPUREG_02F9|GPUREG_02F9]]<br />
| <br />
|<br />
|-<br />
| 02FA<br />
| [[#GPUREG_02FA|GPUREG_02FA]]<br />
| <br />
|<br />
|-<br />
| 02FB<br />
| [[#GPUREG_02FB|GPUREG_02FB]]<br />
| <br />
|<br />
|-<br />
| 02FC<br />
| [[#GPUREG_02FC|GPUREG_02FC]]<br />
| <br />
|<br />
|-<br />
| 02FD<br />
| [[#GPUREG_02FD|GPUREG_02FD]]<br />
| <br />
|<br />
|-<br />
| 02FE<br />
| [[#GPUREG_02FE|GPUREG_02FE]]<br />
| <br />
|<br />
|-<br />
| 02FF<br />
| [[#GPUREG_02FF|GPUREG_02FF]]<br />
| <br />
|<br />
|}<br />
<br />
== Miscellaneous registers ==<br />
<br />
=== GPUREG_FINALIZE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)<br />
|}<br />
<br />
Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.<br />
Failure to write to this register in any command buffer will result in the GPU hanging.<br />
<br />
== Rasterizer registers ==<br />
<br />
=== GPUREG_FACECULLING_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Culling mode<br />
|}<br />
<br />
This register is used to configure the face culling mode.<br />
<br />
Culling mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Front Face (Counter Clockwise)<br />
|-<br />
| 2<br />
| Back Face (Counter Clockwise)<br />
|}<br />
<br />
=== GPUREG_VIEWPORT_WIDTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, width / 2<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.<br />
<br />
=== GPUREG_VIEWPORT_INVW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / width<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.<br />
<br />
=== GPUREG_VIEWPORT_HEIGHT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, height / 2<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.<br />
<br />
=== GPUREG_VIEWPORT_INVH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / height<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.<br />
<br />
=== GPUREG_FRAGOP_CLIP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable clipping planes.<br />
<br />
=== GPUREG_FRAGOP_CLIP_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Clipping plane coefficient ''i''<br />
|}<br />
<br />
This register is used to configure clipping plane coefficients.<br />
<br />
=== GPUREG_DEPTHMAP_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near - Far<br />
|}<br />
<br />
This register is used to configure the depth range scale.<br />
<br />
=== GPUREG_DEPTHMAP_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near + Polygon Offset<br />
|}<br />
<br />
This register is used to configure the depth range bias.<br />
<br />
=== GPUREG_SH_OUTMAP_TOTAL ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of following attributes<br />
|}<br />
<br />
This register is used to configure the total shader output map attributes.<br />
<br />
=== GPUREG_SH_OUTMAP_O''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Semantic for the x component of the register.<br />
|-<br />
| 8-12<br />
| unsigned, Semantic for the y component of the register.<br />
|-<br />
| 16-20<br />
| unsigned, Semantic for the z component of the register.<br />
|-<br />
| 24-28<br />
| unsigned, Semantic for the w component of the register.<br />
|}<br />
<br />
These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.<br />
<br />
Semantic values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Semantic<br />
! Description<br />
|-<br />
| 0x00<br />
| position.x<br />
| rowspan="4" | Vertex Position<br />
|-<br />
| 0x01<br />
| position.y<br />
|-<br />
| 0x02<br />
| position.z<br />
|-<br />
| 0x03<br />
| position.w<br />
|-<br />
| 0x04<br />
| normquat.x<br />
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)<br />
|-<br />
| 0x05<br />
| normquat.y<br />
|-<br />
| 0x06<br />
| normquat.z<br />
|-<br />
| 0x07<br />
| normquat.w<br />
|-<br />
| 0x08<br />
| color.r<br />
| rowspan="4" | Vertex color<br />
|-<br />
| 0x09<br />
| color.g<br />
|-<br />
| 0x0A<br />
| color.b<br />
|-<br />
| 0x0B<br />
| color.a<br />
|-<br />
| 0x0C<br />
| texcoord0.u<br />
| rowspan="2" | Texture coordinates for texture 0<br />
|-<br />
| 0x0D<br />
| texcoord0.v<br />
|-<br />
| 0x0E<br />
| texcoord1.u<br />
| rowspan="2" | Texture coordinates for texture 1<br />
|-<br />
| 0x0F<br />
| texcoord1.v<br />
|-<br />
| 0x10<br />
| texcoord0.w<br />
|<br />
<br />
|-<br />
| 0x12<br />
| view.x<br />
| rowspan="3" | View vector (for fragment lighting)<br />
|-<br />
| 0x13<br />
| view.y<br />
|-<br />
| 0x14<br />
| view.z<br />
<br />
|-<br />
| 0x16<br />
| texcoord2.u<br />
| rowspan="2" | Texture coordinates for texture 2<br />
|-<br />
| 0x17<br />
| texcoord2.v<br />
<br />
|-<br />
| 0x1F<br />
| Unused component<br />
| Should be set for unused components of the output register<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Early depth function<br />
|}<br />
<br />
This register configures the early depth test function.<br />
<br />
Early depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| >=<br />
|-<br />
| 1<br />
| ><br />
|-<br />
| 2<br />
| <=<br />
|-<br />
| 3<br />
| <<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether the early depth test is enabled.<br />
<br />
=== GPUREG_EARLYDEPTH_CLEAR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = clear)<br />
|}<br />
<br />
This register triggers clearing the early depth data.<br />
<br />
=== GPUREG_SH_OUTATTR_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Use texture coordinates (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register is used to configure the shader output attribute mode.<br />
<br />
=== GPUREG_SCISSORTEST_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Enabled (0 = disabled, 3 = enabled)<br />
|}<br />
<br />
This register is used to enable scissor testing.<br />
<br />
=== GPUREG_SCISSORTEST_POS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X1<br />
|-<br />
| 16-25<br />
| unsigned, Y1<br />
|}<br />
<br />
This register is used to configure the scissor test start position.<br />
<br />
=== GPUREG_SCISSORTEST_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X2<br />
|-<br />
| 16-25<br />
| unsigned, Y2<br />
|}<br />
<br />
This register is used to configure the scissor test end position.<br />
<br />
=== GPUREG_VIEWPORT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| signed, X<br />
|-<br />
| 16-25<br />
| signed, Y<br />
|}<br />
<br />
This register is used to configure the viewport position.<br />
<br />
=== GPUREG_EARLYDEPTH_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| unsigned, Clear value<br />
|}<br />
<br />
This register is used to configure the early depth clear value.<br />
<br />
=== GPUREG_DEPTHMAP_ENABLE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable depth range.<br />
<br />
=== GPUREG_RENDERBUF_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register is used to configure the output framebuffer dimensions.<br />
<br />
=== GPUREG_SH_OUTATTR_CLOCK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, 'position.z' present (0 = absent, 1 = present)<br />
|-<br />
| 1<br />
| unsigned, 'color' component present (0 = absent, 1 = present)<br />
|-<br />
| 8<br />
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)<br />
|-<br />
| 9<br />
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)<br />
|-<br />
| 10<br />
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)<br />
|-<br />
| 16<br />
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)<br />
|-<br />
| 24<br />
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)<br />
|}<br />
<br />
This register controls the clock supply to parts relating to certain attributes.<br />
<br />
== Texturing registers ==<br />
<br />
=== GPUREG_TEXUNIT_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| 0x0<br />
|-<br />
| 8-9<br />
| unsigned, Texture 3 coordinates<br />
|-<br />
| 10<br />
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| 0x1<br />
|-<br />
| 13<br />
| unsigned, Texture 2 coordinates<br />
|-<br />
| 16<br />
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)<br />
|-<br />
| 17-31<br />
| 0x0<br />
|}<br />
<br />
This register is used to enable texture units.<br />
<br />
Texture 3 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 0<br />
|-<br />
| 1<br />
| Texture 1<br />
|-<br />
| 2<br />
| Texture 2<br />
|}<br />
<br />
Texture 2 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 2<br />
|-<br />
| 1<br />
| Texture 1<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to set a texture unit's border color.<br />
<br />
=== GPUREG_TEXUNIT''i''_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Height<br />
|-<br />
| 16-26<br />
| unsigned, Width<br />
|}<br />
<br />
This register is used to set a texture unit's dimensions.<br />
<br />
=== GPUREG_TEXUNIT''i''_PARAM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, Magnification filter<br />
|-<br />
| 2<br />
| unsigned, Minification filter<br />
|-<br />
| 4-5<br />
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4<br />
|-<br />
| 8-10<br />
| unsigned, Wrap T<br />
|-<br />
| 12-14<br />
| unsigned, Wrap S<br />
|-<br />
| 16-17<br />
| 0x0<br />
|-<br />
| 20<br />
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)<br />
|-<br />
| 24<br />
| unsigned, Mipmap filter<br />
|-<br />
| 28-30<br />
| unsigned, Type (Texture 0 only)<br />
|}<br />
<br />
This register is used to set a texture unit's extra parameters.<br />
<br />
Filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|}<br />
<br />
Wrap values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to edge<br />
|-<br />
| 1<br />
| Clamp to border<br />
|-<br />
| 2<br />
| Repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|}<br />
<br />
Type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 2D<br />
|-<br />
| 1<br />
| Cube map<br />
|-<br />
| 2<br />
| Shadow 2D<br />
|-<br />
| 3<br />
| Projection<br />
|-<br />
| 4<br />
| Shadow cube<br />
|-<br />
| 5<br />
| Disabled<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_LOD ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.4.8, Bias<br />
|-<br />
| 16-19<br />
| unsigned, Max Level<br />
|-<br />
| 24-27<br />
| unsigned, Min Level<br />
|}<br />
<br />
This register is used to configure a texture unit's level of detail.<br />
<br />
=== GPUREG_TEXUNIT''i''_ADDR''i'' ===<br />
<br />
First ADDR register:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Texture physical address >> 3<br />
|}<br />
<br />
Subsequent ADDR registers:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-21<br />
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)<br />
|}<br />
<br />
This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.<br />
<br />
If the texture is a cube:<br />
<br />
{| class="wikitable" border="1"<br />
! Register<br />
! Description<br />
|-<br />
| ADDR1<br />
| Positive X<br />
|-<br />
| ADDR2<br />
| Negative X<br />
|-<br />
| ADDR3<br />
| Positive Y<br />
|-<br />
| ADDR4<br />
| Negative Y<br />
|-<br />
| ADDR5<br />
| Positive Z<br />
|-<br />
| ADDR6<br />
| Negative Z<br />
|}<br />
<br />
Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.<br />
<br />
=== GPUREG_TEXUNIT''i''_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Perspective (0 = perspective, 1 = not perspective)<br />
|-<br />
| 1-23<br />
| fixed0.0.24, Z bias (upper 23 bits)<br />
|}<br />
<br />
This register is used to set a texture unit's shadow texture properties.<br />
<br />
=== GPUREG_TEXUNIT''i''_TYPE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Format<br />
|}<br />
<br />
This register is used to set a texture unit's data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! GL Format<br />
! GL Data Type<br />
|-<br />
| 0x0<br />
| RGBA8888<br />
| GL_RGBA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x1<br />
| RGB888<br />
| GL_RGB<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x2<br />
| RGBA5551<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_5_5_5_1<br />
|-<br />
| 0x3<br />
| RGB565<br />
| GL_RGB<br />
| GL_UNSIGNED_SHORT_5_6_5<br />
|-<br />
| 0x4<br />
| RGBA4444<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_4_4_4_4<br />
|-<br />
| 0x5<br />
| IA8<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x6<br />
| HILO8<br />
| <br />
| <br />
|-<br />
| 0x7<br />
| I8<br />
| GL_LUMINANCE<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x8<br />
| A8<br />
| GL_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x9<br />
| IA44<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE_4_4_EXT<br />
|-<br />
| 0xA<br />
| I4<br />
| <br />
|<br />
|-<br />
| 0xB<br />
| A4<br />
| GL_ALPHA<br />
| GL_UNSIGNED_NIBBLE_EXT<br />
|-<br />
| 0xC<br />
| ETC1<br />
| GL_ETC1_RGB8_OES<br />
| <br />
|-<br />
| 0xD<br />
| ETC1A4<br />
|<br />
| <br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable lighting.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, U-direction clamp<br />
|-<br />
| 3-5<br />
| unsigned, V-direction clamp<br />
|-<br />
| 6-9<br />
| unsigned, RGB mapping function<br />
|-<br />
| 10-13<br />
| unsigned, Alpha mapping function<br />
|-<br />
| 14<br />
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)<br />
|-<br />
| 15<br />
| unsigned, Noise enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 16-17<br />
| unsigned, U-direction shift<br />
|-<br />
| 18-19<br />
| unsigned, V-direction shift<br />
|-<br />
| 20-27<br />
| float1.5.10, Texture bias (lower 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Clamp values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to zero<br />
|-<br />
| 1<br />
| Clamp to edge<br />
|-<br />
| 2<br />
| Symmetrical repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|-<br />
| 4<br />
| Pulse<br />
|}<br />
<br />
Mapping function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| U<br />
|-<br />
| 1<br />
| U²<br />
|-<br />
| 2<br />
| V<br />
|-<br />
| 3<br />
| V²<br />
|-<br />
| 4<br />
| (U + V) / 2<br />
|-<br />
| 5<br />
| (U² + V²) / 2<br />
|-<br />
| 6<br />
| sqrt(U² + V²)<br />
|-<br />
| 7<br />
| Minimum<br />
|-<br />
| 8<br />
| Maximum<br />
|-<br />
| 9<br />
| Rmax<br />
|}<br />
<br />
Shift values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Odd<br />
|-<br />
| 2<br />
| Even<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, U-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, U-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, V-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX3 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, U-direction noise frequency<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise frequency<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX4 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Minification filter<br />
|-<br />
| 3-10<br />
| 0x60<br />
|-<br />
| 11-18<br />
| unsigned, Texture width<br />
|-<br />
| 19-26<br />
| float1.5.10, Texture bias (upper 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Minification filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|-<br />
| 2<br />
| Nearest, Mipmap Nearest<br />
|-<br />
| 3<br />
| Linear, Mipmap Nearest<br />
|-<br />
| 4<br />
| Nearest, Mipmap Linear<br />
|-<br />
| 5<br />
| Linear, Mipmap Linear<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX5 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Texture offset<br />
|-<br />
| 8-31<br />
| 0xE0C080<br />
|}<br />
<br />
This register is used to set the procedural texture unit's offset.<br />
<br />
=== GPUREG_PROCTEX_LUT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Index<br />
|-<br />
| 8-11<br />
| unsigned, Reference table<br />
|}<br />
<br />
This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.<br />
<br />
Reference table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Noise table<br />
|-<br />
| 2<br />
| RGB mapping function table<br />
|-<br />
| 3<br />
| Alpha mapping function table<br />
|-<br />
| 4<br />
| Color table<br />
|-<br />
| 5<br />
| Color difference table<br />
|}<br />
<br />
=== GPUREG_PROCTEX_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.<br />
<br />
==== Noise Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== RGB Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Alpha Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Color Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
==== Color Difference Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| fixed1.0.7, Red difference between current and next color table elements<br />
|-<br />
| 8-15<br />
| fixed1.0.7, Green difference between current and next color table elements<br />
|-<br />
| 16-23<br />
| fixed1.0.7, Blue difference between current and next color table elements<br />
|-<br />
| 24-31<br />
| fixed1.0.7, Alpha difference between current and next color table elements<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_SOURCE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB source 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB source 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB source 2<br />
|-<br />
| 16-19<br />
| unsigned, Alpha source 0<br />
|-<br />
| 20-23<br />
| unsigned, Alpha source 1<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source 2<br />
|}<br />
<br />
This register configures a texture combiner's sources.<br />
<br />
Source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Primary color<br />
|-<br />
| 1<br />
| Fragment primary color<br />
|-<br />
| 2<br />
| Fragment secondary color<br />
|-<br />
| 3<br />
| Texture 0<br />
|-<br />
| 4<br />
| Texture 1<br />
|-<br />
| 5<br />
| Texture 2<br />
|-<br />
| 6<br />
| Texture 3<br />
|-<br />
| 13<br />
| Previous buffer<br />
|-<br />
| 14<br />
| Constant (from GPUREG_TEXENV''i''_COLOR)<br />
|-<br />
| 15<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_OPERAND ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB operand 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB operand 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB operand 2<br />
|-<br />
| 12-14<br />
| unsigned, Alpha operand 0<br />
|-<br />
| 16-18<br />
| unsigned, Alpha operand 1<br />
|-<br />
| 20-22<br />
| unsigned, Alpha operand 2<br />
|}<br />
<br />
This register configures a texture combiner's operands.<br />
<br />
RGB operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source color<br />
|-<br />
| 1<br />
| One minus source color<br />
|-<br />
| 2<br />
| Source alpha<br />
|-<br />
| 3<br />
| One minus source alpha<br />
|-<br />
| 4<br />
| Source red<br />
|-<br />
| 5<br />
| One minus source red<br />
|-<br />
| 8<br />
| Source green<br />
|-<br />
| 9<br />
| One minus source green<br />
|-<br />
| 12<br />
| Source blue<br />
|-<br />
| 13<br />
| One minus source blue<br />
|}<br />
<br />
Alpha operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source alpha<br />
|-<br />
| 1<br />
| One minus source alpha<br />
|-<br />
| 2<br />
| Source red<br />
|-<br />
| 3<br />
| One minus source red<br />
|-<br />
| 4<br />
| Source green<br />
|-<br />
| 5<br />
| One minus source green<br />
|-<br />
| 6<br />
| Source blue<br />
|-<br />
| 7<br />
| One minus source blue<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COMBINER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB combine<br />
|-<br />
| 16-19<br />
| unsigned, Alpha combine<br />
|}<br />
<br />
This register configures a texture combiner's combine mode.<br />
<br />
Combine values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Replace<br />
|-<br />
| 1<br />
| Modulate<br />
|-<br />
| 2<br />
| Add<br />
|-<br />
| 3<br />
| Add signed<br />
|-<br />
| 4<br />
| Interpolate<br />
|-<br />
| 5<br />
| Subtract<br />
|-<br />
| 6<br />
| Dot3 RGB<br />
|-<br />
| 7<br />
| Dot3 RGBA<br />
|-<br />
| 8<br />
| Multiply then add<br />
|-<br />
| 9<br />
| Add then multiply<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register configures a texture combiner's constant color.<br />
<br />
=== GPUREG_TEXENV''i''_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, RGB scale<br />
|-<br />
| 16-17<br />
| unsigned, Alpha scale<br />
|}<br />
<br />
This register configures a texture combiner's scale value.<br />
<br />
Scale values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|}<br />
<br />
=== GPUREG_TEXENV_UPDATE_BUFFER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fog mode<br />
|-<br />
| 3<br />
| unsigned, Shading density source<br />
|-<br />
| 8<br />
| unsigned, TexEnv 1 RGB buffer input<br />
|-<br />
| 9<br />
| unsigned, TexEnv 2 RGB buffer input<br />
|-<br />
| 10<br />
| unsigned, TexEnv 3 RGB buffer input<br />
|-<br />
| 11<br />
| unsigned, TexEnv 4 RGB buffer input<br />
|-<br />
| 12<br />
| unsigned, TexEnv 1 alpha buffer input<br />
|-<br />
| 13<br />
| unsigned, TexEnv 2 alpha buffer input<br />
|-<br />
| 14<br />
| unsigned, TexEnv 3 alpha buffer input<br />
|-<br />
| 15<br />
| unsigned, TexEnv 4 alpha buffer input<br />
|-<br />
| 16<br />
| unsigned, Z flip (0 = don't flip, 1 = flip)<br />
|-<br />
| 24-25<br />
| 0x0<br />
|}<br />
<br />
This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.<br />
<br />
Fog mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Disabled<br />
|-<br />
| 5<br />
| Fog<br />
|-<br />
| 7<br />
| Gas<br />
|}<br />
<br />
Shading density source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Plain density<br />
|-<br />
| 1<br />
| Depth density<br />
|}<br />
<br />
Buffer input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Previous buffer<br />
|-<br />
| 1<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_FOG_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
This register is used to configure the color of fog.<br />
<br />
=== GPUREG_GAS_ATTENUATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas density attenuation<br />
|}<br />
<br />
This register is used to configure the gas density attenuation.<br />
<br />
=== GPUREG_GAS_ACCMAX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas maximum density accumulation<br />
|}<br />
<br />
This register is used to configure the gas maximum density accumulation.<br />
<br />
=== GPUREG_FOG_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.<br />
<br />
=== GPUREG_FOG_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.<br />
<br />
==== Fog Look-Up Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Difference from next element <br />
|-<br />
| 13-23<br />
| fixed0.0.11, Value<br />
|}<br />
<br />
=== GPUREG_TEXENV_BUFFER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the texture combiner buffer color.<br />
<br />
== Framebuffer registers ==<br />
<br />
=== GPUREG_COLOR_OPERATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Fragment operation mode<br />
|-<br />
| 8<br />
| unsigned, Blend mode<br />
|-<br />
| 16-25<br />
| 0x0E4<br />
|}<br />
<br />
This register is used to configure the fragment operation mode and whether to use logic ops or blending.<br />
<br />
Fragment operation mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Default<br />
|-<br />
| 1<br />
| Gas<br />
|-<br />
| 3<br />
| Shadow<br />
|}<br />
<br />
Blend mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Logic op<br />
|-<br />
| 1<br />
| Blend<br />
|}<br />
<br />
=== GPUREG_BLEND_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, RGB equation<br />
|-<br />
| 8-10<br />
| unsigned, Alpha equation<br />
|-<br />
| 16-19<br />
| unsigned, RGB source function<br />
|-<br />
| 20-23<br />
| unsigned, RGB destination function<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source function<br />
|-<br />
| 28-31<br />
| unsigned, Alpha destination function<br />
|}<br />
<br />
This register is used to configure the blending function.<br />
<br />
Equation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Add<br />
|-<br />
| 1<br />
| Subtract<br />
|-<br />
| 2<br />
| Reverse subtract<br />
|-<br />
| 3<br />
| Minimum<br />
|-<br />
| 4<br />
| Maximum<br />
|}<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Zero<br />
|-<br />
| 1<br />
| One<br />
|-<br />
| 2<br />
| Source color<br />
|-<br />
| 3<br />
| One minus source color<br />
|-<br />
| 4<br />
| Destination color<br />
|-<br />
| 5<br />
| One minus destination color<br />
|-<br />
| 6<br />
| Source alpha<br />
|-<br />
| 7<br />
| One minus source alpha<br />
|-<br />
| 8<br />
| Destination alpha<br />
|-<br />
| 9<br />
| One minus destination alpha<br />
|-<br />
| 10<br />
| Constant color<br />
|-<br />
| 11<br />
| One minus constant color<br />
|-<br />
| 12<br />
| Constant alpha<br />
|-<br />
| 13<br />
| One minus constant alpha<br />
|-<br />
| 14<br />
| Source alpha saturate<br />
|}<br />
<br />
=== GPUREG_LOGIC_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Logic op<br />
|}<br />
<br />
This register is used to configure the logic op.<br />
<br />
Logic op values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clear<br />
|-<br />
| 1<br />
| AND<br />
|-<br />
| 2<br />
| Reverse AND<br />
|-<br />
| 3<br />
| Copy<br />
|-<br />
| 4<br />
| Set<br />
|-<br />
| 5<br />
| Inverted copy<br />
|-<br />
| 6<br />
| Noop<br />
|-<br />
| 7<br />
| Invert<br />
|-<br />
| 8<br />
| NAND<br />
|-<br />
| 9<br />
| OR<br />
|-<br />
| 10<br />
| NOR<br />
|-<br />
| 11<br />
| XOR<br />
|-<br />
| 12<br />
| Equivalent<br />
|-<br />
| 13<br />
| Inverted AND<br />
|-<br />
| 14<br />
| Reverse OR<br />
|-<br />
| 15<br />
| Inverted OR<br />
|}<br />
<br />
=== GPUREG_BLEND_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the blending color.<br />
<br />
=== GPUREG_FRAGOP_ALPHA_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Reference value<br />
|}<br />
<br />
This register is used to configure alpha testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Buffer mask<br />
|-<br />
| 16-23<br />
| signed, Reference value<br />
|-<br />
| 24-31<br />
| unsigned, Mask<br />
|}<br />
<br />
This register is used to configure stencil testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fail operation<br />
|-<br />
| 4-6<br />
| unsigned, Z-fail operation<br />
|-<br />
| 8-10<br />
| unsigned, Z-pass operation<br />
|}<br />
<br />
This register is used to configure stencil result operations.<br />
<br />
Operation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Keep<br />
|-<br />
| 1<br />
| Zero<br />
|-<br />
| 2<br />
| Replace<br />
|-<br />
| 3<br />
| Increment<br />
|-<br />
| 4<br />
| Decrement<br />
|-<br />
| 5<br />
| Invert<br />
|-<br />
| 6<br />
| Increment and wrap<br />
|-<br />
| 7<br />
| Decrement and wrap<br />
|}<br />
<br />
=== GPUREG_DEPTH_COLOR_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Depth function<br />
|-<br />
| 8<br />
| unsigned, Red write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 9<br />
| unsigned, Green write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 10<br />
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 11<br />
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to depth testing and framebuffer write masking.<br />
<br />
Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.<br />
<br />
Depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_FRAMEBUFFER_INVALIDATE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = invalidate)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.<br />
<br />
=== GPUREG_FRAMEBUFFER_FLUSH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = flush)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.<br />
<br />
=== GPUREG_COLORBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow read (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures read access from the color buffer.<br />
<br />
=== GPUREG_COLORBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow write (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures write access to the color buffer.<br />
<br />
=== GPUREG_DEPTHBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil read (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth read (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures read access from the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil write (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth write (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures write access to the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the depth buffer data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit depth<br />
|-<br />
| 2<br />
| 24-bit depth<br />
|-<br />
| 3<br />
| 24-bit depth + 8-bit stencil<br />
|}<br />
<br />
=== GPUREG_COLORBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Pixel size<br />
|-<br />
| 16-18<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.<br />
<br />
Pixel size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit color<br />
|-<br />
| 2<br />
| 32-bit color<br />
|}<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| RGBA8/Gas<br />
|-<br />
| 2<br />
| RGB5A1<br />
|-<br />
| 3<br />
| RGB565<br />
|-<br />
| 4<br />
| RGBA4<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register enables the early depth test.<br />
<br />
=== GPUREG_FRAMEBUFFER_BLOCK32 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Render block mode<br />
|}<br />
<br />
This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.<br />
<br />
Render block mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8x8 blocks<br />
|-<br />
| 1<br />
| 32x32 blocks<br />
|}<br />
<br />
=== GPUREG_DEPTHBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Depth buffer physical address >> 3<br />
|}<br />
<br />
This register configures the depth buffer physical address.<br />
<br />
=== GPUREG_COLORBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Color buffer physical address >> 3<br />
|}<br />
<br />
This register configures the color buffer physical address.<br />
<br />
=== GPUREG_FRAMEBUFFER_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register configures the framebuffer dimensions.<br />
<br />
=== GPUREG_GAS_LIGHT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Planar shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, Planar shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, Planar shading density attenuation<br />
|}<br />
<br />
This register configures gas light planar shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, View shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, View shading density attenuation<br />
|}<br />
<br />
This register configures gas light view shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading effect in line-of-sight direction<br />
|-<br />
| 8<br />
| Gas color LUT input<br />
|}<br />
<br />
This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.<br />
<br />
Color LUT input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Gas density<br />
|-<br />
| 1<br />
| Light factor<br />
|}<br />
<br />
=== GPUREG_GAS_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.<br />
<br />
=== GPUREG_GAS_LUT_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.<br />
<br />
==== Gas Look-Up Table ====<br />
<br />
16 elements:<br />
<br />
First 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| signed, Red<br />
|-<br />
| 8-15<br />
| signed, Green<br />
|-<br />
| 16-23<br />
| signed, Blue<br />
|}<br />
<br />
Last 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
=== GPUREG_GAS_DELTAZ_DEPTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| fixed0.16.8, Depth direction attenuation proportion<br />
|}<br />
<br />
This register is used to configure the gas depth direction attenuation proportion.<br />
<br />
=== GPUREG_FRAGOP_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Sum of penumbra scale and penumbra bias<br />
|-<br />
| 16-31<br />
| float1.5.10, Penumbra scale with reversed sign<br />
|}<br />
<br />
This register is used to configure shadow properties.<br />
<br />
== Fragment lighting registers ==<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR1 ===<br />
<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.<br />
<br />
=== GPUREG_LIGHT''i''_DIFFUSE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.<br />
<br />
=== GPUREG_LIGHT''i''_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.<br />
<br />
=== GPUREG_LIGHT''i''_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, X coordinate<br />
|-<br />
| 16-31<br />
| float1.5.10, Y coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Z coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, X coordinate (negated)<br />
|-<br />
| 16-28<br />
| fixed1.1.11, Y coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Z coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Light type (0 = positional light, 1 = directional light)<br />
|-<br />
| 1<br />
| unsigned, Two side diffuse (0 = one side, 1 = both sides)<br />
|-<br />
| 2<br />
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)<br />
|-<br />
| 3<br />
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures a light's properties.<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation bias<br />
|}<br />
<br />
These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation scale<br />
|}<br />
<br />
These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHTING_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.<br />
<br />
=== GPUREG_LIGHTING_NUM_LIGHTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of active lights - 1<br />
|}<br />
<br />
This register configures the number of active lights.<br />
<br />
=== GPUREG_LIGHTING_CONFIG0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)<br />
|-<br />
| 2-3<br />
| unsigned, Fresnel selector<br />
|-<br />
| 4-7<br />
| unsigned, Light environment configuration<br />
|-<br />
| 8-11<br />
| 0x4<br />
|-<br />
| 16<br />
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 17<br />
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 18<br />
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)<br />
|-<br />
| 19<br />
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)<br />
|-<br />
| 22-23<br />
| unsigned, Bump map texture unit<br />
|-<br />
| 24-25<br />
| unsigned, Shadow map texture unit<br />
|-<br />
| 27<br />
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)<br />
|-<br />
| 28-29<br />
| unsigned, Bump mode<br />
|-<br />
| 30<br />
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)<br />
|-<br />
| 31<br />
| 0x1<br />
|}<br />
<br />
This register configures the light environment.<br />
<br />
Fresnel selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Primary alpha<br />
|-<br />
| 2<br />
| Secondary alpha<br />
|-<br />
| 3<br />
| Primary and secondary alpha<br />
|}<br />
<br />
The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.<br />
<br />
Light environment configuration values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! Available LUTs<br />
|-<br />
| 0<br />
| Configuration 0<br />
| D0, RR, SP, DA<br />
|-<br />
| 1<br />
| Configuration 1<br />
| FR, RR, SP, DA<br />
|-<br />
| 2<br />
| Configuration 2<br />
| D0, D1, RR, DA<br />
|-<br />
| 3<br />
| Configuration 3<br />
| D0, D1, FR, DA<br />
|-<br />
| 4<br />
| Configuration 4<br />
| All except for FR<br />
|-<br />
| 5<br />
| Configuration 5<br />
| All except for D1<br />
|-<br />
| 6<br />
| Configuration 6<br />
| All except for RB and RG<br />
|-<br />
| 8<br />
| Configuration 7<br />
| All<br />
|}<br />
<br />
Bump mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Not used<br />
|-<br />
| 1<br />
| Use as bump map<br />
|-<br />
| 2<br />
| Use as tangent map<br />
|}<br />
<br />
=== GPUREG_LIGHTING_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 1<br />
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 2<br />
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 3<br />
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 4<br />
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 6<br />
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 7<br />
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 8<br />
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 10<br />
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 11<br />
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 12<br />
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 14<br />
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 15<br />
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 16<br />
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 18<br />
| 0x1<br />
|-<br />
| 19<br />
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 20-22<br />
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 21<br />
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 22<br />
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 24<br />
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 26<br />
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 27<br />
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 28<br />
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 29<br />
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 30<br />
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 31<br />
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is used to disable various aspects of the light environment.<br />
<br />
=== GPUREG_LIGHTING_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Starting index<br />
|-<br />
| 8-12<br />
| unsigned, Look-up table<br />
|}<br />
<br />
This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.<br />
<br />
Lookup table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| D0<br />
|-<br />
| 1<br />
| D1<br />
|-<br />
| 3<br />
| FR<br />
|-<br />
| 4<br />
| RB<br />
|-<br />
| 5<br />
| RG<br />
|-<br />
| 6<br />
| RR<br />
|-<br />
| 8-15<br />
| SP0-7<br />
|-<br />
| 16-23<br />
| DA0-7<br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.<br />
<br />
=== GPUREG_LIGHTING_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
Lighting LUT data is written here.<br />
<br />
A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.<br />
<br />
DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.<br />
<br />
Format of an entry:<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Entry value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_ABS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)<br />
|-<br />
| 21<br />
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register controls whether the absolute value of the input is taken before using a LUT.<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SELECT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Input selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Input selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Input selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Input selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Input selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Input selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Input selector for RR<br />
|}<br />
<br />
This register selects the input from LUTs.<br />
<br />
Input selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| N·H<br />
|-<br />
| 1<br />
| V·H<br />
|-<br />
| 2<br />
| N·V<br />
|-<br />
| 3<br />
| L·N<br />
|-<br />
| 4<br />
| -L·P (aka Spotlight aka SP)<br />
|-<br />
| 5<br />
| cos φ (aka CP)<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Scaler selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Scaler selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Scaler selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Scaler selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Scaler selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Scaler selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Scaler selector for RR<br />
|}<br />
<br />
This register controls the scaling that is applied to the output of a LUT.<br />
<br />
Scaler selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|-<br />
| 3<br />
| 8x<br />
|-<br />
| 6<br />
| 0.25x<br />
|-<br />
| 7<br />
| 0.5x<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, ID of the 1st enabled light<br />
|-<br />
| 4-6<br />
| unsigned, ID of the 2nd enabled light<br />
|-<br />
| 8-10<br />
| unsigned, ID of the 3rd enabled light<br />
|-<br />
| 12-14<br />
| unsigned, ID of the 4th enabled light<br />
|-<br />
| 16-18<br />
| unsigned, ID of the 5th enabled light<br />
|-<br />
| 20-22<br />
| unsigned, ID of the 6th enabled light<br />
|-<br />
| 24-26<br />
| unsigned, ID of the 7th enabled light<br />
|-<br />
| 28-30<br />
| unsigned, ID of the 8th enabled light<br />
|}<br />
<br />
This register sets the IDs of enabled light sources.<br />
<br />
== Geometry pipeline registers ==<br />
<br />
=== GPUREG_ATTRIBBUFFERS_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-28<br />
| unsigned, Vertex arrays base address<br />
|}<br />
<br />
This register sets the base address of all vertex arrays.<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 0 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 0 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 1 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 1 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 2 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 2 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 3 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 3 size<br />
|-<br />
| 16-17<br />
| unsigned, Vertex attribute 4 type<br />
|-<br />
| 18-19<br />
| unsigned, Vertex attribute 4 size<br />
|-<br />
| 20-21<br />
| unsigned, Vertex attribute 5 type<br />
|-<br />
| 22-23<br />
| unsigned, Vertex attribute 5 size<br />
|-<br />
| 24-25<br />
| unsigned, Vertex attribute 6 type<br />
|-<br />
| 26-27<br />
| unsigned, Vertex attribute 6 size<br />
|-<br />
| 28-29<br />
| unsigned, Vertex attribute 7 type<br />
|-<br />
| 30-31<br />
| unsigned, Vertex attribute 7 size<br />
|}<br />
<br />
This register configures the types and sizes of the first 8 vertex attributes.<br />
<br />
Vertex attribute type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Byte<br />
|-<br />
| 1<br />
| Unsigned byte<br />
|-<br />
| 2<br />
| Short<br />
|-<br />
| 3<br />
| Float<br />
|}<br />
<br />
Vertex attribute size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8 bits<br />
|-<br />
| 1<br />
| 16 bits<br />
|-<br />
| 2<br />
| 24 bits<br />
|-<br />
| 3<br />
| 32 bits<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 8 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 8 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 9 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 9 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 10 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 10 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 11 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 11 size<br />
|-<br />
| 16-27<br />
| unsigned, Fixed vertex attribute mask<br />
|-<br />
| 28-31<br />
| unsigned, Total vertex attribute count - 1<br />
|}<br />
<br />
This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.<br />
<br />
See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|}<br />
<br />
This register configures the offset of a vertex array from the base vertex arrays address.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 1<br />
|-<br />
| 4-7<br />
| unsigned, Component 2<br />
|-<br />
| 8-11<br />
| unsigned, Component 3<br />
|-<br />
| 12-15<br />
| unsigned, Component 4<br />
|-<br />
| 16-19<br />
| unsigned, Component 5<br />
|-<br />
| 20-23<br />
| unsigned, Component 6<br />
|-<br />
| 24-27<br />
| unsigned, Component 7<br />
|-<br />
| 28-31<br />
| unsigned, Component 8<br />
|}<br />
<br />
This register configures the first 8 component types of a vertex array.<br />
<br />
Component values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Vertex attribute 0<br />
|-<br />
| 1<br />
| Vertex attribute 1<br />
|-<br />
| 2<br />
| Vertex attribute 2<br />
|-<br />
| 3<br />
| Vertex attribute 3<br />
|-<br />
| 4<br />
| Vertex attribute 4<br />
|-<br />
| 5<br />
| Vertex attribute 5<br />
|-<br />
| 6<br />
| Vertex attribute 6<br />
|-<br />
| 7<br />
| Vertex attribute 7<br />
|-<br />
| 8<br />
| Vertex attribute 8<br />
|-<br />
| 9<br />
| Vertex attribute 9<br />
|-<br />
| 10<br />
| Vertex attribute 10<br />
|-<br />
| 11<br />
| Vertex attribute 11<br />
|-<br />
| 12<br />
| 4-byte padding<br />
|-<br />
| 13<br />
| 8-byte padding<br />
|-<br />
| 14<br />
| 12-byte padding<br />
|-<br />
| 15<br />
| 16-byte padding<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 9<br />
|-<br />
| 4-7<br />
| unsigned, Component 10<br />
|-<br />
| 8-11<br />
| unsigned, Component 11<br />
|-<br />
| 12-15<br />
| unsigned, Component 12<br />
|-<br />
| 16-23<br />
| unsigned, Bytes per vertex<br />
|-<br />
| 28-31<br />
| unsigned, Total number of components<br />
|}<br />
<br />
This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.<br />
<br />
See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.<br />
<br />
=== GPUREG_INDEXBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|-<br />
| 31<br />
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)<br />
|}<br />
<br />
This register configures the index array used when drawing elements.<br />
<br />
=== GPUREG_NUMVERTICES ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Number of vertices to render<br />
|}<br />
<br />
This register sets the number of vertices to render.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|-<br />
| 9<br />
| 0x0<br />
|-<br />
| 31<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_VERTEX_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Starting vertex offset<br />
|}<br />
<br />
This register sets the offset of the first vertex in an array to render.<br />
<br />
=== GPUREG_POST_VERTEX_CACHE_NUM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)<br />
|}<br />
<br />
This register configures the post-vertex cache.<br />
<br />
=== GPUREG_DRAWARRAYS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw arrays)<br />
|}<br />
<br />
This register triggers drawing vertex arrays.<br />
<br />
=== GPUREG_DRAWELEMENTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw elements)<br />
|}<br />
<br />
This register triggers drawing vertex array elements.<br />
<br />
=== GPUREG_VTX_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)<br />
|}<br />
<br />
This register triggers clearing the post-vertex cache.<br />
<br />
=== GPUREG_FIXEDATTRIB_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)<br />
|}<br />
<br />
This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.<br />
<br />
=== GPUREG_FIXEDATTRIB_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| colspan="2" | '''DATA0:'''<br />
|-<br />
| 0-7<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)<br />
|-<br />
| 8-31<br />
| float1.7.16, Vertex attribute element 4 (W)<br />
|-<br />
| colspan="2" | '''DATA1:'''<br />
|-<br />
| 0-15<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)<br />
|-<br />
| 16-31<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)<br />
|-<br />
| colspan="2" | '''DATA2:'''<br />
|-<br />
| 0-23<br />
| float1.7.16, Vertex attribute element 1 (X)<br />
|-<br />
| 24-31<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)<br />
|}<br />
<br />
Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.<br />
<br />
=== GPUREG_CMDBUF_SIZE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the size of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_SIZE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the size of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the physical address of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the physical address of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)<br />
|}<br />
<br />
This register triggers a jump to the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)<br />
|}<br />
<br />
This register triggers a jump to the second command buffer.<br />
<br />
=== GPUREG_VSH_NUM_ATTR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader input attributes - 1<br />
|}<br />
<br />
This register sets the number of vertex shader input attributes.<br />
<br />
=== GPUREG_VSH_COM_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.<br />
<br />
=== GPUREG_START_DRAW_FUNC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Mode (0 = drawing, 1 = configuration)<br />
|-<br />
| 1-7<br />
| 0x0<br />
|}<br />
<br />
This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_GSH_MISC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)<br />
|}<br />
<br />
This register configures miscellaneous geometry shader properties.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_GSH_MISC1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)<br />
|}<br />
<br />
This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.<br />
<br />
=== GPUREG_PRIMITIVE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|-<br />
| 8-9<br />
| unsigned, Primitive mode<br />
|}<br />
<br />
This register configures primitive drawing.<br />
<br />
Primitive mode value:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Triangles<br />
|-<br />
| 1<br />
| Triangle strip<br />
|-<br />
| 2<br />
| Triangle fan<br />
|-<br />
| 3<br />
| Geometry primitive<br />
|}<br />
<br />
=== GPUREG_RESTART_PRIMITIVE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = reset primitive)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
This register triggers resetting primitive drawing.<br />
<br />
== Shader registers ==<br />
<br />
=== GPUREG_''SH''_BOOLUNIFORM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Boolean register b0 value (0 = false, 1 = true)<br />
|-<br />
| 1<br />
| unsigned, Boolean register b1 value (0 = false, 1 = true)<br />
|-<br />
| 2<br />
| unsigned, Boolean register b2 value (0 = false, 1 = true)<br />
|-<br />
| 3<br />
| unsigned, Boolean register b3 value (0 = false, 1 = true)<br />
|-<br />
| 4<br />
| unsigned, Boolean register b4 value (0 = false, 1 = true)<br />
|-<br />
| 5<br />
| unsigned, Boolean register b5 value (0 = false, 1 = true)<br />
|-<br />
| 6<br />
| unsigned, Boolean register b6 value (0 = false, 1 = true)<br />
|-<br />
| 7<br />
| unsigned, Boolean register b7 value (0 = false, 1 = true)<br />
|-<br />
| 8<br />
| unsigned, Boolean register b8 value (0 = false, 1 = true)<br />
|-<br />
| 9<br />
| unsigned, Boolean register b9 value (0 = false, 1 = true)<br />
|-<br />
| 10<br />
| unsigned, Boolean register b10 value (0 = false, 1 = true)<br />
|-<br />
| 11<br />
| unsigned, Boolean register b11 value (0 = false, 1 = true)<br />
|-<br />
| 12<br />
| unsigned, Boolean register b12 value (0 = false, 1 = true)<br />
|-<br />
| 13<br />
| unsigned, Boolean register b13 value (0 = false, 1 = true)<br />
|-<br />
| 14<br />
| unsigned, Boolean register b14 value (0 = false, 1 = true)<br />
|-<br />
| 15<br />
| unsigned, Boolean register b15 value (0 = false, 1 = true)<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register is used to set a shader unit's boolean registers.<br />
<br />
=== GPUREG_''SH''_INTUNIFORM_I''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Integer register i''i'' X value<br />
|-<br />
| 8-15<br />
| unsigned, Integer register i''i'' Y value<br />
|-<br />
| 16-23<br />
| unsigned, Integer register i''i'' Z value<br />
|-<br />
| 24-31<br />
| unsigned, Integer register i''i'' W value<br />
|}<br />
<br />
These registers are used to set a shader unit's integer registers.<br />
<br />
=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Input vertex attributes - 1<br />
|-<br />
| 8-15<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)<br />
|-<br />
| 16-23<br />
| 0x0<br />
|-<br />
| 24-31<br />
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)<br />
|}<br />
<br />
This register is used to configure a shader unit's input buffer.<br />
<br />
=== GPUREG_''SH''_ENTRYPOINT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Code entry point offset, in 32-bit words<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register sets a shader unit's code entry point.<br />
<br />
For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.<br />
<br />
For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them. <br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 0 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 1 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 2 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 3 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 4 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 5 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 6 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 7 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.<br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 8 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 9 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 10 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 11 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 12 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 13 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 14 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 15 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.<br />
<br />
=== GPUREG_''SH''_OUTMAP_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4<br />
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 5<br />
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 6<br />
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 7<br />
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 8<br />
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 9<br />
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 10<br />
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 11<br />
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 12<br />
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 13<br />
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 14<br />
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 15<br />
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 16-31<br />
| 0x0<br />
|}<br />
<br />
This register toggles a shader unit's output registers.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_END ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Signal transfer end (0 = idle, non-zero = signal)<br />
|}<br />
<br />
This register's value should be set to 1 in order to finalize the transfer of shader code.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)<br />
|-<br />
| 31<br />
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)<br />
|}<br />
<br />
This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| Floating-point register component data<br />
|}<br />
<br />
This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].<br />
<br />
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:<br />
** first word : ZZWWWWWW<br />
** second word : YYYYZZZZ<br />
** third word : XXXXXXYY<br />
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader code offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader instruction data<br />
|}<br />
<br />
This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.<br />
<br />
=== GPUREG_''SH''_OPDESCS_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader operand descriptor offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_OPDESCS_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader operand descriptor data<br />
|}<br />
<br />
This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=GPU/Internal_Registers&diff=19812
GPU/Internal Registers
2017-04-08T10:57:01Z
<p>Plutooo: </p>
<hr />
<div>[[Category:GPU]]<br />
<br />
== Overview ==<br />
GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.<br />
<br />
Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).<br />
<br />
In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.<br />
<br />
For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).<br />
<br />
Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.<br />
<br />
The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.<br />
<br />
=== Command Header ===<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0-15<br />
| Command ID<br />
|-<br />
| 16-19<br />
| Parameter mask<br />
|-<br />
| 20-30<br />
| Number of extra parameters (may be zero)<br />
|-<br />
| 31<br />
| Consecutive writing mode<br />
|}<br />
<br />
=== Parameter masking ===<br />
<br />
Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.<br />
<br />
=== Types ===<br />
<br />
There are three main types of registers :<br />
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])<br />
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])<br />
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])<br />
<br />
=== Aliases ===<br />
<br />
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]<br />
<br />
=== Data Types ===<br />
<br />
{| class="wikitable" border="1"<br />
! Name<br />
! Description<br />
|-<br />
| signed<br />
| Signed integer<br />
|-<br />
| unsigned<br />
| Unsigned integer<br />
|-<br />
| floatX.Y.Z<br />
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits<br />
|-<br />
| fixedX.Y.Z<br />
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits<br />
|}<br />
<br />
== Register list ==<br />
<br />
=== Miscellaneous registers (0x000-0x03F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0000<br />
| [[#GPUREG_0000|GPUREG_0000]]<br />
| <br />
|<br />
|-<br />
| 0001<br />
| [[#GPUREG_0001|GPUREG_0001]]<br />
| <br />
|<br />
|-<br />
| 0002<br />
| [[#GPUREG_0002|GPUREG_0002]]<br />
| <br />
|<br />
|-<br />
| 0003<br />
| [[#GPUREG_0003|GPUREG_0003]]<br />
| <br />
|<br />
|-<br />
| 0004<br />
| [[#GPUREG_0004|GPUREG_0004]]<br />
| <br />
|<br />
|-<br />
| 0005<br />
| [[#GPUREG_0005|GPUREG_0005]]<br />
| <br />
|<br />
|-<br />
| 0006<br />
| [[#GPUREG_0006|GPUREG_0006]]<br />
| <br />
|<br />
|-<br />
| 0007<br />
| [[#GPUREG_0007|GPUREG_0007]]<br />
| <br />
|<br />
|-<br />
| 0008<br />
| [[#GPUREG_0008|GPUREG_0008]]<br />
| <br />
|<br />
|-<br />
| 0009<br />
| [[#GPUREG_0009|GPUREG_0009]]<br />
| <br />
|<br />
|-<br />
| 000A<br />
| [[#GPUREG_000A|GPUREG_000A]]<br />
| <br />
|<br />
|-<br />
| 000B<br />
| [[#GPUREG_000B|GPUREG_000B]]<br />
| <br />
|<br />
|-<br />
| 000C<br />
| [[#GPUREG_000C|GPUREG_000C]]<br />
| <br />
|<br />
|-<br />
| 000D<br />
| [[#GPUREG_000D|GPUREG_000D]]<br />
| <br />
|<br />
|-<br />
| 000E<br />
| [[#GPUREG_000E|GPUREG_000E]]<br />
| <br />
|<br />
|-<br />
| 000F<br />
| [[#GPUREG_000F|GPUREG_000F]]<br />
| <br />
|<br />
|-<br />
| 0010<br />
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]<br />
| <br />
|PICA_REG_INTERRUPT<br />
|-<br />
| 0011<br />
| [[#GPUREG_0011|GPUREG_0011]]<br />
| <br />
|<br />
|-<br />
| 0012<br />
| [[#GPUREG_0012|GPUREG_0012]]<br />
| <br />
|<br />
|-<br />
| 0013<br />
| [[#GPUREG_0013|GPUREG_0013]]<br />
| <br />
|<br />
|-<br />
| 0014<br />
| [[#GPUREG_0014|GPUREG_0014]]<br />
| <br />
|<br />
|-<br />
| 0015<br />
| [[#GPUREG_0015|GPUREG_0015]]<br />
| <br />
|<br />
|-<br />
| 0016<br />
| [[#GPUREG_0016|GPUREG_0016]]<br />
| <br />
|<br />
|-<br />
| 0017<br />
| [[#GPUREG_0017|GPUREG_0017]]<br />
| <br />
|<br />
|-<br />
| 0018<br />
| [[#GPUREG_0018|GPUREG_0018]]<br />
| <br />
|<br />
|-<br />
| 0019<br />
| [[#GPUREG_0019|GPUREG_0019]]<br />
| <br />
|<br />
|-<br />
| 001A<br />
| [[#GPUREG_001A|GPUREG_001A]]<br />
| <br />
|<br />
|-<br />
| 001B<br />
| [[#GPUREG_001B|GPUREG_001B]]<br />
| <br />
|<br />
|-<br />
| 001C<br />
| [[#GPUREG_001C|GPUREG_001C]]<br />
| <br />
|<br />
|-<br />
| 001D<br />
| [[#GPUREG_001D|GPUREG_001D]]<br />
| <br />
|<br />
|-<br />
| 001E<br />
| [[#GPUREG_001E|GPUREG_001E]]<br />
| <br />
|<br />
|-<br />
| 001F<br />
| [[#GPUREG_001F|GPUREG_001F]]<br />
| <br />
|<br />
|-<br />
| 0020<br />
| [[#GPUREG_0020|GPUREG_0020]]<br />
| <br />
|<br />
|-<br />
| 0021<br />
| [[#GPUREG_0021|GPUREG_0021]]<br />
| <br />
|<br />
|-<br />
| 0022<br />
| [[#GPUREG_0022|GPUREG_0022]]<br />
| <br />
|<br />
|-<br />
| 0023<br />
| [[#GPUREG_0023|GPUREG_0023]]<br />
| <br />
|<br />
|-<br />
| 0024<br />
| [[#GPUREG_0024|GPUREG_0024]]<br />
| <br />
|<br />
|-<br />
| 0025<br />
| [[#GPUREG_0025|GPUREG_0025]]<br />
| <br />
|<br />
|-<br />
| 0026<br />
| [[#GPUREG_0026|GPUREG_0026]]<br />
| <br />
|<br />
|-<br />
| 0027<br />
| [[#GPUREG_0027|GPUREG_0027]]<br />
| <br />
|<br />
|-<br />
| 0028<br />
| [[#GPUREG_0028|GPUREG_0028]]<br />
| <br />
|<br />
|-<br />
| 0029<br />
| [[#GPUREG_0029|GPUREG_0029]]<br />
| <br />
|<br />
|-<br />
| 002A<br />
| [[#GPUREG_002A|GPUREG_002A]]<br />
| <br />
|<br />
|-<br />
| 002B<br />
| [[#GPUREG_002B|GPUREG_002B]]<br />
| <br />
|<br />
|-<br />
| 002C<br />
| [[#GPUREG_002C|GPUREG_002C]]<br />
| <br />
|<br />
|-<br />
| 002D<br />
| [[#GPUREG_002D|GPUREG_002D]]<br />
| <br />
|<br />
|-<br />
| 002E<br />
| [[#GPUREG_002E|GPUREG_002E]]<br />
| <br />
|<br />
|-<br />
| 002F<br />
| [[#GPUREG_002F|GPUREG_002F]]<br />
| <br />
|<br />
|-<br />
| 0030<br />
| [[#GPUREG_0030|GPUREG_0030]]<br />
| <br />
|<br />
|-<br />
| 0031<br />
| [[#GPUREG_0031|GPUREG_0031]]<br />
| <br />
|<br />
|-<br />
| 0032<br />
| [[#GPUREG_0032|GPUREG_0032]]<br />
| <br />
|<br />
|-<br />
| 0033<br />
| [[#GPUREG_0033|GPUREG_0033]]<br />
| <br />
|<br />
|-<br />
| 0034<br />
| [[#GPUREG_0034|GPUREG_0034]]<br />
| <br />
|<br />
|-<br />
| 0035<br />
| [[#GPUREG_0035|GPUREG_0035]]<br />
| <br />
|<br />
|-<br />
| 0036<br />
| [[#GPUREG_0036|GPUREG_0036]]<br />
| <br />
|<br />
|-<br />
| 0037<br />
| [[#GPUREG_0037|GPUREG_0037]]<br />
| <br />
|<br />
|-<br />
| 0038<br />
| [[#GPUREG_0038|GPUREG_0038]]<br />
| <br />
|<br />
|-<br />
| 0039<br />
| [[#GPUREG_0039|GPUREG_0039]]<br />
| <br />
|<br />
|-<br />
| 003A<br />
| [[#GPUREG_003A|GPUREG_003A]]<br />
| <br />
|<br />
|-<br />
| 003B<br />
| [[#GPUREG_003B|GPUREG_003B]]<br />
| <br />
|<br />
|-<br />
| 003C<br />
| [[#GPUREG_003C|GPUREG_003C]]<br />
| <br />
|<br />
|-<br />
| 003D<br />
| [[#GPUREG_003D|GPUREG_003D]]<br />
| <br />
|<br />
|-<br />
| 003E<br />
| [[#GPUREG_003E|GPUREG_003E]]<br />
| <br />
|<br />
|-<br />
| 003F<br />
| [[#GPUREG_003F|GPUREG_003F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Rasterizer registers (0x040-0x07F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0040<br />
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]<br />
| <br />
|PICA_REG_CULL_FACE<br />
|-<br />
| 0041<br />
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH1<br />
|-<br />
| 0042<br />
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH2<br />
|-<br />
| 0043<br />
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT1<br />
|-<br />
| 0044<br />
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT2<br />
|-<br />
| 0045<br />
| [[#GPUREG_0045|GPUREG_0045]]<br />
| <br />
|<br />
|-<br />
| 0046<br />
| [[#GPUREG_0046|GPUREG_0046]]<br />
| <br />
|<br />
|-<br />
| 0047<br />
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP<br />
|-<br />
| 0048<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]<br />
|? <br />
|PICA_REG_FRAGOP_CLIP_DATA1<br />
|-<br />
| 0049<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA2<br />
|-<br />
| 004A<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA3<br />
|-<br />
| 004B<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA4<br />
|-<br />
| 004C<br />
| [[#GPUREG_004C|GPUREG_004C]]<br />
| <br />
|<br />
|-<br />
| 004D<br />
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA1<br />
|-<br />
| 004E<br />
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA2<br />
|-<br />
| 004F<br />
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]<br />
| <br />
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0<br />
|-<br />
| 0050<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0<br />
|-<br />
| 0051<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1<br />
|-<br />
| 0052<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2<br />
|-<br />
| 0053<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3<br />
|-<br />
| 0054<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4<br />
|-<br />
| 0055<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5<br />
|-<br />
| 0056<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6<br />
|-<br />
| 0057<br />
| [[#GPUREG_0057|GPUREG_0057]]<br />
| <br />
|<br />
|-<br />
| 0058<br />
| [[#GPUREG_0058|GPUREG_0058]]<br />
| <br />
|<br />
|-<br />
| 0059<br />
| [[#GPUREG_0059|GPUREG_0059]]<br />
| <br />
|<br />
|-<br />
| 005A<br />
| [[#GPUREG_005A|GPUREG_005A]]<br />
| <br />
|<br />
|-<br />
| 005B<br />
| [[#GPUREG_005B|GPUREG_005B]]<br />
| <br />
|<br />
|-<br />
| 005C<br />
| [[#GPUREG_005C|GPUREG_005C]]<br />
| <br />
|<br />
|-<br />
| 005D<br />
| [[#GPUREG_005D|GPUREG_005D]]<br />
| <br />
|<br />
|-<br />
| 005E<br />
| [[#GPUREG_005E|GPUREG_005E]]<br />
| <br />
|<br />
|-<br />
| 005F<br />
| [[#GPUREG_005F|GPUREG_005F]]<br />
| <br />
|<br />
|-<br />
| 0060<br />
| [[#GPUREG_0060|GPUREG_0060]]<br />
| <br />
|<br />
|-<br />
| 0061<br />
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_FUNC<br />
|-<br />
| 0062<br />
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST1<br />
|-<br />
| 0063<br />
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]<br />
| <br />
|PICA_REG_EARLY_DEPTH_CLEAR<br />
|-<br />
| 0064<br />
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE<br />
|-<br />
| 0065<br />
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]<br />
| <br />
|PICA_REG_SCISSOR<br />
|-<br />
| 0066<br />
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]<br />
| <br />
|PICA_REG_SCISSOR_XY<br />
|-<br />
| 0067<br />
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]<br />
| <br />
|PICA_REG_SCISSOR_SIZE<br />
|-<br />
| 0068<br />
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]<br />
|<br />
|PICA_REG_VIEWPORT_XY<br />
|-<br />
| 0069<br />
| [[#GPUREG_0069|GPUREG_0069]]<br />
| <br />
|<br />
|-<br />
| 006A<br />
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]<br />
|<br />
|PICA_REG_EARLY_DEPTH_DATA<br />
|-<br />
| 006B<br />
| [[#GPUREG_006B|GPUREG_006B]]<br />
| <br />
|<br />
|-<br />
| 006C<br />
| [[#GPUREG_006C|GPUREG_006C]]<br />
| <br />
|<br />
|-<br />
| 006D<br />
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]<br />
|?<br />
|PICA_REG_FRAGOP_WSCALE<br />
|-<br />
| 006E<br />
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]<br />
|?<br />
|PICA_REG_RENDER_BUF_RESOLUTION1<br />
|-<br />
| 006F<br />
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK<br />
|-<br />
| 0070<br />
| [[#GPUREG_0070|GPUREG_0070]]<br />
| <br />
|<br />
|-<br />
| 0071<br />
| [[#GPUREG_0071|GPUREG_0071]]<br />
| <br />
|<br />
|-<br />
| 0072<br />
| [[#GPUREG_0072|GPUREG_0072]]<br />
| <br />
|<br />
|-<br />
| 0073<br />
| [[#GPUREG_0073|GPUREG_0073]]<br />
| <br />
|<br />
|-<br />
| 0074<br />
| [[#GPUREG_0074|GPUREG_0074]]<br />
| <br />
|<br />
|-<br />
| 0075<br />
| [[#GPUREG_0075|GPUREG_0075]]<br />
| <br />
|<br />
|-<br />
| 0076<br />
| [[#GPUREG_0076|GPUREG_0076]]<br />
| <br />
|<br />
|-<br />
| 0077<br />
| [[#GPUREG_0077|GPUREG_0077]]<br />
| <br />
|<br />
|-<br />
| 0078<br />
| [[#GPUREG_0078|GPUREG_0078]]<br />
| <br />
|<br />
|-<br />
| 0079<br />
| [[#GPUREG_0079|GPUREG_0079]]<br />
| <br />
|<br />
|-<br />
| 007A<br />
| [[#GPUREG_007A|GPUREG_007A]]<br />
| <br />
|<br />
|-<br />
| 007B<br />
| [[#GPUREG_007B|GPUREG_007B]]<br />
| <br />
|<br />
|-<br />
| 007C<br />
| [[#GPUREG_007C|GPUREG_007C]]<br />
| <br />
|<br />
|-<br />
| 007D<br />
| [[#GPUREG_007D|GPUREG_007D]]<br />
| <br />
|<br />
|-<br />
| 007E<br />
| [[#GPUREG_007E|GPUREG_007E]]<br />
| <br />
|<br />
|-<br />
| 007F<br />
| [[#GPUREG_007F|GPUREG_007F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Texturing registers (0x080-0x0FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0080<br />
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]<br />
|<br />
|PICA_REG_TEXTURE_FUNC<br />
|-<br />
| 0081<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE0_BORDER_COLOR<br />
|-<br />
| 0082<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]<br />
|<br />
|PICA_REG_TEXTURE0_SIZE<br />
|-<br />
| 0083<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE0_WRAP_FILTER<br />
|-<br />
| 0084<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE0_LOD<br />
|-<br />
| 0085<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR1<br />
|-<br />
| 0086<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR2<br />
|-<br />
| 0087<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR3<br />
|-<br />
| 0088<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR4<br />
|-<br />
| 0089<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR5<br />
|-<br />
| 008A<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR6<br />
|-<br />
| 008B<br />
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]<br />
|?<br />
|PICA_REG_TEXTURE0_SHADOW<br />
|-<br />
| 008C<br />
| [[#GPUREG_008C|GPUREG_008C]]<br />
|<br />
|<br />
|-<br />
| 008D<br />
| [[#GPUREG_008D|GPUREG_008D]]<br />
|<br />
|<br />
|-<br />
| 008E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]<br />
|?<br />
|PICA_REG_TEXTURE0_FORMAT<br />
|-<br />
| 008F<br />
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN0<br />
|-<br />
| 0090<br />
| [[#GPUREG_0090|GPUREG_0090]]<br />
| <br />
|<br />
|-<br />
| 0091<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE1_BORDER_COLOR<br />
|-<br />
| 0092<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]<br />
| <br />
|PICA_REG_TEXTURE1_SIZE<br />
|-<br />
| 0093<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE1_WRAP_FILTER<br />
|-<br />
| 0094<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE1_LOD<br />
|-<br />
| 0095<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]<br />
| <br />
|PICA_REG_TEXTURE1_ADDR<br />
|-<br />
| 0096<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE1_FORMAT<br />
|-<br />
| 0097<br />
| [[#GPUREG_0097|GPUREG_0097]]<br />
| <br />
|<br />
|-<br />
| 0098<br />
| [[#GPUREG_0098|GPUREG_0098]]<br />
| <br />
|<br />
|-<br />
| 0099<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE2_BORDER_COLOR<br />
|-<br />
| 009A<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]<br />
| <br />
|PICA_REG_TEXTURE2_SIZE<br />
|-<br />
| 009B<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE2_WRAP_FILTER<br />
|-<br />
| 009C<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE2_LOD<br />
|-<br />
| 009D<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]<br />
|<br />
|PICA_REG_TEXTURE2_ADDR<br />
|-<br />
| 009E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE2_FORMAT<br />
|-<br />
| 009F<br />
| [[#GPUREG_009F|GPUREG_009F]]<br />
| <br />
|<br />
|-<br />
| 00A0<br />
| [[#GPUREG_00A0|GPUREG_00A0]]<br />
| <br />
|<br />
|-<br />
| 00A1<br />
| [[#GPUREG_00A1|GPUREG_00A1]]<br />
| <br />
|<br />
|-<br />
| 00A2<br />
| [[#GPUREG_00A2|GPUREG_00A2]]<br />
| <br />
|<br />
|-<br />
| 00A3<br />
| [[#GPUREG_00A3|GPUREG_00A3]]<br />
| <br />
|<br />
|-<br />
| 00A4<br />
| [[#GPUREG_00A4|GPUREG_00A4]]<br />
| <br />
|<br />
|-<br />
| 00A5<br />
| [[#GPUREG_00A5|GPUREG_00A5]]<br />
| <br />
|<br />
|-<br />
| 00A6<br />
| [[#GPUREG_00A6|GPUREG_00A6]]<br />
| <br />
|<br />
|-<br />
| 00A7<br />
| [[#GPUREG_00A7|GPUREG_00A7]]<br />
| <br />
|<br />
|-<br />
| 00A8<br />
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX0<br />
|-<br />
| 00A9<br />
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX1<br />
|-<br />
| 00AA<br />
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]<br />
|? <br />
|PICA_REG_TEXTURE3_PROCTEX2<br />
|-<br />
| 00AB<br />
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX3<br />
|-<br />
| 00AC<br />
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX4<br />
|-<br />
| 00AD<br />
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX5<br />
|-<br />
| 00AE<br />
| [[#GPUREG_00AE|GPUREG_00AE]]<br />
| <br />
|<br />
|-<br />
| 00AF<br />
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]<br />
|?<br />
|PICA_REG_PROCTEX_LUT<br />
|-<br />
| 00B0<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA0<br />
|-<br />
| 00B1<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA1<br />
|-<br />
| 00B2<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA2<br />
|-<br />
| 00B3<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA3<br />
|-<br />
| 00B4<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA4<br />
|-<br />
| 00B5<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA5<br />
|-<br />
| 00B6<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA6<br />
|-<br />
| 00B7<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA7<br />
|-<br />
| 00B8<br />
| [[#GPUREG_00B8|GPUREG_00B8]]<br />
| <br />
|<br />
|-<br />
| 00B9<br />
| [[#GPUREG_00B9|GPUREG_00B9]]<br />
| <br />
|<br />
|-<br />
| 00BA<br />
| [[#GPUREG_00BA|GPUREG_00BA]]<br />
| <br />
|<br />
|-<br />
| 00BB<br />
| [[#GPUREG_00BB|GPUREG_00BB]]<br />
| <br />
|<br />
|-<br />
| 00BC<br />
| [[#GPUREG_00BC|GPUREG_00BC]]<br />
| <br />
|<br />
|-<br />
| 00BD<br />
| [[#GPUREG_00BD|GPUREG_00BD]]<br />
| <br />
|<br />
|-<br />
| 00BE<br />
| [[#GPUREG_00BE|GPUREG_00BE]]<br />
| <br />
|<br />
|-<br />
| 00BF<br />
| [[#GPUREG_00BF|GPUREG_00BF]]<br />
| <br />
|<br />
|-<br />
| 00C0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_0<br />
|-<br />
| 00C1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_0_OPERAND<br />
|-<br />
| 00C2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COMBINE<br />
|-<br />
| 00C3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COLOR<br />
|-<br />
| 00C4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_0_SCALE<br />
|-<br />
| 00C5<br />
| [[#GPUREG_00C5|GPUREG_00C5]]<br />
| <br />
|<br />
|-<br />
| 00C6<br />
| [[#GPUREG_00C6|GPUREG_00C6]]<br />
| <br />
|<br />
|-<br />
| 00C7<br />
| [[#GPUREG_00C7|GPUREG_00C7]]<br />
| <br />
|<br />
|-<br />
| 00C8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_1<br />
|-<br />
| 00C9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_1_OPERAND<br />
|-<br />
| 00CA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COMBINE<br />
|-<br />
| 00CB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COLOR<br />
|-<br />
| 00CC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_1_SCALE<br />
|-<br />
| 00CD<br />
| [[#GPUREG_00CD|GPUREG_00CD]]<br />
| <br />
|<br />
|-<br />
| 00CE<br />
| [[#GPUREG_00CE|GPUREG_00CE]]<br />
| <br />
|<br />
|-<br />
| 00CF<br />
| [[#GPUREG_00CF|GPUREG_00CF]]<br />
| <br />
|<br />
|-<br />
| 00D0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_2<br />
|-<br />
| 00D1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_2_OPERAND<br />
|-<br />
| 00D2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COMBINE<br />
|-<br />
| 00D3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COLOR<br />
|-<br />
| 00D4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_2_SCALE<br />
|-<br />
| 00D5<br />
| [[#GPUREG_00D5|GPUREG_00D5]]<br />
| <br />
|<br />
|-<br />
| 00D6<br />
| [[#GPUREG_00D6|GPUREG_00D6]]<br />
| <br />
|<br />
|-<br />
| 00D7<br />
| [[#GPUREG_00D7|GPUREG_00D7]]<br />
| <br />
|<br />
|-<br />
| 00D8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_3<br />
|-<br />
| 00D9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_3_OPERAND<br />
|-<br />
| 00DA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COMBINE<br />
|-<br />
| 00DB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COLOR<br />
|-<br />
| 00DC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_3_SCALE<br />
|-<br />
| 00DD<br />
| [[#GPUREG_00DD|GPUREG_00DD]]<br />
| <br />
|<br />
|-<br />
| 00DE<br />
| [[#GPUREG_00DE|GPUREG_00DE]]<br />
| <br />
|<br />
|-<br />
| 00DF<br />
| [[#GPUREG_00DF|GPUREG_00DF]]<br />
| <br />
|<br />
|-<br />
| 00E0<br />
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]<br />
|?<br />
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT<br />
|-<br />
| 00E1<br />
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]<br />
|?<br />
|PICA_REG_FOG_COLOR<br />
|-<br />
| 00E2<br />
| [[#GPUREG_00E2|GPUREG_00E2]]<br />
| <br />
|<br />
|-<br />
| 00E3<br />
| [[#GPUREG_00E3|GPUREG_00E3]]<br />
| <br />
|<br />
|-<br />
| 00E4<br />
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]<br />
|?<br />
|PICA_REG_GAS_ATTENUATION<br />
|-<br />
| 00E5<br />
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]<br />
|?<br />
|PICA_REG_GAS_ACCMAX<br />
|-<br />
| 00E6<br />
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FOG_LUT_INDEX<br />
|-<br />
| 00E7<br />
| [[#GPUREG_00E7|GPUREG_00E7]]<br />
| <br />
|<br />
|-<br />
| 00E8<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA0<br />
|-<br />
| 00E9<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]<br />
|? <br />
|PICA_REG_FOG_LUT_DATA1<br />
|-<br />
| 00EA<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA2<br />
|-<br />
| 00EB<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA3<br />
|-<br />
| 00EC<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA4<br />
|-<br />
| 00ED<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA5<br />
|-<br />
| 00EE<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA6<br />
|-<br />
| 00EF<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA7<br />
|-<br />
| 00F0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_4<br />
|-<br />
| 00F1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_4_OPERAND<br />
|-<br />
| 00F2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COMBINE<br />
|-<br />
| 00F3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COLOR<br />
|-<br />
| 00F4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_4_SCALE<br />
|-<br />
| 00F5<br />
| [[#GPUREG_00F5|GPUREG_00F5]]<br />
| <br />
|<br />
|-<br />
| 00F6<br />
| [[#GPUREG_00F6|GPUREG_00F6]]<br />
| <br />
|<br />
|-<br />
| 00F7<br />
| [[#GPUREG_00F7|GPUREG_00F7]]<br />
| <br />
|<br />
|-<br />
| 00F8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_5<br />
|-<br />
| 00F9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_5_OPERAND<br />
|-<br />
| 00FA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COMBINE<br />
|-<br />
| 00FB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COLOR<br />
|-<br />
| 00FC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_5_SCALE<br />
|-<br />
| 00FD<br />
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]<br />
|?<br />
|PICA_REG_TEX_ENV_BUF_COLOR<br />
|-<br />
| 00FE<br />
| [[#GPUREG_00FE|GPUREG_00FE]]<br />
| <br />
|<br />
|-<br />
| 00FF<br />
| [[#GPUREG_00FF|GPUREG_00FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Framebuffer registers (0x100-0x13F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0100<br />
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]<br />
|<br />
|PICA_REG_COLOR_OPERATION<br />
|-<br />
| 0101<br />
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]<br />
| <br />
|PICA_REG_BLEND_FUNC<br />
|-<br />
| 0102<br />
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]<br />
| <br />
|PICA_REG_LOGIC_OP<br />
|-<br />
| 0103<br />
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]<br />
| <br />
|PICA_REG_BLEND_COLOR<br />
|-<br />
| 0104<br />
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]<br />
| <br />
|PICA_REG_FRAGOP_ALPHA_TEST<br />
|-<br />
| 0105<br />
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]<br />
| <br />
|PICA_REG_STENCIL_TEST<br />
|-<br />
| 0106<br />
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]<br />
| <br />
|PICA_REG_STENCIL_OP<br />
|-<br />
| 0107<br />
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]<br />
| <br />
|PICA_REG_DEPTH_COLOR_MASK<br />
|-<br />
| 0108<br />
| [[#GPUREG_0108|GPUREG_0108]]<br />
| <br />
|<br />
|-<br />
| 0109<br />
| [[#GPUREG_0109|GPUREG_0109]]<br />
| <br />
|<br />
|-<br />
| 010A<br />
| [[#GPUREG_010A|GPUREG_010A]]<br />
| <br />
|<br />
|-<br />
| 010B<br />
| [[#GPUREG_010B|GPUREG_010B]]<br />
| <br />
|<br />
|-<br />
| 010C<br />
| [[#GPUREG_010C|GPUREG_010C]]<br />
| <br />
|<br />
|-<br />
| 010D<br />
| [[#GPUREG_010D|GPUREG_010D]]<br />
| <br />
|<br />
|-<br />
| 010E<br />
| [[#GPUREG_010E|GPUREG_010E]]<br />
| <br />
|<br />
|-<br />
| 010F<br />
| [[#GPUREG_010F|GPUREG_010F]]<br />
| <br />
|<br />
|-<br />
| 0110<br />
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR0<br />
|-<br />
| 0111<br />
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR1<br />
|-<br />
| 0112<br />
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_READ<br />
|-<br />
| 0113<br />
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_WRITE<br />
|-<br />
| 0114<br />
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_READ<br />
|-<br />
| 0115<br />
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_WRITE<br />
|-<br />
| 0116<br />
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_DEPTH_MODE<br />
|-<br />
| 0117<br />
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_MODE<br />
|-<br />
| 0118<br />
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST2<br />
|-<br />
| 0119<br />
| [[#GPUREG_0119|GPUREG_0119]]<br />
| <br />
|<br />
|-<br />
| 011A<br />
| [[#GPUREG_011A|GPUREG_011A]]<br />
| <br />
|<br />
|-<br />
| 011B<br />
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]<br />
|<br />
|PICA_REG_RENDER_BLOCK_FORMAT<br />
|-<br />
| 011C<br />
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]<br />
|<br />
|PICA_REG_RENDER_BUF_DEPTH_ADDR<br />
|-<br />
| 011D<br />
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_ADDR<br />
|-<br />
| 011E<br />
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]<br />
| <br />
|PICA_REG_RENDER_BUF_RESOLUTION0<br />
|-<br />
| 011F<br />
| [[#GPUREG_011F|GPUREG_011F]]<br />
| <br />
|<br />
|-<br />
| 0120<br />
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_XY<br />
|-<br />
| 0121<br />
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z<br />
|-<br />
| 0122<br />
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z_COLOR<br />
|-<br />
| 0123<br />
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]<br />
|?<br />
|PICA_REG_GAS_LUT_INDEX<br />
|-<br />
| 0124<br />
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]<br />
|?<br />
|PICA_REG_GAS_LUT_DATA<br />
|-<br />
| 0125<br />
| [[#GPUREG_0125|GPUREG_0125]]<br />
| <br />
|<br />
|-<br />
| 0126<br />
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]<br />
|?<br />
|PICA_REG_GAS_DELTAZ_DEPTH<br />
|-<br />
| 0127<br />
| [[#GPUREG_0127|GPUREG_0127]]<br />
| <br />
|<br />
|-<br />
| 0128<br />
| [[#GPUREG_0128|GPUREG_0128]]<br />
| <br />
|<br />
|-<br />
| 0129<br />
| [[#GPUREG_0129|GPUREG_0129]]<br />
| <br />
|<br />
|-<br />
| 012A<br />
| [[#GPUREG_012A|GPUREG_012A]]<br />
| <br />
|<br />
|-<br />
| 012B<br />
| [[#GPUREG_012B|GPUREG_012B]]<br />
| <br />
|<br />
|-<br />
| 012C<br />
| [[#GPUREG_012C|GPUREG_012C]]<br />
| <br />
|<br />
|-<br />
| 012D<br />
| [[#GPUREG_012D|GPUREG_012D]]<br />
| <br />
|<br />
|-<br />
| 012E<br />
| [[#GPUREG_012E|GPUREG_012E]]<br />
| <br />
|<br />
|-<br />
| 012F<br />
| [[#GPUREG_012F|GPUREG_012F]]<br />
| <br />
|<br />
|-<br />
| 0130<br />
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]<br />
|?<br />
|PICA_REG_FRAGOP_SHADOW<br />
|-<br />
| 0131<br />
| [[#GPUREG_0131|GPUREG_0131]]<br />
| <br />
|<br />
|-<br />
| 0132<br />
| [[#GPUREG_0132|GPUREG_0132]]<br />
| <br />
|<br />
|-<br />
| 0133<br />
| [[#GPUREG_0133|GPUREG_0133]]<br />
| <br />
|<br />
|-<br />
| 0134<br />
| [[#GPUREG_0134|GPUREG_0134]]<br />
| <br />
|<br />
|-<br />
| 0135<br />
| [[#GPUREG_0135|GPUREG_0135]]<br />
| <br />
|<br />
|-<br />
| 0136<br />
| [[#GPUREG_0136|GPUREG_0136]]<br />
| <br />
|<br />
|-<br />
| 0137<br />
| [[#GPUREG_0137|GPUREG_0137]]<br />
| <br />
|<br />
|-<br />
| 0138<br />
| [[#GPUREG_0138|GPUREG_0138]]<br />
| <br />
|<br />
|-<br />
| 0139<br />
| [[#GPUREG_0139|GPUREG_0139]]<br />
| <br />
|<br />
|-<br />
| 013A<br />
| [[#GPUREG_013A|GPUREG_013A]]<br />
| <br />
|<br />
|-<br />
| 013B<br />
| [[#GPUREG_013B|GPUREG_013B]]<br />
| <br />
|<br />
|-<br />
| 013C<br />
| [[#GPUREG_013C|GPUREG_013C]]<br />
| <br />
|<br />
|-<br />
| 013D<br />
| [[#GPUREG_013D|GPUREG_013D]]<br />
| <br />
|<br />
|-<br />
| 013E<br />
| [[#GPUREG_013E|GPUREG_013E]]<br />
| <br />
|<br />
|-<br />
| 013F<br />
| [[#GPUREG_013F|GPUREG_013F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Fragment lighting registers (0x140-0x1FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0140<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START<br />
|-<br />
| 0141<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR1<br />
|-<br />
| 0142<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIFFUSE<br />
|-<br />
| 0143<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_AMBIENT<br />
|-<br />
| 0144<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_XY<br />
|-<br />
| 0145<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_Z<br />
|-<br />
| 0146<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_XY<br />
|-<br />
| 0147<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_Z<br />
|-<br />
| 0148<br />
| [[#GPUREG_0148|GPUREG_0148]]<br />
| <br />
|<br />
|-<br />
| 0149<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]<br />
| <br />
|PICA_REG_FRAG_LIGHT0_TYPE<br />
|-<br />
| 014A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS<br />
|-<br />
| 014B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE<br />
|-<br />
| 014C<br />
| [[#GPUREG_014C|GPUREG_014C]]<br />
| <br />
|<br />
|-<br />
| 014D<br />
| [[#GPUREG_014D|GPUREG_014D]]<br />
| <br />
|<br />
|-<br />
| 014E<br />
| [[#GPUREG_014E|GPUREG_014E]]<br />
| <br />
|<br />
|-<br />
| 014F<br />
| [[#GPUREG_014F|GPUREG_014F]]<br />
| <br />
|<br />
|-<br />
| 0150<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR0<br />
|-<br />
| 0151<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR1<br />
|-<br />
| 0152<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIFFUSE<br />
|-<br />
| 0153<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_AMBIENT<br />
|-<br />
| 0154<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_XY<br />
|-<br />
| 0155<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_Z<br />
|-<br />
| 0156<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_XY<br />
|-<br />
| 0157<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_Z<br />
|-<br />
| 0158<br />
| [[#GPUREG_0158|GPUREG_0158]]<br />
| <br />
|<br />
|-<br />
| 0159<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_TYPE<br />
|-<br />
| 015A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS<br />
|-<br />
| 015B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE<br />
|-<br />
| 015C<br />
| [[#GPUREG_015C|GPUREG_015C]]<br />
| <br />
|<br />
|-<br />
| 015D<br />
| [[#GPUREG_015D|GPUREG_015D]]<br />
| <br />
|<br />
|-<br />
| 015E<br />
| [[#GPUREG_015E|GPUREG_015E]]<br />
| <br />
|<br />
|-<br />
| 015F<br />
| [[#GPUREG_015F|GPUREG_015F]]<br />
| <br />
|<br />
|-<br />
| 0160<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR0<br />
|-<br />
| 0161<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR1<br />
|-<br />
| 0162<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIFFUSE<br />
|-<br />
| 0163<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_AMBIENT<br />
|-<br />
| 0164<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_XY<br />
|-<br />
| 0165<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_Z<br />
|-<br />
| 0166<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_XY<br />
|-<br />
| 0167<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_Z<br />
|-<br />
| 0168<br />
| [[#GPUREG_0168|GPUREG_0168]]<br />
| <br />
|<br />
|-<br />
| 0169<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_TYPE<br />
|-<br />
| 016A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS<br />
|-<br />
| 016B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE<br />
|-<br />
| 016C<br />
| [[#GPUREG_016C|GPUREG_016C]]<br />
| <br />
|<br />
|-<br />
| 016D<br />
| [[#GPUREG_016D|GPUREG_016D]]<br />
| <br />
|<br />
|-<br />
| 016E<br />
| [[#GPUREG_016E|GPUREG_016E]]<br />
| <br />
|<br />
|-<br />
| 016F<br />
| [[#GPUREG_016F|GPUREG_016F]]<br />
| <br />
|<br />
|-<br />
| 0170<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR0<br />
|-<br />
| 0171<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR1<br />
|-<br />
| 0172<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIFFUSE<br />
|-<br />
| 0173<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_AMBIENT<br />
|-<br />
| 0174<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_XY<br />
|-<br />
| 0175<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_Z<br />
|-<br />
| 0176<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]<br />
|? <br />
|PICA_REG_FRAG_LIGHT3_SPOT_XY<br />
|-<br />
| 0177<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPOT_Z<br />
|-<br />
| 0178<br />
| [[#GPUREG_0178|GPUREG_0178]]<br />
| <br />
|<br />
|-<br />
| 0179<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_TYPE<br />
|-<br />
| 017A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS<br />
|-<br />
| 017B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE<br />
|-<br />
| 017C<br />
| [[#GPUREG_017C|GPUREG_017C]]<br />
| <br />
|<br />
|-<br />
| 017D<br />
| [[#GPUREG_017D|GPUREG_017D]]<br />
| <br />
|<br />
|-<br />
| 017E<br />
| [[#GPUREG_017E|GPUREG_017E]]<br />
| <br />
|<br />
|-<br />
| 017F<br />
| [[#GPUREG_017F|GPUREG_017F]]<br />
| <br />
|<br />
|-<br />
| 0180<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR0<br />
|-<br />
| 0181<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR1<br />
|-<br />
| 0182<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIFFUSE<br />
|-<br />
| 0183<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_AMBIENT<br />
|-<br />
| 0184<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_XY<br />
|-<br />
| 0185<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_Z<br />
|-<br />
| 0186<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_XY<br />
|-<br />
| 0187<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_Z<br />
|-<br />
| 0188<br />
| [[#GPUREG_0188|GPUREG_0188]]<br />
| <br />
|<br />
|-<br />
| 0189<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_TYPE<br />
|-<br />
| 018A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS<br />
|-<br />
| 018B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE<br />
|-<br />
| 018C<br />
| [[#GPUREG_018C|GPUREG_018C]]<br />
| <br />
|<br />
|-<br />
| 018D<br />
| [[#GPUREG_018D|GPUREG_018D]]<br />
| <br />
|<br />
|-<br />
| 018E<br />
| [[#GPUREG_018E|GPUREG_018E]]<br />
| <br />
|<br />
|-<br />
| 018F<br />
| [[#GPUREG_018F|GPUREG_018F]]<br />
| <br />
|<br />
|-<br />
| 0190<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR0<br />
|-<br />
| 0191<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR1<br />
|-<br />
| 0192<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_DIFFUSE<br />
|-<br />
| 0193<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_AMBIENT<br />
|-<br />
| 0194<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_XY<br />
|-<br />
| 0195<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_Z<br />
|-<br />
| 0196<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_XY<br />
|-<br />
| 0197<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_Z<br />
|-<br />
| 0198<br />
| [[#GPUREG_0198|GPUREG_0198]]<br />
| <br />
|<br />
|-<br />
| 0199<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_TYPE<br />
|-<br />
| 019A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS<br />
|-<br />
| 019B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE<br />
|-<br />
| 019C<br />
| [[#GPUREG_019C|GPUREG_019C]]<br />
| <br />
|<br />
|-<br />
| 019D<br />
| [[#GPUREG_019D|GPUREG_019D]]<br />
| <br />
|<br />
|-<br />
| 019E<br />
| [[#GPUREG_019E|GPUREG_019E]]<br />
| <br />
|<br />
|-<br />
| 019F<br />
| [[#GPUREG_019F|GPUREG_019F]]<br />
| <br />
|<br />
|-<br />
| 01A0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR0<br />
|-<br />
| 01A1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR1<br />
|-<br />
| 01A2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIFFUSE<br />
|-<br />
| 01A3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_AMBIENT<br />
|-<br />
| 01A4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_XY<br />
|-<br />
| 01A5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_Z<br />
|-<br />
| 01A6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_XY<br />
|-<br />
| 01A7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_Z<br />
|-<br />
| 01A8<br />
| [[#GPUREG_01A8|GPUREG_01A8]]<br />
| <br />
|<br />
|-<br />
| 01A9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_TYPE<br />
|-<br />
| 01AA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS<br />
|-<br />
| 01AB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE<br />
|-<br />
| 01AC<br />
| [[#GPUREG_01AC|GPUREG_01AC]]<br />
| <br />
|<br />
|-<br />
| 01AD<br />
| [[#GPUREG_01AD|GPUREG_01AD]]<br />
| <br />
|<br />
|-<br />
| 01AE<br />
| [[#GPUREG_01AE|GPUREG_01AE]]<br />
| <br />
|<br />
|-<br />
| 01AF<br />
| [[#GPUREG_01AF|GPUREG_01AF]]<br />
| <br />
|<br />
|-<br />
| 01B0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR0<br />
|-<br />
| 01B1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR1<br />
|-<br />
| 01B2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_DIFFUSE<br />
|-<br />
| 01B3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_AMBIENT<br />
|-<br />
| 01B4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_XY<br />
|-<br />
| 01B5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_Z<br />
|-<br />
| 01B6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_XY<br />
|-<br />
| 01B7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_Z<br />
|-<br />
| 01B8<br />
| [[#GPUREG_01B8|GPUREG_01B8]]<br />
| <br />
|<br />
|-<br />
| 01B9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_TYPE<br />
|-<br />
| 01BA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS<br />
|-<br />
| 01BB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE<br />
|-<br />
| 01BC<br />
| [[#GPUREG_01BC|GPUREG_01BC]]<br />
| <br />
|<br />
|-<br />
| 01BD<br />
| [[#GPUREG_01BD|GPUREG_01BD]]<br />
| <br />
|<br />
|-<br />
| 01BE<br />
| [[#GPUREG_01BE|GPUREG_01BE]]<br />
| <br />
|<br />
|-<br />
| 01BF<br />
| [[#GPUREG_01BF|GPUREG_01BF]]<br />
| <br />
|<br />
|-<br />
| 01C0<br />
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_AMBIENT<br />
|-<br />
| 01C1<br />
| [[#GPUREG_01C1|GPUREG_01C1]]<br />
| <br />
|<br />
|-<br />
| 01C2<br />
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_NUM<br />
|-<br />
| 01C3<br />
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE0<br />
|-<br />
| 01C4<br />
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE1<br />
|-<br />
| 01C5<br />
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT<br />
|-<br />
| 01C6<br />
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN1<br />
|-<br />
| 01C7<br />
| [[#GPUREG_01C7|GPUREG_01C7]]<br />
| <br />
|<br />
|-<br />
| 01C8<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA0<br />
|-<br />
| 01C9<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA1<br />
|-<br />
| 01CA<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA2<br />
|-<br />
| 01CB<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA3<br />
|-<br />
| 01CC<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA4<br />
|-<br />
| 01CD<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA5<br />
|-<br />
| 01CE<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA6<br />
|-<br />
| 01CF<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA7<br />
|-<br />
| 01D0<br />
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT<br />
|-<br />
| 01D1<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTINPUT<br />
|-<br />
| 01D2<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTSCALE<br />
|-<br />
| 01D3<br />
| [[#GPUREG_01D3|GPUREG_01D3]]<br />
| <br />
|<br />
|-<br />
| 01D4<br />
| [[#GPUREG_01D4|GPUREG_01D4]]<br />
| <br />
|<br />
|-<br />
| 01D5<br />
| [[#GPUREG_01D5|GPUREG_01D5]]<br />
| <br />
|<br />
|-<br />
| 01D6<br />
| [[#GPUREG_01D6|GPUREG_01D6]]<br />
| <br />
|<br />
|-<br />
| 01D7<br />
| [[#GPUREG_01D7|GPUREG_01D7]]<br />
| <br />
|<br />
|-<br />
| 01D8<br />
| [[#GPUREG_01D8|GPUREG_01D8]]<br />
| <br />
|<br />
|-<br />
| 01D9<br />
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_EN_ID<br />
|-<br />
| 01DA<br />
| [[#GPUREG_01DA|GPUREG_01DA]]<br />
| <br />
|<br />
|-<br />
| 01DB<br />
| [[#GPUREG_01DB|GPUREG_01DB]]<br />
| <br />
|<br />
|-<br />
| 01DC<br />
| [[#GPUREG_01DC|GPUREG_01DC]]<br />
| <br />
|<br />
|-<br />
| 01DD<br />
| [[#GPUREG_01DD|GPUREG_01DD]]<br />
| <br />
|<br />
|-<br />
| 01DE<br />
| [[#GPUREG_01DE|GPUREG_01DE]]<br />
| <br />
|<br />
|-<br />
| 01DF<br />
| [[#GPUREG_01DF|GPUREG_01DF]]<br />
| <br />
|<br />
|-<br />
| 01E0<br />
| [[#GPUREG_01E0|GPUREG_01E0]]<br />
| <br />
|<br />
|-<br />
| 01E1<br />
| [[#GPUREG_01E1|GPUREG_01E1]]<br />
| <br />
|<br />
|-<br />
| 01E2<br />
| [[#GPUREG_01E2|GPUREG_01E2]]<br />
| <br />
|<br />
|-<br />
| 01E3<br />
| [[#GPUREG_01E3|GPUREG_01E3]]<br />
| <br />
|<br />
|-<br />
| 01E4<br />
| [[#GPUREG_01E4|GPUREG_01E4]]<br />
| <br />
|<br />
|-<br />
| 01E5<br />
| [[#GPUREG_01E5|GPUREG_01E5]]<br />
| <br />
|<br />
|-<br />
| 01E6<br />
| [[#GPUREG_01E6|GPUREG_01E6]]<br />
| <br />
|<br />
|-<br />
| 01E7<br />
| [[#GPUREG_01E7|GPUREG_01E7]]<br />
| <br />
|<br />
|-<br />
| 01E8<br />
| [[#GPUREG_01E8|GPUREG_01E8]]<br />
| <br />
|<br />
|-<br />
| 01E9<br />
| [[#GPUREG_01E9|GPUREG_01E9]]<br />
| <br />
|<br />
|-<br />
| 01EA<br />
| [[#GPUREG_01EA|GPUREG_01EA]]<br />
| <br />
|<br />
|-<br />
| 01EB<br />
| [[#GPUREG_01EB|GPUREG_01EB]]<br />
| <br />
|<br />
|-<br />
| 01EC<br />
| [[#GPUREG_01EC|GPUREG_01EC]]<br />
| <br />
|<br />
|-<br />
| 01ED<br />
| [[#GPUREG_01ED|GPUREG_01ED]]<br />
| <br />
|<br />
|-<br />
| 01EE<br />
| [[#GPUREG_01EE|GPUREG_01EE]]<br />
| <br />
|<br />
|-<br />
| 01EF<br />
| [[#GPUREG_01EF|GPUREG_01EF]]<br />
| <br />
|<br />
|-<br />
| 01F0<br />
| [[#GPUREG_01F0|GPUREG_01F0]]<br />
| <br />
|<br />
|-<br />
| 01F1<br />
| [[#GPUREG_01F1|GPUREG_01F1]]<br />
| <br />
|<br />
|-<br />
| 01F2<br />
| [[#GPUREG_01F2|GPUREG_01F2]]<br />
| <br />
|<br />
|-<br />
| 01F3<br />
| [[#GPUREG_01F3|GPUREG_01F3]]<br />
| <br />
|<br />
|-<br />
| 01F4<br />
| [[#GPUREG_01F4|GPUREG_01F4]]<br />
| <br />
|<br />
|-<br />
| 01F5<br />
| [[#GPUREG_01F5|GPUREG_01F5]]<br />
| <br />
|<br />
|-<br />
| 01F6<br />
| [[#GPUREG_01F6|GPUREG_01F6]]<br />
| <br />
|<br />
|-<br />
| 01F7<br />
| [[#GPUREG_01F7|GPUREG_01F7]]<br />
| <br />
|<br />
|-<br />
| 01F8<br />
| [[#GPUREG_01F8|GPUREG_01F8]]<br />
| <br />
|<br />
|-<br />
| 01F9<br />
| [[#GPUREG_01F9|GPUREG_01F9]]<br />
| <br />
|<br />
|-<br />
| 01FA<br />
| [[#GPUREG_01FA|GPUREG_01FA]]<br />
| <br />
|<br />
|-<br />
| 01FB<br />
| [[#GPUREG_01FB|GPUREG_01FB]]<br />
| <br />
|<br />
|-<br />
| 01FC<br />
| [[#GPUREG_01FC|GPUREG_01FC]]<br />
| <br />
|<br />
|-<br />
| 01FD<br />
| [[#GPUREG_01FD|GPUREG_01FD]]<br />
| <br />
|<br />
|-<br />
| 01FE<br />
| [[#GPUREG_01FE|GPUREG_01FE]]<br />
| <br />
|<br />
|-<br />
| 01FF<br />
| [[#GPUREG_01FF|GPUREG_01FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Geometry pipeline registers (0x200-0x27F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0200<br />
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR<br />
|-<br />
| 0201<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS0<br />
|-<br />
| 0202<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS1<br />
|-<br />
| 0203<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET<br />
|-<br />
| 0204<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT0<br />
|-<br />
| 0205<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT1<br />
|-<br />
| 0206<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0207<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0208<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0209<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020B<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020C<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020E<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020F<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0210<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0211<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0212<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0213<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0214<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0215<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0216<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0217<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0218<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0219<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021B<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021C<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021E<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021F<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0220<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0221<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0222<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0223<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0224<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0225<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0226<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0227<br />
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET<br />
|-<br />
| 0228<br />
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]<br />
| <br />
|PICA_REG_DRAW_VERTEX_NUM<br />
|-<br />
| 0229<br />
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]<br />
| ?<br />
|PICA_REG_DRAW_MODE0<br />
|-<br />
| 022A<br />
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]<br />
|<br />
|PICA_REG_DRAW_VERTEX_OFFSET<br />
|-<br />
| 022B<br />
| [[#GPUREG_022B|GPUREG_022B]]<br />
| <br />
|<br />
|-<br />
| 022C<br />
| [[#GPUREG_022C|GPUREG_022C]]<br />
| <br />
|<br />
|-<br />
| 022D<br />
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]<br />
| <br />
|PICA_REG_POST_VERTEX_CACHE_NUM<br />
|-<br />
| 022E<br />
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]<br />
|<br />
|PICA_REG_START_DRAW_ARRAY<br />
|-<br />
| 022F<br />
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]<br />
|<br />
|PICA_REG_START_DRAW_ELEMENT<br />
|-<br />
| 0230<br />
| [[#GPUREG_0230|GPUREG_0230]]<br />
| <br />
|<br />
|-<br />
| 0231<br />
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]<br />
|?<br />
|PICA_REG_VTX_FUNC<br />
|-<br />
| 0232<br />
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR<br />
|-<br />
| 0233<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA0<br />
|-<br />
| 0234<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA1<br />
|-<br />
| 0235<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA2<br />
|-<br />
| 0236<br />
| [[#GPUREG_0236|GPUREG_0236]]<br />
| <br />
|<br />
|-<br />
| 0237<br />
| [[#GPUREG_0237|GPUREG_0237]]<br />
| <br />
|<br />
|-<br />
| 0238<br />
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH0<br />
|-<br />
| 0239<br />
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH1<br />
|-<br />
| 023A<br />
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH0<br />
|-<br />
| 023B<br />
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH1<br />
|-<br />
| 023C<br />
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH0<br />
|-<br />
| 023D<br />
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH1<br />
|-<br />
| 023E<br />
| [[#GPUREG_023E|GPUREG_023E]]<br />
| <br />
|<br />
|-<br />
| 023F<br />
| [[#GPUREG_023F|GPUREG_023F]]<br />
| <br />
|<br />
|-<br />
| 0240<br />
| [[#GPUREG_0240|GPUREG_0240]]<br />
| <br />
|<br />
|-<br />
| 0241<br />
| [[#GPUREG_0241|GPUREG_0241]]<br />
| <br />
|<br />
|-<br />
| 0242<br />
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]<br />
|?<br />
|PICA_REG_VS_ATTR_NUM1<br />
|-<br />
| 0243<br />
| [[#GPUREG_0243|GPUREG_0243]]<br />
| <br />
|<br />
|-<br />
| 0244<br />
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]<br />
|?<br />
|PICA_REG_VS_COM_MODE<br />
|-<br />
| 0245<br />
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC0<br />
|-<br />
| 0246<br />
| [[#GPUREG_0246|GPUREG_0246]]<br />
| <br />
|<br />
|-<br />
| 0247<br />
| [[#GPUREG_0247|GPUREG_0247]]<br />
| <br />
|<br />
|-<br />
| 0248<br />
| [[#GPUREG_0248|GPUREG_0248]]<br />
| <br />
|<br />
|-<br />
| 0249<br />
| [[#GPUREG_0249|GPUREG_0249]]<br />
| <br />
|<br />
|-<br />
| 024A<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM1<br />
|-<br />
| 024B<br />
| [[#GPUREG_024B|GPUREG_024B]]<br />
|<br />
|<br />
|-<br />
| 024C<br />
| [[#GPUREG_024C|GPUREG_024C]]<br />
| <br />
|<br />
|-<br />
| 024D<br />
| [[#GPUREG_024D|GPUREG_024D]]<br />
| <br />
|<br />
|-<br />
| 024E<br />
| [[#GPUREG_024E|GPUREG_024E]]<br />
| <br />
|<br />
|-<br />
| 024F<br />
| [[#GPUREG_024F|GPUREG_024F]]<br />
| <br />
|<br />
|-<br />
| 0250<br />
| [[#GPUREG_0250|GPUREG_0250]]<br />
| <br />
|<br />
|-<br />
| 0251<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM2<br />
|-<br />
| 0252<br />
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]<br />
|?<br />
|PICA_REG_GS_MISC_REG0<br />
|-<br />
| 0253<br />
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]<br />
|?<br />
|PICA_REG_DRAW_MODE1<br />
|-<br />
| 0254<br />
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]<br />
|?<br />
|PICA_REG_GS_MISC_REG1<br />
|-<br />
| 0255<br />
| [[#GPUREG_0255|GPUREG_0255]]<br />
| <br />
|<br />
|-<br />
| 0256<br />
| [[#GPUREG_0256|GPUREG_0256]]<br />
| <br />
|<br />
|-<br />
| 0257<br />
| [[#GPUREG_0257|GPUREG_0257]]<br />
| <br />
|<br />
|-<br />
| 0258<br />
| [[#GPUREG_0258|GPUREG_0258]]<br />
| <br />
|<br />
|-<br />
| 0259<br />
| [[#GPUREG_0259|GPUREG_0259]]<br />
| <br />
|<br />
|-<br />
| 025A<br />
| [[#GPUREG_025A|GPUREG_025A]]<br />
| <br />
|<br />
|-<br />
| 025B<br />
| [[#GPUREG_025B|GPUREG_025B]]<br />
| <br />
|<br />
|-<br />
| 025C<br />
| [[#GPUREG_025C|GPUREG_025C]]<br />
| <br />
|<br />
|-<br />
| 025D<br />
| [[#GPUREG_025D|GPUREG_025D]]<br />
| <br />
|<br />
|-<br />
| 025E<br />
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]<br />
| ?<br />
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3<br />
|-<br />
| 025F<br />
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC1<br />
|-<br />
| 0260<br />
| [[#GPUREG_0260|GPUREG_0260]]<br />
| <br />
|<br />
|-<br />
| 0261<br />
| [[#GPUREG_0261|GPUREG_0261]]<br />
| <br />
|<br />
|-<br />
| 0262<br />
| [[#GPUREG_0262|GPUREG_0262]]<br />
| <br />
|<br />
|-<br />
| 0263<br />
| [[#GPUREG_0263|GPUREG_0263]]<br />
| <br />
|<br />
|-<br />
| 0264<br />
| [[#GPUREG_0264|GPUREG_0264]]<br />
| <br />
|<br />
|-<br />
| 0265<br />
| [[#GPUREG_0265|GPUREG_0265]]<br />
| <br />
|<br />
|-<br />
| 0266<br />
| [[#GPUREG_0266|GPUREG_0266]]<br />
| <br />
|<br />
|-<br />
| 0267<br />
| [[#GPUREG_0267|GPUREG_0267]]<br />
| <br />
|<br />
|-<br />
| 0268<br />
| [[#GPUREG_0268|GPUREG_0268]]<br />
| <br />
|<br />
|-<br />
| 0269<br />
| [[#GPUREG_0269|GPUREG_0269]]<br />
| <br />
|<br />
|-<br />
| 026A<br />
| [[#GPUREG_026A|GPUREG_026A]]<br />
| <br />
|<br />
|-<br />
| 026B<br />
| [[#GPUREG_026B|GPUREG_026B]]<br />
| <br />
|<br />
|-<br />
| 026C<br />
| [[#GPUREG_026C|GPUREG_026C]]<br />
| <br />
|<br />
|-<br />
| 026D<br />
| [[#GPUREG_026D|GPUREG_026D]]<br />
| <br />
|<br />
|-<br />
| 026E<br />
| [[#GPUREG_026E|GPUREG_026E]]<br />
| <br />
|<br />
|-<br />
| 026F<br />
| [[#GPUREG_026F|GPUREG_026F]]<br />
| <br />
|<br />
|-<br />
| 0270<br />
| [[#GPUREG_0270|GPUREG_0270]]<br />
| <br />
|<br />
|-<br />
| 0271<br />
| [[#GPUREG_0271|GPUREG_0271]]<br />
| <br />
|<br />
|-<br />
| 0272<br />
| [[#GPUREG_0272|GPUREG_0272]]<br />
| <br />
|<br />
|-<br />
| 0273<br />
| [[#GPUREG_0273|GPUREG_0273]]<br />
| <br />
|<br />
|-<br />
| 0274<br />
| [[#GPUREG_0274|GPUREG_0274]]<br />
| <br />
|<br />
|-<br />
| 0275<br />
| [[#GPUREG_0275|GPUREG_0275]]<br />
| <br />
|<br />
|-<br />
| 0276<br />
| [[#GPUREG_0276|GPUREG_0276]]<br />
| <br />
|<br />
|-<br />
| 0277<br />
| [[#GPUREG_0277|GPUREG_0277]]<br />
| <br />
|<br />
|-<br />
| 0278<br />
| [[#GPUREG_0278|GPUREG_0278]]<br />
| <br />
|<br />
|-<br />
| 0279<br />
| [[#GPUREG_0279|GPUREG_0279]]<br />
| <br />
|<br />
|-<br />
| 027A<br />
| [[#GPUREG_027A|GPUREG_027A]]<br />
| <br />
|<br />
|-<br />
| 027B<br />
| [[#GPUREG_027B|GPUREG_027B]]<br />
| <br />
|<br />
|-<br />
| 027C<br />
| [[#GPUREG_027C|GPUREG_027C]]<br />
| <br />
|<br />
|-<br />
| 027D<br />
| [[#GPUREG_027D|GPUREG_027D]]<br />
| <br />
|<br />
|-<br />
| 027E<br />
| [[#GPUREG_027E|GPUREG_027E]]<br />
| <br />
|<br />
|-<br />
| 027F<br />
| [[#GPUREG_027F|GPUREG_027F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Shader registers (0x280-0x2DF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
! colspan=4 | Geometry shader<br />
|-<br />
| 0280<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_GS_BOOL<br />
|-<br />
| 0281<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_GS_INT0<br />
|-<br />
| 0282<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_GS_INT1<br />
|-<br />
| 0283<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_GS_INT2<br />
|-<br />
| 0284<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_GS_INT3<br />
|-<br />
| 0285<br />
| [[#GPUREG_0285|GPUREG_0285]]<br />
| <br />
|<br />
|-<br />
| 0286<br />
| [[#GPUREG_0286|GPUREG_0286]]<br />
| <br />
|<br />
|-<br />
| 0287<br />
| [[#GPUREG_0287|GPUREG_0287]]<br />
| <br />
|<br />
|-<br />
| 0288<br />
| [[#GPUREG_0288|GPUREG_0288]]<br />
| <br />
|<br />
|-<br />
| 0289<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_GS_ATTR_NUM<br />
|-<br />
| 028A<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_GS_START_ADDR<br />
|-<br />
| 028B<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP0<br />
|-<br />
| 028C<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP1<br />
|-<br />
| 028D<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_GS_OUT_REG_MASK<br />
|-<br />
| 028E<br />
| [[#GPUREG_028E|GPUREG_028E]]<br />
| <br />
|<br />
|-<br />
| 028F<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_GS_PROG_RENEWAL_END<br />
|-<br />
| 0290<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_GS_FLOAT_ADDR<br />
|-<br />
| 0291<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA0<br />
|-<br />
| 0292<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA1<br />
|-<br />
| 0293<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA2<br />
|-<br />
| 0294<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA3<br />
|-<br />
| 0295<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA4<br />
|-<br />
| 0296<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA5<br />
|-<br />
| 0297<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA6<br />
|-<br />
| 0298<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA7<br />
|-<br />
| 0299<br />
| [[#GPUREG_0299|GPUREG_0299]]<br />
| <br />
|<br />
|-<br />
| 029A<br />
| [[#GPUREG_029A|GPUREG_029A]]<br />
| <br />
|<br />
|-<br />
| 029B<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_GS_PROG_ADDR<br />
|-<br />
| 029C<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_DATA0<br />
|-<br />
| 029D<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_DATA1<br />
|-<br />
| 029E<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_DATA2<br />
|-<br />
| 029F<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_DATA3<br />
|-<br />
| 02A0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_DATA4<br />
|-<br />
| 02A1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_DATA5<br />
|-<br />
| 02A2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_DATA6<br />
|-<br />
| 02A3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_DATA7<br />
|-<br />
| 02A4<br />
| [[#GPUREG_02A4|GPUREG_02A4]]<br />
| <br />
|<br />
|-<br />
| 02A5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02A6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02A7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02A8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02A9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02AA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02AB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02AC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02AD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02AE<br />
| [[#GPUREG_02AE|GPUREG_02AE]]<br />
| <br />
|<br />
|-<br />
| 02AF<br />
| [[#GPUREG_02AF|GPUREG_02AF]]<br />
| <br />
|<br />
|-<br />
! colspan=4 | Vertex shader<br />
|-<br />
| 02B0<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_VS_BOOL<br />
|-<br />
| 02B1<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_VS_INT0<br />
|-<br />
| 02B2<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_VS_INT1<br />
|-<br />
| 02B3<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_VS_INT2<br />
|-<br />
| 02B4<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_VS_INT3<br />
|-<br />
| 02B5<br />
| [[#GPUREG_02B5|GPUREG_02B5]]<br />
| <br />
|<br />
|-<br />
| 02B6<br />
| [[#GPUREG_02B6|GPUREG_02B6]]<br />
| <br />
|<br />
|-<br />
| 02B7<br />
| [[#GPUREG_02B7|GPUREG_02B7]]<br />
| <br />
|<br />
|-<br />
| 02B8<br />
| [[#GPUREG_02B8|GPUREG_02B8]]<br />
| <br />
|<br />
|-<br />
| 02B9<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_VS_ATTR_NUM0<br />
|-<br />
| 02BA<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_VS_START_ADDR<br />
|-<br />
| 02BB<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP0<br />
|-<br />
| 02BC<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP1<br />
|-<br />
| 02BD<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_VS_OUT_REG_MASK<br />
|-<br />
| 02BE<br />
| [[#GPUREG_02BE|GPUREG_02BE]]<br />
| <br />
|<br />
|-<br />
| 02BF<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_VS_PROG_RENEWAL_END<br />
|-<br />
| 02C0<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_VS_FLOAT_ADDR<br />
|-<br />
| 02C1<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA0<br />
|-<br />
| 02C2<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA1<br />
|-<br />
| 02C3<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA2<br />
|-<br />
| 02C4<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA3<br />
|-<br />
| 02C5<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA4<br />
|-<br />
| 02C6<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA5<br />
|-<br />
| 02C7<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA6<br />
|-<br />
| 02C8<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA7<br />
|-<br />
| 02C9<br />
| [[#GPUREG_02C9|GPUREG_02C9]]<br />
| <br />
|<br />
|-<br />
| 02CA<br />
| [[#GPUREG_02CA|GPUREG_02CA]]<br />
| <br />
|<br />
|-<br />
| 02CB<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_ADDR<br />
|-<br />
| 02CC<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_DATA0<br />
|-<br />
| 02CD<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_DATA1<br />
|-<br />
| 02CE<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_DATA2<br />
|-<br />
| 02CF<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_DATA3<br />
|-<br />
| 02D0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_DATA4<br />
|-<br />
| 02D1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_DATA5<br />
|-<br />
| 02D2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_DATA6<br />
|-<br />
| 02D3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_DATA7<br />
|-<br />
| 02D4<br />
| [[#GPUREG_02D4|GPUREG_02D4]]<br />
| <br />
|<br />
|-<br />
| 02D5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02D6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02D7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02D8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02D9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02DA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02DB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02DC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02DD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02DE<br />
| [[#GPUREG_02DE|GPUREG_02DE]]<br />
| <br />
|<br />
|-<br />
| 02DF<br />
| [[#GPUREG_02DF|GPUREG_02DF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Unknown registers (0x2E0-0x2FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 02E0<br />
| [[#GPUREG_02E0|GPUREG_02E0]]<br />
| <br />
|<br />
|-<br />
| 02E1<br />
| [[#GPUREG_02E1|GPUREG_02E1]]<br />
| <br />
|<br />
|-<br />
| 02E2<br />
| [[#GPUREG_02E2|GPUREG_02E2]]<br />
| <br />
|<br />
|-<br />
| 02E3<br />
| [[#GPUREG_02E3|GPUREG_02E3]]<br />
| <br />
|<br />
|-<br />
| 02E4<br />
| [[#GPUREG_02E4|GPUREG_02E4]]<br />
| <br />
|<br />
|-<br />
| 02E5<br />
| [[#GPUREG_02E5|GPUREG_02E5]]<br />
| <br />
|<br />
|-<br />
| 02E6<br />
| [[#GPUREG_02E6|GPUREG_02E6]]<br />
| <br />
|<br />
|-<br />
| 02E7<br />
| [[#GPUREG_02E7|GPUREG_02E7]]<br />
| <br />
|<br />
|-<br />
| 02E8<br />
| [[#GPUREG_02E8|GPUREG_02E8]]<br />
| <br />
|<br />
|-<br />
| 02E9<br />
| [[#GPUREG_02E9|GPUREG_02E9]]<br />
| <br />
|<br />
|-<br />
| 02EA<br />
| [[#GPUREG_02EA|GPUREG_02EA]]<br />
| <br />
|<br />
|-<br />
| 02EB<br />
| [[#GPUREG_02EB|GPUREG_02EB]]<br />
| <br />
|<br />
|-<br />
| 02EC<br />
| [[#GPUREG_02EC|GPUREG_02EC]]<br />
| <br />
|<br />
|-<br />
| 02ED<br />
| [[#GPUREG_02ED|GPUREG_02ED]]<br />
| <br />
|<br />
|-<br />
| 02EE<br />
| [[#GPUREG_02EE|GPUREG_02EE]]<br />
| <br />
|<br />
|-<br />
| 02EF<br />
| [[#GPUREG_02EF|GPUREG_02EF]]<br />
| <br />
|<br />
|-<br />
| 02F0<br />
| [[#GPUREG_02F0|GPUREG_02F0]]<br />
| <br />
|<br />
|-<br />
| 02F1<br />
| [[#GPUREG_02F1|GPUREG_02F1]]<br />
| <br />
|<br />
|-<br />
| 02F2<br />
| [[#GPUREG_02F2|GPUREG_02F2]]<br />
| <br />
|<br />
|-<br />
| 02F3<br />
| [[#GPUREG_02F3|GPUREG_02F3]]<br />
| <br />
|<br />
|-<br />
| 02F4<br />
| [[#GPUREG_02F4|GPUREG_02F4]]<br />
| <br />
|<br />
|-<br />
| 02F5<br />
| [[#GPUREG_02F5|GPUREG_02F5]]<br />
| <br />
|<br />
|-<br />
| 02F6<br />
| [[#GPUREG_02F6|GPUREG_02F6]]<br />
| <br />
|<br />
|-<br />
| 02F7<br />
| [[#GPUREG_02F7|GPUREG_02F7]]<br />
| <br />
|<br />
|-<br />
| 02F8<br />
| [[#GPUREG_02F8|GPUREG_02F8]]<br />
| <br />
|<br />
|-<br />
| 02F9<br />
| [[#GPUREG_02F9|GPUREG_02F9]]<br />
| <br />
|<br />
|-<br />
| 02FA<br />
| [[#GPUREG_02FA|GPUREG_02FA]]<br />
| <br />
|<br />
|-<br />
| 02FB<br />
| [[#GPUREG_02FB|GPUREG_02FB]]<br />
| <br />
|<br />
|-<br />
| 02FC<br />
| [[#GPUREG_02FC|GPUREG_02FC]]<br />
| <br />
|<br />
|-<br />
| 02FD<br />
| [[#GPUREG_02FD|GPUREG_02FD]]<br />
| <br />
|<br />
|-<br />
| 02FE<br />
| [[#GPUREG_02FE|GPUREG_02FE]]<br />
| <br />
|<br />
|-<br />
| 02FF<br />
| [[#GPUREG_02FF|GPUREG_02FF]]<br />
| <br />
|<br />
|}<br />
<br />
== Miscellaneous registers ==<br />
<br />
=== GPUREG_FINALIZE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)<br />
|}<br />
<br />
Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.<br />
Failure to write to this register in any command buffer will result in the GPU hanging.<br />
<br />
== Rasterizer registers ==<br />
<br />
=== GPUREG_FACECULLING_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Culling mode<br />
|}<br />
<br />
This register is used to configure the face culling mode.<br />
<br />
Culling mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Front Face (Counter Clockwise)<br />
|-<br />
| 2<br />
| Back Face (Counter Clockwise)<br />
|}<br />
<br />
=== GPUREG_VIEWPORT_WIDTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, width / 2<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.<br />
<br />
=== GPUREG_VIEWPORT_INVW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / width<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.<br />
<br />
=== GPUREG_VIEWPORT_HEIGHT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, height / 2<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.<br />
<br />
=== GPUREG_VIEWPORT_INVH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / height<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.<br />
<br />
=== GPUREG_FRAGOP_CLIP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable clipping planes.<br />
<br />
=== GPUREG_FRAGOP_CLIP_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Clipping plane coefficient ''i''<br />
|}<br />
<br />
This register is used to configure clipping plane coefficients.<br />
<br />
=== GPUREG_DEPTHMAP_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near - Far<br />
|}<br />
<br />
This register is used to configure the depth range scale.<br />
<br />
=== GPUREG_DEPTHMAP_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near + Polygon Offset<br />
|}<br />
<br />
This register is used to configure the depth range bias.<br />
<br />
=== GPUREG_SH_OUTMAP_TOTAL ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of following attributes<br />
|}<br />
<br />
This register is used to configure the total shader output map attributes.<br />
<br />
=== GPUREG_SH_OUTMAP_O''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Semantic for the x component of the register.<br />
|-<br />
| 8-12<br />
| unsigned, Semantic for the y component of the register.<br />
|-<br />
| 16-20<br />
| unsigned, Semantic for the z component of the register.<br />
|-<br />
| 24-28<br />
| unsigned, Semantic for the w component of the register.<br />
|}<br />
<br />
These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.<br />
<br />
Semantic values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Semantic<br />
! Description<br />
|-<br />
| 0x00<br />
| position.x<br />
| rowspan="4" | Vertex Position<br />
|-<br />
| 0x01<br />
| position.y<br />
|-<br />
| 0x02<br />
| position.z<br />
|-<br />
| 0x03<br />
| position.w<br />
|-<br />
| 0x04<br />
| normquat.x<br />
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)<br />
|-<br />
| 0x05<br />
| normquat.y<br />
|-<br />
| 0x06<br />
| normquat.z<br />
|-<br />
| 0x07<br />
| normquat.w<br />
|-<br />
| 0x08<br />
| color.r<br />
| rowspan="4" | Vertex color<br />
|-<br />
| 0x09<br />
| color.g<br />
|-<br />
| 0x0A<br />
| color.b<br />
|-<br />
| 0x0B<br />
| color.a<br />
|-<br />
| 0x0C<br />
| texcoord0.u<br />
| rowspan="2" | Texture coordinates for texture 0<br />
|-<br />
| 0x0D<br />
| texcoord0.v<br />
|-<br />
| 0x0E<br />
| texcoord1.u<br />
| rowspan="2" | Texture coordinates for texture 1<br />
|-<br />
| 0x0F<br />
| texcoord1.v<br />
|-<br />
| 0x10<br />
| texcoord0.w<br />
|<br />
<br />
|-<br />
| 0x12<br />
| view.x<br />
| rowspan="3" | View vector (for fragment lighting)<br />
|-<br />
| 0x13<br />
| view.y<br />
|-<br />
| 0x14<br />
| view.z<br />
<br />
|-<br />
| 0x16<br />
| texcoord2.u<br />
| rowspan="2" | Texture coordinates for texture 2<br />
|-<br />
| 0x17<br />
| texcoord2.v<br />
<br />
|-<br />
| 0x1F<br />
| Unused component<br />
| Should be set for unused components of the output register<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Early depth function<br />
|}<br />
<br />
This register configures the early depth test function.<br />
<br />
Early depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| >=<br />
|-<br />
| 1<br />
| ><br />
|-<br />
| 2<br />
| <=<br />
|-<br />
| 3<br />
| <<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether the early depth test is enabled.<br />
<br />
=== GPUREG_EARLYDEPTH_CLEAR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = clear)<br />
|}<br />
<br />
This register triggers clearing the early depth data.<br />
<br />
=== GPUREG_SH_OUTATTR_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Use texture coordinates (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register is used to configure the shader output attribute mode.<br />
<br />
=== GPUREG_SCISSORTEST_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Enabled (0 = disabled, 3 = enabled)<br />
|}<br />
<br />
This register is used to enable scissor testing.<br />
<br />
=== GPUREG_SCISSORTEST_POS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X1<br />
|-<br />
| 16-25<br />
| unsigned, Y1<br />
|}<br />
<br />
This register is used to configure the scissor test start position.<br />
<br />
=== GPUREG_SCISSORTEST_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X2<br />
|-<br />
| 16-25<br />
| unsigned, Y2<br />
|}<br />
<br />
This register is used to configure the scissor test end position.<br />
<br />
=== GPUREG_VIEWPORT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| signed, X<br />
|-<br />
| 16-25<br />
| signed, Y<br />
|}<br />
<br />
This register is used to configure the viewport position.<br />
<br />
=== GPUREG_EARLYDEPTH_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| unsigned, Clear value<br />
|}<br />
<br />
This register is used to configure the early depth clear value.<br />
<br />
=== GPUREG_DEPTHMAP_ENABLE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable depth range.<br />
<br />
=== GPUREG_RENDERBUF_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register is used to configure the output framebuffer dimensions.<br />
<br />
=== GPUREG_SH_OUTATTR_CLOCK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, 'position.z' present (0 = absent, 1 = present)<br />
|-<br />
| 1<br />
| unsigned, 'color' component present (0 = absent, 1 = present)<br />
|-<br />
| 8<br />
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)<br />
|-<br />
| 9<br />
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)<br />
|-<br />
| 10<br />
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)<br />
|-<br />
| 16<br />
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)<br />
|-<br />
| 24<br />
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)<br />
|}<br />
<br />
This register controls the clock supply to parts relating to certain attributes.<br />
<br />
== Texturing registers ==<br />
<br />
=== GPUREG_TEXUNIT_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| 0x0<br />
|-<br />
| 8-9<br />
| unsigned, Texture 3 coordinates<br />
|-<br />
| 10<br />
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| 0x1<br />
|-<br />
| 13<br />
| unsigned, Texture 2 coordinates<br />
|-<br />
| 16<br />
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)<br />
|-<br />
| 17-31<br />
| 0x0<br />
|}<br />
<br />
This register is used to enable texture units.<br />
<br />
Texture 3 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 0<br />
|-<br />
| 1<br />
| Texture 1<br />
|-<br />
| 2<br />
| Texture 2<br />
|}<br />
<br />
Texture 2 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 2<br />
|-<br />
| 1<br />
| Texture 1<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to set a texture unit's border color.<br />
<br />
=== GPUREG_TEXUNIT''i''_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Height<br />
|-<br />
| 16-26<br />
| unsigned, Width<br />
|}<br />
<br />
This register is used to set a texture unit's dimensions.<br />
<br />
=== GPUREG_TEXUNIT''i''_PARAM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, Magnification filter<br />
|-<br />
| 2<br />
| unsigned, Minification filter<br />
|-<br />
| 4-5<br />
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4<br />
|-<br />
| 8-10<br />
| unsigned, Wrap T<br />
|-<br />
| 12-14<br />
| unsigned, Wrap S<br />
|-<br />
| 16-17<br />
| 0x0<br />
|-<br />
| 20<br />
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)<br />
|-<br />
| 24<br />
| unsigned, Mipmap filter<br />
|-<br />
| 28-30<br />
| unsigned, Type (Texture 0 only)<br />
|}<br />
<br />
This register is used to set a texture unit's extra parameters.<br />
<br />
Filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|}<br />
<br />
Wrap values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to edge<br />
|-<br />
| 1<br />
| Clamp to border<br />
|-<br />
| 2<br />
| Repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|}<br />
<br />
Type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 2D<br />
|-<br />
| 1<br />
| Cube map<br />
|-<br />
| 2<br />
| Shadow 2D<br />
|-<br />
| 3<br />
| Projection<br />
|-<br />
| 4<br />
| Shadow cube<br />
|-<br />
| 5<br />
| Disabled<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_LOD ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.4.8, Bias<br />
|-<br />
| 16-19<br />
| unsigned, Max Level<br />
|-<br />
| 24-27<br />
| unsigned, Min Level<br />
|}<br />
<br />
This register is used to configure a texture unit's level of detail.<br />
<br />
=== GPUREG_TEXUNIT''i''_ADDR''i'' ===<br />
<br />
First ADDR register:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Texture physical address >> 3<br />
|}<br />
<br />
Subsequent ADDR registers:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-21<br />
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)<br />
|}<br />
<br />
This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.<br />
<br />
If the texture is a cube:<br />
<br />
{| class="wikitable" border="1"<br />
! Register<br />
! Description<br />
|-<br />
| ADDR1<br />
| Positive X<br />
|-<br />
| ADDR2<br />
| Negative X<br />
|-<br />
| ADDR3<br />
| Positive Y<br />
|-<br />
| ADDR4<br />
| Negative Y<br />
|-<br />
| ADDR5<br />
| Positive Z<br />
|-<br />
| ADDR6<br />
| Negative Z<br />
|}<br />
<br />
Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.<br />
<br />
=== GPUREG_TEXUNIT''i''_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Perspective (0 = perspective, 1 = not perspective)<br />
|-<br />
| 1-23<br />
| fixed0.0.24, Z bias (upper 23 bits)<br />
|}<br />
<br />
This register is used to set a texture unit's shadow texture properties.<br />
<br />
=== GPUREG_TEXUNIT''i''_TYPE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Format<br />
|}<br />
<br />
This register is used to set a texture unit's data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! GL Format<br />
! GL Data Type<br />
|-<br />
| 0x0<br />
| RGBA8888<br />
| GL_RGBA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x1<br />
| RGB888<br />
| GL_RGB<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x2<br />
| RGBA5551<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_5_5_5_1<br />
|-<br />
| 0x3<br />
| RGB565<br />
| GL_RGB<br />
| GL_UNSIGNED_SHORT_5_6_5<br />
|-<br />
| 0x4<br />
| RGBA4444<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_4_4_4_4<br />
|-<br />
| 0x5<br />
| IA8<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x6<br />
| HILO8<br />
| <br />
| <br />
|-<br />
| 0x7<br />
| I8<br />
| GL_LUMINANCE<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x8<br />
| A8<br />
| GL_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x9<br />
| IA44<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE_4_4_EXT<br />
|-<br />
| 0xA<br />
| I4<br />
| <br />
|<br />
|-<br />
| 0xB<br />
| A4<br />
| GL_ALPHA<br />
| GL_UNSIGNED_NIBBLE_EXT<br />
|-<br />
| 0xC<br />
| ETC1<br />
| GL_ETC1_RGB8_OES<br />
| <br />
|-<br />
| 0xD<br />
| ETC1A4<br />
|<br />
| <br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable lighting.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, U-direction clamp<br />
|-<br />
| 3-5<br />
| unsigned, V-direction clamp<br />
|-<br />
| 6-9<br />
| unsigned, RGB mapping function<br />
|-<br />
| 10-13<br />
| unsigned, Alpha mapping function<br />
|-<br />
| 14<br />
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)<br />
|-<br />
| 15<br />
| unsigned, Noise enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 16-17<br />
| unsigned, U-direction shift<br />
|-<br />
| 18-19<br />
| unsigned, V-direction shift<br />
|-<br />
| 20-27<br />
| float1.5.10, Texture bias (lower 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Clamp values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to zero<br />
|-<br />
| 1<br />
| Clamp to edge<br />
|-<br />
| 2<br />
| Symmetrical repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|-<br />
| 4<br />
| Pulse<br />
|}<br />
<br />
Mapping function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| U<br />
|-<br />
| 1<br />
| U²<br />
|-<br />
| 2<br />
| V<br />
|-<br />
| 3<br />
| V²<br />
|-<br />
| 4<br />
| (U + V) / 2<br />
|-<br />
| 5<br />
| (U² + V²) / 2<br />
|-<br />
| 6<br />
| sqrt(U² + V²)<br />
|-<br />
| 7<br />
| Minimum<br />
|-<br />
| 8<br />
| Maximum<br />
|-<br />
| 9<br />
| Rmax<br />
|}<br />
<br />
Shift values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Odd<br />
|-<br />
| 2<br />
| Even<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, U-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, U-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, V-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX3 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, U-direction noise frequency<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise frequency<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX4 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Minification filter<br />
|-<br />
| 3-10<br />
| 0x60<br />
|-<br />
| 11-18<br />
| unsigned, Texture width<br />
|-<br />
| 19-26<br />
| float1.5.10, Texture bias (upper 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Minification filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|-<br />
| 2<br />
| Nearest, Mipmap Nearest<br />
|-<br />
| 3<br />
| Linear, Mipmap Nearest<br />
|-<br />
| 4<br />
| Nearest, Mipmap Linear<br />
|-<br />
| 5<br />
| Linear, Mipmap Linear<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX5 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Texture offset<br />
|-<br />
| 8-31<br />
| 0xE0C080<br />
|}<br />
<br />
This register is used to set the procedural texture unit's offset.<br />
<br />
=== GPUREG_PROCTEX_LUT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Index<br />
|-<br />
| 8-11<br />
| unsigned, Reference table<br />
|}<br />
<br />
This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.<br />
<br />
Reference table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Noise table<br />
|-<br />
| 2<br />
| RGB mapping function table<br />
|-<br />
| 3<br />
| Alpha mapping function table<br />
|-<br />
| 4<br />
| Color table<br />
|-<br />
| 5<br />
| Color difference table<br />
|}<br />
<br />
=== GPUREG_PROCTEX_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.<br />
<br />
==== Noise Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== RGB Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Alpha Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Color Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
==== Color Difference Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| fixed1.0.7, Red difference between current and next color table elements<br />
|-<br />
| 8-15<br />
| fixed1.0.7, Green difference between current and next color table elements<br />
|-<br />
| 16-23<br />
| fixed1.0.7, Blue difference between current and next color table elements<br />
|-<br />
| 24-31<br />
| fixed1.0.7, Alpha difference between current and next color table elements<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_SOURCE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB source 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB source 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB source 2<br />
|-<br />
| 16-19<br />
| unsigned, Alpha source 0<br />
|-<br />
| 20-23<br />
| unsigned, Alpha source 1<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source 2<br />
|}<br />
<br />
This register configures a texture combiner's sources.<br />
<br />
Source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Primary color<br />
|-<br />
| 1<br />
| Fragment primary color<br />
|-<br />
| 2<br />
| Fragment secondary color<br />
|-<br />
| 3<br />
| Texture 0<br />
|-<br />
| 4<br />
| Texture 1<br />
|-<br />
| 5<br />
| Texture 2<br />
|-<br />
| 6<br />
| Texture 3<br />
|-<br />
| 13<br />
| Previous buffer<br />
|-<br />
| 14<br />
| Constant (from GPUREG_TEXENV''i''_COLOR)<br />
|-<br />
| 15<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_OPERAND ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB operand 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB operand 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB operand 2<br />
|-<br />
| 12-14<br />
| unsigned, Alpha operand 0<br />
|-<br />
| 16-18<br />
| unsigned, Alpha operand 1<br />
|-<br />
| 20-22<br />
| unsigned, Alpha operand 2<br />
|}<br />
<br />
This register configures a texture combiner's operands.<br />
<br />
RGB operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source color<br />
|-<br />
| 1<br />
| One minus source color<br />
|-<br />
| 2<br />
| Source alpha<br />
|-<br />
| 3<br />
| One minus source alpha<br />
|-<br />
| 4<br />
| Source red<br />
|-<br />
| 5<br />
| One minus source red<br />
|-<br />
| 8<br />
| Source green<br />
|-<br />
| 9<br />
| One minus source green<br />
|-<br />
| 12<br />
| Source blue<br />
|-<br />
| 13<br />
| One minus source blue<br />
|}<br />
<br />
Alpha operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source alpha<br />
|-<br />
| 1<br />
| One minus source alpha<br />
|-<br />
| 2<br />
| Source red<br />
|-<br />
| 3<br />
| One minus source red<br />
|-<br />
| 4<br />
| Source green<br />
|-<br />
| 5<br />
| One minus source green<br />
|-<br />
| 6<br />
| Source blue<br />
|-<br />
| 7<br />
| One minus source blue<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COMBINER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB combine<br />
|-<br />
| 16-19<br />
| unsigned, Alpha combine<br />
|}<br />
<br />
This register configures a texture combiner's combine mode.<br />
<br />
Combine values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Replace<br />
|-<br />
| 1<br />
| Modulate<br />
|-<br />
| 2<br />
| Add<br />
|-<br />
| 3<br />
| Add signed<br />
|-<br />
| 4<br />
| Interpolate<br />
|-<br />
| 5<br />
| Subtract<br />
|-<br />
| 6<br />
| Dot3 RGB<br />
|-<br />
| 7<br />
| Dot3 RGBA<br />
|-<br />
| 8<br />
| Multiply then add<br />
|-<br />
| 9<br />
| Add then multiply<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register configures a texture combiner's constant color.<br />
<br />
=== GPUREG_TEXENV''i''_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, RGB scale<br />
|-<br />
| 16-17<br />
| unsigned, Alpha scale<br />
|}<br />
<br />
This register configures a texture combiner's scale value.<br />
<br />
Scale values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|}<br />
<br />
=== GPUREG_TEXENV_UPDATE_BUFFER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fog mode<br />
|-<br />
| 3<br />
| unsigned, Shading density source<br />
|-<br />
| 8<br />
| unsigned, TexEnv 1 RGB buffer input<br />
|-<br />
| 9<br />
| unsigned, TexEnv 2 RGB buffer input<br />
|-<br />
| 10<br />
| unsigned, TexEnv 3 RGB buffer input<br />
|-<br />
| 11<br />
| unsigned, TexEnv 4 RGB buffer input<br />
|-<br />
| 12<br />
| unsigned, TexEnv 1 alpha buffer input<br />
|-<br />
| 13<br />
| unsigned, TexEnv 2 alpha buffer input<br />
|-<br />
| 14<br />
| unsigned, TexEnv 3 alpha buffer input<br />
|-<br />
| 15<br />
| unsigned, TexEnv 4 alpha buffer input<br />
|-<br />
| 16<br />
| unsigned, Z flip (0 = don't flip, 1 = flip)<br />
|-<br />
| 24-25<br />
| 0x0<br />
|}<br />
<br />
This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.<br />
<br />
Fog mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Disabled<br />
|-<br />
| 5<br />
| Fog<br />
|-<br />
| 7<br />
| Gas<br />
|}<br />
<br />
Shading density source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Plain density<br />
|-<br />
| 1<br />
| Depth density<br />
|}<br />
<br />
Buffer input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Previous buffer<br />
|-<br />
| 1<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_FOG_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
This register is used to configure the color of fog.<br />
<br />
=== GPUREG_GAS_ATTENUATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas density attenuation<br />
|}<br />
<br />
This register is used to configure the gas density attenuation.<br />
<br />
=== GPUREG_GAS_ACCMAX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas maximum density accumulation<br />
|}<br />
<br />
This register is used to configure the gas maximum density accumulation.<br />
<br />
=== GPUREG_FOG_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.<br />
<br />
=== GPUREG_FOG_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.<br />
<br />
==== Fog Look-Up Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Difference from next element <br />
|-<br />
| 13-23<br />
| fixed0.0.11, Value<br />
|}<br />
<br />
=== GPUREG_TEXENV_BUFFER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the texture combiner buffer color.<br />
<br />
== Framebuffer registers ==<br />
<br />
=== GPUREG_COLOR_OPERATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Fragment operation mode<br />
|-<br />
| 8<br />
| unsigned, Blend mode<br />
|-<br />
| 16-25<br />
| 0x0E4<br />
|}<br />
<br />
This register is used to configure the fragment operation mode and whether to use logic ops or blending.<br />
<br />
Fragment operation mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Default<br />
|-<br />
| 1<br />
| Gas<br />
|-<br />
| 3<br />
| Shadow<br />
|}<br />
<br />
Blend mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Logic op<br />
|-<br />
| 1<br />
| Blend<br />
|}<br />
<br />
=== GPUREG_BLEND_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, RGB equation<br />
|-<br />
| 8-10<br />
| unsigned, Alpha equation<br />
|-<br />
| 16-19<br />
| unsigned, RGB source function<br />
|-<br />
| 20-23<br />
| unsigned, RGB destination function<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source function<br />
|-<br />
| 28-31<br />
| unsigned, Alpha destination function<br />
|}<br />
<br />
This register is used to configure the blending function.<br />
<br />
Equation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Add<br />
|-<br />
| 1<br />
| Subtract<br />
|-<br />
| 2<br />
| Reverse subtract<br />
|-<br />
| 3<br />
| Minimum<br />
|-<br />
| 4<br />
| Maximum<br />
|}<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Zero<br />
|-<br />
| 1<br />
| One<br />
|-<br />
| 2<br />
| Source color<br />
|-<br />
| 3<br />
| One minus source color<br />
|-<br />
| 4<br />
| Destination color<br />
|-<br />
| 5<br />
| One minus destination color<br />
|-<br />
| 6<br />
| Source alpha<br />
|-<br />
| 7<br />
| One minus source alpha<br />
|-<br />
| 8<br />
| Destination alpha<br />
|-<br />
| 9<br />
| One minus destination alpha<br />
|-<br />
| 10<br />
| Constant color<br />
|-<br />
| 11<br />
| One minus constant color<br />
|-<br />
| 12<br />
| Constant alpha<br />
|-<br />
| 13<br />
| One minus constant alpha<br />
|-<br />
| 14<br />
| Source alpha saturate<br />
|}<br />
<br />
=== GPUREG_LOGIC_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Logic op<br />
|}<br />
<br />
This register is used to configure the logic op.<br />
<br />
Logic op values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clear<br />
|-<br />
| 1<br />
| AND<br />
|-<br />
| 2<br />
| Reverse AND<br />
|-<br />
| 3<br />
| Copy<br />
|-<br />
| 4<br />
| Set<br />
|-<br />
| 5<br />
| Inverted copy<br />
|-<br />
| 6<br />
| Noop<br />
|-<br />
| 7<br />
| Invert<br />
|-<br />
| 8<br />
| NAND<br />
|-<br />
| 9<br />
| OR<br />
|-<br />
| 10<br />
| NOR<br />
|-<br />
| 11<br />
| XOR<br />
|-<br />
| 12<br />
| Equivalent<br />
|-<br />
| 13<br />
| Inverted AND<br />
|-<br />
| 14<br />
| Reverse OR<br />
|-<br />
| 15<br />
| Inverted OR<br />
|}<br />
<br />
=== GPUREG_BLEND_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the blending color.<br />
<br />
=== GPUREG_FRAGOP_ALPHA_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Reference value<br />
|}<br />
<br />
This register is used to configure alpha testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Buffer mask<br />
|-<br />
| 16-23<br />
| signed, Reference value<br />
|-<br />
| 24-31<br />
| unsigned, Mask<br />
|}<br />
<br />
This register is used to configure stencil testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fail operation<br />
|-<br />
| 4-6<br />
| unsigned, Z-fail operation<br />
|-<br />
| 8-10<br />
| unsigned, Z-pass operation<br />
|}<br />
<br />
This register is used to configure stencil result operations.<br />
<br />
Operation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Keep<br />
|-<br />
| 1<br />
| Zero<br />
|-<br />
| 2<br />
| Replace<br />
|-<br />
| 3<br />
| Increment<br />
|-<br />
| 4<br />
| Decrement<br />
|-<br />
| 5<br />
| Invert<br />
|-<br />
| 6<br />
| Increment and wrap<br />
|-<br />
| 7<br />
| Decrement and wrap<br />
|}<br />
<br />
=== GPUREG_DEPTH_COLOR_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Depth function<br />
|-<br />
| 8<br />
| unsigned, Red write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 9<br />
| unsigned, Green write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 10<br />
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 11<br />
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to depth testing and framebuffer write masking.<br />
<br />
Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.<br />
<br />
Depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_FRAMEBUFFER_INVALIDATE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = invalidate)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.<br />
<br />
=== GPUREG_FRAMEBUFFER_FLUSH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = flush)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.<br />
<br />
=== GPUREG_COLORBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow read (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures read access from the color buffer.<br />
<br />
=== GPUREG_COLORBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow write (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures write access to the color buffer.<br />
<br />
=== GPUREG_DEPTHBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil read (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth read (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures read access from the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil write (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth write (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures write access to the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the depth buffer data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit depth<br />
|-<br />
| 2<br />
| 24-bit depth<br />
|-<br />
| 3<br />
| 24-bit depth + 8-bit stencil<br />
|}<br />
<br />
=== GPUREG_COLORBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Pixel size<br />
|-<br />
| 16-18<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.<br />
<br />
Pixel size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit color<br />
|-<br />
| 2<br />
| 32-bit color<br />
|}<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| RGBA8/Gas<br />
|-<br />
| 2<br />
| RGB5A1<br />
|-<br />
| 3<br />
| RGB565<br />
|-<br />
| 4<br />
| RGBA4<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register enables the early depth test.<br />
<br />
=== GPUREG_FRAMEBUFFER_BLOCK32 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Render block mode<br />
|}<br />
<br />
This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.<br />
<br />
Render block mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8x8 blocks<br />
|-<br />
| 1<br />
| 32x32 blocks<br />
|}<br />
<br />
=== GPUREG_DEPTHBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Depth buffer physical address >> 3<br />
|}<br />
<br />
This register configures the depth buffer physical address.<br />
<br />
=== GPUREG_COLORBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Color buffer physical address >> 3<br />
|}<br />
<br />
This register configures the color buffer physical address.<br />
<br />
=== GPUREG_FRAMEBUFFER_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register configures the framebuffer dimensions.<br />
<br />
=== GPUREG_GAS_LIGHT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Planar shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, Planar shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, Planar shading density attenuation<br />
|}<br />
<br />
This register configures gas light planar shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, View shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, View shading density attenuation<br />
|}<br />
<br />
This register configures gas light view shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading effect in line-of-sight direction<br />
|-<br />
| 8<br />
| Gas color LUT input<br />
|}<br />
<br />
This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.<br />
<br />
Color LUT input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Gas density<br />
|-<br />
| 1<br />
| Light factor<br />
|}<br />
<br />
=== GPUREG_GAS_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.<br />
<br />
=== GPUREG_GAS_LUT_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.<br />
<br />
==== Gas Look-Up Table ====<br />
<br />
16 elements:<br />
<br />
First 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| signed, Red<br />
|-<br />
| 8-15<br />
| signed, Green<br />
|-<br />
| 16-23<br />
| signed, Blue<br />
|}<br />
<br />
Last 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
=== GPUREG_GAS_DELTAZ_DEPTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| fixed0.16.8, Depth direction attenuation proportion<br />
|}<br />
<br />
This register is used to configure the gas depth direction attenuation proportion.<br />
<br />
=== GPUREG_FRAGOP_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Sum of penumbra scale and penumbra bias<br />
|-<br />
| 16-31<br />
| float1.5.10, Penumbra scale with reversed sign<br />
|}<br />
<br />
This register is used to configure shadow properties.<br />
<br />
== Fragment lighting registers ==<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR1 ===<br />
<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.<br />
<br />
=== GPUREG_LIGHT''i''_DIFFUSE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.<br />
<br />
=== GPUREG_LIGHT''i''_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.<br />
<br />
=== GPUREG_LIGHT''i''_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, X coordinate<br />
|-<br />
| 16-31<br />
| float1.5.10, Y coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Z coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, X coordinate (negated)<br />
|-<br />
| 16-28<br />
| fixed1.1.11, Y coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Z coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Light type (0 = positional light, 1 = directional light)<br />
|-<br />
| 1<br />
| unsigned, Two side diffuse (0 = one side, 1 = both sides)<br />
|-<br />
| 2<br />
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)<br />
|-<br />
| 3<br />
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures a light's properties.<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation bias<br />
|}<br />
<br />
These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation scale<br />
|}<br />
<br />
These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHTING_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.<br />
<br />
=== GPUREG_LIGHTING_NUM_LIGHTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of active lights - 1<br />
|}<br />
<br />
This register configures the number of active lights.<br />
<br />
=== GPUREG_LIGHTING_CONFIG0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)<br />
|-<br />
| 2-3<br />
| unsigned, Fresnel selector<br />
|-<br />
| 4-7<br />
| unsigned, Light environment configuration<br />
|-<br />
| 8-11<br />
| 0x4<br />
|-<br />
| 16<br />
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 17<br />
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 18<br />
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)<br />
|-<br />
| 19<br />
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)<br />
|-<br />
| 22-23<br />
| unsigned, Bump map texture unit<br />
|-<br />
| 24-25<br />
| unsigned, Shadow map texture unit<br />
|-<br />
| 27<br />
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)<br />
|-<br />
| 28-29<br />
| unsigned, Bump mode<br />
|-<br />
| 30<br />
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)<br />
|-<br />
| 31<br />
| 0x1<br />
|}<br />
<br />
This register configures the light environment.<br />
<br />
Fresnel selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Primary alpha<br />
|-<br />
| 2<br />
| Secondary alpha<br />
|-<br />
| 3<br />
| Primary and secondary alpha<br />
|}<br />
<br />
The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.<br />
<br />
Light environment configuration values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! Available LUTs<br />
|-<br />
| 0<br />
| Configuration 0<br />
| D0, RR, SP, DA<br />
|-<br />
| 1<br />
| Configuration 1<br />
| FR, RR, SP, DA<br />
|-<br />
| 2<br />
| Configuration 2<br />
| D0, D1, RR, DA<br />
|-<br />
| 3<br />
| Configuration 3<br />
| D0, D1, FR, DA<br />
|-<br />
| 4<br />
| Configuration 4<br />
| All except for FR<br />
|-<br />
| 5<br />
| Configuration 5<br />
| All except for D1<br />
|-<br />
| 6<br />
| Configuration 6<br />
| All except for RB and RG<br />
|-<br />
| 8<br />
| Configuration 7<br />
| All<br />
|}<br />
<br />
Bump mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Not used<br />
|-<br />
| 1<br />
| Use as bump map<br />
|-<br />
| 2<br />
| Use as tangent map<br />
|}<br />
<br />
=== GPUREG_LIGHTING_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 1<br />
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 2<br />
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 3<br />
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 4<br />
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 6<br />
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 7<br />
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 8<br />
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 10<br />
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 11<br />
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 12<br />
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 14<br />
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 15<br />
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 16<br />
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 18<br />
| 0x1<br />
|-<br />
| 19<br />
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 20-22<br />
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 21<br />
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 22<br />
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 24<br />
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 26<br />
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 27<br />
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 28<br />
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 29<br />
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 30<br />
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 31<br />
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is used to disable various aspects of the light environment.<br />
<br />
=== GPUREG_LIGHTING_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Starting index<br />
|-<br />
| 8-12<br />
| unsigned, Look-up table<br />
|}<br />
<br />
This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.<br />
<br />
Lookup table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| D0<br />
|-<br />
| 1<br />
| D1<br />
|-<br />
| 3<br />
| FR<br />
|-<br />
| 4<br />
| RB<br />
|-<br />
| 5<br />
| RG<br />
|-<br />
| 6<br />
| RR<br />
|-<br />
| 8-15<br />
| SP0-7<br />
|-<br />
| 16-23<br />
| DA0-7<br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.<br />
<br />
=== GPUREG_LIGHTING_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
Lighting LUT data is written here.<br />
<br />
A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.<br />
<br />
DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.<br />
<br />
Format of an entry:<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Entry value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_ABS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)<br />
|-<br />
| 21<br />
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register controls whether the absolute value of the input is taken before using a LUT.<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SELECT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Input selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Input selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Input selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Input selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Input selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Input selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Input selector for RR<br />
|}<br />
<br />
This register selects the input from LUTs.<br />
<br />
Input selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| N·H<br />
|-<br />
| 1<br />
| V·H<br />
|-<br />
| 2<br />
| N·V<br />
|-<br />
| 3<br />
| L·N<br />
|-<br />
| 4<br />
| -L·P (aka Spotlight aka SP)<br />
|-<br />
| 5<br />
| cos φ (aka CP)<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Scaler selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Scaler selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Scaler selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Scaler selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Scaler selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Scaler selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Scaler selector for RR<br />
|}<br />
<br />
This register controls the scaling that is applied to the output of a LUT.<br />
<br />
Scaler selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|-<br />
| 3<br />
| 8x<br />
|-<br />
| 6<br />
| 0.25x<br />
|-<br />
| 7<br />
| 0.5x<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, ID of the 1st enabled light<br />
|-<br />
| 4-6<br />
| unsigned, ID of the 2nd enabled light<br />
|-<br />
| 8-10<br />
| unsigned, ID of the 3rd enabled light<br />
|-<br />
| 12-14<br />
| unsigned, ID of the 4th enabled light<br />
|-<br />
| 16-18<br />
| unsigned, ID of the 5th enabled light<br />
|-<br />
| 20-22<br />
| unsigned, ID of the 6th enabled light<br />
|-<br />
| 24-26<br />
| unsigned, ID of the 7th enabled light<br />
|-<br />
| 28-30<br />
| unsigned, ID of the 8th enabled light<br />
|}<br />
<br />
This register sets the IDs of enabled light sources.<br />
<br />
== Geometry pipeline registers ==<br />
<br />
=== GPUREG_ATTRIBBUFFERS_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-28<br />
| unsigned, Vertex arrays base address<br />
|}<br />
<br />
This register sets the base address of all vertex arrays.<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 0 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 0 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 1 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 1 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 2 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 2 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 3 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 3 size<br />
|-<br />
| 16-17<br />
| unsigned, Vertex attribute 4 type<br />
|-<br />
| 18-19<br />
| unsigned, Vertex attribute 4 size<br />
|-<br />
| 20-21<br />
| unsigned, Vertex attribute 5 type<br />
|-<br />
| 22-23<br />
| unsigned, Vertex attribute 5 size<br />
|-<br />
| 24-25<br />
| unsigned, Vertex attribute 6 type<br />
|-<br />
| 26-27<br />
| unsigned, Vertex attribute 6 size<br />
|-<br />
| 28-29<br />
| unsigned, Vertex attribute 7 type<br />
|-<br />
| 30-31<br />
| unsigned, Vertex attribute 7 size<br />
|}<br />
<br />
This register configures the types and sizes of the first 8 vertex attributes.<br />
<br />
Vertex attribute type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Byte<br />
|-<br />
| 1<br />
| Unsigned byte<br />
|-<br />
| 2<br />
| Short<br />
|-<br />
| 3<br />
| Float<br />
|}<br />
<br />
Vertex attribute size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8 bits<br />
|-<br />
| 1<br />
| 16 bits<br />
|-<br />
| 2<br />
| 24 bits<br />
|-<br />
| 3<br />
| 32 bits<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 8 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 8 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 9 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 9 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 10 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 10 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 11 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 11 size<br />
|-<br />
| 16-27<br />
| unsigned, Fixed vertex attribute mask<br />
|-<br />
| 28-31<br />
| unsigned, Total vertex attribute count - 1<br />
|}<br />
<br />
This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.<br />
<br />
See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|}<br />
<br />
This register configures the offset of a vertex array from the base vertex arrays address.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 1<br />
|-<br />
| 4-7<br />
| unsigned, Component 2<br />
|-<br />
| 8-11<br />
| unsigned, Component 3<br />
|-<br />
| 12-15<br />
| unsigned, Component 4<br />
|-<br />
| 16-19<br />
| unsigned, Component 5<br />
|-<br />
| 20-23<br />
| unsigned, Component 6<br />
|-<br />
| 24-27<br />
| unsigned, Component 7<br />
|-<br />
| 28-31<br />
| unsigned, Component 8<br />
|}<br />
<br />
This register configures the first 8 component types of a vertex array.<br />
<br />
Component values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Vertex attribute 0<br />
|-<br />
| 1<br />
| Vertex attribute 1<br />
|-<br />
| 2<br />
| Vertex attribute 2<br />
|-<br />
| 3<br />
| Vertex attribute 3<br />
|-<br />
| 4<br />
| Vertex attribute 4<br />
|-<br />
| 5<br />
| Vertex attribute 5<br />
|-<br />
| 6<br />
| Vertex attribute 6<br />
|-<br />
| 7<br />
| Vertex attribute 7<br />
|-<br />
| 8<br />
| Vertex attribute 8<br />
|-<br />
| 9<br />
| Vertex attribute 9<br />
|-<br />
| 10<br />
| Vertex attribute 10<br />
|-<br />
| 11<br />
| Vertex attribute 11<br />
|-<br />
| 12<br />
| 4-byte padding<br />
|-<br />
| 13<br />
| 8-byte padding<br />
|-<br />
| 14<br />
| 12-byte padding<br />
|-<br />
| 15<br />
| 16-byte padding<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 9<br />
|-<br />
| 4-7<br />
| unsigned, Component 10<br />
|-<br />
| 8-11<br />
| unsigned, Component 11<br />
|-<br />
| 12-15<br />
| unsigned, Component 12<br />
|-<br />
| 16-23<br />
| unsigned, Bytes per vertex<br />
|-<br />
| 28-31<br />
| unsigned, Total number of components<br />
|}<br />
<br />
This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.<br />
<br />
See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.<br />
<br />
=== GPUREG_INDEXBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|-<br />
| 31<br />
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)<br />
|}<br />
<br />
This register configures the index array used when drawing elements.<br />
<br />
=== GPUREG_NUMVERTICES ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Number of vertices to render<br />
|}<br />
<br />
This register sets the number of vertices to render.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|-<br />
| 9<br />
| 0x0<br />
|-<br />
| 31<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_VERTEX_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Starting vertex offset<br />
|}<br />
<br />
This register sets the offset of the first vertex in an array to render.<br />
<br />
=== GPUREG_POST_VERTEX_CACHE_NUM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)<br />
|}<br />
<br />
This register configures the post-vertex cache.<br />
<br />
=== GPUREG_DRAWARRAYS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw arrays)<br />
|}<br />
<br />
This register triggers drawing vertex arrays.<br />
<br />
=== GPUREG_DRAWELEMENTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw elements)<br />
|}<br />
<br />
This register triggers drawing vertex array elements.<br />
<br />
=== GPUREG_VTX_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)<br />
|}<br />
<br />
This register triggers clearing the post-vertex cache.<br />
<br />
=== GPUREG_FIXEDATTRIB_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)<br />
|}<br />
<br />
This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.<br />
<br />
=== GPUREG_FIXEDATTRIB_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| colspan="2" | '''DATA0:'''<br />
|-<br />
| 0-7<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)<br />
|-<br />
| 8-31<br />
| float1.7.16, Vertex attribute element 4 (W)<br />
|-<br />
| colspan="2" | '''DATA1:'''<br />
|-<br />
| 0-15<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)<br />
|-<br />
| 16-31<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)<br />
|-<br />
| colspan="2" | '''DATA2:'''<br />
|-<br />
| 0-23<br />
| float1.7.16, Vertex attribute element 1 (X)<br />
|-<br />
| 24-31<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)<br />
|}<br />
<br />
Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.<br />
<br />
=== GPUREG_CMDBUF_SIZE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the size of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_SIZE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the size of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the physical address of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the physical address of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)<br />
|}<br />
<br />
This register triggers a jump to the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)<br />
|}<br />
<br />
This register triggers a jump to the second command buffer.<br />
<br />
=== GPUREG_VSH_NUM_ATTR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader input attributes - 1<br />
|}<br />
<br />
This register sets the number of vertex shader input attributes.<br />
<br />
=== GPUREG_VSH_COM_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.<br />
<br />
=== GPUREG_START_DRAW_FUNC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Mode (0 = drawing, 1 = configuration)<br />
|-<br />
| 1-7<br />
| 0x0<br />
|}<br />
<br />
This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_GSH_MISC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)<br />
|}<br />
<br />
This register configures miscellaneous geometry shader properties.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_GSH_MISC1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)<br />
|}<br />
<br />
This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.<br />
<br />
=== GPUREG_PRIMITIVE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|-<br />
| 8-9<br />
| unsigned, Primitive mode<br />
|}<br />
<br />
This register configures primitive drawing.<br />
<br />
Primitive mode value:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Triangles<br />
|-<br />
| 1<br />
| Triangle strip<br />
|-<br />
| 2<br />
| Triangle fan<br />
|-<br />
| 3<br />
| Geometry primitive<br />
|}<br />
<br />
=== GPUREG_RESTART_PRIMITIVE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = reset primitive)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
This register triggers resetting primitive drawing.<br />
<br />
== Shader registers ==<br />
<br />
=== GPUREG_''SH''_BOOLUNIFORM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Boolean register b0 value (0 = false, 1 = true)<br />
|-<br />
| 1<br />
| unsigned, Boolean register b1 value (0 = false, 1 = true)<br />
|-<br />
| 2<br />
| unsigned, Boolean register b2 value (0 = false, 1 = true)<br />
|-<br />
| 3<br />
| unsigned, Boolean register b3 value (0 = false, 1 = true)<br />
|-<br />
| 4<br />
| unsigned, Boolean register b4 value (0 = false, 1 = true)<br />
|-<br />
| 5<br />
| unsigned, Boolean register b5 value (0 = false, 1 = true)<br />
|-<br />
| 6<br />
| unsigned, Boolean register b6 value (0 = false, 1 = true)<br />
|-<br />
| 7<br />
| unsigned, Boolean register b7 value (0 = false, 1 = true)<br />
|-<br />
| 8<br />
| unsigned, Boolean register b8 value (0 = false, 1 = true)<br />
|-<br />
| 9<br />
| unsigned, Boolean register b9 value (0 = false, 1 = true)<br />
|-<br />
| 10<br />
| unsigned, Boolean register b10 value (0 = false, 1 = true)<br />
|-<br />
| 11<br />
| unsigned, Boolean register b11 value (0 = false, 1 = true)<br />
|-<br />
| 12<br />
| unsigned, Boolean register b12 value (0 = false, 1 = true)<br />
|-<br />
| 13<br />
| unsigned, Boolean register b13 value (0 = false, 1 = true)<br />
|-<br />
| 14<br />
| unsigned, Boolean register b14 value (0 = false, 1 = true)<br />
|-<br />
| 15<br />
| unsigned, Boolean register b15 value (0 = false, 1 = true)<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register is used to set a shader unit's boolean registers.<br />
<br />
=== GPUREG_''SH''_INTUNIFORM_I''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Integer register i''i'' X value<br />
|-<br />
| 8-15<br />
| unsigned, Integer register i''i'' Y value<br />
|-<br />
| 16-23<br />
| unsigned, Integer register i''i'' Z value<br />
|-<br />
| 24-31<br />
| unsigned, Integer register i''i'' W value<br />
|}<br />
<br />
These registers are used to set a shader unit's integer registers.<br />
<br />
=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Input vertex attributes - 1<br />
|-<br />
| 8-15<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)<br />
|-<br />
| 16-23<br />
| 0x0<br />
|-<br />
| 24-31<br />
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)<br />
|}<br />
<br />
This register is used to configure a shader unit's input buffer.<br />
<br />
=== GPUREG_''SH''_ENTRYPOINT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Code entry point offset, in 32-bit words<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register sets a shader unit's code entry point.<br />
<br />
For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.<br />
<br />
For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them. <br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 0 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 1 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 2 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 3 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 4 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 5 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 6 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 7 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.<br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 8 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 9 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 10 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 11 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 12 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 13 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 14 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 15 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.<br />
<br />
=== GPUREG_''SH''_OUTMAP_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4<br />
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 5<br />
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 6<br />
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 7<br />
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 8<br />
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 9<br />
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 10<br />
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 11<br />
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 12<br />
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 13<br />
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 14<br />
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 15<br />
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 16-31<br />
| 0x0<br />
|}<br />
<br />
This register toggles a shader unit's output registers.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_END ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Signal transfer end (0 = idle, non-zero = signal)<br />
|}<br />
<br />
This register's value should be set to 1 in order to finalize the transfer of shader code.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)<br />
|-<br />
| 31<br />
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)<br />
|}<br />
<br />
This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| Floating-point register component data<br />
|}<br />
<br />
This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].<br />
<br />
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:<br />
** first word : ZZWWWWWW<br />
** second word : YYYYZZZZ<br />
** third word : XXXXXXYY<br />
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader code offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader instruction data<br />
|}<br />
<br />
This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.<br />
<br />
=== GPUREG_''SH''_OPDESCS_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader operand descriptor offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_OPDESCS_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader operand descriptor data<br />
|}<br />
<br />
This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=GPU/Internal_Registers&diff=19811
GPU/Internal Registers
2017-04-08T10:52:26Z
<p>Plutooo: </p>
<hr />
<div>[[Category:GPU]]<br />
<br />
== Overview ==<br />
<br />
GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.<br />
<br />
Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).<br />
<br />
In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.<br />
<br />
For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).<br />
<br />
Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.<br />
<br />
The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.<br />
<br />
=== Command Header ===<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0-15<br />
| Command ID<br />
|-<br />
| 16-19<br />
| Parameter mask<br />
|-<br />
| 20-30<br />
| Number of extra parameters (may be zero)<br />
|-<br />
| 31<br />
| Consecutive writing mode<br />
|}<br />
<br />
=== Parameter masking ===<br />
<br />
Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.<br />
<br />
=== Types ===<br />
<br />
There are three main types of registers :<br />
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])<br />
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])<br />
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])<br />
<br />
=== Aliases ===<br />
<br />
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]<br />
<br />
=== Data Types ===<br />
<br />
{| class="wikitable" border="1"<br />
! Name<br />
! Description<br />
|-<br />
| signed<br />
| Signed integer<br />
|-<br />
| unsigned<br />
| Unsigned integer<br />
|-<br />
| floatX.Y.Z<br />
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits<br />
|-<br />
| fixedX.Y.Z<br />
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits<br />
|}<br />
<br />
== Register list ==<br />
<br />
=== Miscellaneous registers (0x000-0x03F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0000<br />
| [[#GPUREG_0000|GPUREG_0000]]<br />
| <br />
|<br />
|-<br />
| 0001<br />
| [[#GPUREG_0001|GPUREG_0001]]<br />
| <br />
|<br />
|-<br />
| 0002<br />
| [[#GPUREG_0002|GPUREG_0002]]<br />
| <br />
|<br />
|-<br />
| 0003<br />
| [[#GPUREG_0003|GPUREG_0003]]<br />
| <br />
|<br />
|-<br />
| 0004<br />
| [[#GPUREG_0004|GPUREG_0004]]<br />
| <br />
|<br />
|-<br />
| 0005<br />
| [[#GPUREG_0005|GPUREG_0005]]<br />
| <br />
|<br />
|-<br />
| 0006<br />
| [[#GPUREG_0006|GPUREG_0006]]<br />
| <br />
|<br />
|-<br />
| 0007<br />
| [[#GPUREG_0007|GPUREG_0007]]<br />
| <br />
|<br />
|-<br />
| 0008<br />
| [[#GPUREG_0008|GPUREG_0008]]<br />
| <br />
|<br />
|-<br />
| 0009<br />
| [[#GPUREG_0009|GPUREG_0009]]<br />
| <br />
|<br />
|-<br />
| 000A<br />
| [[#GPUREG_000A|GPUREG_000A]]<br />
| <br />
|<br />
|-<br />
| 000B<br />
| [[#GPUREG_000B|GPUREG_000B]]<br />
| <br />
|<br />
|-<br />
| 000C<br />
| [[#GPUREG_000C|GPUREG_000C]]<br />
| <br />
|<br />
|-<br />
| 000D<br />
| [[#GPUREG_000D|GPUREG_000D]]<br />
| <br />
|<br />
|-<br />
| 000E<br />
| [[#GPUREG_000E|GPUREG_000E]]<br />
| <br />
|<br />
|-<br />
| 000F<br />
| [[#GPUREG_000F|GPUREG_000F]]<br />
| <br />
|<br />
|-<br />
| 0010<br />
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]<br />
| <br />
|PICA_REG_INTERRUPT<br />
|-<br />
| 0011<br />
| [[#GPUREG_0011|GPUREG_0011]]<br />
| <br />
|<br />
|-<br />
| 0012<br />
| [[#GPUREG_0012|GPUREG_0012]]<br />
| <br />
|<br />
|-<br />
| 0013<br />
| [[#GPUREG_0013|GPUREG_0013]]<br />
| <br />
|<br />
|-<br />
| 0014<br />
| [[#GPUREG_0014|GPUREG_0014]]<br />
| <br />
|<br />
|-<br />
| 0015<br />
| [[#GPUREG_0015|GPUREG_0015]]<br />
| <br />
|<br />
|-<br />
| 0016<br />
| [[#GPUREG_0016|GPUREG_0016]]<br />
| <br />
|<br />
|-<br />
| 0017<br />
| [[#GPUREG_0017|GPUREG_0017]]<br />
| <br />
|<br />
|-<br />
| 0018<br />
| [[#GPUREG_0018|GPUREG_0018]]<br />
| <br />
|<br />
|-<br />
| 0019<br />
| [[#GPUREG_0019|GPUREG_0019]]<br />
| <br />
|<br />
|-<br />
| 001A<br />
| [[#GPUREG_001A|GPUREG_001A]]<br />
| <br />
|<br />
|-<br />
| 001B<br />
| [[#GPUREG_001B|GPUREG_001B]]<br />
| <br />
|<br />
|-<br />
| 001C<br />
| [[#GPUREG_001C|GPUREG_001C]]<br />
| <br />
|<br />
|-<br />
| 001D<br />
| [[#GPUREG_001D|GPUREG_001D]]<br />
| <br />
|<br />
|-<br />
| 001E<br />
| [[#GPUREG_001E|GPUREG_001E]]<br />
| <br />
|<br />
|-<br />
| 001F<br />
| [[#GPUREG_001F|GPUREG_001F]]<br />
| <br />
|<br />
|-<br />
| 0020<br />
| [[#GPUREG_0020|GPUREG_0020]]<br />
| <br />
|<br />
|-<br />
| 0021<br />
| [[#GPUREG_0021|GPUREG_0021]]<br />
| <br />
|<br />
|-<br />
| 0022<br />
| [[#GPUREG_0022|GPUREG_0022]]<br />
| <br />
|<br />
|-<br />
| 0023<br />
| [[#GPUREG_0023|GPUREG_0023]]<br />
| <br />
|<br />
|-<br />
| 0024<br />
| [[#GPUREG_0024|GPUREG_0024]]<br />
| <br />
|<br />
|-<br />
| 0025<br />
| [[#GPUREG_0025|GPUREG_0025]]<br />
| <br />
|<br />
|-<br />
| 0026<br />
| [[#GPUREG_0026|GPUREG_0026]]<br />
| <br />
|<br />
|-<br />
| 0027<br />
| [[#GPUREG_0027|GPUREG_0027]]<br />
| <br />
|<br />
|-<br />
| 0028<br />
| [[#GPUREG_0028|GPUREG_0028]]<br />
| <br />
|<br />
|-<br />
| 0029<br />
| [[#GPUREG_0029|GPUREG_0029]]<br />
| <br />
|<br />
|-<br />
| 002A<br />
| [[#GPUREG_002A|GPUREG_002A]]<br />
| <br />
|<br />
|-<br />
| 002B<br />
| [[#GPUREG_002B|GPUREG_002B]]<br />
| <br />
|<br />
|-<br />
| 002C<br />
| [[#GPUREG_002C|GPUREG_002C]]<br />
| <br />
|<br />
|-<br />
| 002D<br />
| [[#GPUREG_002D|GPUREG_002D]]<br />
| <br />
|<br />
|-<br />
| 002E<br />
| [[#GPUREG_002E|GPUREG_002E]]<br />
| <br />
|<br />
|-<br />
| 002F<br />
| [[#GPUREG_002F|GPUREG_002F]]<br />
| <br />
|<br />
|-<br />
| 0030<br />
| [[#GPUREG_0030|GPUREG_0030]]<br />
| <br />
|<br />
|-<br />
| 0031<br />
| [[#GPUREG_0031|GPUREG_0031]]<br />
| <br />
|<br />
|-<br />
| 0032<br />
| [[#GPUREG_0032|GPUREG_0032]]<br />
| <br />
|<br />
|-<br />
| 0033<br />
| [[#GPUREG_0033|GPUREG_0033]]<br />
| <br />
|<br />
|-<br />
| 0034<br />
| [[#GPUREG_0034|GPUREG_0034]]<br />
| <br />
|<br />
|-<br />
| 0035<br />
| [[#GPUREG_0035|GPUREG_0035]]<br />
| <br />
|<br />
|-<br />
| 0036<br />
| [[#GPUREG_0036|GPUREG_0036]]<br />
| <br />
|<br />
|-<br />
| 0037<br />
| [[#GPUREG_0037|GPUREG_0037]]<br />
| <br />
|<br />
|-<br />
| 0038<br />
| [[#GPUREG_0038|GPUREG_0038]]<br />
| <br />
|<br />
|-<br />
| 0039<br />
| [[#GPUREG_0039|GPUREG_0039]]<br />
| <br />
|<br />
|-<br />
| 003A<br />
| [[#GPUREG_003A|GPUREG_003A]]<br />
| <br />
|<br />
|-<br />
| 003B<br />
| [[#GPUREG_003B|GPUREG_003B]]<br />
| <br />
|<br />
|-<br />
| 003C<br />
| [[#GPUREG_003C|GPUREG_003C]]<br />
| <br />
|<br />
|-<br />
| 003D<br />
| [[#GPUREG_003D|GPUREG_003D]]<br />
| <br />
|<br />
|-<br />
| 003E<br />
| [[#GPUREG_003E|GPUREG_003E]]<br />
| <br />
|<br />
|-<br />
| 003F<br />
| [[#GPUREG_003F|GPUREG_003F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Rasterizer registers (0x040-0x07F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0040<br />
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]<br />
| <br />
|PICA_REG_CULL_FACE<br />
|-<br />
| 0041<br />
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH1<br />
|-<br />
| 0042<br />
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH2<br />
|-<br />
| 0043<br />
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT1<br />
|-<br />
| 0044<br />
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT2<br />
|-<br />
| 0045<br />
| [[#GPUREG_0045|GPUREG_0045]]<br />
| <br />
|<br />
|-<br />
| 0046<br />
| [[#GPUREG_0046|GPUREG_0046]]<br />
| <br />
|<br />
|-<br />
| 0047<br />
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP<br />
|-<br />
| 0048<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]<br />
|? <br />
|PICA_REG_FRAGOP_CLIP_DATA1<br />
|-<br />
| 0049<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA2<br />
|-<br />
| 004A<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA3<br />
|-<br />
| 004B<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA4<br />
|-<br />
| 004C<br />
| [[#GPUREG_004C|GPUREG_004C]]<br />
| <br />
|<br />
|-<br />
| 004D<br />
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA1<br />
|-<br />
| 004E<br />
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA2<br />
|-<br />
| 004F<br />
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]<br />
| <br />
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0<br />
|-<br />
| 0050<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0<br />
|-<br />
| 0051<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1<br />
|-<br />
| 0052<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2<br />
|-<br />
| 0053<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3<br />
|-<br />
| 0054<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4<br />
|-<br />
| 0055<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5<br />
|-<br />
| 0056<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6<br />
|-<br />
| 0057<br />
| [[#GPUREG_0057|GPUREG_0057]]<br />
| <br />
|<br />
|-<br />
| 0058<br />
| [[#GPUREG_0058|GPUREG_0058]]<br />
| <br />
|<br />
|-<br />
| 0059<br />
| [[#GPUREG_0059|GPUREG_0059]]<br />
| <br />
|<br />
|-<br />
| 005A<br />
| [[#GPUREG_005A|GPUREG_005A]]<br />
| <br />
|<br />
|-<br />
| 005B<br />
| [[#GPUREG_005B|GPUREG_005B]]<br />
| <br />
|<br />
|-<br />
| 005C<br />
| [[#GPUREG_005C|GPUREG_005C]]<br />
| <br />
|<br />
|-<br />
| 005D<br />
| [[#GPUREG_005D|GPUREG_005D]]<br />
| <br />
|<br />
|-<br />
| 005E<br />
| [[#GPUREG_005E|GPUREG_005E]]<br />
| <br />
|<br />
|-<br />
| 005F<br />
| [[#GPUREG_005F|GPUREG_005F]]<br />
| <br />
|<br />
|-<br />
| 0060<br />
| [[#GPUREG_0060|GPUREG_0060]]<br />
| <br />
|<br />
|-<br />
| 0061<br />
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_FUNC<br />
|-<br />
| 0062<br />
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST1<br />
|-<br />
| 0063<br />
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]<br />
| <br />
|PICA_REG_EARLY_DEPTH_CLEAR<br />
|-<br />
| 0064<br />
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE<br />
|-<br />
| 0065<br />
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]<br />
| <br />
|PICA_REG_SCISSOR<br />
|-<br />
| 0066<br />
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]<br />
| <br />
|PICA_REG_SCISSOR_XY<br />
|-<br />
| 0067<br />
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]<br />
| <br />
|PICA_REG_SCISSOR_SIZE<br />
|-<br />
| 0068<br />
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]<br />
|<br />
|PICA_REG_VIEWPORT_XY<br />
|-<br />
| 0069<br />
| [[#GPUREG_0069|GPUREG_0069]]<br />
| <br />
|<br />
|-<br />
| 006A<br />
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]<br />
|<br />
|PICA_REG_EARLY_DEPTH_DATA<br />
|-<br />
| 006B<br />
| [[#GPUREG_006B|GPUREG_006B]]<br />
| <br />
|<br />
|-<br />
| 006C<br />
| [[#GPUREG_006C|GPUREG_006C]]<br />
| <br />
|<br />
|-<br />
| 006D<br />
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]<br />
|?<br />
|PICA_REG_FRAGOP_WSCALE<br />
|-<br />
| 006E<br />
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]<br />
|?<br />
|PICA_REG_RENDER_BUF_RESOLUTION1<br />
|-<br />
| 006F<br />
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK<br />
|-<br />
| 0070<br />
| [[#GPUREG_0070|GPUREG_0070]]<br />
| <br />
|<br />
|-<br />
| 0071<br />
| [[#GPUREG_0071|GPUREG_0071]]<br />
| <br />
|<br />
|-<br />
| 0072<br />
| [[#GPUREG_0072|GPUREG_0072]]<br />
| <br />
|<br />
|-<br />
| 0073<br />
| [[#GPUREG_0073|GPUREG_0073]]<br />
| <br />
|<br />
|-<br />
| 0074<br />
| [[#GPUREG_0074|GPUREG_0074]]<br />
| <br />
|<br />
|-<br />
| 0075<br />
| [[#GPUREG_0075|GPUREG_0075]]<br />
| <br />
|<br />
|-<br />
| 0076<br />
| [[#GPUREG_0076|GPUREG_0076]]<br />
| <br />
|<br />
|-<br />
| 0077<br />
| [[#GPUREG_0077|GPUREG_0077]]<br />
| <br />
|<br />
|-<br />
| 0078<br />
| [[#GPUREG_0078|GPUREG_0078]]<br />
| <br />
|<br />
|-<br />
| 0079<br />
| [[#GPUREG_0079|GPUREG_0079]]<br />
| <br />
|<br />
|-<br />
| 007A<br />
| [[#GPUREG_007A|GPUREG_007A]]<br />
| <br />
|<br />
|-<br />
| 007B<br />
| [[#GPUREG_007B|GPUREG_007B]]<br />
| <br />
|<br />
|-<br />
| 007C<br />
| [[#GPUREG_007C|GPUREG_007C]]<br />
| <br />
|<br />
|-<br />
| 007D<br />
| [[#GPUREG_007D|GPUREG_007D]]<br />
| <br />
|<br />
|-<br />
| 007E<br />
| [[#GPUREG_007E|GPUREG_007E]]<br />
| <br />
|<br />
|-<br />
| 007F<br />
| [[#GPUREG_007F|GPUREG_007F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Texturing registers (0x080-0x0FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0080<br />
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]<br />
|<br />
|PICA_REG_TEXTURE_FUNC<br />
|-<br />
| 0081<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE0_BORDER_COLOR<br />
|-<br />
| 0082<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]<br />
|<br />
|PICA_REG_TEXTURE0_SIZE<br />
|-<br />
| 0083<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE0_WRAP_FILTER<br />
|-<br />
| 0084<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE0_LOD<br />
|-<br />
| 0085<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR1<br />
|-<br />
| 0086<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR2<br />
|-<br />
| 0087<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR3<br />
|-<br />
| 0088<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR4<br />
|-<br />
| 0089<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR5<br />
|-<br />
| 008A<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR6<br />
|-<br />
| 008B<br />
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]<br />
|?<br />
|PICA_REG_TEXTURE0_SHADOW<br />
|-<br />
| 008C<br />
| [[#GPUREG_008C|GPUREG_008C]]<br />
|<br />
|<br />
|-<br />
| 008D<br />
| [[#GPUREG_008D|GPUREG_008D]]<br />
|<br />
|<br />
|-<br />
| 008E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]<br />
|?<br />
|PICA_REG_TEXTURE0_FORMAT<br />
|-<br />
| 008F<br />
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN0<br />
|-<br />
| 0090<br />
| [[#GPUREG_0090|GPUREG_0090]]<br />
| <br />
|<br />
|-<br />
| 0091<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE1_BORDER_COLOR<br />
|-<br />
| 0092<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]<br />
| <br />
|PICA_REG_TEXTURE1_SIZE<br />
|-<br />
| 0093<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE1_WRAP_FILTER<br />
|-<br />
| 0094<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE1_LOD<br />
|-<br />
| 0095<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]<br />
| <br />
|PICA_REG_TEXTURE1_ADDR<br />
|-<br />
| 0096<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE1_FORMAT<br />
|-<br />
| 0097<br />
| [[#GPUREG_0097|GPUREG_0097]]<br />
| <br />
|<br />
|-<br />
| 0098<br />
| [[#GPUREG_0098|GPUREG_0098]]<br />
| <br />
|<br />
|-<br />
| 0099<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE2_BORDER_COLOR<br />
|-<br />
| 009A<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]<br />
| <br />
|PICA_REG_TEXTURE2_SIZE<br />
|-<br />
| 009B<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE2_WRAP_FILTER<br />
|-<br />
| 009C<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE2_LOD<br />
|-<br />
| 009D<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]<br />
|<br />
|PICA_REG_TEXTURE2_ADDR<br />
|-<br />
| 009E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE2_FORMAT<br />
|-<br />
| 009F<br />
| [[#GPUREG_009F|GPUREG_009F]]<br />
| <br />
|<br />
|-<br />
| 00A0<br />
| [[#GPUREG_00A0|GPUREG_00A0]]<br />
| <br />
|<br />
|-<br />
| 00A1<br />
| [[#GPUREG_00A1|GPUREG_00A1]]<br />
| <br />
|<br />
|-<br />
| 00A2<br />
| [[#GPUREG_00A2|GPUREG_00A2]]<br />
| <br />
|<br />
|-<br />
| 00A3<br />
| [[#GPUREG_00A3|GPUREG_00A3]]<br />
| <br />
|<br />
|-<br />
| 00A4<br />
| [[#GPUREG_00A4|GPUREG_00A4]]<br />
| <br />
|<br />
|-<br />
| 00A5<br />
| [[#GPUREG_00A5|GPUREG_00A5]]<br />
| <br />
|<br />
|-<br />
| 00A6<br />
| [[#GPUREG_00A6|GPUREG_00A6]]<br />
| <br />
|<br />
|-<br />
| 00A7<br />
| [[#GPUREG_00A7|GPUREG_00A7]]<br />
| <br />
|<br />
|-<br />
| 00A8<br />
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX0<br />
|-<br />
| 00A9<br />
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX1<br />
|-<br />
| 00AA<br />
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]<br />
|? <br />
|PICA_REG_TEXTURE3_PROCTEX2<br />
|-<br />
| 00AB<br />
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX3<br />
|-<br />
| 00AC<br />
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX4<br />
|-<br />
| 00AD<br />
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX5<br />
|-<br />
| 00AE<br />
| [[#GPUREG_00AE|GPUREG_00AE]]<br />
| <br />
|<br />
|-<br />
| 00AF<br />
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]<br />
|?<br />
|PICA_REG_PROCTEX_LUT<br />
|-<br />
| 00B0<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA0<br />
|-<br />
| 00B1<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA1<br />
|-<br />
| 00B2<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA2<br />
|-<br />
| 00B3<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA3<br />
|-<br />
| 00B4<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA4<br />
|-<br />
| 00B5<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA5<br />
|-<br />
| 00B6<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA6<br />
|-<br />
| 00B7<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA7<br />
|-<br />
| 00B8<br />
| [[#GPUREG_00B8|GPUREG_00B8]]<br />
| <br />
|<br />
|-<br />
| 00B9<br />
| [[#GPUREG_00B9|GPUREG_00B9]]<br />
| <br />
|<br />
|-<br />
| 00BA<br />
| [[#GPUREG_00BA|GPUREG_00BA]]<br />
| <br />
|<br />
|-<br />
| 00BB<br />
| [[#GPUREG_00BB|GPUREG_00BB]]<br />
| <br />
|<br />
|-<br />
| 00BC<br />
| [[#GPUREG_00BC|GPUREG_00BC]]<br />
| <br />
|<br />
|-<br />
| 00BD<br />
| [[#GPUREG_00BD|GPUREG_00BD]]<br />
| <br />
|<br />
|-<br />
| 00BE<br />
| [[#GPUREG_00BE|GPUREG_00BE]]<br />
| <br />
|<br />
|-<br />
| 00BF<br />
| [[#GPUREG_00BF|GPUREG_00BF]]<br />
| <br />
|<br />
|-<br />
| 00C0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_0<br />
|-<br />
| 00C1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_0_OPERAND<br />
|-<br />
| 00C2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COMBINE<br />
|-<br />
| 00C3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COLOR<br />
|-<br />
| 00C4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_0_SCALE<br />
|-<br />
| 00C5<br />
| [[#GPUREG_00C5|GPUREG_00C5]]<br />
| <br />
|<br />
|-<br />
| 00C6<br />
| [[#GPUREG_00C6|GPUREG_00C6]]<br />
| <br />
|<br />
|-<br />
| 00C7<br />
| [[#GPUREG_00C7|GPUREG_00C7]]<br />
| <br />
|<br />
|-<br />
| 00C8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_1<br />
|-<br />
| 00C9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_1_OPERAND<br />
|-<br />
| 00CA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COMBINE<br />
|-<br />
| 00CB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COLOR<br />
|-<br />
| 00CC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_1_SCALE<br />
|-<br />
| 00CD<br />
| [[#GPUREG_00CD|GPUREG_00CD]]<br />
| <br />
|<br />
|-<br />
| 00CE<br />
| [[#GPUREG_00CE|GPUREG_00CE]]<br />
| <br />
|<br />
|-<br />
| 00CF<br />
| [[#GPUREG_00CF|GPUREG_00CF]]<br />
| <br />
|<br />
|-<br />
| 00D0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_2<br />
|-<br />
| 00D1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_2_OPERAND<br />
|-<br />
| 00D2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COMBINE<br />
|-<br />
| 00D3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COLOR<br />
|-<br />
| 00D4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_2_SCALE<br />
|-<br />
| 00D5<br />
| [[#GPUREG_00D5|GPUREG_00D5]]<br />
| <br />
|<br />
|-<br />
| 00D6<br />
| [[#GPUREG_00D6|GPUREG_00D6]]<br />
| <br />
|<br />
|-<br />
| 00D7<br />
| [[#GPUREG_00D7|GPUREG_00D7]]<br />
| <br />
|<br />
|-<br />
| 00D8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_3<br />
|-<br />
| 00D9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_3_OPERAND<br />
|-<br />
| 00DA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COMBINE<br />
|-<br />
| 00DB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COLOR<br />
|-<br />
| 00DC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_3_SCALE<br />
|-<br />
| 00DD<br />
| [[#GPUREG_00DD|GPUREG_00DD]]<br />
| <br />
|<br />
|-<br />
| 00DE<br />
| [[#GPUREG_00DE|GPUREG_00DE]]<br />
| <br />
|<br />
|-<br />
| 00DF<br />
| [[#GPUREG_00DF|GPUREG_00DF]]<br />
| <br />
|<br />
|-<br />
| 00E0<br />
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]<br />
|?<br />
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT<br />
|-<br />
| 00E1<br />
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]<br />
|?<br />
|PICA_REG_FOG_COLOR<br />
|-<br />
| 00E2<br />
| [[#GPUREG_00E2|GPUREG_00E2]]<br />
| <br />
|<br />
|-<br />
| 00E3<br />
| [[#GPUREG_00E3|GPUREG_00E3]]<br />
| <br />
|<br />
|-<br />
| 00E4<br />
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]<br />
|?<br />
|PICA_REG_GAS_ATTENUATION<br />
|-<br />
| 00E5<br />
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]<br />
|?<br />
|PICA_REG_GAS_ACCMAX<br />
|-<br />
| 00E6<br />
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FOG_LUT_INDEX<br />
|-<br />
| 00E7<br />
| [[#GPUREG_00E7|GPUREG_00E7]]<br />
| <br />
|<br />
|-<br />
| 00E8<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA0<br />
|-<br />
| 00E9<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]<br />
|? <br />
|PICA_REG_FOG_LUT_DATA1<br />
|-<br />
| 00EA<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA2<br />
|-<br />
| 00EB<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA3<br />
|-<br />
| 00EC<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA4<br />
|-<br />
| 00ED<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA5<br />
|-<br />
| 00EE<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA6<br />
|-<br />
| 00EF<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA7<br />
|-<br />
| 00F0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_4<br />
|-<br />
| 00F1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_4_OPERAND<br />
|-<br />
| 00F2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COMBINE<br />
|-<br />
| 00F3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COLOR<br />
|-<br />
| 00F4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_4_SCALE<br />
|-<br />
| 00F5<br />
| [[#GPUREG_00F5|GPUREG_00F5]]<br />
| <br />
|<br />
|-<br />
| 00F6<br />
| [[#GPUREG_00F6|GPUREG_00F6]]<br />
| <br />
|<br />
|-<br />
| 00F7<br />
| [[#GPUREG_00F7|GPUREG_00F7]]<br />
| <br />
|<br />
|-<br />
| 00F8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_5<br />
|-<br />
| 00F9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_5_OPERAND<br />
|-<br />
| 00FA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COMBINE<br />
|-<br />
| 00FB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COLOR<br />
|-<br />
| 00FC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_5_SCALE<br />
|-<br />
| 00FD<br />
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]<br />
|?<br />
|PICA_REG_TEX_ENV_BUF_COLOR<br />
|-<br />
| 00FE<br />
| [[#GPUREG_00FE|GPUREG_00FE]]<br />
| <br />
|<br />
|-<br />
| 00FF<br />
| [[#GPUREG_00FF|GPUREG_00FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Framebuffer registers (0x100-0x13F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0100<br />
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]<br />
|<br />
|PICA_REG_COLOR_OPERATION<br />
|-<br />
| 0101<br />
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]<br />
| <br />
|PICA_REG_BLEND_FUNC<br />
|-<br />
| 0102<br />
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]<br />
| <br />
|PICA_REG_LOGIC_OP<br />
|-<br />
| 0103<br />
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]<br />
| <br />
|PICA_REG_BLEND_COLOR<br />
|-<br />
| 0104<br />
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]<br />
| <br />
|PICA_REG_FRAGOP_ALPHA_TEST<br />
|-<br />
| 0105<br />
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]<br />
| <br />
|PICA_REG_STENCIL_TEST<br />
|-<br />
| 0106<br />
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]<br />
| <br />
|PICA_REG_STENCIL_OP<br />
|-<br />
| 0107<br />
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]<br />
| <br />
|PICA_REG_DEPTH_COLOR_MASK<br />
|-<br />
| 0108<br />
| [[#GPUREG_0108|GPUREG_0108]]<br />
| <br />
|<br />
|-<br />
| 0109<br />
| [[#GPUREG_0109|GPUREG_0109]]<br />
| <br />
|<br />
|-<br />
| 010A<br />
| [[#GPUREG_010A|GPUREG_010A]]<br />
| <br />
|<br />
|-<br />
| 010B<br />
| [[#GPUREG_010B|GPUREG_010B]]<br />
| <br />
|<br />
|-<br />
| 010C<br />
| [[#GPUREG_010C|GPUREG_010C]]<br />
| <br />
|<br />
|-<br />
| 010D<br />
| [[#GPUREG_010D|GPUREG_010D]]<br />
| <br />
|<br />
|-<br />
| 010E<br />
| [[#GPUREG_010E|GPUREG_010E]]<br />
| <br />
|<br />
|-<br />
| 010F<br />
| [[#GPUREG_010F|GPUREG_010F]]<br />
| <br />
|<br />
|-<br />
| 0110<br />
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR0<br />
|-<br />
| 0111<br />
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR1<br />
|-<br />
| 0112<br />
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_READ<br />
|-<br />
| 0113<br />
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_WRITE<br />
|-<br />
| 0114<br />
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_READ<br />
|-<br />
| 0115<br />
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_WRITE<br />
|-<br />
| 0116<br />
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_DEPTH_MODE<br />
|-<br />
| 0117<br />
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_MODE<br />
|-<br />
| 0118<br />
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST2<br />
|-<br />
| 0119<br />
| [[#GPUREG_0119|GPUREG_0119]]<br />
| <br />
|<br />
|-<br />
| 011A<br />
| [[#GPUREG_011A|GPUREG_011A]]<br />
| <br />
|<br />
|-<br />
| 011B<br />
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]<br />
|<br />
|PICA_REG_RENDER_BLOCK_FORMAT<br />
|-<br />
| 011C<br />
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]<br />
|<br />
|PICA_REG_RENDER_BUF_DEPTH_ADDR<br />
|-<br />
| 011D<br />
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_ADDR<br />
|-<br />
| 011E<br />
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]<br />
| <br />
|PICA_REG_RENDER_BUF_RESOLUTION0<br />
|-<br />
| 011F<br />
| [[#GPUREG_011F|GPUREG_011F]]<br />
| <br />
|<br />
|-<br />
| 0120<br />
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_XY<br />
|-<br />
| 0121<br />
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z<br />
|-<br />
| 0122<br />
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z_COLOR<br />
|-<br />
| 0123<br />
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]<br />
|?<br />
|PICA_REG_GAS_LUT_INDEX<br />
|-<br />
| 0124<br />
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]<br />
|?<br />
|PICA_REG_GAS_LUT_DATA<br />
|-<br />
| 0125<br />
| [[#GPUREG_0125|GPUREG_0125]]<br />
| <br />
|<br />
|-<br />
| 0126<br />
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]<br />
|?<br />
|PICA_REG_GAS_DELTAZ_DEPTH<br />
|-<br />
| 0127<br />
| [[#GPUREG_0127|GPUREG_0127]]<br />
| <br />
|<br />
|-<br />
| 0128<br />
| [[#GPUREG_0128|GPUREG_0128]]<br />
| <br />
|<br />
|-<br />
| 0129<br />
| [[#GPUREG_0129|GPUREG_0129]]<br />
| <br />
|<br />
|-<br />
| 012A<br />
| [[#GPUREG_012A|GPUREG_012A]]<br />
| <br />
|<br />
|-<br />
| 012B<br />
| [[#GPUREG_012B|GPUREG_012B]]<br />
| <br />
|<br />
|-<br />
| 012C<br />
| [[#GPUREG_012C|GPUREG_012C]]<br />
| <br />
|<br />
|-<br />
| 012D<br />
| [[#GPUREG_012D|GPUREG_012D]]<br />
| <br />
|<br />
|-<br />
| 012E<br />
| [[#GPUREG_012E|GPUREG_012E]]<br />
| <br />
|<br />
|-<br />
| 012F<br />
| [[#GPUREG_012F|GPUREG_012F]]<br />
| <br />
|<br />
|-<br />
| 0130<br />
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]<br />
|?<br />
|PICA_REG_FRAGOP_SHADOW<br />
|-<br />
| 0131<br />
| [[#GPUREG_0131|GPUREG_0131]]<br />
| <br />
|<br />
|-<br />
| 0132<br />
| [[#GPUREG_0132|GPUREG_0132]]<br />
| <br />
|<br />
|-<br />
| 0133<br />
| [[#GPUREG_0133|GPUREG_0133]]<br />
| <br />
|<br />
|-<br />
| 0134<br />
| [[#GPUREG_0134|GPUREG_0134]]<br />
| <br />
|<br />
|-<br />
| 0135<br />
| [[#GPUREG_0135|GPUREG_0135]]<br />
| <br />
|<br />
|-<br />
| 0136<br />
| [[#GPUREG_0136|GPUREG_0136]]<br />
| <br />
|<br />
|-<br />
| 0137<br />
| [[#GPUREG_0137|GPUREG_0137]]<br />
| <br />
|<br />
|-<br />
| 0138<br />
| [[#GPUREG_0138|GPUREG_0138]]<br />
| <br />
|<br />
|-<br />
| 0139<br />
| [[#GPUREG_0139|GPUREG_0139]]<br />
| <br />
|<br />
|-<br />
| 013A<br />
| [[#GPUREG_013A|GPUREG_013A]]<br />
| <br />
|<br />
|-<br />
| 013B<br />
| [[#GPUREG_013B|GPUREG_013B]]<br />
| <br />
|<br />
|-<br />
| 013C<br />
| [[#GPUREG_013C|GPUREG_013C]]<br />
| <br />
|<br />
|-<br />
| 013D<br />
| [[#GPUREG_013D|GPUREG_013D]]<br />
| <br />
|<br />
|-<br />
| 013E<br />
| [[#GPUREG_013E|GPUREG_013E]]<br />
| <br />
|<br />
|-<br />
| 013F<br />
| [[#GPUREG_013F|GPUREG_013F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Fragment lighting registers (0x140-0x1FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0140<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START<br />
|-<br />
| 0141<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR1<br />
|-<br />
| 0142<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIFFUSE<br />
|-<br />
| 0143<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_AMBIENT<br />
|-<br />
| 0144<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_XY<br />
|-<br />
| 0145<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_Z<br />
|-<br />
| 0146<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_XY<br />
|-<br />
| 0147<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_Z<br />
|-<br />
| 0148<br />
| [[#GPUREG_0148|GPUREG_0148]]<br />
| <br />
|<br />
|-<br />
| 0149<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]<br />
| <br />
|PICA_REG_FRAG_LIGHT0_TYPE<br />
|-<br />
| 014A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS<br />
|-<br />
| 014B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE<br />
|-<br />
| 014C<br />
| [[#GPUREG_014C|GPUREG_014C]]<br />
| <br />
|<br />
|-<br />
| 014D<br />
| [[#GPUREG_014D|GPUREG_014D]]<br />
| <br />
|<br />
|-<br />
| 014E<br />
| [[#GPUREG_014E|GPUREG_014E]]<br />
| <br />
|<br />
|-<br />
| 014F<br />
| [[#GPUREG_014F|GPUREG_014F]]<br />
| <br />
|<br />
|-<br />
| 0150<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR0<br />
|-<br />
| 0151<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR1<br />
|-<br />
| 0152<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIFFUSE<br />
|-<br />
| 0153<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_AMBIENT<br />
|-<br />
| 0154<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_XY<br />
|-<br />
| 0155<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_Z<br />
|-<br />
| 0156<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_XY<br />
|-<br />
| 0157<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_Z<br />
|-<br />
| 0158<br />
| [[#GPUREG_0158|GPUREG_0158]]<br />
| <br />
|<br />
|-<br />
| 0159<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_TYPE<br />
|-<br />
| 015A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS<br />
|-<br />
| 015B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE<br />
|-<br />
| 015C<br />
| [[#GPUREG_015C|GPUREG_015C]]<br />
| <br />
|<br />
|-<br />
| 015D<br />
| [[#GPUREG_015D|GPUREG_015D]]<br />
| <br />
|<br />
|-<br />
| 015E<br />
| [[#GPUREG_015E|GPUREG_015E]]<br />
| <br />
|<br />
|-<br />
| 015F<br />
| [[#GPUREG_015F|GPUREG_015F]]<br />
| <br />
|<br />
|-<br />
| 0160<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR0<br />
|-<br />
| 0161<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR1<br />
|-<br />
| 0162<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIFFUSE<br />
|-<br />
| 0163<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_AMBIENT<br />
|-<br />
| 0164<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_XY<br />
|-<br />
| 0165<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_Z<br />
|-<br />
| 0166<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_XY<br />
|-<br />
| 0167<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_Z<br />
|-<br />
| 0168<br />
| [[#GPUREG_0168|GPUREG_0168]]<br />
| <br />
|<br />
|-<br />
| 0169<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_TYPE<br />
|-<br />
| 016A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS<br />
|-<br />
| 016B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE<br />
|-<br />
| 016C<br />
| [[#GPUREG_016C|GPUREG_016C]]<br />
| <br />
|<br />
|-<br />
| 016D<br />
| [[#GPUREG_016D|GPUREG_016D]]<br />
| <br />
|<br />
|-<br />
| 016E<br />
| [[#GPUREG_016E|GPUREG_016E]]<br />
| <br />
|<br />
|-<br />
| 016F<br />
| [[#GPUREG_016F|GPUREG_016F]]<br />
| <br />
|<br />
|-<br />
| 0170<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR0<br />
|-<br />
| 0171<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR1<br />
|-<br />
| 0172<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIFFUSE<br />
|-<br />
| 0173<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_AMBIENT<br />
|-<br />
| 0174<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_XY<br />
|-<br />
| 0175<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_Z<br />
|-<br />
| 0176<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]<br />
|? <br />
|PICA_REG_FRAG_LIGHT3_SPOT_XY<br />
|-<br />
| 0177<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPOT_Z<br />
|-<br />
| 0178<br />
| [[#GPUREG_0178|GPUREG_0178]]<br />
| <br />
|<br />
|-<br />
| 0179<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_TYPE<br />
|-<br />
| 017A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS<br />
|-<br />
| 017B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE<br />
|-<br />
| 017C<br />
| [[#GPUREG_017C|GPUREG_017C]]<br />
| <br />
|<br />
|-<br />
| 017D<br />
| [[#GPUREG_017D|GPUREG_017D]]<br />
| <br />
|<br />
|-<br />
| 017E<br />
| [[#GPUREG_017E|GPUREG_017E]]<br />
| <br />
|<br />
|-<br />
| 017F<br />
| [[#GPUREG_017F|GPUREG_017F]]<br />
| <br />
|<br />
|-<br />
| 0180<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR0<br />
|-<br />
| 0181<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR1<br />
|-<br />
| 0182<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIFFUSE<br />
|-<br />
| 0183<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_AMBIENT<br />
|-<br />
| 0184<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_XY<br />
|-<br />
| 0185<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_Z<br />
|-<br />
| 0186<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_XY<br />
|-<br />
| 0187<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_Z<br />
|-<br />
| 0188<br />
| [[#GPUREG_0188|GPUREG_0188]]<br />
| <br />
|<br />
|-<br />
| 0189<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_TYPE<br />
|-<br />
| 018A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS<br />
|-<br />
| 018B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE<br />
|-<br />
| 018C<br />
| [[#GPUREG_018C|GPUREG_018C]]<br />
| <br />
|<br />
|-<br />
| 018D<br />
| [[#GPUREG_018D|GPUREG_018D]]<br />
| <br />
|<br />
|-<br />
| 018E<br />
| [[#GPUREG_018E|GPUREG_018E]]<br />
| <br />
|<br />
|-<br />
| 018F<br />
| [[#GPUREG_018F|GPUREG_018F]]<br />
| <br />
|<br />
|-<br />
| 0190<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR0<br />
|-<br />
| 0191<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR1<br />
|-<br />
| 0192<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_DIFFUSE<br />
|-<br />
| 0193<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_AMBIENT<br />
|-<br />
| 0194<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_XY<br />
|-<br />
| 0195<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_Z<br />
|-<br />
| 0196<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_XY<br />
|-<br />
| 0197<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_Z<br />
|-<br />
| 0198<br />
| [[#GPUREG_0198|GPUREG_0198]]<br />
| <br />
|<br />
|-<br />
| 0199<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_TYPE<br />
|-<br />
| 019A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS<br />
|-<br />
| 019B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE<br />
|-<br />
| 019C<br />
| [[#GPUREG_019C|GPUREG_019C]]<br />
| <br />
|<br />
|-<br />
| 019D<br />
| [[#GPUREG_019D|GPUREG_019D]]<br />
| <br />
|<br />
|-<br />
| 019E<br />
| [[#GPUREG_019E|GPUREG_019E]]<br />
| <br />
|<br />
|-<br />
| 019F<br />
| [[#GPUREG_019F|GPUREG_019F]]<br />
| <br />
|<br />
|-<br />
| 01A0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR0<br />
|-<br />
| 01A1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR1<br />
|-<br />
| 01A2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIFFUSE<br />
|-<br />
| 01A3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_AMBIENT<br />
|-<br />
| 01A4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_XY<br />
|-<br />
| 01A5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_Z<br />
|-<br />
| 01A6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_XY<br />
|-<br />
| 01A7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_Z<br />
|-<br />
| 01A8<br />
| [[#GPUREG_01A8|GPUREG_01A8]]<br />
| <br />
|<br />
|-<br />
| 01A9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_TYPE<br />
|-<br />
| 01AA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS<br />
|-<br />
| 01AB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE<br />
|-<br />
| 01AC<br />
| [[#GPUREG_01AC|GPUREG_01AC]]<br />
| <br />
|<br />
|-<br />
| 01AD<br />
| [[#GPUREG_01AD|GPUREG_01AD]]<br />
| <br />
|<br />
|-<br />
| 01AE<br />
| [[#GPUREG_01AE|GPUREG_01AE]]<br />
| <br />
|<br />
|-<br />
| 01AF<br />
| [[#GPUREG_01AF|GPUREG_01AF]]<br />
| <br />
|<br />
|-<br />
| 01B0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR0<br />
|-<br />
| 01B1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR1<br />
|-<br />
| 01B2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_DIFFUSE<br />
|-<br />
| 01B3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_AMBIENT<br />
|-<br />
| 01B4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_XY<br />
|-<br />
| 01B5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_Z<br />
|-<br />
| 01B6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_XY<br />
|-<br />
| 01B7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_Z<br />
|-<br />
| 01B8<br />
| [[#GPUREG_01B8|GPUREG_01B8]]<br />
| <br />
|<br />
|-<br />
| 01B9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_TYPE<br />
|-<br />
| 01BA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS<br />
|-<br />
| 01BB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE<br />
|-<br />
| 01BC<br />
| [[#GPUREG_01BC|GPUREG_01BC]]<br />
| <br />
|<br />
|-<br />
| 01BD<br />
| [[#GPUREG_01BD|GPUREG_01BD]]<br />
| <br />
|<br />
|-<br />
| 01BE<br />
| [[#GPUREG_01BE|GPUREG_01BE]]<br />
| <br />
|<br />
|-<br />
| 01BF<br />
| [[#GPUREG_01BF|GPUREG_01BF]]<br />
| <br />
|<br />
|-<br />
| 01C0<br />
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_AMBIENT<br />
|-<br />
| 01C1<br />
| [[#GPUREG_01C1|GPUREG_01C1]]<br />
| <br />
|<br />
|-<br />
| 01C2<br />
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_NUM<br />
|-<br />
| 01C3<br />
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE0<br />
|-<br />
| 01C4<br />
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE1<br />
|-<br />
| 01C5<br />
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT<br />
|-<br />
| 01C6<br />
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN1<br />
|-<br />
| 01C7<br />
| [[#GPUREG_01C7|GPUREG_01C7]]<br />
| <br />
|<br />
|-<br />
| 01C8<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA0<br />
|-<br />
| 01C9<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA1<br />
|-<br />
| 01CA<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA2<br />
|-<br />
| 01CB<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA3<br />
|-<br />
| 01CC<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA4<br />
|-<br />
| 01CD<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA5<br />
|-<br />
| 01CE<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA6<br />
|-<br />
| 01CF<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA7<br />
|-<br />
| 01D0<br />
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT<br />
|-<br />
| 01D1<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTINPUT<br />
|-<br />
| 01D2<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTSCALE<br />
|-<br />
| 01D3<br />
| [[#GPUREG_01D3|GPUREG_01D3]]<br />
| <br />
|<br />
|-<br />
| 01D4<br />
| [[#GPUREG_01D4|GPUREG_01D4]]<br />
| <br />
|<br />
|-<br />
| 01D5<br />
| [[#GPUREG_01D5|GPUREG_01D5]]<br />
| <br />
|<br />
|-<br />
| 01D6<br />
| [[#GPUREG_01D6|GPUREG_01D6]]<br />
| <br />
|<br />
|-<br />
| 01D7<br />
| [[#GPUREG_01D7|GPUREG_01D7]]<br />
| <br />
|<br />
|-<br />
| 01D8<br />
| [[#GPUREG_01D8|GPUREG_01D8]]<br />
| <br />
|<br />
|-<br />
| 01D9<br />
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_EN_ID<br />
|-<br />
| 01DA<br />
| [[#GPUREG_01DA|GPUREG_01DA]]<br />
| <br />
|<br />
|-<br />
| 01DB<br />
| [[#GPUREG_01DB|GPUREG_01DB]]<br />
| <br />
|<br />
|-<br />
| 01DC<br />
| [[#GPUREG_01DC|GPUREG_01DC]]<br />
| <br />
|<br />
|-<br />
| 01DD<br />
| [[#GPUREG_01DD|GPUREG_01DD]]<br />
| <br />
|<br />
|-<br />
| 01DE<br />
| [[#GPUREG_01DE|GPUREG_01DE]]<br />
| <br />
|<br />
|-<br />
| 01DF<br />
| [[#GPUREG_01DF|GPUREG_01DF]]<br />
| <br />
|<br />
|-<br />
| 01E0<br />
| [[#GPUREG_01E0|GPUREG_01E0]]<br />
| <br />
|<br />
|-<br />
| 01E1<br />
| [[#GPUREG_01E1|GPUREG_01E1]]<br />
| <br />
|<br />
|-<br />
| 01E2<br />
| [[#GPUREG_01E2|GPUREG_01E2]]<br />
| <br />
|<br />
|-<br />
| 01E3<br />
| [[#GPUREG_01E3|GPUREG_01E3]]<br />
| <br />
|<br />
|-<br />
| 01E4<br />
| [[#GPUREG_01E4|GPUREG_01E4]]<br />
| <br />
|<br />
|-<br />
| 01E5<br />
| [[#GPUREG_01E5|GPUREG_01E5]]<br />
| <br />
|<br />
|-<br />
| 01E6<br />
| [[#GPUREG_01E6|GPUREG_01E6]]<br />
| <br />
|<br />
|-<br />
| 01E7<br />
| [[#GPUREG_01E7|GPUREG_01E7]]<br />
| <br />
|<br />
|-<br />
| 01E8<br />
| [[#GPUREG_01E8|GPUREG_01E8]]<br />
| <br />
|<br />
|-<br />
| 01E9<br />
| [[#GPUREG_01E9|GPUREG_01E9]]<br />
| <br />
|<br />
|-<br />
| 01EA<br />
| [[#GPUREG_01EA|GPUREG_01EA]]<br />
| <br />
|<br />
|-<br />
| 01EB<br />
| [[#GPUREG_01EB|GPUREG_01EB]]<br />
| <br />
|<br />
|-<br />
| 01EC<br />
| [[#GPUREG_01EC|GPUREG_01EC]]<br />
| <br />
|<br />
|-<br />
| 01ED<br />
| [[#GPUREG_01ED|GPUREG_01ED]]<br />
| <br />
|<br />
|-<br />
| 01EE<br />
| [[#GPUREG_01EE|GPUREG_01EE]]<br />
| <br />
|<br />
|-<br />
| 01EF<br />
| [[#GPUREG_01EF|GPUREG_01EF]]<br />
| <br />
|<br />
|-<br />
| 01F0<br />
| [[#GPUREG_01F0|GPUREG_01F0]]<br />
| <br />
|<br />
|-<br />
| 01F1<br />
| [[#GPUREG_01F1|GPUREG_01F1]]<br />
| <br />
|<br />
|-<br />
| 01F2<br />
| [[#GPUREG_01F2|GPUREG_01F2]]<br />
| <br />
|<br />
|-<br />
| 01F3<br />
| [[#GPUREG_01F3|GPUREG_01F3]]<br />
| <br />
|<br />
|-<br />
| 01F4<br />
| [[#GPUREG_01F4|GPUREG_01F4]]<br />
| <br />
|<br />
|-<br />
| 01F5<br />
| [[#GPUREG_01F5|GPUREG_01F5]]<br />
| <br />
|<br />
|-<br />
| 01F6<br />
| [[#GPUREG_01F6|GPUREG_01F6]]<br />
| <br />
|<br />
|-<br />
| 01F7<br />
| [[#GPUREG_01F7|GPUREG_01F7]]<br />
| <br />
|<br />
|-<br />
| 01F8<br />
| [[#GPUREG_01F8|GPUREG_01F8]]<br />
| <br />
|<br />
|-<br />
| 01F9<br />
| [[#GPUREG_01F9|GPUREG_01F9]]<br />
| <br />
|<br />
|-<br />
| 01FA<br />
| [[#GPUREG_01FA|GPUREG_01FA]]<br />
| <br />
|<br />
|-<br />
| 01FB<br />
| [[#GPUREG_01FB|GPUREG_01FB]]<br />
| <br />
|<br />
|-<br />
| 01FC<br />
| [[#GPUREG_01FC|GPUREG_01FC]]<br />
| <br />
|<br />
|-<br />
| 01FD<br />
| [[#GPUREG_01FD|GPUREG_01FD]]<br />
| <br />
|<br />
|-<br />
| 01FE<br />
| [[#GPUREG_01FE|GPUREG_01FE]]<br />
| <br />
|<br />
|-<br />
| 01FF<br />
| [[#GPUREG_01FF|GPUREG_01FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Geometry pipeline registers (0x200-0x27F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0200<br />
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR<br />
|-<br />
| 0201<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS0<br />
|-<br />
| 0202<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS1<br />
|-<br />
| 0203<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET<br />
|-<br />
| 0204<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT0<br />
|-<br />
| 0205<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT1<br />
|-<br />
| 0206<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0207<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0208<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0209<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020B<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020C<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020E<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020F<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0210<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0211<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0212<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0213<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0214<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0215<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0216<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0217<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0218<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0219<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021B<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021C<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021E<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021F<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0220<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0221<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0222<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0223<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0224<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0225<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0226<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0227<br />
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET<br />
|-<br />
| 0228<br />
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]<br />
| <br />
|PICA_REG_DRAW_VERTEX_NUM<br />
|-<br />
| 0229<br />
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]<br />
| ?<br />
|PICA_REG_DRAW_MODE0<br />
|-<br />
| 022A<br />
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]<br />
|<br />
|PICA_REG_DRAW_VERTEX_OFFSET<br />
|-<br />
| 022B<br />
| [[#GPUREG_022B|GPUREG_022B]]<br />
| <br />
|<br />
|-<br />
| 022C<br />
| [[#GPUREG_022C|GPUREG_022C]]<br />
| <br />
|<br />
|-<br />
| 022D<br />
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]<br />
| <br />
|PICA_REG_POST_VERTEX_CACHE_NUM<br />
|-<br />
| 022E<br />
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]<br />
|<br />
|PICA_REG_START_DRAW_ARRAY<br />
|-<br />
| 022F<br />
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]<br />
|<br />
|PICA_REG_START_DRAW_ELEMENT<br />
|-<br />
| 0230<br />
| [[#GPUREG_0230|GPUREG_0230]]<br />
| <br />
|<br />
|-<br />
| 0231<br />
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]<br />
|?<br />
|PICA_REG_VTX_FUNC<br />
|-<br />
| 0232<br />
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR<br />
|-<br />
| 0233<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA0<br />
|-<br />
| 0234<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA1<br />
|-<br />
| 0235<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA2<br />
|-<br />
| 0236<br />
| [[#GPUREG_0236|GPUREG_0236]]<br />
| <br />
|<br />
|-<br />
| 0237<br />
| [[#GPUREG_0237|GPUREG_0237]]<br />
| <br />
|<br />
|-<br />
| 0238<br />
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH0<br />
|-<br />
| 0239<br />
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH1<br />
|-<br />
| 023A<br />
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH0<br />
|-<br />
| 023B<br />
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH1<br />
|-<br />
| 023C<br />
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH0<br />
|-<br />
| 023D<br />
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH1<br />
|-<br />
| 023E<br />
| [[#GPUREG_023E|GPUREG_023E]]<br />
| <br />
|<br />
|-<br />
| 023F<br />
| [[#GPUREG_023F|GPUREG_023F]]<br />
| <br />
|<br />
|-<br />
| 0240<br />
| [[#GPUREG_0240|GPUREG_0240]]<br />
| <br />
|<br />
|-<br />
| 0241<br />
| [[#GPUREG_0241|GPUREG_0241]]<br />
| <br />
|<br />
|-<br />
| 0242<br />
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]<br />
|?<br />
|PICA_REG_VS_ATTR_NUM1<br />
|-<br />
| 0243<br />
| [[#GPUREG_0243|GPUREG_0243]]<br />
| <br />
|<br />
|-<br />
| 0244<br />
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]<br />
|?<br />
|PICA_REG_VS_COM_MODE<br />
|-<br />
| 0245<br />
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC0<br />
|-<br />
| 0246<br />
| [[#GPUREG_0246|GPUREG_0246]]<br />
| <br />
|<br />
|-<br />
| 0247<br />
| [[#GPUREG_0247|GPUREG_0247]]<br />
| <br />
|<br />
|-<br />
| 0248<br />
| [[#GPUREG_0248|GPUREG_0248]]<br />
| <br />
|<br />
|-<br />
| 0249<br />
| [[#GPUREG_0249|GPUREG_0249]]<br />
| <br />
|<br />
|-<br />
| 024A<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM1<br />
|-<br />
| 024B<br />
| [[#GPUREG_024B|GPUREG_024B]]<br />
|<br />
|<br />
|-<br />
| 024C<br />
| [[#GPUREG_024C|GPUREG_024C]]<br />
| <br />
|<br />
|-<br />
| 024D<br />
| [[#GPUREG_024D|GPUREG_024D]]<br />
| <br />
|<br />
|-<br />
| 024E<br />
| [[#GPUREG_024E|GPUREG_024E]]<br />
| <br />
|<br />
|-<br />
| 024F<br />
| [[#GPUREG_024F|GPUREG_024F]]<br />
| <br />
|<br />
|-<br />
| 0250<br />
| [[#GPUREG_0250|GPUREG_0250]]<br />
| <br />
|<br />
|-<br />
| 0251<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM2<br />
|-<br />
| 0252<br />
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]<br />
|?<br />
|PICA_REG_GS_MISC_REG0<br />
|-<br />
| 0253<br />
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]<br />
|?<br />
|PICA_REG_DRAW_MODE1<br />
|-<br />
| 0254<br />
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]<br />
|?<br />
|PICA_REG_GS_MISC_REG1<br />
|-<br />
| 0255<br />
| [[#GPUREG_0255|GPUREG_0255]]<br />
| <br />
|<br />
|-<br />
| 0256<br />
| [[#GPUREG_0256|GPUREG_0256]]<br />
| <br />
|<br />
|-<br />
| 0257<br />
| [[#GPUREG_0257|GPUREG_0257]]<br />
| <br />
|<br />
|-<br />
| 0258<br />
| [[#GPUREG_0258|GPUREG_0258]]<br />
| <br />
|<br />
|-<br />
| 0259<br />
| [[#GPUREG_0259|GPUREG_0259]]<br />
| <br />
|<br />
|-<br />
| 025A<br />
| [[#GPUREG_025A|GPUREG_025A]]<br />
| <br />
|<br />
|-<br />
| 025B<br />
| [[#GPUREG_025B|GPUREG_025B]]<br />
| <br />
|<br />
|-<br />
| 025C<br />
| [[#GPUREG_025C|GPUREG_025C]]<br />
| <br />
|<br />
|-<br />
| 025D<br />
| [[#GPUREG_025D|GPUREG_025D]]<br />
| <br />
|<br />
|-<br />
| 025E<br />
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]<br />
| ?<br />
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3<br />
|-<br />
| 025F<br />
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC1<br />
|-<br />
| 0260<br />
| [[#GPUREG_0260|GPUREG_0260]]<br />
| <br />
|<br />
|-<br />
| 0261<br />
| [[#GPUREG_0261|GPUREG_0261]]<br />
| <br />
|<br />
|-<br />
| 0262<br />
| [[#GPUREG_0262|GPUREG_0262]]<br />
| <br />
|<br />
|-<br />
| 0263<br />
| [[#GPUREG_0263|GPUREG_0263]]<br />
| <br />
|<br />
|-<br />
| 0264<br />
| [[#GPUREG_0264|GPUREG_0264]]<br />
| <br />
|<br />
|-<br />
| 0265<br />
| [[#GPUREG_0265|GPUREG_0265]]<br />
| <br />
|<br />
|-<br />
| 0266<br />
| [[#GPUREG_0266|GPUREG_0266]]<br />
| <br />
|<br />
|-<br />
| 0267<br />
| [[#GPUREG_0267|GPUREG_0267]]<br />
| <br />
|<br />
|-<br />
| 0268<br />
| [[#GPUREG_0268|GPUREG_0268]]<br />
| <br />
|<br />
|-<br />
| 0269<br />
| [[#GPUREG_0269|GPUREG_0269]]<br />
| <br />
|<br />
|-<br />
| 026A<br />
| [[#GPUREG_026A|GPUREG_026A]]<br />
| <br />
|<br />
|-<br />
| 026B<br />
| [[#GPUREG_026B|GPUREG_026B]]<br />
| <br />
|<br />
|-<br />
| 026C<br />
| [[#GPUREG_026C|GPUREG_026C]]<br />
| <br />
|<br />
|-<br />
| 026D<br />
| [[#GPUREG_026D|GPUREG_026D]]<br />
| <br />
|<br />
|-<br />
| 026E<br />
| [[#GPUREG_026E|GPUREG_026E]]<br />
| <br />
|<br />
|-<br />
| 026F<br />
| [[#GPUREG_026F|GPUREG_026F]]<br />
| <br />
|<br />
|-<br />
| 0270<br />
| [[#GPUREG_0270|GPUREG_0270]]<br />
| <br />
|<br />
|-<br />
| 0271<br />
| [[#GPUREG_0271|GPUREG_0271]]<br />
| <br />
|<br />
|-<br />
| 0272<br />
| [[#GPUREG_0272|GPUREG_0272]]<br />
| <br />
|<br />
|-<br />
| 0273<br />
| [[#GPUREG_0273|GPUREG_0273]]<br />
| <br />
|<br />
|-<br />
| 0274<br />
| [[#GPUREG_0274|GPUREG_0274]]<br />
| <br />
|<br />
|-<br />
| 0275<br />
| [[#GPUREG_0275|GPUREG_0275]]<br />
| <br />
|<br />
|-<br />
| 0276<br />
| [[#GPUREG_0276|GPUREG_0276]]<br />
| <br />
|<br />
|-<br />
| 0277<br />
| [[#GPUREG_0277|GPUREG_0277]]<br />
| <br />
|<br />
|-<br />
| 0278<br />
| [[#GPUREG_0278|GPUREG_0278]]<br />
| <br />
|<br />
|-<br />
| 0279<br />
| [[#GPUREG_0279|GPUREG_0279]]<br />
| <br />
|<br />
|-<br />
| 027A<br />
| [[#GPUREG_027A|GPUREG_027A]]<br />
| <br />
|<br />
|-<br />
| 027B<br />
| [[#GPUREG_027B|GPUREG_027B]]<br />
| <br />
|<br />
|-<br />
| 027C<br />
| [[#GPUREG_027C|GPUREG_027C]]<br />
| <br />
|<br />
|-<br />
| 027D<br />
| [[#GPUREG_027D|GPUREG_027D]]<br />
| <br />
|<br />
|-<br />
| 027E<br />
| [[#GPUREG_027E|GPUREG_027E]]<br />
| <br />
|<br />
|-<br />
| 027F<br />
| [[#GPUREG_027F|GPUREG_027F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Shader registers (0x280-0x2DF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
! colspan=4 | Geometry shader<br />
|-<br />
| 0280<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_GS_BOOL<br />
|-<br />
| 0281<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_GS_INT0<br />
|-<br />
| 0282<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_GS_INT1<br />
|-<br />
| 0283<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_GS_INT2<br />
|-<br />
| 0284<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_GS_INT3<br />
|-<br />
| 0285<br />
| [[#GPUREG_0285|GPUREG_0285]]<br />
| <br />
|<br />
|-<br />
| 0286<br />
| [[#GPUREG_0286|GPUREG_0286]]<br />
| <br />
|<br />
|-<br />
| 0287<br />
| [[#GPUREG_0287|GPUREG_0287]]<br />
| <br />
|<br />
|-<br />
| 0288<br />
| [[#GPUREG_0288|GPUREG_0288]]<br />
| <br />
|<br />
|-<br />
| 0289<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_GS_ATTR_NUM<br />
|-<br />
| 028A<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_GS_START_ADDR<br />
|-<br />
| 028B<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP0<br />
|-<br />
| 028C<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP1<br />
|-<br />
| 028D<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_GS_OUT_REG_MASK<br />
|-<br />
| 028E<br />
| [[#GPUREG_028E|GPUREG_028E]]<br />
| <br />
|<br />
|-<br />
| 028F<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_GS_PROG_RENEWAL_END<br />
|-<br />
| 0290<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_GS_FLOAT_ADDR<br />
|-<br />
| 0291<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA0<br />
|-<br />
| 0292<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA1<br />
|-<br />
| 0293<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA2<br />
|-<br />
| 0294<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA3<br />
|-<br />
| 0295<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA4<br />
|-<br />
| 0296<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA5<br />
|-<br />
| 0297<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA6<br />
|-<br />
| 0298<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA7<br />
|-<br />
| 0299<br />
| [[#GPUREG_0299|GPUREG_0299]]<br />
| <br />
|<br />
|-<br />
| 029A<br />
| [[#GPUREG_029A|GPUREG_029A]]<br />
| <br />
|<br />
|-<br />
| 029B<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_GS_PROG_ADDR<br />
|-<br />
| 029C<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_DATA0<br />
|-<br />
| 029D<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_DATA1<br />
|-<br />
| 029E<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_DATA2<br />
|-<br />
| 029F<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_DATA3<br />
|-<br />
| 02A0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_DATA4<br />
|-<br />
| 02A1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_DATA5<br />
|-<br />
| 02A2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_DATA6<br />
|-<br />
| 02A3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_DATA7<br />
|-<br />
| 02A4<br />
| [[#GPUREG_02A4|GPUREG_02A4]]<br />
| <br />
|<br />
|-<br />
| 02A5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02A6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02A7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02A8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02A9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02AA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02AB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02AC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02AD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02AE<br />
| [[#GPUREG_02AE|GPUREG_02AE]]<br />
| <br />
|<br />
|-<br />
| 02AF<br />
| [[#GPUREG_02AF|GPUREG_02AF]]<br />
| <br />
|<br />
|-<br />
! colspan=4 | Vertex shader<br />
|-<br />
| 02B0<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_VS_BOOL<br />
|-<br />
| 02B1<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_VS_INT0<br />
|-<br />
| 02B2<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_VS_INT1<br />
|-<br />
| 02B3<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_VS_INT2<br />
|-<br />
| 02B4<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_VS_INT3<br />
|-<br />
| 02B5<br />
| [[#GPUREG_02B5|GPUREG_02B5]]<br />
| <br />
|<br />
|-<br />
| 02B6<br />
| [[#GPUREG_02B6|GPUREG_02B6]]<br />
| <br />
|<br />
|-<br />
| 02B7<br />
| [[#GPUREG_02B7|GPUREG_02B7]]<br />
| <br />
|<br />
|-<br />
| 02B8<br />
| [[#GPUREG_02B8|GPUREG_02B8]]<br />
| <br />
|<br />
|-<br />
| 02B9<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_VS_ATTR_NUM0<br />
|-<br />
| 02BA<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_VS_START_ADDR<br />
|-<br />
| 02BB<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP0<br />
|-<br />
| 02BC<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP1<br />
|-<br />
| 02BD<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_VS_OUT_REG_MASK<br />
|-<br />
| 02BE<br />
| [[#GPUREG_02BE|GPUREG_02BE]]<br />
| <br />
|<br />
|-<br />
| 02BF<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_VS_PROG_RENEWAL_END<br />
|-<br />
| 02C0<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_VS_FLOAT_ADDR<br />
|-<br />
| 02C1<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA0<br />
|-<br />
| 02C2<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA1<br />
|-<br />
| 02C3<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA2<br />
|-<br />
| 02C4<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA3<br />
|-<br />
| 02C5<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA4<br />
|-<br />
| 02C6<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA5<br />
|-<br />
| 02C7<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA6<br />
|-<br />
| 02C8<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA7<br />
|-<br />
| 02C9<br />
| [[#GPUREG_02C9|GPUREG_02C9]]<br />
| <br />
|<br />
|-<br />
| 02CA<br />
| [[#GPUREG_02CA|GPUREG_02CA]]<br />
| <br />
|<br />
|-<br />
| 02CB<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_ADDR<br />
|-<br />
| 02CC<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_DATA0<br />
|-<br />
| 02CD<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_DATA1<br />
|-<br />
| 02CE<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_DATA2<br />
|-<br />
| 02CF<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_DATA3<br />
|-<br />
| 02D0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_DATA4<br />
|-<br />
| 02D1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_DATA5<br />
|-<br />
| 02D2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_DATA6<br />
|-<br />
| 02D3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_DATA7<br />
|-<br />
| 02D4<br />
| [[#GPUREG_02D4|GPUREG_02D4]]<br />
| <br />
|<br />
|-<br />
| 02D5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02D6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02D7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02D8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02D9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02DA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02DB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02DC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02DD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02DE<br />
| [[#GPUREG_02DE|GPUREG_02DE]]<br />
| <br />
|<br />
|-<br />
| 02DF<br />
| [[#GPUREG_02DF|GPUREG_02DF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Unknown registers (0x2E0-0x2FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 02E0<br />
| [[#GPUREG_02E0|GPUREG_02E0]]<br />
| <br />
|<br />
|-<br />
| 02E1<br />
| [[#GPUREG_02E1|GPUREG_02E1]]<br />
| <br />
|<br />
|-<br />
| 02E2<br />
| [[#GPUREG_02E2|GPUREG_02E2]]<br />
| <br />
|<br />
|-<br />
| 02E3<br />
| [[#GPUREG_02E3|GPUREG_02E3]]<br />
| <br />
|<br />
|-<br />
| 02E4<br />
| [[#GPUREG_02E4|GPUREG_02E4]]<br />
| <br />
|<br />
|-<br />
| 02E5<br />
| [[#GPUREG_02E5|GPUREG_02E5]]<br />
| <br />
|<br />
|-<br />
| 02E6<br />
| [[#GPUREG_02E6|GPUREG_02E6]]<br />
| <br />
|<br />
|-<br />
| 02E7<br />
| [[#GPUREG_02E7|GPUREG_02E7]]<br />
| <br />
|<br />
|-<br />
| 02E8<br />
| [[#GPUREG_02E8|GPUREG_02E8]]<br />
| <br />
|<br />
|-<br />
| 02E9<br />
| [[#GPUREG_02E9|GPUREG_02E9]]<br />
| <br />
|<br />
|-<br />
| 02EA<br />
| [[#GPUREG_02EA|GPUREG_02EA]]<br />
| <br />
|<br />
|-<br />
| 02EB<br />
| [[#GPUREG_02EB|GPUREG_02EB]]<br />
| <br />
|<br />
|-<br />
| 02EC<br />
| [[#GPUREG_02EC|GPUREG_02EC]]<br />
| <br />
|<br />
|-<br />
| 02ED<br />
| [[#GPUREG_02ED|GPUREG_02ED]]<br />
| <br />
|<br />
|-<br />
| 02EE<br />
| [[#GPUREG_02EE|GPUREG_02EE]]<br />
| <br />
|<br />
|-<br />
| 02EF<br />
| [[#GPUREG_02EF|GPUREG_02EF]]<br />
| <br />
|<br />
|-<br />
| 02F0<br />
| [[#GPUREG_02F0|GPUREG_02F0]]<br />
| <br />
|<br />
|-<br />
| 02F1<br />
| [[#GPUREG_02F1|GPUREG_02F1]]<br />
| <br />
|<br />
|-<br />
| 02F2<br />
| [[#GPUREG_02F2|GPUREG_02F2]]<br />
| <br />
|<br />
|-<br />
| 02F3<br />
| [[#GPUREG_02F3|GPUREG_02F3]]<br />
| <br />
|<br />
|-<br />
| 02F4<br />
| [[#GPUREG_02F4|GPUREG_02F4]]<br />
| <br />
|<br />
|-<br />
| 02F5<br />
| [[#GPUREG_02F5|GPUREG_02F5]]<br />
| <br />
|<br />
|-<br />
| 02F6<br />
| [[#GPUREG_02F6|GPUREG_02F6]]<br />
| <br />
|<br />
|-<br />
| 02F7<br />
| [[#GPUREG_02F7|GPUREG_02F7]]<br />
| <br />
|<br />
|-<br />
| 02F8<br />
| [[#GPUREG_02F8|GPUREG_02F8]]<br />
| <br />
|<br />
|-<br />
| 02F9<br />
| [[#GPUREG_02F9|GPUREG_02F9]]<br />
| <br />
|<br />
|-<br />
| 02FA<br />
| [[#GPUREG_02FA|GPUREG_02FA]]<br />
| <br />
|<br />
|-<br />
| 02FB<br />
| [[#GPUREG_02FB|GPUREG_02FB]]<br />
| <br />
|<br />
|-<br />
| 02FC<br />
| [[#GPUREG_02FC|GPUREG_02FC]]<br />
| <br />
|<br />
|-<br />
| 02FD<br />
| [[#GPUREG_02FD|GPUREG_02FD]]<br />
| <br />
|<br />
|-<br />
| 02FE<br />
| [[#GPUREG_02FE|GPUREG_02FE]]<br />
| <br />
|<br />
|-<br />
| 02FF<br />
| [[#GPUREG_02FF|GPUREG_02FF]]<br />
| <br />
|<br />
|}<br />
<br />
== Miscellaneous registers ==<br />
<br />
=== GPUREG_FINALIZE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)<br />
|}<br />
<br />
Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.<br />
Failure to write to this register in any command buffer will result in the GPU hanging.<br />
<br />
== Rasterizer registers ==<br />
<br />
=== GPUREG_FACECULLING_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Culling mode<br />
|}<br />
<br />
This register is used to configure the face culling mode.<br />
<br />
Culling mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Front Face (Counter Clockwise)<br />
|-<br />
| 2<br />
| Back Face (Counter Clockwise)<br />
|}<br />
<br />
=== GPUREG_VIEWPORT_WIDTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, width / 2<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.<br />
<br />
=== GPUREG_VIEWPORT_INVW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / width<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.<br />
<br />
=== GPUREG_VIEWPORT_HEIGHT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, height / 2<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.<br />
<br />
=== GPUREG_VIEWPORT_INVH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / height<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.<br />
<br />
=== GPUREG_FRAGOP_CLIP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable clipping planes.<br />
<br />
=== GPUREG_FRAGOP_CLIP_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Clipping plane coefficient ''i''<br />
|}<br />
<br />
This register is used to configure clipping plane coefficients.<br />
<br />
=== GPUREG_DEPTHMAP_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near - Far<br />
|}<br />
<br />
This register is used to configure the depth range scale.<br />
<br />
=== GPUREG_DEPTHMAP_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near + Polygon Offset<br />
|}<br />
<br />
This register is used to configure the depth range bias.<br />
<br />
=== GPUREG_SH_OUTMAP_TOTAL ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of following attributes<br />
|}<br />
<br />
This register is used to configure the total shader output map attributes.<br />
<br />
=== GPUREG_SH_OUTMAP_O''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Semantic for the x component of the register.<br />
|-<br />
| 8-12<br />
| unsigned, Semantic for the y component of the register.<br />
|-<br />
| 16-20<br />
| unsigned, Semantic for the z component of the register.<br />
|-<br />
| 24-28<br />
| unsigned, Semantic for the w component of the register.<br />
|}<br />
<br />
These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.<br />
<br />
Semantic values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Semantic<br />
! Description<br />
|-<br />
| 0x00<br />
| position.x<br />
| rowspan="4" | Vertex Position<br />
|-<br />
| 0x01<br />
| position.y<br />
|-<br />
| 0x02<br />
| position.z<br />
|-<br />
| 0x03<br />
| position.w<br />
|-<br />
| 0x04<br />
| normquat.x<br />
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)<br />
|-<br />
| 0x05<br />
| normquat.y<br />
|-<br />
| 0x06<br />
| normquat.z<br />
|-<br />
| 0x07<br />
| normquat.w<br />
|-<br />
| 0x08<br />
| color.r<br />
| rowspan="4" | Vertex color<br />
|-<br />
| 0x09<br />
| color.g<br />
|-<br />
| 0x0A<br />
| color.b<br />
|-<br />
| 0x0B<br />
| color.a<br />
|-<br />
| 0x0C<br />
| texcoord0.u<br />
| rowspan="2" | Texture coordinates for texture 0<br />
|-<br />
| 0x0D<br />
| texcoord0.v<br />
|-<br />
| 0x0E<br />
| texcoord1.u<br />
| rowspan="2" | Texture coordinates for texture 1<br />
|-<br />
| 0x0F<br />
| texcoord1.v<br />
|-<br />
| 0x10<br />
| texcoord0.w<br />
|<br />
<br />
|-<br />
| 0x12<br />
| view.x<br />
| rowspan="3" | View vector (for fragment lighting)<br />
|-<br />
| 0x13<br />
| view.y<br />
|-<br />
| 0x14<br />
| view.z<br />
<br />
|-<br />
| 0x16<br />
| texcoord2.u<br />
| rowspan="2" | Texture coordinates for texture 2<br />
|-<br />
| 0x17<br />
| texcoord2.v<br />
<br />
|-<br />
| 0x1F<br />
| Unused component<br />
| Should be set for unused components of the output register<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Early depth function<br />
|}<br />
<br />
This register configures the early depth test function.<br />
<br />
Early depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| >=<br />
|-<br />
| 1<br />
| ><br />
|-<br />
| 2<br />
| <=<br />
|-<br />
| 3<br />
| <<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether the early depth test is enabled.<br />
<br />
=== GPUREG_EARLYDEPTH_CLEAR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = clear)<br />
|}<br />
<br />
This register triggers clearing the early depth data.<br />
<br />
=== GPUREG_SH_OUTATTR_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Use texture coordinates (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register is used to configure the shader output attribute mode.<br />
<br />
=== GPUREG_SCISSORTEST_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Enabled (0 = disabled, 3 = enabled)<br />
|}<br />
<br />
This register is used to enable scissor testing.<br />
<br />
=== GPUREG_SCISSORTEST_POS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X1<br />
|-<br />
| 16-25<br />
| unsigned, Y1<br />
|}<br />
<br />
This register is used to configure the scissor test start position.<br />
<br />
=== GPUREG_SCISSORTEST_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X2<br />
|-<br />
| 16-25<br />
| unsigned, Y2<br />
|}<br />
<br />
This register is used to configure the scissor test end position.<br />
<br />
=== GPUREG_VIEWPORT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| signed, X<br />
|-<br />
| 16-25<br />
| signed, Y<br />
|}<br />
<br />
This register is used to configure the viewport position.<br />
<br />
=== GPUREG_EARLYDEPTH_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| unsigned, Clear value<br />
|}<br />
<br />
This register is used to configure the early depth clear value.<br />
<br />
=== GPUREG_DEPTHMAP_ENABLE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable depth range.<br />
<br />
=== GPUREG_RENDERBUF_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register is used to configure the output framebuffer dimensions.<br />
<br />
=== GPUREG_SH_OUTATTR_CLOCK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, 'position.z' present (0 = absent, 1 = present)<br />
|-<br />
| 1<br />
| unsigned, 'color' component present (0 = absent, 1 = present)<br />
|-<br />
| 8<br />
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)<br />
|-<br />
| 9<br />
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)<br />
|-<br />
| 10<br />
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)<br />
|-<br />
| 16<br />
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)<br />
|-<br />
| 24<br />
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)<br />
|}<br />
<br />
This register controls the clock supply to parts relating to certain attributes.<br />
<br />
== Texturing registers ==<br />
<br />
=== GPUREG_TEXUNIT_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| 0x0<br />
|-<br />
| 8-9<br />
| unsigned, Texture 3 coordinates<br />
|-<br />
| 10<br />
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| 0x1<br />
|-<br />
| 13<br />
| unsigned, Texture 2 coordinates<br />
|-<br />
| 16<br />
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)<br />
|-<br />
| 17-31<br />
| 0x0<br />
|}<br />
<br />
This register is used to enable texture units.<br />
<br />
Texture 3 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 0<br />
|-<br />
| 1<br />
| Texture 1<br />
|-<br />
| 2<br />
| Texture 2<br />
|}<br />
<br />
Texture 2 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 2<br />
|-<br />
| 1<br />
| Texture 1<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to set a texture unit's border color.<br />
<br />
=== GPUREG_TEXUNIT''i''_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Height<br />
|-<br />
| 16-26<br />
| unsigned, Width<br />
|}<br />
<br />
This register is used to set a texture unit's dimensions.<br />
<br />
=== GPUREG_TEXUNIT''i''_PARAM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, Magnification filter<br />
|-<br />
| 2<br />
| unsigned, Minification filter<br />
|-<br />
| 4-5<br />
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4<br />
|-<br />
| 8-10<br />
| unsigned, Wrap T<br />
|-<br />
| 12-14<br />
| unsigned, Wrap S<br />
|-<br />
| 16-17<br />
| 0x0<br />
|-<br />
| 20<br />
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)<br />
|-<br />
| 24<br />
| unsigned, Mipmap filter<br />
|-<br />
| 28-30<br />
| unsigned, Type (Texture 0 only)<br />
|}<br />
<br />
This register is used to set a texture unit's extra parameters.<br />
<br />
Filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|}<br />
<br />
Wrap values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to edge<br />
|-<br />
| 1<br />
| Clamp to border<br />
|-<br />
| 2<br />
| Repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|}<br />
<br />
Type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 2D<br />
|-<br />
| 1<br />
| Cube map<br />
|-<br />
| 2<br />
| Shadow 2D<br />
|-<br />
| 3<br />
| Projection<br />
|-<br />
| 4<br />
| Shadow cube<br />
|-<br />
| 5<br />
| Disabled<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_LOD ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.4.8, Bias<br />
|-<br />
| 16-19<br />
| unsigned, Max Level<br />
|-<br />
| 24-27<br />
| unsigned, Min Level<br />
|}<br />
<br />
This register is used to configure a texture unit's level of detail.<br />
<br />
=== GPUREG_TEXUNIT''i''_ADDR''i'' ===<br />
<br />
First ADDR register:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Texture physical address >> 3<br />
|}<br />
<br />
Subsequent ADDR registers:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-21<br />
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)<br />
|}<br />
<br />
This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.<br />
<br />
If the texture is a cube:<br />
<br />
{| class="wikitable" border="1"<br />
! Register<br />
! Description<br />
|-<br />
| ADDR1<br />
| Positive X<br />
|-<br />
| ADDR2<br />
| Negative X<br />
|-<br />
| ADDR3<br />
| Positive Y<br />
|-<br />
| ADDR4<br />
| Negative Y<br />
|-<br />
| ADDR5<br />
| Positive Z<br />
|-<br />
| ADDR6<br />
| Negative Z<br />
|}<br />
<br />
Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.<br />
<br />
=== GPUREG_TEXUNIT''i''_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Perspective (0 = perspective, 1 = not perspective)<br />
|-<br />
| 1-23<br />
| fixed0.0.24, Z bias (upper 23 bits)<br />
|}<br />
<br />
This register is used to set a texture unit's shadow texture properties.<br />
<br />
=== GPUREG_TEXUNIT''i''_TYPE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Format<br />
|}<br />
<br />
This register is used to set a texture unit's data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! GL Format<br />
! GL Data Type<br />
|-<br />
| 0x0<br />
| RGBA8888<br />
| GL_RGBA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x1<br />
| RGB888<br />
| GL_RGB<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x2<br />
| RGBA5551<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_5_5_5_1<br />
|-<br />
| 0x3<br />
| RGB565<br />
| GL_RGB<br />
| GL_UNSIGNED_SHORT_5_6_5<br />
|-<br />
| 0x4<br />
| RGBA4444<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_4_4_4_4<br />
|-<br />
| 0x5<br />
| IA8<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x6<br />
| HILO8<br />
| <br />
| <br />
|-<br />
| 0x7<br />
| I8<br />
| GL_LUMINANCE<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x8<br />
| A8<br />
| GL_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x9<br />
| IA44<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE_4_4_EXT<br />
|-<br />
| 0xA<br />
| I4<br />
| <br />
|<br />
|-<br />
| 0xB<br />
| A4<br />
| GL_ALPHA<br />
| GL_UNSIGNED_NIBBLE_EXT<br />
|-<br />
| 0xC<br />
| ETC1<br />
| GL_ETC1_RGB8_OES<br />
| <br />
|-<br />
| 0xD<br />
| ETC1A4<br />
|<br />
| <br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable lighting.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, U-direction clamp<br />
|-<br />
| 3-5<br />
| unsigned, V-direction clamp<br />
|-<br />
| 6-9<br />
| unsigned, RGB mapping function<br />
|-<br />
| 10-13<br />
| unsigned, Alpha mapping function<br />
|-<br />
| 14<br />
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)<br />
|-<br />
| 15<br />
| unsigned, Noise enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 16-17<br />
| unsigned, U-direction shift<br />
|-<br />
| 18-19<br />
| unsigned, V-direction shift<br />
|-<br />
| 20-27<br />
| float1.5.10, Texture bias (lower 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Clamp values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to zero<br />
|-<br />
| 1<br />
| Clamp to edge<br />
|-<br />
| 2<br />
| Symmetrical repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|-<br />
| 4<br />
| Pulse<br />
|}<br />
<br />
Mapping function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| U<br />
|-<br />
| 1<br />
| U²<br />
|-<br />
| 2<br />
| V<br />
|-<br />
| 3<br />
| V²<br />
|-<br />
| 4<br />
| (U + V) / 2<br />
|-<br />
| 5<br />
| (U² + V²) / 2<br />
|-<br />
| 6<br />
| sqrt(U² + V²)<br />
|-<br />
| 7<br />
| Minimum<br />
|-<br />
| 8<br />
| Maximum<br />
|-<br />
| 9<br />
| Rmax<br />
|}<br />
<br />
Shift values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Odd<br />
|-<br />
| 2<br />
| Even<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, U-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, U-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, V-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX3 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, U-direction noise frequency<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise frequency<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX4 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Minification filter<br />
|-<br />
| 3-10<br />
| 0x60<br />
|-<br />
| 11-18<br />
| unsigned, Texture width<br />
|-<br />
| 19-26<br />
| float1.5.10, Texture bias (upper 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Minification filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|-<br />
| 2<br />
| Nearest, Mipmap Nearest<br />
|-<br />
| 3<br />
| Linear, Mipmap Nearest<br />
|-<br />
| 4<br />
| Nearest, Mipmap Linear<br />
|-<br />
| 5<br />
| Linear, Mipmap Linear<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX5 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Texture offset<br />
|-<br />
| 8-31<br />
| 0xE0C080<br />
|}<br />
<br />
This register is used to set the procedural texture unit's offset.<br />
<br />
=== GPUREG_PROCTEX_LUT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Index<br />
|-<br />
| 8-11<br />
| unsigned, Reference table<br />
|}<br />
<br />
This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.<br />
<br />
Reference table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Noise table<br />
|-<br />
| 2<br />
| RGB mapping function table<br />
|-<br />
| 3<br />
| Alpha mapping function table<br />
|-<br />
| 4<br />
| Color table<br />
|-<br />
| 5<br />
| Color difference table<br />
|}<br />
<br />
=== GPUREG_PROCTEX_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.<br />
<br />
==== Noise Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== RGB Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Alpha Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Color Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
==== Color Difference Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| fixed1.0.7, Red difference between current and next color table elements<br />
|-<br />
| 8-15<br />
| fixed1.0.7, Green difference between current and next color table elements<br />
|-<br />
| 16-23<br />
| fixed1.0.7, Blue difference between current and next color table elements<br />
|-<br />
| 24-31<br />
| fixed1.0.7, Alpha difference between current and next color table elements<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_SOURCE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB source 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB source 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB source 2<br />
|-<br />
| 16-19<br />
| unsigned, Alpha source 0<br />
|-<br />
| 20-23<br />
| unsigned, Alpha source 1<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source 2<br />
|}<br />
<br />
This register configures a texture combiner's sources.<br />
<br />
Source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Primary color<br />
|-<br />
| 1<br />
| Fragment primary color<br />
|-<br />
| 2<br />
| Fragment secondary color<br />
|-<br />
| 3<br />
| Texture 0<br />
|-<br />
| 4<br />
| Texture 1<br />
|-<br />
| 5<br />
| Texture 2<br />
|-<br />
| 6<br />
| Texture 3<br />
|-<br />
| 13<br />
| Previous buffer<br />
|-<br />
| 14<br />
| Constant (from GPUREG_TEXENV''i''_COLOR)<br />
|-<br />
| 15<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_OPERAND ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB operand 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB operand 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB operand 2<br />
|-<br />
| 12-14<br />
| unsigned, Alpha operand 0<br />
|-<br />
| 16-18<br />
| unsigned, Alpha operand 1<br />
|-<br />
| 20-22<br />
| unsigned, Alpha operand 2<br />
|}<br />
<br />
This register configures a texture combiner's operands.<br />
<br />
RGB operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source color<br />
|-<br />
| 1<br />
| One minus source color<br />
|-<br />
| 2<br />
| Source alpha<br />
|-<br />
| 3<br />
| One minus source alpha<br />
|-<br />
| 4<br />
| Source red<br />
|-<br />
| 5<br />
| One minus source red<br />
|-<br />
| 8<br />
| Source green<br />
|-<br />
| 9<br />
| One minus source green<br />
|-<br />
| 12<br />
| Source blue<br />
|-<br />
| 13<br />
| One minus source blue<br />
|}<br />
<br />
Alpha operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source alpha<br />
|-<br />
| 1<br />
| One minus source alpha<br />
|-<br />
| 2<br />
| Source red<br />
|-<br />
| 3<br />
| One minus source red<br />
|-<br />
| 4<br />
| Source green<br />
|-<br />
| 5<br />
| One minus source green<br />
|-<br />
| 6<br />
| Source blue<br />
|-<br />
| 7<br />
| One minus source blue<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COMBINER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB combine<br />
|-<br />
| 16-19<br />
| unsigned, Alpha combine<br />
|}<br />
<br />
This register configures a texture combiner's combine mode.<br />
<br />
Combine values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Replace<br />
|-<br />
| 1<br />
| Modulate<br />
|-<br />
| 2<br />
| Add<br />
|-<br />
| 3<br />
| Add signed<br />
|-<br />
| 4<br />
| Interpolate<br />
|-<br />
| 5<br />
| Subtract<br />
|-<br />
| 6<br />
| Dot3 RGB<br />
|-<br />
| 7<br />
| Dot3 RGBA<br />
|-<br />
| 8<br />
| Multiply then add<br />
|-<br />
| 9<br />
| Add then multiply<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register configures a texture combiner's constant color.<br />
<br />
=== GPUREG_TEXENV''i''_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, RGB scale<br />
|-<br />
| 16-17<br />
| unsigned, Alpha scale<br />
|}<br />
<br />
This register configures a texture combiner's scale value.<br />
<br />
Scale values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|}<br />
<br />
=== GPUREG_TEXENV_UPDATE_BUFFER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fog mode<br />
|-<br />
| 3<br />
| unsigned, Shading density source<br />
|-<br />
| 8<br />
| unsigned, TexEnv 1 RGB buffer input<br />
|-<br />
| 9<br />
| unsigned, TexEnv 2 RGB buffer input<br />
|-<br />
| 10<br />
| unsigned, TexEnv 3 RGB buffer input<br />
|-<br />
| 11<br />
| unsigned, TexEnv 4 RGB buffer input<br />
|-<br />
| 12<br />
| unsigned, TexEnv 1 alpha buffer input<br />
|-<br />
| 13<br />
| unsigned, TexEnv 2 alpha buffer input<br />
|-<br />
| 14<br />
| unsigned, TexEnv 3 alpha buffer input<br />
|-<br />
| 15<br />
| unsigned, TexEnv 4 alpha buffer input<br />
|-<br />
| 16<br />
| unsigned, Z flip (0 = don't flip, 1 = flip)<br />
|-<br />
| 24-25<br />
| 0x0<br />
|}<br />
<br />
This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.<br />
<br />
Fog mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Disabled<br />
|-<br />
| 5<br />
| Fog<br />
|-<br />
| 7<br />
| Gas<br />
|}<br />
<br />
Shading density source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Plain density<br />
|-<br />
| 1<br />
| Depth density<br />
|}<br />
<br />
Buffer input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Previous buffer<br />
|-<br />
| 1<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_FOG_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
This register is used to configure the color of fog.<br />
<br />
=== GPUREG_GAS_ATTENUATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas density attenuation<br />
|}<br />
<br />
This register is used to configure the gas density attenuation.<br />
<br />
=== GPUREG_GAS_ACCMAX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas maximum density accumulation<br />
|}<br />
<br />
This register is used to configure the gas maximum density accumulation.<br />
<br />
=== GPUREG_FOG_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.<br />
<br />
=== GPUREG_FOG_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.<br />
<br />
==== Fog Look-Up Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Difference from next element <br />
|-<br />
| 13-23<br />
| fixed0.0.11, Value<br />
|}<br />
<br />
=== GPUREG_TEXENV_BUFFER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the texture combiner buffer color.<br />
<br />
== Framebuffer registers ==<br />
<br />
=== GPUREG_COLOR_OPERATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Fragment operation mode<br />
|-<br />
| 8<br />
| unsigned, Blend mode<br />
|-<br />
| 16-25<br />
| 0x0E4<br />
|}<br />
<br />
This register is used to configure the fragment operation mode and whether to use logic ops or blending.<br />
<br />
Fragment operation mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Default<br />
|-<br />
| 1<br />
| Gas<br />
|-<br />
| 3<br />
| Shadow<br />
|}<br />
<br />
Blend mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Logic op<br />
|-<br />
| 1<br />
| Blend<br />
|}<br />
<br />
=== GPUREG_BLEND_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, RGB equation<br />
|-<br />
| 8-10<br />
| unsigned, Alpha equation<br />
|-<br />
| 16-19<br />
| unsigned, RGB source function<br />
|-<br />
| 20-23<br />
| unsigned, RGB destination function<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source function<br />
|-<br />
| 28-31<br />
| unsigned, Alpha destination function<br />
|}<br />
<br />
This register is used to configure the blending function.<br />
<br />
Equation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Add<br />
|-<br />
| 1<br />
| Subtract<br />
|-<br />
| 2<br />
| Reverse subtract<br />
|-<br />
| 3<br />
| Minimum<br />
|-<br />
| 4<br />
| Maximum<br />
|}<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Zero<br />
|-<br />
| 1<br />
| One<br />
|-<br />
| 2<br />
| Source color<br />
|-<br />
| 3<br />
| One minus source color<br />
|-<br />
| 4<br />
| Destination color<br />
|-<br />
| 5<br />
| One minus destination color<br />
|-<br />
| 6<br />
| Source alpha<br />
|-<br />
| 7<br />
| One minus source alpha<br />
|-<br />
| 8<br />
| Destination alpha<br />
|-<br />
| 9<br />
| One minus destination alpha<br />
|-<br />
| 10<br />
| Constant color<br />
|-<br />
| 11<br />
| One minus constant color<br />
|-<br />
| 12<br />
| Constant alpha<br />
|-<br />
| 13<br />
| One minus constant alpha<br />
|-<br />
| 14<br />
| Source alpha saturate<br />
|}<br />
<br />
=== GPUREG_LOGIC_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Logic op<br />
|}<br />
<br />
This register is used to configure the logic op.<br />
<br />
Logic op values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clear<br />
|-<br />
| 1<br />
| AND<br />
|-<br />
| 2<br />
| Reverse AND<br />
|-<br />
| 3<br />
| Copy<br />
|-<br />
| 4<br />
| Set<br />
|-<br />
| 5<br />
| Inverted copy<br />
|-<br />
| 6<br />
| Noop<br />
|-<br />
| 7<br />
| Invert<br />
|-<br />
| 8<br />
| NAND<br />
|-<br />
| 9<br />
| OR<br />
|-<br />
| 10<br />
| NOR<br />
|-<br />
| 11<br />
| XOR<br />
|-<br />
| 12<br />
| Equivalent<br />
|-<br />
| 13<br />
| Inverted AND<br />
|-<br />
| 14<br />
| Reverse OR<br />
|-<br />
| 15<br />
| Inverted OR<br />
|}<br />
<br />
=== GPUREG_BLEND_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the blending color.<br />
<br />
=== GPUREG_FRAGOP_ALPHA_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Reference value<br />
|}<br />
<br />
This register is used to configure alpha testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Buffer mask<br />
|-<br />
| 16-23<br />
| signed, Reference value<br />
|-<br />
| 24-31<br />
| unsigned, Mask<br />
|}<br />
<br />
This register is used to configure stencil testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fail operation<br />
|-<br />
| 4-6<br />
| unsigned, Z-fail operation<br />
|-<br />
| 8-10<br />
| unsigned, Z-pass operation<br />
|}<br />
<br />
This register is used to configure stencil result operations.<br />
<br />
Operation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Keep<br />
|-<br />
| 1<br />
| Zero<br />
|-<br />
| 2<br />
| Replace<br />
|-<br />
| 3<br />
| Increment<br />
|-<br />
| 4<br />
| Decrement<br />
|-<br />
| 5<br />
| Invert<br />
|-<br />
| 6<br />
| Increment and wrap<br />
|-<br />
| 7<br />
| Decrement and wrap<br />
|}<br />
<br />
=== GPUREG_DEPTH_COLOR_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Depth function<br />
|-<br />
| 8<br />
| unsigned, Red write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 9<br />
| unsigned, Green write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 10<br />
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 11<br />
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to depth testing and framebuffer write masking.<br />
<br />
Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.<br />
<br />
Depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_FRAMEBUFFER_INVALIDATE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = invalidate)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.<br />
<br />
=== GPUREG_FRAMEBUFFER_FLUSH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = flush)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.<br />
<br />
=== GPUREG_COLORBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow read (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures read access from the color buffer.<br />
<br />
=== GPUREG_COLORBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow write (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures write access to the color buffer.<br />
<br />
=== GPUREG_DEPTHBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil read (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth read (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures read access from the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil write (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth write (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures write access to the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the depth buffer data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit depth<br />
|-<br />
| 2<br />
| 24-bit depth<br />
|-<br />
| 3<br />
| 24-bit depth + 8-bit stencil<br />
|}<br />
<br />
=== GPUREG_COLORBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Pixel size<br />
|-<br />
| 16-18<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.<br />
<br />
Pixel size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit color<br />
|-<br />
| 2<br />
| 32-bit color<br />
|}<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| RGBA8/Gas<br />
|-<br />
| 2<br />
| RGB5A1<br />
|-<br />
| 3<br />
| RGB565<br />
|-<br />
| 4<br />
| RGBA4<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register enables the early depth test.<br />
<br />
=== GPUREG_FRAMEBUFFER_BLOCK32 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Render block mode<br />
|}<br />
<br />
This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.<br />
<br />
Render block mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8x8 blocks<br />
|-<br />
| 1<br />
| 32x32 blocks<br />
|}<br />
<br />
=== GPUREG_DEPTHBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Depth buffer physical address >> 3<br />
|}<br />
<br />
This register configures the depth buffer physical address.<br />
<br />
=== GPUREG_COLORBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Color buffer physical address >> 3<br />
|}<br />
<br />
This register configures the color buffer physical address.<br />
<br />
=== GPUREG_FRAMEBUFFER_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register configures the framebuffer dimensions.<br />
<br />
=== GPUREG_GAS_LIGHT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Planar shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, Planar shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, Planar shading density attenuation<br />
|}<br />
<br />
This register configures gas light planar shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, View shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, View shading density attenuation<br />
|}<br />
<br />
This register configures gas light view shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading effect in line-of-sight direction<br />
|-<br />
| 8<br />
| Gas color LUT input<br />
|}<br />
<br />
This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.<br />
<br />
Color LUT input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Gas density<br />
|-<br />
| 1<br />
| Light factor<br />
|}<br />
<br />
=== GPUREG_GAS_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.<br />
<br />
=== GPUREG_GAS_LUT_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.<br />
<br />
==== Gas Look-Up Table ====<br />
<br />
16 elements:<br />
<br />
First 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| signed, Red<br />
|-<br />
| 8-15<br />
| signed, Green<br />
|-<br />
| 16-23<br />
| signed, Blue<br />
|}<br />
<br />
Last 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
=== GPUREG_GAS_DELTAZ_DEPTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| fixed0.16.8, Depth direction attenuation proportion<br />
|}<br />
<br />
This register is used to configure the gas depth direction attenuation proportion.<br />
<br />
=== GPUREG_FRAGOP_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Sum of penumbra scale and penumbra bias<br />
|-<br />
| 16-31<br />
| float1.5.10, Penumbra scale with reversed sign<br />
|}<br />
<br />
This register is used to configure shadow properties.<br />
<br />
== Fragment lighting registers ==<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR1 ===<br />
<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.<br />
<br />
=== GPUREG_LIGHT''i''_DIFFUSE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.<br />
<br />
=== GPUREG_LIGHT''i''_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.<br />
<br />
=== GPUREG_LIGHT''i''_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, X coordinate<br />
|-<br />
| 16-31<br />
| float1.5.10, Y coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Z coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, X coordinate (negated)<br />
|-<br />
| 16-28<br />
| fixed1.1.11, Y coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Z coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Light type (0 = positional light, 1 = directional light)<br />
|-<br />
| 1<br />
| unsigned, Two side diffuse (0 = one side, 1 = both sides)<br />
|-<br />
| 2<br />
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)<br />
|-<br />
| 3<br />
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures a light's properties.<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation bias<br />
|}<br />
<br />
These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation scale<br />
|}<br />
<br />
These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHTING_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.<br />
<br />
=== GPUREG_LIGHTING_NUM_LIGHTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of active lights - 1<br />
|}<br />
<br />
This register configures the number of active lights.<br />
<br />
=== GPUREG_LIGHTING_CONFIG0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)<br />
|-<br />
| 2-3<br />
| unsigned, Fresnel selector<br />
|-<br />
| 4-7<br />
| unsigned, Light environment configuration<br />
|-<br />
| 8-11<br />
| 0x4<br />
|-<br />
| 16<br />
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 17<br />
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 18<br />
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)<br />
|-<br />
| 19<br />
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)<br />
|-<br />
| 22-23<br />
| unsigned, Bump map texture unit<br />
|-<br />
| 24-25<br />
| unsigned, Shadow map texture unit<br />
|-<br />
| 27<br />
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)<br />
|-<br />
| 28-29<br />
| unsigned, Bump mode<br />
|-<br />
| 30<br />
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)<br />
|-<br />
| 31<br />
| 0x1<br />
|}<br />
<br />
This register configures the light environment.<br />
<br />
Fresnel selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Primary alpha<br />
|-<br />
| 2<br />
| Secondary alpha<br />
|-<br />
| 3<br />
| Primary and secondary alpha<br />
|}<br />
<br />
The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.<br />
<br />
Light environment configuration values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! Available LUTs<br />
|-<br />
| 0<br />
| Configuration 0<br />
| D0, RR, SP, DA<br />
|-<br />
| 1<br />
| Configuration 1<br />
| FR, RR, SP, DA<br />
|-<br />
| 2<br />
| Configuration 2<br />
| D0, D1, RR, DA<br />
|-<br />
| 3<br />
| Configuration 3<br />
| D0, D1, FR, DA<br />
|-<br />
| 4<br />
| Configuration 4<br />
| All except for FR<br />
|-<br />
| 5<br />
| Configuration 5<br />
| All except for D1<br />
|-<br />
| 6<br />
| Configuration 6<br />
| All except for RB and RG<br />
|-<br />
| 8<br />
| Configuration 7<br />
| All<br />
|}<br />
<br />
Bump mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Not used<br />
|-<br />
| 1<br />
| Use as bump map<br />
|-<br />
| 2<br />
| Use as tangent map<br />
|}<br />
<br />
=== GPUREG_LIGHTING_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 1<br />
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 2<br />
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 3<br />
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 4<br />
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 6<br />
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 7<br />
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 8<br />
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 10<br />
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 11<br />
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 12<br />
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 14<br />
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 15<br />
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 16<br />
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 18<br />
| 0x1<br />
|-<br />
| 19<br />
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 20-22<br />
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 21<br />
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 22<br />
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 24<br />
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 26<br />
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 27<br />
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 28<br />
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 29<br />
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 30<br />
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 31<br />
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is used to disable various aspects of the light environment.<br />
<br />
=== GPUREG_LIGHTING_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Starting index<br />
|-<br />
| 8-12<br />
| unsigned, Look-up table<br />
|}<br />
<br />
This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.<br />
<br />
Lookup table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| D0<br />
|-<br />
| 1<br />
| D1<br />
|-<br />
| 3<br />
| FR<br />
|-<br />
| 4<br />
| RB<br />
|-<br />
| 5<br />
| RG<br />
|-<br />
| 6<br />
| RR<br />
|-<br />
| 8-15<br />
| SP0-7<br />
|-<br />
| 16-23<br />
| DA0-7<br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.<br />
<br />
=== GPUREG_LIGHTING_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
Lighting LUT data is written here.<br />
<br />
A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.<br />
<br />
DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.<br />
<br />
Format of an entry:<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Entry value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_ABS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)<br />
|-<br />
| 21<br />
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register controls whether the absolute value of the input is taken before using a LUT.<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SELECT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Input selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Input selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Input selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Input selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Input selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Input selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Input selector for RR<br />
|}<br />
<br />
This register selects the input from LUTs.<br />
<br />
Input selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| N·H<br />
|-<br />
| 1<br />
| V·H<br />
|-<br />
| 2<br />
| N·V<br />
|-<br />
| 3<br />
| L·N<br />
|-<br />
| 4<br />
| -L·P (aka Spotlight aka SP)<br />
|-<br />
| 5<br />
| cos φ (aka CP)<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Scaler selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Scaler selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Scaler selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Scaler selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Scaler selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Scaler selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Scaler selector for RR<br />
|}<br />
<br />
This register controls the scaling that is applied to the output of a LUT.<br />
<br />
Scaler selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|-<br />
| 3<br />
| 8x<br />
|-<br />
| 6<br />
| 0.25x<br />
|-<br />
| 7<br />
| 0.5x<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, ID of the 1st enabled light<br />
|-<br />
| 4-6<br />
| unsigned, ID of the 2nd enabled light<br />
|-<br />
| 8-10<br />
| unsigned, ID of the 3rd enabled light<br />
|-<br />
| 12-14<br />
| unsigned, ID of the 4th enabled light<br />
|-<br />
| 16-18<br />
| unsigned, ID of the 5th enabled light<br />
|-<br />
| 20-22<br />
| unsigned, ID of the 6th enabled light<br />
|-<br />
| 24-26<br />
| unsigned, ID of the 7th enabled light<br />
|-<br />
| 28-30<br />
| unsigned, ID of the 8th enabled light<br />
|}<br />
<br />
This register sets the IDs of enabled light sources.<br />
<br />
== Geometry pipeline registers ==<br />
<br />
=== GPUREG_ATTRIBBUFFERS_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-28<br />
| unsigned, Vertex arrays base address<br />
|}<br />
<br />
This register sets the base address of all vertex arrays.<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 0 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 0 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 1 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 1 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 2 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 2 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 3 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 3 size<br />
|-<br />
| 16-17<br />
| unsigned, Vertex attribute 4 type<br />
|-<br />
| 18-19<br />
| unsigned, Vertex attribute 4 size<br />
|-<br />
| 20-21<br />
| unsigned, Vertex attribute 5 type<br />
|-<br />
| 22-23<br />
| unsigned, Vertex attribute 5 size<br />
|-<br />
| 24-25<br />
| unsigned, Vertex attribute 6 type<br />
|-<br />
| 26-27<br />
| unsigned, Vertex attribute 6 size<br />
|-<br />
| 28-29<br />
| unsigned, Vertex attribute 7 type<br />
|-<br />
| 30-31<br />
| unsigned, Vertex attribute 7 size<br />
|}<br />
<br />
This register configures the types and sizes of the first 8 vertex attributes.<br />
<br />
Vertex attribute type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Byte<br />
|-<br />
| 1<br />
| Unsigned byte<br />
|-<br />
| 2<br />
| Short<br />
|-<br />
| 3<br />
| Float<br />
|}<br />
<br />
Vertex attribute size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8 bits<br />
|-<br />
| 1<br />
| 16 bits<br />
|-<br />
| 2<br />
| 24 bits<br />
|-<br />
| 3<br />
| 32 bits<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 8 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 8 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 9 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 9 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 10 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 10 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 11 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 11 size<br />
|-<br />
| 16-27<br />
| unsigned, Fixed vertex attribute mask<br />
|-<br />
| 28-31<br />
| unsigned, Total vertex attribute count - 1<br />
|}<br />
<br />
This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.<br />
<br />
See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|}<br />
<br />
This register configures the offset of a vertex array from the base vertex arrays address.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 1<br />
|-<br />
| 4-7<br />
| unsigned, Component 2<br />
|-<br />
| 8-11<br />
| unsigned, Component 3<br />
|-<br />
| 12-15<br />
| unsigned, Component 4<br />
|-<br />
| 16-19<br />
| unsigned, Component 5<br />
|-<br />
| 20-23<br />
| unsigned, Component 6<br />
|-<br />
| 24-27<br />
| unsigned, Component 7<br />
|-<br />
| 28-31<br />
| unsigned, Component 8<br />
|}<br />
<br />
This register configures the first 8 component types of a vertex array.<br />
<br />
Component values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Vertex attribute 0<br />
|-<br />
| 1<br />
| Vertex attribute 1<br />
|-<br />
| 2<br />
| Vertex attribute 2<br />
|-<br />
| 3<br />
| Vertex attribute 3<br />
|-<br />
| 4<br />
| Vertex attribute 4<br />
|-<br />
| 5<br />
| Vertex attribute 5<br />
|-<br />
| 6<br />
| Vertex attribute 6<br />
|-<br />
| 7<br />
| Vertex attribute 7<br />
|-<br />
| 8<br />
| Vertex attribute 8<br />
|-<br />
| 9<br />
| Vertex attribute 9<br />
|-<br />
| 10<br />
| Vertex attribute 10<br />
|-<br />
| 11<br />
| Vertex attribute 11<br />
|-<br />
| 12<br />
| 4-byte padding<br />
|-<br />
| 13<br />
| 8-byte padding<br />
|-<br />
| 14<br />
| 12-byte padding<br />
|-<br />
| 15<br />
| 16-byte padding<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 9<br />
|-<br />
| 4-7<br />
| unsigned, Component 10<br />
|-<br />
| 8-11<br />
| unsigned, Component 11<br />
|-<br />
| 12-15<br />
| unsigned, Component 12<br />
|-<br />
| 16-23<br />
| unsigned, Bytes per vertex<br />
|-<br />
| 28-31<br />
| unsigned, Total number of components<br />
|}<br />
<br />
This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.<br />
<br />
See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.<br />
<br />
=== GPUREG_INDEXBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|-<br />
| 31<br />
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)<br />
|}<br />
<br />
This register configures the index array used when drawing elements.<br />
<br />
=== GPUREG_NUMVERTICES ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Number of vertices to render<br />
|}<br />
<br />
This register sets the number of vertices to render.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|-<br />
| 9<br />
| 0x0<br />
|-<br />
| 31<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_VERTEX_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Starting vertex offset<br />
|}<br />
<br />
This register sets the offset of the first vertex in an array to render.<br />
<br />
=== GPUREG_POST_VERTEX_CACHE_NUM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)<br />
|}<br />
<br />
This register configures the post-vertex cache.<br />
<br />
=== GPUREG_DRAWARRAYS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw arrays)<br />
|}<br />
<br />
This register triggers drawing vertex arrays.<br />
<br />
=== GPUREG_DRAWELEMENTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw elements)<br />
|}<br />
<br />
This register triggers drawing vertex array elements.<br />
<br />
=== GPUREG_VTX_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)<br />
|}<br />
<br />
This register triggers clearing the post-vertex cache.<br />
<br />
=== GPUREG_FIXEDATTRIB_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)<br />
|}<br />
<br />
This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.<br />
<br />
=== GPUREG_FIXEDATTRIB_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| colspan="2" | '''DATA0:'''<br />
|-<br />
| 0-7<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)<br />
|-<br />
| 8-31<br />
| float1.7.16, Vertex attribute element 4 (W)<br />
|-<br />
| colspan="2" | '''DATA1:'''<br />
|-<br />
| 0-15<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)<br />
|-<br />
| 16-31<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)<br />
|-<br />
| colspan="2" | '''DATA2:'''<br />
|-<br />
| 0-23<br />
| float1.7.16, Vertex attribute element 1 (X)<br />
|-<br />
| 24-31<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)<br />
|}<br />
<br />
Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.<br />
<br />
=== GPUREG_CMDBUF_SIZE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the size of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_SIZE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the size of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the physical address of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the physical address of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)<br />
|}<br />
<br />
This register triggers a jump to the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)<br />
|}<br />
<br />
This register triggers a jump to the second command buffer.<br />
<br />
=== GPUREG_VSH_NUM_ATTR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader input attributes - 1<br />
|}<br />
<br />
This register sets the number of vertex shader input attributes.<br />
<br />
=== GPUREG_VSH_COM_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.<br />
<br />
=== GPUREG_START_DRAW_FUNC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Mode (0 = drawing, 1 = configuration)<br />
|-<br />
| 1-7<br />
| 0x0<br />
|}<br />
<br />
This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_GSH_MISC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)<br />
|}<br />
<br />
This register configures miscellaneous geometry shader properties.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_GSH_MISC1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)<br />
|}<br />
<br />
This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.<br />
<br />
=== GPUREG_PRIMITIVE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|-<br />
| 8-9<br />
| unsigned, Primitive mode<br />
|}<br />
<br />
This register configures primitive drawing.<br />
<br />
Primitive mode value:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Triangles<br />
|-<br />
| 1<br />
| Triangle strip<br />
|-<br />
| 2<br />
| Triangle fan<br />
|-<br />
| 3<br />
| Geometry primitive<br />
|}<br />
<br />
=== GPUREG_RESTART_PRIMITIVE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = reset primitive)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
This register triggers resetting primitive drawing.<br />
<br />
== Shader registers ==<br />
<br />
=== GPUREG_''SH''_BOOLUNIFORM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Boolean register b0 value (0 = false, 1 = true)<br />
|-<br />
| 1<br />
| unsigned, Boolean register b1 value (0 = false, 1 = true)<br />
|-<br />
| 2<br />
| unsigned, Boolean register b2 value (0 = false, 1 = true)<br />
|-<br />
| 3<br />
| unsigned, Boolean register b3 value (0 = false, 1 = true)<br />
|-<br />
| 4<br />
| unsigned, Boolean register b4 value (0 = false, 1 = true)<br />
|-<br />
| 5<br />
| unsigned, Boolean register b5 value (0 = false, 1 = true)<br />
|-<br />
| 6<br />
| unsigned, Boolean register b6 value (0 = false, 1 = true)<br />
|-<br />
| 7<br />
| unsigned, Boolean register b7 value (0 = false, 1 = true)<br />
|-<br />
| 8<br />
| unsigned, Boolean register b8 value (0 = false, 1 = true)<br />
|-<br />
| 9<br />
| unsigned, Boolean register b9 value (0 = false, 1 = true)<br />
|-<br />
| 10<br />
| unsigned, Boolean register b10 value (0 = false, 1 = true)<br />
|-<br />
| 11<br />
| unsigned, Boolean register b11 value (0 = false, 1 = true)<br />
|-<br />
| 12<br />
| unsigned, Boolean register b12 value (0 = false, 1 = true)<br />
|-<br />
| 13<br />
| unsigned, Boolean register b13 value (0 = false, 1 = true)<br />
|-<br />
| 14<br />
| unsigned, Boolean register b14 value (0 = false, 1 = true)<br />
|-<br />
| 15<br />
| unsigned, Boolean register b15 value (0 = false, 1 = true)<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register is used to set a shader unit's boolean registers.<br />
<br />
=== GPUREG_''SH''_INTUNIFORM_I''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Integer register i''i'' X value<br />
|-<br />
| 8-15<br />
| unsigned, Integer register i''i'' Y value<br />
|-<br />
| 16-23<br />
| unsigned, Integer register i''i'' Z value<br />
|-<br />
| 24-31<br />
| unsigned, Integer register i''i'' W value<br />
|}<br />
<br />
These registers are used to set a shader unit's integer registers.<br />
<br />
=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Input vertex attributes - 1<br />
|-<br />
| 8-15<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)<br />
|-<br />
| 16-23<br />
| 0x0<br />
|-<br />
| 24-31<br />
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)<br />
|}<br />
<br />
This register is used to configure a shader unit's input buffer.<br />
<br />
=== GPUREG_''SH''_ENTRYPOINT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Code entry point offset, in 32-bit words<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register sets a shader unit's code entry point.<br />
<br />
For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.<br />
<br />
For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them. <br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 0 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 1 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 2 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 3 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 4 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 5 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 6 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 7 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.<br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 8 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 9 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 10 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 11 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 12 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 13 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 14 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 15 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.<br />
<br />
=== GPUREG_''SH''_OUTMAP_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4<br />
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 5<br />
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 6<br />
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 7<br />
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 8<br />
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 9<br />
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 10<br />
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 11<br />
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 12<br />
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 13<br />
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 14<br />
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 15<br />
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 16-31<br />
| 0x0<br />
|}<br />
<br />
This register toggles a shader unit's output registers.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_END ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Signal transfer end (0 = idle, non-zero = signal)<br />
|}<br />
<br />
This register's value should be set to 1 in order to finalize the transfer of shader code.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)<br />
|-<br />
| 31<br />
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)<br />
|}<br />
<br />
This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| Floating-point register component data<br />
|}<br />
<br />
This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].<br />
<br />
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:<br />
** first word : ZZWWWWWW<br />
** second word : YYYYZZZZ<br />
** third word : XXXXXXYY<br />
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader code offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader instruction data<br />
|}<br />
<br />
This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.<br />
<br />
=== GPUREG_''SH''_OPDESCS_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader operand descriptor offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_OPDESCS_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader operand descriptor data<br />
|}<br />
<br />
This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=GPU/Internal_Registers&diff=19810
GPU/Internal Registers
2017-04-08T10:50:05Z
<p>Plutooo: </p>
<hr />
<div>[[Category:GPU]]<br />
<br />
== Overview ==<br />
GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.<br />
<br />
Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).<br />
<br />
In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.<br />
<br />
For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).<br />
<br />
Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.<br />
<br />
The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.<br />
<br />
=== Command Header ===<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0-15<br />
| Command ID<br />
|-<br />
| 16-19<br />
| Parameter mask<br />
|-<br />
| 20-30<br />
| Number of extra parameters (may be zero)<br />
|-<br />
| 31<br />
| Consecutive writing mode<br />
|}<br />
<br />
=== Parameter masking ===<br />
<br />
Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.<br />
<br />
=== Types ===<br />
<br />
There are three main types of registers :<br />
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])<br />
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])<br />
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])<br />
<br />
=== Aliases ===<br />
<br />
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]<br />
<br />
=== Data Types ===<br />
<br />
{| class="wikitable" border="1"<br />
! Name<br />
! Description<br />
|-<br />
| signed<br />
| Signed integer<br />
|-<br />
| unsigned<br />
| Unsigned integer<br />
|-<br />
| floatX.Y.Z<br />
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits<br />
|-<br />
| fixedX.Y.Z<br />
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits<br />
|}<br />
<br />
== Register list ==<br />
<br />
=== Miscellaneous registers (0x000-0x03F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0000<br />
| [[#GPUREG_0000|GPUREG_0000]]<br />
| <br />
|<br />
|-<br />
| 0001<br />
| [[#GPUREG_0001|GPUREG_0001]]<br />
| <br />
|<br />
|-<br />
| 0002<br />
| [[#GPUREG_0002|GPUREG_0002]]<br />
| <br />
|<br />
|-<br />
| 0003<br />
| [[#GPUREG_0003|GPUREG_0003]]<br />
| <br />
|<br />
|-<br />
| 0004<br />
| [[#GPUREG_0004|GPUREG_0004]]<br />
| <br />
|<br />
|-<br />
| 0005<br />
| [[#GPUREG_0005|GPUREG_0005]]<br />
| <br />
|<br />
|-<br />
| 0006<br />
| [[#GPUREG_0006|GPUREG_0006]]<br />
| <br />
|<br />
|-<br />
| 0007<br />
| [[#GPUREG_0007|GPUREG_0007]]<br />
| <br />
|<br />
|-<br />
| 0008<br />
| [[#GPUREG_0008|GPUREG_0008]]<br />
| <br />
|<br />
|-<br />
| 0009<br />
| [[#GPUREG_0009|GPUREG_0009]]<br />
| <br />
|<br />
|-<br />
| 000A<br />
| [[#GPUREG_000A|GPUREG_000A]]<br />
| <br />
|<br />
|-<br />
| 000B<br />
| [[#GPUREG_000B|GPUREG_000B]]<br />
| <br />
|<br />
|-<br />
| 000C<br />
| [[#GPUREG_000C|GPUREG_000C]]<br />
| <br />
|<br />
|-<br />
| 000D<br />
| [[#GPUREG_000D|GPUREG_000D]]<br />
| <br />
|<br />
|-<br />
| 000E<br />
| [[#GPUREG_000E|GPUREG_000E]]<br />
| <br />
|<br />
|-<br />
| 000F<br />
| [[#GPUREG_000F|GPUREG_000F]]<br />
| <br />
|<br />
|-<br />
| 0010<br />
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]<br />
| <br />
|PICA_REG_INTERRUPT<br />
|-<br />
| 0011<br />
| [[#GPUREG_0011|GPUREG_0011]]<br />
| <br />
|<br />
|-<br />
| 0012<br />
| [[#GPUREG_0012|GPUREG_0012]]<br />
| <br />
|<br />
|-<br />
| 0013<br />
| [[#GPUREG_0013|GPUREG_0013]]<br />
| <br />
|<br />
|-<br />
| 0014<br />
| [[#GPUREG_0014|GPUREG_0014]]<br />
| <br />
|<br />
|-<br />
| 0015<br />
| [[#GPUREG_0015|GPUREG_0015]]<br />
| <br />
|<br />
|-<br />
| 0016<br />
| [[#GPUREG_0016|GPUREG_0016]]<br />
| <br />
|<br />
|-<br />
| 0017<br />
| [[#GPUREG_0017|GPUREG_0017]]<br />
| <br />
|<br />
|-<br />
| 0018<br />
| [[#GPUREG_0018|GPUREG_0018]]<br />
| <br />
|<br />
|-<br />
| 0019<br />
| [[#GPUREG_0019|GPUREG_0019]]<br />
| <br />
|<br />
|-<br />
| 001A<br />
| [[#GPUREG_001A|GPUREG_001A]]<br />
| <br />
|<br />
|-<br />
| 001B<br />
| [[#GPUREG_001B|GPUREG_001B]]<br />
| <br />
|<br />
|-<br />
| 001C<br />
| [[#GPUREG_001C|GPUREG_001C]]<br />
| <br />
|<br />
|-<br />
| 001D<br />
| [[#GPUREG_001D|GPUREG_001D]]<br />
| <br />
|<br />
|-<br />
| 001E<br />
| [[#GPUREG_001E|GPUREG_001E]]<br />
| <br />
|<br />
|-<br />
| 001F<br />
| [[#GPUREG_001F|GPUREG_001F]]<br />
| <br />
|<br />
|-<br />
| 0020<br />
| [[#GPUREG_0020|GPUREG_0020]]<br />
| <br />
|<br />
|-<br />
| 0021<br />
| [[#GPUREG_0021|GPUREG_0021]]<br />
| <br />
|<br />
|-<br />
| 0022<br />
| [[#GPUREG_0022|GPUREG_0022]]<br />
| <br />
|<br />
|-<br />
| 0023<br />
| [[#GPUREG_0023|GPUREG_0023]]<br />
| <br />
|<br />
|-<br />
| 0024<br />
| [[#GPUREG_0024|GPUREG_0024]]<br />
| <br />
|<br />
|-<br />
| 0025<br />
| [[#GPUREG_0025|GPUREG_0025]]<br />
| <br />
|<br />
|-<br />
| 0026<br />
| [[#GPUREG_0026|GPUREG_0026]]<br />
| <br />
|<br />
|-<br />
| 0027<br />
| [[#GPUREG_0027|GPUREG_0027]]<br />
| <br />
|<br />
|-<br />
| 0028<br />
| [[#GPUREG_0028|GPUREG_0028]]<br />
| <br />
|<br />
|-<br />
| 0029<br />
| [[#GPUREG_0029|GPUREG_0029]]<br />
| <br />
|<br />
|-<br />
| 002A<br />
| [[#GPUREG_002A|GPUREG_002A]]<br />
| <br />
|<br />
|-<br />
| 002B<br />
| [[#GPUREG_002B|GPUREG_002B]]<br />
| <br />
|<br />
|-<br />
| 002C<br />
| [[#GPUREG_002C|GPUREG_002C]]<br />
| <br />
|<br />
|-<br />
| 002D<br />
| [[#GPUREG_002D|GPUREG_002D]]<br />
| <br />
|<br />
|-<br />
| 002E<br />
| [[#GPUREG_002E|GPUREG_002E]]<br />
| <br />
|<br />
|-<br />
| 002F<br />
| [[#GPUREG_002F|GPUREG_002F]]<br />
| <br />
|<br />
|-<br />
| 0030<br />
| [[#GPUREG_0030|GPUREG_0030]]<br />
| <br />
|<br />
|-<br />
| 0031<br />
| [[#GPUREG_0031|GPUREG_0031]]<br />
| <br />
|<br />
|-<br />
| 0032<br />
| [[#GPUREG_0032|GPUREG_0032]]<br />
| <br />
|<br />
|-<br />
| 0033<br />
| [[#GPUREG_0033|GPUREG_0033]]<br />
| <br />
|<br />
|-<br />
| 0034<br />
| [[#GPUREG_0034|GPUREG_0034]]<br />
| <br />
|<br />
|-<br />
| 0035<br />
| [[#GPUREG_0035|GPUREG_0035]]<br />
| <br />
|<br />
|-<br />
| 0036<br />
| [[#GPUREG_0036|GPUREG_0036]]<br />
| <br />
|<br />
|-<br />
| 0037<br />
| [[#GPUREG_0037|GPUREG_0037]]<br />
| <br />
|<br />
|-<br />
| 0038<br />
| [[#GPUREG_0038|GPUREG_0038]]<br />
| <br />
|<br />
|-<br />
| 0039<br />
| [[#GPUREG_0039|GPUREG_0039]]<br />
| <br />
|<br />
|-<br />
| 003A<br />
| [[#GPUREG_003A|GPUREG_003A]]<br />
| <br />
|<br />
|-<br />
| 003B<br />
| [[#GPUREG_003B|GPUREG_003B]]<br />
| <br />
|<br />
|-<br />
| 003C<br />
| [[#GPUREG_003C|GPUREG_003C]]<br />
| <br />
|<br />
|-<br />
| 003D<br />
| [[#GPUREG_003D|GPUREG_003D]]<br />
| <br />
|<br />
|-<br />
| 003E<br />
| [[#GPUREG_003E|GPUREG_003E]]<br />
| <br />
|<br />
|-<br />
| 003F<br />
| [[#GPUREG_003F|GPUREG_003F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Rasterizer registers (0x040-0x07F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0040<br />
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]<br />
| <br />
|PICA_REG_CULL_FACE<br />
|-<br />
| 0041<br />
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH1<br />
|-<br />
| 0042<br />
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH2<br />
|-<br />
| 0043<br />
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT1<br />
|-<br />
| 0044<br />
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT2<br />
|-<br />
| 0045<br />
| [[#GPUREG_0045|GPUREG_0045]]<br />
| <br />
|<br />
|-<br />
| 0046<br />
| [[#GPUREG_0046|GPUREG_0046]]<br />
| <br />
|<br />
|-<br />
| 0047<br />
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP<br />
|-<br />
| 0048<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]<br />
|? <br />
|PICA_REG_FRAGOP_CLIP_DATA1<br />
|-<br />
| 0049<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA2<br />
|-<br />
| 004A<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA3<br />
|-<br />
| 004B<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA4<br />
|-<br />
| 004C<br />
| [[#GPUREG_004C|GPUREG_004C]]<br />
| <br />
|<br />
|-<br />
| 004D<br />
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA1<br />
|-<br />
| 004E<br />
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA2<br />
|-<br />
| 004F<br />
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]<br />
| <br />
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0<br />
|-<br />
| 0050<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0<br />
|-<br />
| 0051<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1<br />
|-<br />
| 0052<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2<br />
|-<br />
| 0053<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3<br />
|-<br />
| 0054<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4<br />
|-<br />
| 0055<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5<br />
|-<br />
| 0056<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6<br />
|-<br />
| 0057<br />
| [[#GPUREG_0057|GPUREG_0057]]<br />
| <br />
|<br />
|-<br />
| 0058<br />
| [[#GPUREG_0058|GPUREG_0058]]<br />
| <br />
|<br />
|-<br />
| 0059<br />
| [[#GPUREG_0059|GPUREG_0059]]<br />
| <br />
|<br />
|-<br />
| 005A<br />
| [[#GPUREG_005A|GPUREG_005A]]<br />
| <br />
|<br />
|-<br />
| 005B<br />
| [[#GPUREG_005B|GPUREG_005B]]<br />
| <br />
|<br />
|-<br />
| 005C<br />
| [[#GPUREG_005C|GPUREG_005C]]<br />
| <br />
|<br />
|-<br />
| 005D<br />
| [[#GPUREG_005D|GPUREG_005D]]<br />
| <br />
|<br />
|-<br />
| 005E<br />
| [[#GPUREG_005E|GPUREG_005E]]<br />
| <br />
|<br />
|-<br />
| 005F<br />
| [[#GPUREG_005F|GPUREG_005F]]<br />
| <br />
|<br />
|-<br />
| 0060<br />
| [[#GPUREG_0060|GPUREG_0060]]<br />
| <br />
|<br />
|-<br />
| 0061<br />
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_FUNC<br />
|-<br />
| 0062<br />
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST1<br />
|-<br />
| 0063<br />
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]<br />
| <br />
|PICA_REG_EARLY_DEPTH_CLEAR<br />
|-<br />
| 0064<br />
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE<br />
|-<br />
| 0065<br />
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]<br />
| <br />
|PICA_REG_SCISSOR<br />
|-<br />
| 0066<br />
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]<br />
| <br />
|PICA_REG_SCISSOR_XY<br />
|-<br />
| 0067<br />
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]<br />
| <br />
|PICA_REG_SCISSOR_SIZE<br />
|-<br />
| 0068<br />
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]<br />
|<br />
|PICA_REG_VIEWPORT_XY<br />
|-<br />
| 0069<br />
| [[#GPUREG_0069|GPUREG_0069]]<br />
| <br />
|<br />
|-<br />
| 006A<br />
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]<br />
|<br />
|PICA_REG_EARLY_DEPTH_DATA<br />
|-<br />
| 006B<br />
| [[#GPUREG_006B|GPUREG_006B]]<br />
| <br />
|<br />
|-<br />
| 006C<br />
| [[#GPUREG_006C|GPUREG_006C]]<br />
| <br />
|<br />
|-<br />
| 006D<br />
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]<br />
|?<br />
|PICA_REG_FRAGOP_WSCALE<br />
|-<br />
| 006E<br />
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]<br />
|?<br />
|PICA_REG_RENDER_BUF_RESOLUTION1<br />
|-<br />
| 006F<br />
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK<br />
|-<br />
| 0070<br />
| [[#GPUREG_0070|GPUREG_0070]]<br />
| <br />
|<br />
|-<br />
| 0071<br />
| [[#GPUREG_0071|GPUREG_0071]]<br />
| <br />
|<br />
|-<br />
| 0072<br />
| [[#GPUREG_0072|GPUREG_0072]]<br />
| <br />
|<br />
|-<br />
| 0073<br />
| [[#GPUREG_0073|GPUREG_0073]]<br />
| <br />
|<br />
|-<br />
| 0074<br />
| [[#GPUREG_0074|GPUREG_0074]]<br />
| <br />
|<br />
|-<br />
| 0075<br />
| [[#GPUREG_0075|GPUREG_0075]]<br />
| <br />
|<br />
|-<br />
| 0076<br />
| [[#GPUREG_0076|GPUREG_0076]]<br />
| <br />
|<br />
|-<br />
| 0077<br />
| [[#GPUREG_0077|GPUREG_0077]]<br />
| <br />
|<br />
|-<br />
| 0078<br />
| [[#GPUREG_0078|GPUREG_0078]]<br />
| <br />
|<br />
|-<br />
| 0079<br />
| [[#GPUREG_0079|GPUREG_0079]]<br />
| <br />
|<br />
|-<br />
| 007A<br />
| [[#GPUREG_007A|GPUREG_007A]]<br />
| <br />
|<br />
|-<br />
| 007B<br />
| [[#GPUREG_007B|GPUREG_007B]]<br />
| <br />
|<br />
|-<br />
| 007C<br />
| [[#GPUREG_007C|GPUREG_007C]]<br />
| <br />
|<br />
|-<br />
| 007D<br />
| [[#GPUREG_007D|GPUREG_007D]]<br />
| <br />
|<br />
|-<br />
| 007E<br />
| [[#GPUREG_007E|GPUREG_007E]]<br />
| <br />
|<br />
|-<br />
| 007F<br />
| [[#GPUREG_007F|GPUREG_007F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Texturing registers (0x080-0x0FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0080<br />
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]<br />
|<br />
|PICA_REG_TEXTURE_FUNC<br />
|-<br />
| 0081<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE0_BORDER_COLOR<br />
|-<br />
| 0082<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]<br />
|<br />
|PICA_REG_TEXTURE0_SIZE<br />
|-<br />
| 0083<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE0_WRAP_FILTER<br />
|-<br />
| 0084<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE0_LOD<br />
|-<br />
| 0085<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR1<br />
|-<br />
| 0086<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR2<br />
|-<br />
| 0087<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR3<br />
|-<br />
| 0088<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR4<br />
|-<br />
| 0089<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR5<br />
|-<br />
| 008A<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR6<br />
|-<br />
| 008B<br />
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]<br />
|?<br />
|PICA_REG_TEXTURE0_SHADOW<br />
|-<br />
| 008C<br />
| [[#GPUREG_008C|GPUREG_008C]]<br />
|<br />
|<br />
|-<br />
| 008D<br />
| [[#GPUREG_008D|GPUREG_008D]]<br />
|<br />
|<br />
|-<br />
| 008E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]<br />
|?<br />
|PICA_REG_TEXTURE0_FORMAT<br />
|-<br />
| 008F<br />
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN0<br />
|-<br />
| 0090<br />
| [[#GPUREG_0090|GPUREG_0090]]<br />
| <br />
|<br />
|-<br />
| 0091<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE1_BORDER_COLOR<br />
|-<br />
| 0092<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]<br />
| <br />
|PICA_REG_TEXTURE1_SIZE<br />
|-<br />
| 0093<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE1_WRAP_FILTER<br />
|-<br />
| 0094<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE1_LOD<br />
|-<br />
| 0095<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]<br />
| <br />
|PICA_REG_TEXTURE1_ADDR<br />
|-<br />
| 0096<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE1_FORMAT<br />
|-<br />
| 0097<br />
| [[#GPUREG_0097|GPUREG_0097]]<br />
| <br />
|<br />
|-<br />
| 0098<br />
| [[#GPUREG_0098|GPUREG_0098]]<br />
| <br />
|<br />
|-<br />
| 0099<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE2_BORDER_COLOR<br />
|-<br />
| 009A<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]<br />
| <br />
|PICA_REG_TEXTURE2_SIZE<br />
|-<br />
| 009B<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE2_WRAP_FILTER<br />
|-<br />
| 009C<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE2_LOD<br />
|-<br />
| 009D<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]<br />
|<br />
|PICA_REG_TEXTURE2_ADDR<br />
|-<br />
| 009E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE2_FORMAT<br />
|-<br />
| 009F<br />
| [[#GPUREG_009F|GPUREG_009F]]<br />
| <br />
|<br />
|-<br />
| 00A0<br />
| [[#GPUREG_00A0|GPUREG_00A0]]<br />
| <br />
|<br />
|-<br />
| 00A1<br />
| [[#GPUREG_00A1|GPUREG_00A1]]<br />
| <br />
|<br />
|-<br />
| 00A2<br />
| [[#GPUREG_00A2|GPUREG_00A2]]<br />
| <br />
|<br />
|-<br />
| 00A3<br />
| [[#GPUREG_00A3|GPUREG_00A3]]<br />
| <br />
|<br />
|-<br />
| 00A4<br />
| [[#GPUREG_00A4|GPUREG_00A4]]<br />
| <br />
|<br />
|-<br />
| 00A5<br />
| [[#GPUREG_00A5|GPUREG_00A5]]<br />
| <br />
|<br />
|-<br />
| 00A6<br />
| [[#GPUREG_00A6|GPUREG_00A6]]<br />
| <br />
|<br />
|-<br />
| 00A7<br />
| [[#GPUREG_00A7|GPUREG_00A7]]<br />
| <br />
|<br />
|-<br />
| 00A8<br />
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX0<br />
|-<br />
| 00A9<br />
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX1<br />
|-<br />
| 00AA<br />
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]<br />
|? <br />
|PICA_REG_TEXTURE3_PROCTEX2<br />
|-<br />
| 00AB<br />
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX3<br />
|-<br />
| 00AC<br />
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX4<br />
|-<br />
| 00AD<br />
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX5<br />
|-<br />
| 00AE<br />
| [[#GPUREG_00AE|GPUREG_00AE]]<br />
| <br />
|<br />
|-<br />
| 00AF<br />
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]<br />
|?<br />
|PICA_REG_PROCTEX_LUT<br />
|-<br />
| 00B0<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA0<br />
|-<br />
| 00B1<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA1<br />
|-<br />
| 00B2<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA2<br />
|-<br />
| 00B3<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA3<br />
|-<br />
| 00B4<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA4<br />
|-<br />
| 00B5<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA5<br />
|-<br />
| 00B6<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA6<br />
|-<br />
| 00B7<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA7<br />
|-<br />
| 00B8<br />
| [[#GPUREG_00B8|GPUREG_00B8]]<br />
| <br />
|<br />
|-<br />
| 00B9<br />
| [[#GPUREG_00B9|GPUREG_00B9]]<br />
| <br />
|<br />
|-<br />
| 00BA<br />
| [[#GPUREG_00BA|GPUREG_00BA]]<br />
| <br />
|<br />
|-<br />
| 00BB<br />
| [[#GPUREG_00BB|GPUREG_00BB]]<br />
| <br />
|<br />
|-<br />
| 00BC<br />
| [[#GPUREG_00BC|GPUREG_00BC]]<br />
| <br />
|<br />
|-<br />
| 00BD<br />
| [[#GPUREG_00BD|GPUREG_00BD]]<br />
| <br />
|<br />
|-<br />
| 00BE<br />
| [[#GPUREG_00BE|GPUREG_00BE]]<br />
| <br />
|<br />
|-<br />
| 00BF<br />
| [[#GPUREG_00BF|GPUREG_00BF]]<br />
| <br />
|<br />
|-<br />
| 00C0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_0<br />
|-<br />
| 00C1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_0_OPERAND<br />
|-<br />
| 00C2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COMBINE<br />
|-<br />
| 00C3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COLOR<br />
|-<br />
| 00C4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_0_SCALE<br />
|-<br />
| 00C5<br />
| [[#GPUREG_00C5|GPUREG_00C5]]<br />
| <br />
|<br />
|-<br />
| 00C6<br />
| [[#GPUREG_00C6|GPUREG_00C6]]<br />
| <br />
|<br />
|-<br />
| 00C7<br />
| [[#GPUREG_00C7|GPUREG_00C7]]<br />
| <br />
|<br />
|-<br />
| 00C8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_1<br />
|-<br />
| 00C9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_1_OPERAND<br />
|-<br />
| 00CA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COMBINE<br />
|-<br />
| 00CB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COLOR<br />
|-<br />
| 00CC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_1_SCALE<br />
|-<br />
| 00CD<br />
| [[#GPUREG_00CD|GPUREG_00CD]]<br />
| <br />
|<br />
|-<br />
| 00CE<br />
| [[#GPUREG_00CE|GPUREG_00CE]]<br />
| <br />
|<br />
|-<br />
| 00CF<br />
| [[#GPUREG_00CF|GPUREG_00CF]]<br />
| <br />
|<br />
|-<br />
| 00D0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_2<br />
|-<br />
| 00D1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_2_OPERAND<br />
|-<br />
| 00D2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COMBINE<br />
|-<br />
| 00D3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COLOR<br />
|-<br />
| 00D4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_2_SCALE<br />
|-<br />
| 00D5<br />
| [[#GPUREG_00D5|GPUREG_00D5]]<br />
| <br />
|<br />
|-<br />
| 00D6<br />
| [[#GPUREG_00D6|GPUREG_00D6]]<br />
| <br />
|<br />
|-<br />
| 00D7<br />
| [[#GPUREG_00D7|GPUREG_00D7]]<br />
| <br />
|<br />
|-<br />
| 00D8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_3<br />
|-<br />
| 00D9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_3_OPERAND<br />
|-<br />
| 00DA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COMBINE<br />
|-<br />
| 00DB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COLOR<br />
|-<br />
| 00DC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_3_SCALE<br />
|-<br />
| 00DD<br />
| [[#GPUREG_00DD|GPUREG_00DD]]<br />
| <br />
|<br />
|-<br />
| 00DE<br />
| [[#GPUREG_00DE|GPUREG_00DE]]<br />
| <br />
|<br />
|-<br />
| 00DF<br />
| [[#GPUREG_00DF|GPUREG_00DF]]<br />
| <br />
|<br />
|-<br />
| 00E0<br />
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]<br />
|?<br />
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT<br />
|-<br />
| 00E1<br />
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]<br />
|?<br />
|PICA_REG_FOG_COLOR<br />
|-<br />
| 00E2<br />
| [[#GPUREG_00E2|GPUREG_00E2]]<br />
| <br />
|<br />
|-<br />
| 00E3<br />
| [[#GPUREG_00E3|GPUREG_00E3]]<br />
| <br />
|<br />
|-<br />
| 00E4<br />
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]<br />
|?<br />
|PICA_REG_GAS_ATTENUATION<br />
|-<br />
| 00E5<br />
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]<br />
|?<br />
|PICA_REG_GAS_ACCMAX<br />
|-<br />
| 00E6<br />
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FOG_LUT_INDEX<br />
|-<br />
| 00E7<br />
| [[#GPUREG_00E7|GPUREG_00E7]]<br />
| <br />
|<br />
|-<br />
| 00E8<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA0<br />
|-<br />
| 00E9<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]<br />
|? <br />
|PICA_REG_FOG_LUT_DATA1<br />
|-<br />
| 00EA<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA2<br />
|-<br />
| 00EB<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA3<br />
|-<br />
| 00EC<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA4<br />
|-<br />
| 00ED<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA5<br />
|-<br />
| 00EE<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA6<br />
|-<br />
| 00EF<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA7<br />
|-<br />
| 00F0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_4<br />
|-<br />
| 00F1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_4_OPERAND<br />
|-<br />
| 00F2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COMBINE<br />
|-<br />
| 00F3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COLOR<br />
|-<br />
| 00F4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_4_SCALE<br />
|-<br />
| 00F5<br />
| [[#GPUREG_00F5|GPUREG_00F5]]<br />
| <br />
|<br />
|-<br />
| 00F6<br />
| [[#GPUREG_00F6|GPUREG_00F6]]<br />
| <br />
|<br />
|-<br />
| 00F7<br />
| [[#GPUREG_00F7|GPUREG_00F7]]<br />
| <br />
|<br />
|-<br />
| 00F8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_5<br />
|-<br />
| 00F9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_5_OPERAND<br />
|-<br />
| 00FA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COMBINE<br />
|-<br />
| 00FB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COLOR<br />
|-<br />
| 00FC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_5_SCALE<br />
|-<br />
| 00FD<br />
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]<br />
|?<br />
|PICA_REG_TEX_ENV_BUF_COLOR<br />
|-<br />
| 00FE<br />
| [[#GPUREG_00FE|GPUREG_00FE]]<br />
| <br />
|<br />
|-<br />
| 00FF<br />
| [[#GPUREG_00FF|GPUREG_00FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Framebuffer registers (0x100-0x13F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0100<br />
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]<br />
|<br />
|PICA_REG_COLOR_OPERATION<br />
|-<br />
| 0101<br />
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]<br />
| <br />
|PICA_REG_BLEND_FUNC<br />
|-<br />
| 0102<br />
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]<br />
| <br />
|PICA_REG_LOGIC_OP<br />
|-<br />
| 0103<br />
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]<br />
| <br />
|PICA_REG_BLEND_COLOR<br />
|-<br />
| 0104<br />
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]<br />
| <br />
|PICA_REG_FRAGOP_ALPHA_TEST<br />
|-<br />
| 0105<br />
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]<br />
| <br />
|PICA_REG_STENCIL_TEST<br />
|-<br />
| 0106<br />
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]<br />
| <br />
|PICA_REG_STENCIL_OP<br />
|-<br />
| 0107<br />
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]<br />
| <br />
|PICA_REG_DEPTH_COLOR_MASK<br />
|-<br />
| 0108<br />
| [[#GPUREG_0108|GPUREG_0108]]<br />
| <br />
|<br />
|-<br />
| 0109<br />
| [[#GPUREG_0109|GPUREG_0109]]<br />
| <br />
|<br />
|-<br />
| 010A<br />
| [[#GPUREG_010A|GPUREG_010A]]<br />
| <br />
|<br />
|-<br />
| 010B<br />
| [[#GPUREG_010B|GPUREG_010B]]<br />
| <br />
|<br />
|-<br />
| 010C<br />
| [[#GPUREG_010C|GPUREG_010C]]<br />
| <br />
|<br />
|-<br />
| 010D<br />
| [[#GPUREG_010D|GPUREG_010D]]<br />
| <br />
|<br />
|-<br />
| 010E<br />
| [[#GPUREG_010E|GPUREG_010E]]<br />
| <br />
|<br />
|-<br />
| 010F<br />
| [[#GPUREG_010F|GPUREG_010F]]<br />
| <br />
|<br />
|-<br />
| 0110<br />
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR0<br />
|-<br />
| 0111<br />
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR1<br />
|-<br />
| 0112<br />
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_READ<br />
|-<br />
| 0113<br />
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_WRITE<br />
|-<br />
| 0114<br />
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_READ<br />
|-<br />
| 0115<br />
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_WRITE<br />
|-<br />
| 0116<br />
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_DEPTH_MODE<br />
|-<br />
| 0117<br />
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_MODE<br />
|-<br />
| 0118<br />
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST2<br />
|-<br />
| 0119<br />
| [[#GPUREG_0119|GPUREG_0119]]<br />
| <br />
|<br />
|-<br />
| 011A<br />
| [[#GPUREG_011A|GPUREG_011A]]<br />
| <br />
|<br />
|-<br />
| 011B<br />
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]<br />
|<br />
|PICA_REG_RENDER_BLOCK_FORMAT<br />
|-<br />
| 011C<br />
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]<br />
|<br />
|PICA_REG_RENDER_BUF_DEPTH_ADDR<br />
|-<br />
| 011D<br />
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_ADDR<br />
|-<br />
| 011E<br />
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]<br />
| <br />
|PICA_REG_RENDER_BUF_RESOLUTION0<br />
|-<br />
| 011F<br />
| [[#GPUREG_011F|GPUREG_011F]]<br />
| <br />
|<br />
|-<br />
| 0120<br />
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_XY<br />
|-<br />
| 0121<br />
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z<br />
|-<br />
| 0122<br />
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z_COLOR<br />
|-<br />
| 0123<br />
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]<br />
|?<br />
|PICA_REG_GAS_LUT_INDEX<br />
|-<br />
| 0124<br />
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]<br />
|?<br />
|PICA_REG_GAS_LUT_DATA<br />
|-<br />
| 0125<br />
| [[#GPUREG_0125|GPUREG_0125]]<br />
| <br />
|<br />
|-<br />
| 0126<br />
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]<br />
|?<br />
|PICA_REG_GAS_DELTAZ_DEPTH<br />
|-<br />
| 0127<br />
| [[#GPUREG_0127|GPUREG_0127]]<br />
| <br />
|<br />
|-<br />
| 0128<br />
| [[#GPUREG_0128|GPUREG_0128]]<br />
| <br />
|<br />
|-<br />
| 0129<br />
| [[#GPUREG_0129|GPUREG_0129]]<br />
| <br />
|<br />
|-<br />
| 012A<br />
| [[#GPUREG_012A|GPUREG_012A]]<br />
| <br />
|<br />
|-<br />
| 012B<br />
| [[#GPUREG_012B|GPUREG_012B]]<br />
| <br />
|<br />
|-<br />
| 012C<br />
| [[#GPUREG_012C|GPUREG_012C]]<br />
| <br />
|<br />
|-<br />
| 012D<br />
| [[#GPUREG_012D|GPUREG_012D]]<br />
| <br />
|<br />
|-<br />
| 012E<br />
| [[#GPUREG_012E|GPUREG_012E]]<br />
| <br />
|<br />
|-<br />
| 012F<br />
| [[#GPUREG_012F|GPUREG_012F]]<br />
| <br />
|<br />
|-<br />
| 0130<br />
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]<br />
|?<br />
|PICA_REG_FRAGOP_SHADOW<br />
|-<br />
| 0131<br />
| [[#GPUREG_0131|GPUREG_0131]]<br />
| <br />
|<br />
|-<br />
| 0132<br />
| [[#GPUREG_0132|GPUREG_0132]]<br />
| <br />
|<br />
|-<br />
| 0133<br />
| [[#GPUREG_0133|GPUREG_0133]]<br />
| <br />
|<br />
|-<br />
| 0134<br />
| [[#GPUREG_0134|GPUREG_0134]]<br />
| <br />
|<br />
|-<br />
| 0135<br />
| [[#GPUREG_0135|GPUREG_0135]]<br />
| <br />
|<br />
|-<br />
| 0136<br />
| [[#GPUREG_0136|GPUREG_0136]]<br />
| <br />
|<br />
|-<br />
| 0137<br />
| [[#GPUREG_0137|GPUREG_0137]]<br />
| <br />
|<br />
|-<br />
| 0138<br />
| [[#GPUREG_0138|GPUREG_0138]]<br />
| <br />
|<br />
|-<br />
| 0139<br />
| [[#GPUREG_0139|GPUREG_0139]]<br />
| <br />
|<br />
|-<br />
| 013A<br />
| [[#GPUREG_013A|GPUREG_013A]]<br />
| <br />
|<br />
|-<br />
| 013B<br />
| [[#GPUREG_013B|GPUREG_013B]]<br />
| <br />
|<br />
|-<br />
| 013C<br />
| [[#GPUREG_013C|GPUREG_013C]]<br />
| <br />
|<br />
|-<br />
| 013D<br />
| [[#GPUREG_013D|GPUREG_013D]]<br />
| <br />
|<br />
|-<br />
| 013E<br />
| [[#GPUREG_013E|GPUREG_013E]]<br />
| <br />
|<br />
|-<br />
| 013F<br />
| [[#GPUREG_013F|GPUREG_013F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Fragment lighting registers (0x140-0x1FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0140<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START<br />
|-<br />
| 0141<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR1<br />
|-<br />
| 0142<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIFFUSE<br />
|-<br />
| 0143<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_AMBIENT<br />
|-<br />
| 0144<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_XY<br />
|-<br />
| 0145<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_Z<br />
|-<br />
| 0146<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_XY<br />
|-<br />
| 0147<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_Z<br />
|-<br />
| 0148<br />
| [[#GPUREG_0148|GPUREG_0148]]<br />
| <br />
|<br />
|-<br />
| 0149<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]<br />
| <br />
|PICA_REG_FRAG_LIGHT0_TYPE<br />
|-<br />
| 014A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS<br />
|-<br />
| 014B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE<br />
|-<br />
| 014C<br />
| [[#GPUREG_014C|GPUREG_014C]]<br />
| <br />
|<br />
|-<br />
| 014D<br />
| [[#GPUREG_014D|GPUREG_014D]]<br />
| <br />
|<br />
|-<br />
| 014E<br />
| [[#GPUREG_014E|GPUREG_014E]]<br />
| <br />
|<br />
|-<br />
| 014F<br />
| [[#GPUREG_014F|GPUREG_014F]]<br />
| <br />
|<br />
|-<br />
| 0150<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR0<br />
|-<br />
| 0151<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR1<br />
|-<br />
| 0152<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIFFUSE<br />
|-<br />
| 0153<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_AMBIENT<br />
|-<br />
| 0154<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_XY<br />
|-<br />
| 0155<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_Z<br />
|-<br />
| 0156<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_XY<br />
|-<br />
| 0157<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_Z<br />
|-<br />
| 0158<br />
| [[#GPUREG_0158|GPUREG_0158]]<br />
| <br />
|<br />
|-<br />
| 0159<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_TYPE<br />
|-<br />
| 015A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS<br />
|-<br />
| 015B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE<br />
|-<br />
| 015C<br />
| [[#GPUREG_015C|GPUREG_015C]]<br />
| <br />
|<br />
|-<br />
| 015D<br />
| [[#GPUREG_015D|GPUREG_015D]]<br />
| <br />
|<br />
|-<br />
| 015E<br />
| [[#GPUREG_015E|GPUREG_015E]]<br />
| <br />
|<br />
|-<br />
| 015F<br />
| [[#GPUREG_015F|GPUREG_015F]]<br />
| <br />
|<br />
|-<br />
| 0160<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR0<br />
|-<br />
| 0161<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR1<br />
|-<br />
| 0162<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIFFUSE<br />
|-<br />
| 0163<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_AMBIENT<br />
|-<br />
| 0164<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_XY<br />
|-<br />
| 0165<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_Z<br />
|-<br />
| 0166<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_XY<br />
|-<br />
| 0167<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_Z<br />
|-<br />
| 0168<br />
| [[#GPUREG_0168|GPUREG_0168]]<br />
| <br />
|<br />
|-<br />
| 0169<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_TYPE<br />
|-<br />
| 016A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS<br />
|-<br />
| 016B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE<br />
|-<br />
| 016C<br />
| [[#GPUREG_016C|GPUREG_016C]]<br />
| <br />
|<br />
|-<br />
| 016D<br />
| [[#GPUREG_016D|GPUREG_016D]]<br />
| <br />
|<br />
|-<br />
| 016E<br />
| [[#GPUREG_016E|GPUREG_016E]]<br />
| <br />
|<br />
|-<br />
| 016F<br />
| [[#GPUREG_016F|GPUREG_016F]]<br />
| <br />
|<br />
|-<br />
| 0170<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR0<br />
|-<br />
| 0171<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR1<br />
|-<br />
| 0172<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIFFUSE<br />
|-<br />
| 0173<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_AMBIENT<br />
|-<br />
| 0174<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_XY<br />
|-<br />
| 0175<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_Z<br />
|-<br />
| 0176<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]<br />
|? <br />
|PICA_REG_FRAG_LIGHT3_SPOT_XY<br />
|-<br />
| 0177<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPOT_Z<br />
|-<br />
| 0178<br />
| [[#GPUREG_0178|GPUREG_0178]]<br />
| <br />
|<br />
|-<br />
| 0179<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_TYPE<br />
|-<br />
| 017A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS<br />
|-<br />
| 017B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE<br />
|-<br />
| 017C<br />
| [[#GPUREG_017C|GPUREG_017C]]<br />
| <br />
|<br />
|-<br />
| 017D<br />
| [[#GPUREG_017D|GPUREG_017D]]<br />
| <br />
|<br />
|-<br />
| 017E<br />
| [[#GPUREG_017E|GPUREG_017E]]<br />
| <br />
|<br />
|-<br />
| 017F<br />
| [[#GPUREG_017F|GPUREG_017F]]<br />
| <br />
|<br />
|-<br />
| 0180<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR0<br />
|-<br />
| 0181<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR1<br />
|-<br />
| 0182<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIFFUSE<br />
|-<br />
| 0183<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_AMBIENT<br />
|-<br />
| 0184<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_XY<br />
|-<br />
| 0185<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_Z<br />
|-<br />
| 0186<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_XY<br />
|-<br />
| 0187<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_Z<br />
|-<br />
| 0188<br />
| [[#GPUREG_0188|GPUREG_0188]]<br />
| <br />
|<br />
|-<br />
| 0189<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_TYPE<br />
|-<br />
| 018A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS<br />
|-<br />
| 018B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE<br />
|-<br />
| 018C<br />
| [[#GPUREG_018C|GPUREG_018C]]<br />
| <br />
|<br />
|-<br />
| 018D<br />
| [[#GPUREG_018D|GPUREG_018D]]<br />
| <br />
|<br />
|-<br />
| 018E<br />
| [[#GPUREG_018E|GPUREG_018E]]<br />
| <br />
|<br />
|-<br />
| 018F<br />
| [[#GPUREG_018F|GPUREG_018F]]<br />
| <br />
|<br />
|-<br />
| 0190<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR0<br />
|-<br />
| 0191<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR1<br />
|-<br />
| 0192<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_DIFFUSE<br />
|-<br />
| 0193<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_AMBIENT<br />
|-<br />
| 0194<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_XY<br />
|-<br />
| 0195<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_Z<br />
|-<br />
| 0196<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_XY<br />
|-<br />
| 0197<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_Z<br />
|-<br />
| 0198<br />
| [[#GPUREG_0198|GPUREG_0198]]<br />
| <br />
|<br />
|-<br />
| 0199<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_TYPE<br />
|-<br />
| 019A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS<br />
|-<br />
| 019B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE<br />
|-<br />
| 019C<br />
| [[#GPUREG_019C|GPUREG_019C]]<br />
| <br />
|<br />
|-<br />
| 019D<br />
| [[#GPUREG_019D|GPUREG_019D]]<br />
| <br />
|<br />
|-<br />
| 019E<br />
| [[#GPUREG_019E|GPUREG_019E]]<br />
| <br />
|<br />
|-<br />
| 019F<br />
| [[#GPUREG_019F|GPUREG_019F]]<br />
| <br />
|<br />
|-<br />
| 01A0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR0<br />
|-<br />
| 01A1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR1<br />
|-<br />
| 01A2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIFFUSE<br />
|-<br />
| 01A3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_AMBIENT<br />
|-<br />
| 01A4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_XY<br />
|-<br />
| 01A5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_Z<br />
|-<br />
| 01A6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_XY<br />
|-<br />
| 01A7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_Z<br />
|-<br />
| 01A8<br />
| [[#GPUREG_01A8|GPUREG_01A8]]<br />
| <br />
|<br />
|-<br />
| 01A9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_TYPE<br />
|-<br />
| 01AA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS<br />
|-<br />
| 01AB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE<br />
|-<br />
| 01AC<br />
| [[#GPUREG_01AC|GPUREG_01AC]]<br />
| <br />
|<br />
|-<br />
| 01AD<br />
| [[#GPUREG_01AD|GPUREG_01AD]]<br />
| <br />
|<br />
|-<br />
| 01AE<br />
| [[#GPUREG_01AE|GPUREG_01AE]]<br />
| <br />
|<br />
|-<br />
| 01AF<br />
| [[#GPUREG_01AF|GPUREG_01AF]]<br />
| <br />
|<br />
|-<br />
| 01B0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR0<br />
|-<br />
| 01B1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR1<br />
|-<br />
| 01B2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_DIFFUSE<br />
|-<br />
| 01B3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_AMBIENT<br />
|-<br />
| 01B4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_XY<br />
|-<br />
| 01B5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_Z<br />
|-<br />
| 01B6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_XY<br />
|-<br />
| 01B7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_Z<br />
|-<br />
| 01B8<br />
| [[#GPUREG_01B8|GPUREG_01B8]]<br />
| <br />
|<br />
|-<br />
| 01B9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_TYPE<br />
|-<br />
| 01BA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS<br />
|-<br />
| 01BB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE<br />
|-<br />
| 01BC<br />
| [[#GPUREG_01BC|GPUREG_01BC]]<br />
| <br />
|<br />
|-<br />
| 01BD<br />
| [[#GPUREG_01BD|GPUREG_01BD]]<br />
| <br />
|<br />
|-<br />
| 01BE<br />
| [[#GPUREG_01BE|GPUREG_01BE]]<br />
| <br />
|<br />
|-<br />
| 01BF<br />
| [[#GPUREG_01BF|GPUREG_01BF]]<br />
| <br />
|<br />
|-<br />
| 01C0<br />
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_AMBIENT<br />
|-<br />
| 01C1<br />
| [[#GPUREG_01C1|GPUREG_01C1]]<br />
| <br />
|<br />
|-<br />
| 01C2<br />
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_NUM<br />
|-<br />
| 01C3<br />
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE0<br />
|-<br />
| 01C4<br />
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE1<br />
|-<br />
| 01C5<br />
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT<br />
|-<br />
| 01C6<br />
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN1<br />
|-<br />
| 01C7<br />
| [[#GPUREG_01C7|GPUREG_01C7]]<br />
| <br />
|<br />
|-<br />
| 01C8<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA0<br />
|-<br />
| 01C9<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA1<br />
|-<br />
| 01CA<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA2<br />
|-<br />
| 01CB<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA3<br />
|-<br />
| 01CC<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA4<br />
|-<br />
| 01CD<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA5<br />
|-<br />
| 01CE<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA6<br />
|-<br />
| 01CF<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA7<br />
|-<br />
| 01D0<br />
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT<br />
|-<br />
| 01D1<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTINPUT<br />
|-<br />
| 01D2<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTSCALE<br />
|-<br />
| 01D3<br />
| [[#GPUREG_01D3|GPUREG_01D3]]<br />
| <br />
|<br />
|-<br />
| 01D4<br />
| [[#GPUREG_01D4|GPUREG_01D4]]<br />
| <br />
|<br />
|-<br />
| 01D5<br />
| [[#GPUREG_01D5|GPUREG_01D5]]<br />
| <br />
|<br />
|-<br />
| 01D6<br />
| [[#GPUREG_01D6|GPUREG_01D6]]<br />
| <br />
|<br />
|-<br />
| 01D7<br />
| [[#GPUREG_01D7|GPUREG_01D7]]<br />
| <br />
|<br />
|-<br />
| 01D8<br />
| [[#GPUREG_01D8|GPUREG_01D8]]<br />
| <br />
|<br />
|-<br />
| 01D9<br />
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_EN_ID<br />
|-<br />
| 01DA<br />
| [[#GPUREG_01DA|GPUREG_01DA]]<br />
| <br />
|<br />
|-<br />
| 01DB<br />
| [[#GPUREG_01DB|GPUREG_01DB]]<br />
| <br />
|<br />
|-<br />
| 01DC<br />
| [[#GPUREG_01DC|GPUREG_01DC]]<br />
| <br />
|<br />
|-<br />
| 01DD<br />
| [[#GPUREG_01DD|GPUREG_01DD]]<br />
| <br />
|<br />
|-<br />
| 01DE<br />
| [[#GPUREG_01DE|GPUREG_01DE]]<br />
| <br />
|<br />
|-<br />
| 01DF<br />
| [[#GPUREG_01DF|GPUREG_01DF]]<br />
| <br />
|<br />
|-<br />
| 01E0<br />
| [[#GPUREG_01E0|GPUREG_01E0]]<br />
| <br />
|<br />
|-<br />
| 01E1<br />
| [[#GPUREG_01E1|GPUREG_01E1]]<br />
| <br />
|<br />
|-<br />
| 01E2<br />
| [[#GPUREG_01E2|GPUREG_01E2]]<br />
| <br />
|<br />
|-<br />
| 01E3<br />
| [[#GPUREG_01E3|GPUREG_01E3]]<br />
| <br />
|<br />
|-<br />
| 01E4<br />
| [[#GPUREG_01E4|GPUREG_01E4]]<br />
| <br />
|<br />
|-<br />
| 01E5<br />
| [[#GPUREG_01E5|GPUREG_01E5]]<br />
| <br />
|<br />
|-<br />
| 01E6<br />
| [[#GPUREG_01E6|GPUREG_01E6]]<br />
| <br />
|<br />
|-<br />
| 01E7<br />
| [[#GPUREG_01E7|GPUREG_01E7]]<br />
| <br />
|<br />
|-<br />
| 01E8<br />
| [[#GPUREG_01E8|GPUREG_01E8]]<br />
| <br />
|<br />
|-<br />
| 01E9<br />
| [[#GPUREG_01E9|GPUREG_01E9]]<br />
| <br />
|<br />
|-<br />
| 01EA<br />
| [[#GPUREG_01EA|GPUREG_01EA]]<br />
| <br />
|<br />
|-<br />
| 01EB<br />
| [[#GPUREG_01EB|GPUREG_01EB]]<br />
| <br />
|<br />
|-<br />
| 01EC<br />
| [[#GPUREG_01EC|GPUREG_01EC]]<br />
| <br />
|<br />
|-<br />
| 01ED<br />
| [[#GPUREG_01ED|GPUREG_01ED]]<br />
| <br />
|<br />
|-<br />
| 01EE<br />
| [[#GPUREG_01EE|GPUREG_01EE]]<br />
| <br />
|<br />
|-<br />
| 01EF<br />
| [[#GPUREG_01EF|GPUREG_01EF]]<br />
| <br />
|<br />
|-<br />
| 01F0<br />
| [[#GPUREG_01F0|GPUREG_01F0]]<br />
| <br />
|<br />
|-<br />
| 01F1<br />
| [[#GPUREG_01F1|GPUREG_01F1]]<br />
| <br />
|<br />
|-<br />
| 01F2<br />
| [[#GPUREG_01F2|GPUREG_01F2]]<br />
| <br />
|<br />
|-<br />
| 01F3<br />
| [[#GPUREG_01F3|GPUREG_01F3]]<br />
| <br />
|<br />
|-<br />
| 01F4<br />
| [[#GPUREG_01F4|GPUREG_01F4]]<br />
| <br />
|<br />
|-<br />
| 01F5<br />
| [[#GPUREG_01F5|GPUREG_01F5]]<br />
| <br />
|<br />
|-<br />
| 01F6<br />
| [[#GPUREG_01F6|GPUREG_01F6]]<br />
| <br />
|<br />
|-<br />
| 01F7<br />
| [[#GPUREG_01F7|GPUREG_01F7]]<br />
| <br />
|<br />
|-<br />
| 01F8<br />
| [[#GPUREG_01F8|GPUREG_01F8]]<br />
| <br />
|<br />
|-<br />
| 01F9<br />
| [[#GPUREG_01F9|GPUREG_01F9]]<br />
| <br />
|<br />
|-<br />
| 01FA<br />
| [[#GPUREG_01FA|GPUREG_01FA]]<br />
| <br />
|<br />
|-<br />
| 01FB<br />
| [[#GPUREG_01FB|GPUREG_01FB]]<br />
| <br />
|<br />
|-<br />
| 01FC<br />
| [[#GPUREG_01FC|GPUREG_01FC]]<br />
| <br />
|<br />
|-<br />
| 01FD<br />
| [[#GPUREG_01FD|GPUREG_01FD]]<br />
| <br />
|<br />
|-<br />
| 01FE<br />
| [[#GPUREG_01FE|GPUREG_01FE]]<br />
| <br />
|<br />
|-<br />
| 01FF<br />
| [[#GPUREG_01FF|GPUREG_01FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Geometry pipeline registers (0x200-0x27F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0200<br />
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR<br />
|-<br />
| 0201<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS0<br />
|-<br />
| 0202<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS1<br />
|-<br />
| 0203<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET<br />
|-<br />
| 0204<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT0<br />
|-<br />
| 0205<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT1<br />
|-<br />
| 0206<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0207<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0208<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0209<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020B<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020C<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020E<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020F<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0210<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0211<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0212<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0213<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0214<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0215<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0216<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0217<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0218<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0219<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021B<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021C<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021E<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021F<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0220<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0221<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0222<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0223<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0224<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0225<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0226<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0227<br />
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET<br />
|-<br />
| 0228<br />
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]<br />
| <br />
|PICA_REG_DRAW_VERTEX_NUM<br />
|-<br />
| 0229<br />
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]<br />
| ?<br />
|PICA_REG_DRAW_MODE0<br />
|-<br />
| 022A<br />
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]<br />
|<br />
|PICA_REG_DRAW_VERTEX_OFFSET<br />
|-<br />
| 022B<br />
| [[#GPUREG_022B|GPUREG_022B]]<br />
| <br />
|<br />
|-<br />
| 022C<br />
| [[#GPUREG_022C|GPUREG_022C]]<br />
| <br />
|<br />
|-<br />
| 022D<br />
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]<br />
| <br />
|PICA_REG_POST_VERTEX_CACHE_NUM<br />
|-<br />
| 022E<br />
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]<br />
|<br />
|PICA_REG_START_DRAW_ARRAY<br />
|-<br />
| 022F<br />
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]<br />
|<br />
|PICA_REG_START_DRAW_ELEMENT<br />
|-<br />
| 0230<br />
| [[#GPUREG_0230|GPUREG_0230]]<br />
| <br />
|<br />
|-<br />
| 0231<br />
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]<br />
|?<br />
|PICA_REG_VTX_FUNC<br />
|-<br />
| 0232<br />
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR<br />
|-<br />
| 0233<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA0<br />
|-<br />
| 0234<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA1<br />
|-<br />
| 0235<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA2<br />
|-<br />
| 0236<br />
| [[#GPUREG_0236|GPUREG_0236]]<br />
| <br />
|<br />
|-<br />
| 0237<br />
| [[#GPUREG_0237|GPUREG_0237]]<br />
| <br />
|<br />
|-<br />
| 0238<br />
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH0<br />
|-<br />
| 0239<br />
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH1<br />
|-<br />
| 023A<br />
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH0<br />
|-<br />
| 023B<br />
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH1<br />
|-<br />
| 023C<br />
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH0<br />
|-<br />
| 023D<br />
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH1<br />
|-<br />
| 023E<br />
| [[#GPUREG_023E|GPUREG_023E]]<br />
| <br />
|<br />
|-<br />
| 023F<br />
| [[#GPUREG_023F|GPUREG_023F]]<br />
| <br />
|<br />
|-<br />
| 0240<br />
| [[#GPUREG_0240|GPUREG_0240]]<br />
| <br />
|<br />
|-<br />
| 0241<br />
| [[#GPUREG_0241|GPUREG_0241]]<br />
| <br />
|<br />
|-<br />
| 0242<br />
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]<br />
|?<br />
|PICA_REG_VS_ATTR_NUM1<br />
|-<br />
| 0243<br />
| [[#GPUREG_0243|GPUREG_0243]]<br />
| <br />
|<br />
|-<br />
| 0244<br />
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]<br />
|?<br />
|PICA_REG_VS_COM_MODE<br />
|-<br />
| 0245<br />
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC0<br />
|-<br />
| 0246<br />
| [[#GPUREG_0246|GPUREG_0246]]<br />
| <br />
|<br />
|-<br />
| 0247<br />
| [[#GPUREG_0247|GPUREG_0247]]<br />
| <br />
|<br />
|-<br />
| 0248<br />
| [[#GPUREG_0248|GPUREG_0248]]<br />
| <br />
|<br />
|-<br />
| 0249<br />
| [[#GPUREG_0249|GPUREG_0249]]<br />
| <br />
|<br />
|-<br />
| 024A<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM1<br />
|-<br />
| 024B<br />
| [[#GPUREG_024B|GPUREG_024B]]<br />
|<br />
|<br />
|-<br />
| 024C<br />
| [[#GPUREG_024C|GPUREG_024C]]<br />
| <br />
|<br />
|-<br />
| 024D<br />
| [[#GPUREG_024D|GPUREG_024D]]<br />
| <br />
|<br />
|-<br />
| 024E<br />
| [[#GPUREG_024E|GPUREG_024E]]<br />
| <br />
|<br />
|-<br />
| 024F<br />
| [[#GPUREG_024F|GPUREG_024F]]<br />
| <br />
|<br />
|-<br />
| 0250<br />
| [[#GPUREG_0250|GPUREG_0250]]<br />
| <br />
|<br />
|-<br />
| 0251<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM2<br />
|-<br />
| 0252<br />
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]<br />
|?<br />
|PICA_REG_GS_MISC_REG0<br />
|-<br />
| 0253<br />
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]<br />
|?<br />
|PICA_REG_DRAW_MODE1<br />
|-<br />
| 0254<br />
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]<br />
|?<br />
|PICA_REG_GS_MISC_REG1<br />
|-<br />
| 0255<br />
| [[#GPUREG_0255|GPUREG_0255]]<br />
| <br />
|<br />
|-<br />
| 0256<br />
| [[#GPUREG_0256|GPUREG_0256]]<br />
| <br />
|<br />
|-<br />
| 0257<br />
| [[#GPUREG_0257|GPUREG_0257]]<br />
| <br />
|<br />
|-<br />
| 0258<br />
| [[#GPUREG_0258|GPUREG_0258]]<br />
| <br />
|<br />
|-<br />
| 0259<br />
| [[#GPUREG_0259|GPUREG_0259]]<br />
| <br />
|<br />
|-<br />
| 025A<br />
| [[#GPUREG_025A|GPUREG_025A]]<br />
| <br />
|<br />
|-<br />
| 025B<br />
| [[#GPUREG_025B|GPUREG_025B]]<br />
| <br />
|<br />
|-<br />
| 025C<br />
| [[#GPUREG_025C|GPUREG_025C]]<br />
| <br />
|<br />
|-<br />
| 025D<br />
| [[#GPUREG_025D|GPUREG_025D]]<br />
| <br />
|<br />
|-<br />
| 025E<br />
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]<br />
| ?<br />
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3<br />
|-<br />
| 025F<br />
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC1<br />
|-<br />
| 0260<br />
| [[#GPUREG_0260|GPUREG_0260]]<br />
| <br />
|<br />
|-<br />
| 0261<br />
| [[#GPUREG_0261|GPUREG_0261]]<br />
| <br />
|<br />
|-<br />
| 0262<br />
| [[#GPUREG_0262|GPUREG_0262]]<br />
| <br />
|<br />
|-<br />
| 0263<br />
| [[#GPUREG_0263|GPUREG_0263]]<br />
| <br />
|<br />
|-<br />
| 0264<br />
| [[#GPUREG_0264|GPUREG_0264]]<br />
| <br />
|<br />
|-<br />
| 0265<br />
| [[#GPUREG_0265|GPUREG_0265]]<br />
| <br />
|<br />
|-<br />
| 0266<br />
| [[#GPUREG_0266|GPUREG_0266]]<br />
| <br />
|<br />
|-<br />
| 0267<br />
| [[#GPUREG_0267|GPUREG_0267]]<br />
| <br />
|<br />
|-<br />
| 0268<br />
| [[#GPUREG_0268|GPUREG_0268]]<br />
| <br />
|<br />
|-<br />
| 0269<br />
| [[#GPUREG_0269|GPUREG_0269]]<br />
| <br />
|<br />
|-<br />
| 026A<br />
| [[#GPUREG_026A|GPUREG_026A]]<br />
| <br />
|<br />
|-<br />
| 026B<br />
| [[#GPUREG_026B|GPUREG_026B]]<br />
| <br />
|<br />
|-<br />
| 026C<br />
| [[#GPUREG_026C|GPUREG_026C]]<br />
| <br />
|<br />
|-<br />
| 026D<br />
| [[#GPUREG_026D|GPUREG_026D]]<br />
| <br />
|<br />
|-<br />
| 026E<br />
| [[#GPUREG_026E|GPUREG_026E]]<br />
| <br />
|<br />
|-<br />
| 026F<br />
| [[#GPUREG_026F|GPUREG_026F]]<br />
| <br />
|<br />
|-<br />
| 0270<br />
| [[#GPUREG_0270|GPUREG_0270]]<br />
| <br />
|<br />
|-<br />
| 0271<br />
| [[#GPUREG_0271|GPUREG_0271]]<br />
| <br />
|<br />
|-<br />
| 0272<br />
| [[#GPUREG_0272|GPUREG_0272]]<br />
| <br />
|<br />
|-<br />
| 0273<br />
| [[#GPUREG_0273|GPUREG_0273]]<br />
| <br />
|<br />
|-<br />
| 0274<br />
| [[#GPUREG_0274|GPUREG_0274]]<br />
| <br />
|<br />
|-<br />
| 0275<br />
| [[#GPUREG_0275|GPUREG_0275]]<br />
| <br />
|<br />
|-<br />
| 0276<br />
| [[#GPUREG_0276|GPUREG_0276]]<br />
| <br />
|<br />
|-<br />
| 0277<br />
| [[#GPUREG_0277|GPUREG_0277]]<br />
| <br />
|<br />
|-<br />
| 0278<br />
| [[#GPUREG_0278|GPUREG_0278]]<br />
| <br />
|<br />
|-<br />
| 0279<br />
| [[#GPUREG_0279|GPUREG_0279]]<br />
| <br />
|<br />
|-<br />
| 027A<br />
| [[#GPUREG_027A|GPUREG_027A]]<br />
| <br />
|<br />
|-<br />
| 027B<br />
| [[#GPUREG_027B|GPUREG_027B]]<br />
| <br />
|<br />
|-<br />
| 027C<br />
| [[#GPUREG_027C|GPUREG_027C]]<br />
| <br />
|<br />
|-<br />
| 027D<br />
| [[#GPUREG_027D|GPUREG_027D]]<br />
| <br />
|<br />
|-<br />
| 027E<br />
| [[#GPUREG_027E|GPUREG_027E]]<br />
| <br />
|<br />
|-<br />
| 027F<br />
| [[#GPUREG_027F|GPUREG_027F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Shader registers (0x280-0x2DF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
! colspan=4 | Geometry shader<br />
|-<br />
| 0280<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_GS_BOOL<br />
|-<br />
| 0281<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_GS_INT0<br />
|-<br />
| 0282<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_GS_INT1<br />
|-<br />
| 0283<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_GS_INT2<br />
|-<br />
| 0284<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_GS_INT3<br />
|-<br />
| 0285<br />
| [[#GPUREG_0285|GPUREG_0285]]<br />
| <br />
|<br />
|-<br />
| 0286<br />
| [[#GPUREG_0286|GPUREG_0286]]<br />
| <br />
|<br />
|-<br />
| 0287<br />
| [[#GPUREG_0287|GPUREG_0287]]<br />
| <br />
|<br />
|-<br />
| 0288<br />
| [[#GPUREG_0288|GPUREG_0288]]<br />
| <br />
|<br />
|-<br />
| 0289<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_GS_ATTR_NUM<br />
|-<br />
| 028A<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_GS_START_ADDR<br />
|-<br />
| 028B<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP0<br />
|-<br />
| 028C<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP1<br />
|-<br />
| 028D<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_GS_OUT_REG_MASK<br />
|-<br />
| 028E<br />
| [[#GPUREG_028E|GPUREG_028E]]<br />
| <br />
|<br />
|-<br />
| 028F<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_GS_PROG_RENEWAL_END<br />
|-<br />
| 0290<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_GS_FLOAT_ADDR<br />
|-<br />
| 0291<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA0<br />
|-<br />
| 0292<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA1<br />
|-<br />
| 0293<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA2<br />
|-<br />
| 0294<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA3<br />
|-<br />
| 0295<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA4<br />
|-<br />
| 0296<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA5<br />
|-<br />
| 0297<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA6<br />
|-<br />
| 0298<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA7<br />
|-<br />
| 0299<br />
| [[#GPUREG_0299|GPUREG_0299]]<br />
| <br />
|<br />
|-<br />
| 029A<br />
| [[#GPUREG_029A|GPUREG_029A]]<br />
| <br />
|<br />
|-<br />
| 029B<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_GS_PROG_ADDR<br />
|-<br />
| 029C<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_DATA0<br />
|-<br />
| 029D<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_DATA1<br />
|-<br />
| 029E<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_DATA2<br />
|-<br />
| 029F<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_DATA3<br />
|-<br />
| 02A0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_DATA4<br />
|-<br />
| 02A1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_DATA5<br />
|-<br />
| 02A2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_DATA6<br />
|-<br />
| 02A3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_DATA7<br />
|-<br />
| 02A4<br />
| [[#GPUREG_02A4|GPUREG_02A4]]<br />
| <br />
|<br />
|-<br />
| 02A5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02A6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02A7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02A8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02A9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02AA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02AB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02AC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02AD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02AE<br />
| [[#GPUREG_02AE|GPUREG_02AE]]<br />
| <br />
|<br />
|-<br />
| 02AF<br />
| [[#GPUREG_02AF|GPUREG_02AF]]<br />
| <br />
|<br />
|-<br />
! colspan=4 | Vertex shader<br />
|-<br />
| 02B0<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_VS_BOOL<br />
|-<br />
| 02B1<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_VS_INT0<br />
|-<br />
| 02B2<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_VS_INT1<br />
|-<br />
| 02B3<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_VS_INT2<br />
|-<br />
| 02B4<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_VS_INT3<br />
|-<br />
| 02B5<br />
| [[#GPUREG_02B5|GPUREG_02B5]]<br />
| <br />
|<br />
|-<br />
| 02B6<br />
| [[#GPUREG_02B6|GPUREG_02B6]]<br />
| <br />
|<br />
|-<br />
| 02B7<br />
| [[#GPUREG_02B7|GPUREG_02B7]]<br />
| <br />
|<br />
|-<br />
| 02B8<br />
| [[#GPUREG_02B8|GPUREG_02B8]]<br />
| <br />
|<br />
|-<br />
| 02B9<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_VS_ATTR_NUM0<br />
|-<br />
| 02BA<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_VS_START_ADDR<br />
|-<br />
| 02BB<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP0<br />
|-<br />
| 02BC<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP1<br />
|-<br />
| 02BD<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_VS_OUT_REG_MASK<br />
|-<br />
| 02BE<br />
| [[#GPUREG_02BE|GPUREG_02BE]]<br />
| <br />
|<br />
|-<br />
| 02BF<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_VS_PROG_RENEWAL_END<br />
|-<br />
| 02C0<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_VS_FLOAT_ADDR<br />
|-<br />
| 02C1<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA0<br />
|-<br />
| 02C2<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA1<br />
|-<br />
| 02C3<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA2<br />
|-<br />
| 02C4<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA3<br />
|-<br />
| 02C5<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA4<br />
|-<br />
| 02C6<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA5<br />
|-<br />
| 02C7<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA6<br />
|-<br />
| 02C8<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA7<br />
|-<br />
| 02C9<br />
| [[#GPUREG_02C9|GPUREG_02C9]]<br />
| <br />
|<br />
|-<br />
| 02CA<br />
| [[#GPUREG_02CA|GPUREG_02CA]]<br />
| <br />
|<br />
|-<br />
| 02CB<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_ADDR<br />
|-<br />
| 02CC<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_DATA0<br />
|-<br />
| 02CD<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_DATA1<br />
|-<br />
| 02CE<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_DATA2<br />
|-<br />
| 02CF<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_DATA3<br />
|-<br />
| 02D0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_DATA4<br />
|-<br />
| 02D1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_DATA5<br />
|-<br />
| 02D2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_DATA6<br />
|-<br />
| 02D3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_DATA7<br />
|-<br />
| 02D4<br />
| [[#GPUREG_02D4|GPUREG_02D4]]<br />
| <br />
|<br />
|-<br />
| 02D5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02D6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02D7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02D8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02D9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02DA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02DB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02DC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02DD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02DE<br />
| [[#GPUREG_02DE|GPUREG_02DE]]<br />
| <br />
|<br />
|-<br />
| 02DF<br />
| [[#GPUREG_02DF|GPUREG_02DF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Unknown registers (0x2E0-0x2FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 02E0<br />
| [[#GPUREG_02E0|GPUREG_02E0]]<br />
| <br />
|<br />
|-<br />
| 02E1<br />
| [[#GPUREG_02E1|GPUREG_02E1]]<br />
| <br />
|<br />
|-<br />
| 02E2<br />
| [[#GPUREG_02E2|GPUREG_02E2]]<br />
| <br />
|<br />
|-<br />
| 02E3<br />
| [[#GPUREG_02E3|GPUREG_02E3]]<br />
| <br />
|<br />
|-<br />
| 02E4<br />
| [[#GPUREG_02E4|GPUREG_02E4]]<br />
| <br />
|<br />
|-<br />
| 02E5<br />
| [[#GPUREG_02E5|GPUREG_02E5]]<br />
| <br />
|<br />
|-<br />
| 02E6<br />
| [[#GPUREG_02E6|GPUREG_02E6]]<br />
| <br />
|<br />
|-<br />
| 02E7<br />
| [[#GPUREG_02E7|GPUREG_02E7]]<br />
| <br />
|<br />
|-<br />
| 02E8<br />
| [[#GPUREG_02E8|GPUREG_02E8]]<br />
| <br />
|<br />
|-<br />
| 02E9<br />
| [[#GPUREG_02E9|GPUREG_02E9]]<br />
| <br />
|<br />
|-<br />
| 02EA<br />
| [[#GPUREG_02EA|GPUREG_02EA]]<br />
| <br />
|<br />
|-<br />
| 02EB<br />
| [[#GPUREG_02EB|GPUREG_02EB]]<br />
| <br />
|<br />
|-<br />
| 02EC<br />
| [[#GPUREG_02EC|GPUREG_02EC]]<br />
| <br />
|<br />
|-<br />
| 02ED<br />
| [[#GPUREG_02ED|GPUREG_02ED]]<br />
| <br />
|<br />
|-<br />
| 02EE<br />
| [[#GPUREG_02EE|GPUREG_02EE]]<br />
| <br />
|<br />
|-<br />
| 02EF<br />
| [[#GPUREG_02EF|GPUREG_02EF]]<br />
| <br />
|<br />
|-<br />
| 02F0<br />
| [[#GPUREG_02F0|GPUREG_02F0]]<br />
| <br />
|<br />
|-<br />
| 02F1<br />
| [[#GPUREG_02F1|GPUREG_02F1]]<br />
| <br />
|<br />
|-<br />
| 02F2<br />
| [[#GPUREG_02F2|GPUREG_02F2]]<br />
| <br />
|<br />
|-<br />
| 02F3<br />
| [[#GPUREG_02F3|GPUREG_02F3]]<br />
| <br />
|<br />
|-<br />
| 02F4<br />
| [[#GPUREG_02F4|GPUREG_02F4]]<br />
| <br />
|<br />
|-<br />
| 02F5<br />
| [[#GPUREG_02F5|GPUREG_02F5]]<br />
| <br />
|<br />
|-<br />
| 02F6<br />
| [[#GPUREG_02F6|GPUREG_02F6]]<br />
| <br />
|<br />
|-<br />
| 02F7<br />
| [[#GPUREG_02F7|GPUREG_02F7]]<br />
| <br />
|<br />
|-<br />
| 02F8<br />
| [[#GPUREG_02F8|GPUREG_02F8]]<br />
| <br />
|<br />
|-<br />
| 02F9<br />
| [[#GPUREG_02F9|GPUREG_02F9]]<br />
| <br />
|<br />
|-<br />
| 02FA<br />
| [[#GPUREG_02FA|GPUREG_02FA]]<br />
| <br />
|<br />
|-<br />
| 02FB<br />
| [[#GPUREG_02FB|GPUREG_02FB]]<br />
| <br />
|<br />
|-<br />
| 02FC<br />
| [[#GPUREG_02FC|GPUREG_02FC]]<br />
| <br />
|<br />
|-<br />
| 02FD<br />
| [[#GPUREG_02FD|GPUREG_02FD]]<br />
| <br />
|<br />
|-<br />
| 02FE<br />
| [[#GPUREG_02FE|GPUREG_02FE]]<br />
| <br />
|<br />
|-<br />
| 02FF<br />
| [[#GPUREG_02FF|GPUREG_02FF]]<br />
| <br />
|<br />
|}<br />
<br />
== Miscellaneous registers ==<br />
<br />
=== GPUREG_FINALIZE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)<br />
|}<br />
<br />
Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.<br />
Failure to write to this register in any command buffer will result in the GPU hanging.<br />
<br />
== Rasterizer registers ==<br />
<br />
=== GPUREG_FACECULLING_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Culling mode<br />
|}<br />
<br />
This register is used to configure the face culling mode.<br />
<br />
Culling mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Front Face (Counter Clockwise)<br />
|-<br />
| 2<br />
| Back Face (Counter Clockwise)<br />
|}<br />
<br />
=== GPUREG_VIEWPORT_WIDTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, width / 2<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.<br />
<br />
=== GPUREG_VIEWPORT_INVW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / width<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.<br />
<br />
=== GPUREG_VIEWPORT_HEIGHT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, height / 2<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.<br />
<br />
=== GPUREG_VIEWPORT_INVH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / height<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.<br />
<br />
=== GPUREG_FRAGOP_CLIP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable clipping planes.<br />
<br />
=== GPUREG_FRAGOP_CLIP_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Clipping plane coefficient ''i''<br />
|}<br />
<br />
This register is used to configure clipping plane coefficients.<br />
<br />
=== GPUREG_DEPTHMAP_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near - Far<br />
|}<br />
<br />
This register is used to configure the depth range scale.<br />
<br />
=== GPUREG_DEPTHMAP_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near + Polygon Offset<br />
|}<br />
<br />
This register is used to configure the depth range bias.<br />
<br />
=== GPUREG_SH_OUTMAP_TOTAL ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of following attributes<br />
|}<br />
<br />
This register is used to configure the total shader output map attributes.<br />
<br />
=== GPUREG_SH_OUTMAP_O''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Semantic for the x component of the register.<br />
|-<br />
| 8-12<br />
| unsigned, Semantic for the y component of the register.<br />
|-<br />
| 16-20<br />
| unsigned, Semantic for the z component of the register.<br />
|-<br />
| 24-28<br />
| unsigned, Semantic for the w component of the register.<br />
|}<br />
<br />
These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.<br />
<br />
Semantic values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Semantic<br />
! Description<br />
|-<br />
| 0x00<br />
| position.x<br />
| rowspan="4" | Vertex Position<br />
|-<br />
| 0x01<br />
| position.y<br />
|-<br />
| 0x02<br />
| position.z<br />
|-<br />
| 0x03<br />
| position.w<br />
|-<br />
| 0x04<br />
| normquat.x<br />
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)<br />
|-<br />
| 0x05<br />
| normquat.y<br />
|-<br />
| 0x06<br />
| normquat.z<br />
|-<br />
| 0x07<br />
| normquat.w<br />
|-<br />
| 0x08<br />
| color.r<br />
| rowspan="4" | Vertex color<br />
|-<br />
| 0x09<br />
| color.g<br />
|-<br />
| 0x0A<br />
| color.b<br />
|-<br />
| 0x0B<br />
| color.a<br />
|-<br />
| 0x0C<br />
| texcoord0.u<br />
| rowspan="2" | Texture coordinates for texture 0<br />
|-<br />
| 0x0D<br />
| texcoord0.v<br />
|-<br />
| 0x0E<br />
| texcoord1.u<br />
| rowspan="2" | Texture coordinates for texture 1<br />
|-<br />
| 0x0F<br />
| texcoord1.v<br />
|-<br />
| 0x10<br />
| texcoord0.w<br />
|<br />
<br />
|-<br />
| 0x12<br />
| view.x<br />
| rowspan="3" | View vector (for fragment lighting)<br />
|-<br />
| 0x13<br />
| view.y<br />
|-<br />
| 0x14<br />
| view.z<br />
<br />
|-<br />
| 0x16<br />
| texcoord2.u<br />
| rowspan="2" | Texture coordinates for texture 2<br />
|-<br />
| 0x17<br />
| texcoord2.v<br />
<br />
|-<br />
| 0x1F<br />
| Unused component<br />
| Should be set for unused components of the output register<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Early depth function<br />
|}<br />
<br />
This register configures the early depth test function.<br />
<br />
Early depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| >=<br />
|-<br />
| 1<br />
| ><br />
|-<br />
| 2<br />
| <=<br />
|-<br />
| 3<br />
| <<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether the early depth test is enabled.<br />
<br />
=== GPUREG_EARLYDEPTH_CLEAR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = clear)<br />
|}<br />
<br />
This register triggers clearing the early depth data.<br />
<br />
=== GPUREG_SH_OUTATTR_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Use texture coordinates (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register is used to configure the shader output attribute mode.<br />
<br />
=== GPUREG_SCISSORTEST_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Enabled (0 = disabled, 3 = enabled)<br />
|}<br />
<br />
This register is used to enable scissor testing.<br />
<br />
=== GPUREG_SCISSORTEST_POS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X1<br />
|-<br />
| 16-25<br />
| unsigned, Y1<br />
|}<br />
<br />
This register is used to configure the scissor test start position.<br />
<br />
=== GPUREG_SCISSORTEST_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X2<br />
|-<br />
| 16-25<br />
| unsigned, Y2<br />
|}<br />
<br />
This register is used to configure the scissor test end position.<br />
<br />
=== GPUREG_VIEWPORT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| signed, X<br />
|-<br />
| 16-25<br />
| signed, Y<br />
|}<br />
<br />
This register is used to configure the viewport position.<br />
<br />
=== GPUREG_EARLYDEPTH_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| unsigned, Clear value<br />
|}<br />
<br />
This register is used to configure the early depth clear value.<br />
<br />
=== GPUREG_DEPTHMAP_ENABLE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable depth range.<br />
<br />
=== GPUREG_RENDERBUF_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register is used to configure the output framebuffer dimensions.<br />
<br />
=== GPUREG_SH_OUTATTR_CLOCK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, 'position.z' present (0 = absent, 1 = present)<br />
|-<br />
| 1<br />
| unsigned, 'color' component present (0 = absent, 1 = present)<br />
|-<br />
| 8<br />
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)<br />
|-<br />
| 9<br />
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)<br />
|-<br />
| 10<br />
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)<br />
|-<br />
| 16<br />
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)<br />
|-<br />
| 24<br />
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)<br />
|}<br />
<br />
This register controls the clock supply to parts relating to certain attributes.<br />
<br />
== Texturing registers ==<br />
<br />
=== GPUREG_TEXUNIT_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| 0x0<br />
|-<br />
| 8-9<br />
| unsigned, Texture 3 coordinates<br />
|-<br />
| 10<br />
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| 0x1<br />
|-<br />
| 13<br />
| unsigned, Texture 2 coordinates<br />
|-<br />
| 16<br />
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)<br />
|-<br />
| 17-31<br />
| 0x0<br />
|}<br />
<br />
This register is used to enable texture units.<br />
<br />
Texture 3 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 0<br />
|-<br />
| 1<br />
| Texture 1<br />
|-<br />
| 2<br />
| Texture 2<br />
|}<br />
<br />
Texture 2 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 2<br />
|-<br />
| 1<br />
| Texture 1<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to set a texture unit's border color.<br />
<br />
=== GPUREG_TEXUNIT''i''_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Height<br />
|-<br />
| 16-26<br />
| unsigned, Width<br />
|}<br />
<br />
This register is used to set a texture unit's dimensions.<br />
<br />
=== GPUREG_TEXUNIT''i''_PARAM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, Magnification filter<br />
|-<br />
| 2<br />
| unsigned, Minification filter<br />
|-<br />
| 4-5<br />
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4<br />
|-<br />
| 8-10<br />
| unsigned, Wrap T<br />
|-<br />
| 12-14<br />
| unsigned, Wrap S<br />
|-<br />
| 16-17<br />
| 0x0<br />
|-<br />
| 20<br />
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)<br />
|-<br />
| 24<br />
| unsigned, Mipmap filter<br />
|-<br />
| 28-30<br />
| unsigned, Type (Texture 0 only)<br />
|}<br />
<br />
This register is used to set a texture unit's extra parameters.<br />
<br />
Filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|}<br />
<br />
Wrap values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to edge<br />
|-<br />
| 1<br />
| Clamp to border<br />
|-<br />
| 2<br />
| Repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|}<br />
<br />
Type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 2D<br />
|-<br />
| 1<br />
| Cube map<br />
|-<br />
| 2<br />
| Shadow 2D<br />
|-<br />
| 3<br />
| Projection<br />
|-<br />
| 4<br />
| Shadow cube<br />
|-<br />
| 5<br />
| Disabled<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_LOD ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.4.8, Bias<br />
|-<br />
| 16-19<br />
| unsigned, Max Level<br />
|-<br />
| 24-27<br />
| unsigned, Min Level<br />
|}<br />
<br />
This register is used to configure a texture unit's level of detail.<br />
<br />
=== GPUREG_TEXUNIT''i''_ADDR''i'' ===<br />
<br />
First ADDR register:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Texture physical address >> 3<br />
|}<br />
<br />
Subsequent ADDR registers:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-21<br />
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)<br />
|}<br />
<br />
This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.<br />
<br />
If the texture is a cube:<br />
<br />
{| class="wikitable" border="1"<br />
! Register<br />
! Description<br />
|-<br />
| ADDR1<br />
| Positive X<br />
|-<br />
| ADDR2<br />
| Negative X<br />
|-<br />
| ADDR3<br />
| Positive Y<br />
|-<br />
| ADDR4<br />
| Negative Y<br />
|-<br />
| ADDR5<br />
| Positive Z<br />
|-<br />
| ADDR6<br />
| Negative Z<br />
|}<br />
<br />
Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.<br />
<br />
=== GPUREG_TEXUNIT''i''_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Perspective (0 = perspective, 1 = not perspective)<br />
|-<br />
| 1-23<br />
| fixed0.0.24, Z bias (upper 23 bits)<br />
|}<br />
<br />
This register is used to set a texture unit's shadow texture properties.<br />
<br />
=== GPUREG_TEXUNIT''i''_TYPE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Format<br />
|}<br />
<br />
This register is used to set a texture unit's data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! GL Format<br />
! GL Data Type<br />
|-<br />
| 0x0<br />
| RGBA8888<br />
| GL_RGBA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x1<br />
| RGB888<br />
| GL_RGB<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x2<br />
| RGBA5551<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_5_5_5_1<br />
|-<br />
| 0x3<br />
| RGB565<br />
| GL_RGB<br />
| GL_UNSIGNED_SHORT_5_6_5<br />
|-<br />
| 0x4<br />
| RGBA4444<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_4_4_4_4<br />
|-<br />
| 0x5<br />
| IA8<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x6<br />
| HILO8<br />
| <br />
| <br />
|-<br />
| 0x7<br />
| I8<br />
| GL_LUMINANCE<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x8<br />
| A8<br />
| GL_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x9<br />
| IA44<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE_4_4_EXT<br />
|-<br />
| 0xA<br />
| I4<br />
| <br />
|<br />
|-<br />
| 0xB<br />
| A4<br />
| GL_ALPHA<br />
| GL_UNSIGNED_NIBBLE_EXT<br />
|-<br />
| 0xC<br />
| ETC1<br />
| GL_ETC1_RGB8_OES<br />
| <br />
|-<br />
| 0xD<br />
| ETC1A4<br />
|<br />
| <br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable lighting.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, U-direction clamp<br />
|-<br />
| 3-5<br />
| unsigned, V-direction clamp<br />
|-<br />
| 6-9<br />
| unsigned, RGB mapping function<br />
|-<br />
| 10-13<br />
| unsigned, Alpha mapping function<br />
|-<br />
| 14<br />
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)<br />
|-<br />
| 15<br />
| unsigned, Noise enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 16-17<br />
| unsigned, U-direction shift<br />
|-<br />
| 18-19<br />
| unsigned, V-direction shift<br />
|-<br />
| 20-27<br />
| float1.5.10, Texture bias (lower 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Clamp values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to zero<br />
|-<br />
| 1<br />
| Clamp to edge<br />
|-<br />
| 2<br />
| Symmetrical repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|-<br />
| 4<br />
| Pulse<br />
|}<br />
<br />
Mapping function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| U<br />
|-<br />
| 1<br />
| U²<br />
|-<br />
| 2<br />
| V<br />
|-<br />
| 3<br />
| V²<br />
|-<br />
| 4<br />
| (U + V) / 2<br />
|-<br />
| 5<br />
| (U² + V²) / 2<br />
|-<br />
| 6<br />
| sqrt(U² + V²)<br />
|-<br />
| 7<br />
| Minimum<br />
|-<br />
| 8<br />
| Maximum<br />
|-<br />
| 9<br />
| Rmax<br />
|}<br />
<br />
Shift values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Odd<br />
|-<br />
| 2<br />
| Even<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, U-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, U-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, V-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX3 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, U-direction noise frequency<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise frequency<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX4 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Minification filter<br />
|-<br />
| 3-10<br />
| 0x60<br />
|-<br />
| 11-18<br />
| unsigned, Texture width<br />
|-<br />
| 19-26<br />
| float1.5.10, Texture bias (upper 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Minification filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|-<br />
| 2<br />
| Nearest, Mipmap Nearest<br />
|-<br />
| 3<br />
| Linear, Mipmap Nearest<br />
|-<br />
| 4<br />
| Nearest, Mipmap Linear<br />
|-<br />
| 5<br />
| Linear, Mipmap Linear<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX5 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Texture offset<br />
|-<br />
| 8-31<br />
| 0xE0C080<br />
|}<br />
<br />
This register is used to set the procedural texture unit's offset.<br />
<br />
=== GPUREG_PROCTEX_LUT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Index<br />
|-<br />
| 8-11<br />
| unsigned, Reference table<br />
|}<br />
<br />
This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.<br />
<br />
Reference table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Noise table<br />
|-<br />
| 2<br />
| RGB mapping function table<br />
|-<br />
| 3<br />
| Alpha mapping function table<br />
|-<br />
| 4<br />
| Color table<br />
|-<br />
| 5<br />
| Color difference table<br />
|}<br />
<br />
=== GPUREG_PROCTEX_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.<br />
<br />
==== Noise Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== RGB Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Alpha Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Color Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
==== Color Difference Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| fixed1.0.7, Red difference between current and next color table elements<br />
|-<br />
| 8-15<br />
| fixed1.0.7, Green difference between current and next color table elements<br />
|-<br />
| 16-23<br />
| fixed1.0.7, Blue difference between current and next color table elements<br />
|-<br />
| 24-31<br />
| fixed1.0.7, Alpha difference between current and next color table elements<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_SOURCE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB source 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB source 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB source 2<br />
|-<br />
| 16-19<br />
| unsigned, Alpha source 0<br />
|-<br />
| 20-23<br />
| unsigned, Alpha source 1<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source 2<br />
|}<br />
<br />
This register configures a texture combiner's sources.<br />
<br />
Source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Primary color<br />
|-<br />
| 1<br />
| Fragment primary color<br />
|-<br />
| 2<br />
| Fragment secondary color<br />
|-<br />
| 3<br />
| Texture 0<br />
|-<br />
| 4<br />
| Texture 1<br />
|-<br />
| 5<br />
| Texture 2<br />
|-<br />
| 6<br />
| Texture 3<br />
|-<br />
| 13<br />
| Previous buffer<br />
|-<br />
| 14<br />
| Constant (from GPUREG_TEXENV''i''_COLOR)<br />
|-<br />
| 15<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_OPERAND ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB operand 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB operand 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB operand 2<br />
|-<br />
| 12-14<br />
| unsigned, Alpha operand 0<br />
|-<br />
| 16-18<br />
| unsigned, Alpha operand 1<br />
|-<br />
| 20-22<br />
| unsigned, Alpha operand 2<br />
|}<br />
<br />
This register configures a texture combiner's operands.<br />
<br />
RGB operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source color<br />
|-<br />
| 1<br />
| One minus source color<br />
|-<br />
| 2<br />
| Source alpha<br />
|-<br />
| 3<br />
| One minus source alpha<br />
|-<br />
| 4<br />
| Source red<br />
|-<br />
| 5<br />
| One minus source red<br />
|-<br />
| 8<br />
| Source green<br />
|-<br />
| 9<br />
| One minus source green<br />
|-<br />
| 12<br />
| Source blue<br />
|-<br />
| 13<br />
| One minus source blue<br />
|}<br />
<br />
Alpha operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source alpha<br />
|-<br />
| 1<br />
| One minus source alpha<br />
|-<br />
| 2<br />
| Source red<br />
|-<br />
| 3<br />
| One minus source red<br />
|-<br />
| 4<br />
| Source green<br />
|-<br />
| 5<br />
| One minus source green<br />
|-<br />
| 6<br />
| Source blue<br />
|-<br />
| 7<br />
| One minus source blue<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COMBINER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB combine<br />
|-<br />
| 16-19<br />
| unsigned, Alpha combine<br />
|}<br />
<br />
This register configures a texture combiner's combine mode.<br />
<br />
Combine values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Replace<br />
|-<br />
| 1<br />
| Modulate<br />
|-<br />
| 2<br />
| Add<br />
|-<br />
| 3<br />
| Add signed<br />
|-<br />
| 4<br />
| Interpolate<br />
|-<br />
| 5<br />
| Subtract<br />
|-<br />
| 6<br />
| Dot3 RGB<br />
|-<br />
| 7<br />
| Dot3 RGBA<br />
|-<br />
| 8<br />
| Multiply then add<br />
|-<br />
| 9<br />
| Add then multiply<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register configures a texture combiner's constant color.<br />
<br />
=== GPUREG_TEXENV''i''_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, RGB scale<br />
|-<br />
| 16-17<br />
| unsigned, Alpha scale<br />
|}<br />
<br />
This register configures a texture combiner's scale value.<br />
<br />
Scale values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|}<br />
<br />
=== GPUREG_TEXENV_UPDATE_BUFFER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fog mode<br />
|-<br />
| 3<br />
| unsigned, Shading density source<br />
|-<br />
| 8<br />
| unsigned, TexEnv 1 RGB buffer input<br />
|-<br />
| 9<br />
| unsigned, TexEnv 2 RGB buffer input<br />
|-<br />
| 10<br />
| unsigned, TexEnv 3 RGB buffer input<br />
|-<br />
| 11<br />
| unsigned, TexEnv 4 RGB buffer input<br />
|-<br />
| 12<br />
| unsigned, TexEnv 1 alpha buffer input<br />
|-<br />
| 13<br />
| unsigned, TexEnv 2 alpha buffer input<br />
|-<br />
| 14<br />
| unsigned, TexEnv 3 alpha buffer input<br />
|-<br />
| 15<br />
| unsigned, TexEnv 4 alpha buffer input<br />
|-<br />
| 16<br />
| unsigned, Z flip (0 = don't flip, 1 = flip)<br />
|-<br />
| 24-25<br />
| 0x0<br />
|}<br />
<br />
This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.<br />
<br />
Fog mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Disabled<br />
|-<br />
| 5<br />
| Fog<br />
|-<br />
| 7<br />
| Gas<br />
|}<br />
<br />
Shading density source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Plain density<br />
|-<br />
| 1<br />
| Depth density<br />
|}<br />
<br />
Buffer input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Previous buffer<br />
|-<br />
| 1<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_FOG_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
This register is used to configure the color of fog.<br />
<br />
=== GPUREG_GAS_ATTENUATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas density attenuation<br />
|}<br />
<br />
This register is used to configure the gas density attenuation.<br />
<br />
=== GPUREG_GAS_ACCMAX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas maximum density accumulation<br />
|}<br />
<br />
This register is used to configure the gas maximum density accumulation.<br />
<br />
=== GPUREG_FOG_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.<br />
<br />
=== GPUREG_FOG_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.<br />
<br />
==== Fog Look-Up Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Difference from next element <br />
|-<br />
| 13-23<br />
| fixed0.0.11, Value<br />
|}<br />
<br />
=== GPUREG_TEXENV_BUFFER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the texture combiner buffer color.<br />
<br />
== Framebuffer registers ==<br />
<br />
=== GPUREG_COLOR_OPERATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Fragment operation mode<br />
|-<br />
| 8<br />
| unsigned, Blend mode<br />
|-<br />
| 16-25<br />
| 0x0E4<br />
|}<br />
<br />
This register is used to configure the fragment operation mode and whether to use logic ops or blending.<br />
<br />
Fragment operation mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Default<br />
|-<br />
| 1<br />
| Gas<br />
|-<br />
| 3<br />
| Shadow<br />
|}<br />
<br />
Blend mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Logic op<br />
|-<br />
| 1<br />
| Blend<br />
|}<br />
<br />
=== GPUREG_BLEND_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, RGB equation<br />
|-<br />
| 8-10<br />
| unsigned, Alpha equation<br />
|-<br />
| 16-19<br />
| unsigned, RGB source function<br />
|-<br />
| 20-23<br />
| unsigned, RGB destination function<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source function<br />
|-<br />
| 28-31<br />
| unsigned, Alpha destination function<br />
|}<br />
<br />
This register is used to configure the blending function.<br />
<br />
Equation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Add<br />
|-<br />
| 1<br />
| Subtract<br />
|-<br />
| 2<br />
| Reverse subtract<br />
|-<br />
| 3<br />
| Minimum<br />
|-<br />
| 4<br />
| Maximum<br />
|}<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Zero<br />
|-<br />
| 1<br />
| One<br />
|-<br />
| 2<br />
| Source color<br />
|-<br />
| 3<br />
| One minus source color<br />
|-<br />
| 4<br />
| Destination color<br />
|-<br />
| 5<br />
| One minus destination color<br />
|-<br />
| 6<br />
| Source alpha<br />
|-<br />
| 7<br />
| One minus source alpha<br />
|-<br />
| 8<br />
| Destination alpha<br />
|-<br />
| 9<br />
| One minus destination alpha<br />
|-<br />
| 10<br />
| Constant color<br />
|-<br />
| 11<br />
| One minus constant color<br />
|-<br />
| 12<br />
| Constant alpha<br />
|-<br />
| 13<br />
| One minus constant alpha<br />
|-<br />
| 14<br />
| Source alpha saturate<br />
|}<br />
<br />
=== GPUREG_LOGIC_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Logic op<br />
|}<br />
<br />
This register is used to configure the logic op.<br />
<br />
Logic op values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clear<br />
|-<br />
| 1<br />
| AND<br />
|-<br />
| 2<br />
| Reverse AND<br />
|-<br />
| 3<br />
| Copy<br />
|-<br />
| 4<br />
| Set<br />
|-<br />
| 5<br />
| Inverted copy<br />
|-<br />
| 6<br />
| Noop<br />
|-<br />
| 7<br />
| Invert<br />
|-<br />
| 8<br />
| NAND<br />
|-<br />
| 9<br />
| OR<br />
|-<br />
| 10<br />
| NOR<br />
|-<br />
| 11<br />
| XOR<br />
|-<br />
| 12<br />
| Equivalent<br />
|-<br />
| 13<br />
| Inverted AND<br />
|-<br />
| 14<br />
| Reverse OR<br />
|-<br />
| 15<br />
| Inverted OR<br />
|}<br />
<br />
=== GPUREG_BLEND_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the blending color.<br />
<br />
=== GPUREG_FRAGOP_ALPHA_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Reference value<br />
|}<br />
<br />
This register is used to configure alpha testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Buffer mask<br />
|-<br />
| 16-23<br />
| signed, Reference value<br />
|-<br />
| 24-31<br />
| unsigned, Mask<br />
|}<br />
<br />
This register is used to configure stencil testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fail operation<br />
|-<br />
| 4-6<br />
| unsigned, Z-fail operation<br />
|-<br />
| 8-10<br />
| unsigned, Z-pass operation<br />
|}<br />
<br />
This register is used to configure stencil result operations.<br />
<br />
Operation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Keep<br />
|-<br />
| 1<br />
| Zero<br />
|-<br />
| 2<br />
| Replace<br />
|-<br />
| 3<br />
| Increment<br />
|-<br />
| 4<br />
| Decrement<br />
|-<br />
| 5<br />
| Invert<br />
|-<br />
| 6<br />
| Increment and wrap<br />
|-<br />
| 7<br />
| Decrement and wrap<br />
|}<br />
<br />
=== GPUREG_DEPTH_COLOR_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Depth function<br />
|-<br />
| 8<br />
| unsigned, Red write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 9<br />
| unsigned, Green write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 10<br />
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 11<br />
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to depth testing and framebuffer write masking.<br />
<br />
Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.<br />
<br />
Depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_FRAMEBUFFER_INVALIDATE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = invalidate)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.<br />
<br />
=== GPUREG_FRAMEBUFFER_FLUSH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = flush)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.<br />
<br />
=== GPUREG_COLORBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow read (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures read access from the color buffer.<br />
<br />
=== GPUREG_COLORBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow write (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures write access to the color buffer.<br />
<br />
=== GPUREG_DEPTHBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil read (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth read (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures read access from the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil write (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth write (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures write access to the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the depth buffer data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit depth<br />
|-<br />
| 2<br />
| 24-bit depth<br />
|-<br />
| 3<br />
| 24-bit depth + 8-bit stencil<br />
|}<br />
<br />
=== GPUREG_COLORBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Pixel size<br />
|-<br />
| 16-18<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.<br />
<br />
Pixel size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit color<br />
|-<br />
| 2<br />
| 32-bit color<br />
|}<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| RGBA8/Gas<br />
|-<br />
| 2<br />
| RGB5A1<br />
|-<br />
| 3<br />
| RGB565<br />
|-<br />
| 4<br />
| RGBA4<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register enables the early depth test.<br />
<br />
=== GPUREG_FRAMEBUFFER_BLOCK32 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Render block mode<br />
|}<br />
<br />
This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.<br />
<br />
Render block mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8x8 blocks<br />
|-<br />
| 1<br />
| 32x32 blocks<br />
|}<br />
<br />
=== GPUREG_DEPTHBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Depth buffer physical address >> 3<br />
|}<br />
<br />
This register configures the depth buffer physical address.<br />
<br />
=== GPUREG_COLORBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Color buffer physical address >> 3<br />
|}<br />
<br />
This register configures the color buffer physical address.<br />
<br />
=== GPUREG_FRAMEBUFFER_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register configures the framebuffer dimensions.<br />
<br />
=== GPUREG_GAS_LIGHT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Planar shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, Planar shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, Planar shading density attenuation<br />
|}<br />
<br />
This register configures gas light planar shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, View shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, View shading density attenuation<br />
|}<br />
<br />
This register configures gas light view shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading effect in line-of-sight direction<br />
|-<br />
| 8<br />
| Gas color LUT input<br />
|}<br />
<br />
This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.<br />
<br />
Color LUT input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Gas density<br />
|-<br />
| 1<br />
| Light factor<br />
|}<br />
<br />
=== GPUREG_GAS_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.<br />
<br />
=== GPUREG_GAS_LUT_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.<br />
<br />
==== Gas Look-Up Table ====<br />
<br />
16 elements:<br />
<br />
First 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| signed, Red<br />
|-<br />
| 8-15<br />
| signed, Green<br />
|-<br />
| 16-23<br />
| signed, Blue<br />
|}<br />
<br />
Last 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
=== GPUREG_GAS_DELTAZ_DEPTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| fixed0.16.8, Depth direction attenuation proportion<br />
|}<br />
<br />
This register is used to configure the gas depth direction attenuation proportion.<br />
<br />
=== GPUREG_FRAGOP_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Sum of penumbra scale and penumbra bias<br />
|-<br />
| 16-31<br />
| float1.5.10, Penumbra scale with reversed sign<br />
|}<br />
<br />
This register is used to configure shadow properties.<br />
<br />
== Fragment lighting registers ==<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR1 ===<br />
<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.<br />
<br />
=== GPUREG_LIGHT''i''_DIFFUSE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.<br />
<br />
=== GPUREG_LIGHT''i''_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.<br />
<br />
=== GPUREG_LIGHT''i''_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, X coordinate<br />
|-<br />
| 16-31<br />
| float1.5.10, Y coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Z coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, X coordinate (negated)<br />
|-<br />
| 16-28<br />
| fixed1.1.11, Y coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Z coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Light type (0 = positional light, 1 = directional light)<br />
|-<br />
| 1<br />
| unsigned, Two side diffuse (0 = one side, 1 = both sides)<br />
|-<br />
| 2<br />
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)<br />
|-<br />
| 3<br />
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures a light's properties.<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation bias<br />
|}<br />
<br />
These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation scale<br />
|}<br />
<br />
These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHTING_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.<br />
<br />
=== GPUREG_LIGHTING_NUM_LIGHTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of active lights - 1<br />
|}<br />
<br />
This register configures the number of active lights.<br />
<br />
=== GPUREG_LIGHTING_CONFIG0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)<br />
|-<br />
| 2-3<br />
| unsigned, Fresnel selector<br />
|-<br />
| 4-7<br />
| unsigned, Light environment configuration<br />
|-<br />
| 8-11<br />
| 0x4<br />
|-<br />
| 16<br />
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 17<br />
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 18<br />
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)<br />
|-<br />
| 19<br />
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)<br />
|-<br />
| 22-23<br />
| unsigned, Bump map texture unit<br />
|-<br />
| 24-25<br />
| unsigned, Shadow map texture unit<br />
|-<br />
| 27<br />
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)<br />
|-<br />
| 28-29<br />
| unsigned, Bump mode<br />
|-<br />
| 30<br />
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)<br />
|-<br />
| 31<br />
| 0x1<br />
|}<br />
<br />
This register configures the light environment.<br />
<br />
Fresnel selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Primary alpha<br />
|-<br />
| 2<br />
| Secondary alpha<br />
|-<br />
| 3<br />
| Primary and secondary alpha<br />
|}<br />
<br />
The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.<br />
<br />
Light environment configuration values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! Available LUTs<br />
|-<br />
| 0<br />
| Configuration 0<br />
| D0, RR, SP, DA<br />
|-<br />
| 1<br />
| Configuration 1<br />
| FR, RR, SP, DA<br />
|-<br />
| 2<br />
| Configuration 2<br />
| D0, D1, RR, DA<br />
|-<br />
| 3<br />
| Configuration 3<br />
| D0, D1, FR, DA<br />
|-<br />
| 4<br />
| Configuration 4<br />
| All except for FR<br />
|-<br />
| 5<br />
| Configuration 5<br />
| All except for D1<br />
|-<br />
| 6<br />
| Configuration 6<br />
| All except for RB and RG<br />
|-<br />
| 8<br />
| Configuration 7<br />
| All<br />
|}<br />
<br />
Bump mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Not used<br />
|-<br />
| 1<br />
| Use as bump map<br />
|-<br />
| 2<br />
| Use as tangent map<br />
|}<br />
<br />
=== GPUREG_LIGHTING_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 1<br />
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 2<br />
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 3<br />
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 4<br />
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 6<br />
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 7<br />
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 8<br />
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 10<br />
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 11<br />
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 12<br />
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 14<br />
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 15<br />
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 16<br />
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 18<br />
| 0x1<br />
|-<br />
| 19<br />
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 20-22<br />
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 21<br />
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 22<br />
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 24<br />
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 26<br />
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 27<br />
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 28<br />
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 29<br />
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 30<br />
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 31<br />
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is used to disable various aspects of the light environment.<br />
<br />
=== GPUREG_LIGHTING_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Starting index<br />
|-<br />
| 8-12<br />
| unsigned, Look-up table<br />
|}<br />
<br />
This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.<br />
<br />
Lookup table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| D0<br />
|-<br />
| 1<br />
| D1<br />
|-<br />
| 3<br />
| FR<br />
|-<br />
| 4<br />
| RB<br />
|-<br />
| 5<br />
| RG<br />
|-<br />
| 6<br />
| RR<br />
|-<br />
| 8-15<br />
| SP0-7<br />
|-<br />
| 16-23<br />
| DA0-7<br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.<br />
<br />
=== GPUREG_LIGHTING_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
Lighting LUT data is written here.<br />
<br />
A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.<br />
<br />
DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.<br />
<br />
Format of an entry:<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Entry value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_ABS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)<br />
|-<br />
| 21<br />
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register controls whether the absolute value of the input is taken before using a LUT.<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SELECT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Input selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Input selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Input selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Input selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Input selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Input selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Input selector for RR<br />
|}<br />
<br />
This register selects the input from LUTs.<br />
<br />
Input selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| N·H<br />
|-<br />
| 1<br />
| V·H<br />
|-<br />
| 2<br />
| N·V<br />
|-<br />
| 3<br />
| L·N<br />
|-<br />
| 4<br />
| -L·P (aka Spotlight aka SP)<br />
|-<br />
| 5<br />
| cos φ (aka CP)<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Scaler selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Scaler selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Scaler selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Scaler selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Scaler selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Scaler selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Scaler selector for RR<br />
|}<br />
<br />
This register controls the scaling that is applied to the output of a LUT.<br />
<br />
Scaler selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|-<br />
| 3<br />
| 8x<br />
|-<br />
| 6<br />
| 0.25x<br />
|-<br />
| 7<br />
| 0.5x<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, ID of the 1st enabled light<br />
|-<br />
| 4-6<br />
| unsigned, ID of the 2nd enabled light<br />
|-<br />
| 8-10<br />
| unsigned, ID of the 3rd enabled light<br />
|-<br />
| 12-14<br />
| unsigned, ID of the 4th enabled light<br />
|-<br />
| 16-18<br />
| unsigned, ID of the 5th enabled light<br />
|-<br />
| 20-22<br />
| unsigned, ID of the 6th enabled light<br />
|-<br />
| 24-26<br />
| unsigned, ID of the 7th enabled light<br />
|-<br />
| 28-30<br />
| unsigned, ID of the 8th enabled light<br />
|}<br />
<br />
This register sets the IDs of enabled light sources.<br />
<br />
== Geometry pipeline registers ==<br />
<br />
=== GPUREG_ATTRIBBUFFERS_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-28<br />
| unsigned, Vertex arrays base address<br />
|}<br />
<br />
This register sets the base address of all vertex arrays.<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 0 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 0 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 1 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 1 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 2 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 2 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 3 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 3 size<br />
|-<br />
| 16-17<br />
| unsigned, Vertex attribute 4 type<br />
|-<br />
| 18-19<br />
| unsigned, Vertex attribute 4 size<br />
|-<br />
| 20-21<br />
| unsigned, Vertex attribute 5 type<br />
|-<br />
| 22-23<br />
| unsigned, Vertex attribute 5 size<br />
|-<br />
| 24-25<br />
| unsigned, Vertex attribute 6 type<br />
|-<br />
| 26-27<br />
| unsigned, Vertex attribute 6 size<br />
|-<br />
| 28-29<br />
| unsigned, Vertex attribute 7 type<br />
|-<br />
| 30-31<br />
| unsigned, Vertex attribute 7 size<br />
|}<br />
<br />
This register configures the types and sizes of the first 8 vertex attributes.<br />
<br />
Vertex attribute type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Byte<br />
|-<br />
| 1<br />
| Unsigned byte<br />
|-<br />
| 2<br />
| Short<br />
|-<br />
| 3<br />
| Float<br />
|}<br />
<br />
Vertex attribute size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8 bits<br />
|-<br />
| 1<br />
| 16 bits<br />
|-<br />
| 2<br />
| 24 bits<br />
|-<br />
| 3<br />
| 32 bits<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 8 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 8 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 9 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 9 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 10 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 10 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 11 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 11 size<br />
|-<br />
| 16-27<br />
| unsigned, Fixed vertex attribute mask<br />
|-<br />
| 28-31<br />
| unsigned, Total vertex attribute count - 1<br />
|}<br />
<br />
This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.<br />
<br />
See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|}<br />
<br />
This register configures the offset of a vertex array from the base vertex arrays address.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 1<br />
|-<br />
| 4-7<br />
| unsigned, Component 2<br />
|-<br />
| 8-11<br />
| unsigned, Component 3<br />
|-<br />
| 12-15<br />
| unsigned, Component 4<br />
|-<br />
| 16-19<br />
| unsigned, Component 5<br />
|-<br />
| 20-23<br />
| unsigned, Component 6<br />
|-<br />
| 24-27<br />
| unsigned, Component 7<br />
|-<br />
| 28-31<br />
| unsigned, Component 8<br />
|}<br />
<br />
This register configures the first 8 component types of a vertex array.<br />
<br />
Component values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Vertex attribute 0<br />
|-<br />
| 1<br />
| Vertex attribute 1<br />
|-<br />
| 2<br />
| Vertex attribute 2<br />
|-<br />
| 3<br />
| Vertex attribute 3<br />
|-<br />
| 4<br />
| Vertex attribute 4<br />
|-<br />
| 5<br />
| Vertex attribute 5<br />
|-<br />
| 6<br />
| Vertex attribute 6<br />
|-<br />
| 7<br />
| Vertex attribute 7<br />
|-<br />
| 8<br />
| Vertex attribute 8<br />
|-<br />
| 9<br />
| Vertex attribute 9<br />
|-<br />
| 10<br />
| Vertex attribute 10<br />
|-<br />
| 11<br />
| Vertex attribute 11<br />
|-<br />
| 12<br />
| 4-byte padding<br />
|-<br />
| 13<br />
| 8-byte padding<br />
|-<br />
| 14<br />
| 12-byte padding<br />
|-<br />
| 15<br />
| 16-byte padding<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 9<br />
|-<br />
| 4-7<br />
| unsigned, Component 10<br />
|-<br />
| 8-11<br />
| unsigned, Component 11<br />
|-<br />
| 12-15<br />
| unsigned, Component 12<br />
|-<br />
| 16-23<br />
| unsigned, Bytes per vertex<br />
|-<br />
| 28-31<br />
| unsigned, Total number of components<br />
|}<br />
<br />
This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.<br />
<br />
See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.<br />
<br />
=== GPUREG_INDEXBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|-<br />
| 31<br />
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)<br />
|}<br />
<br />
This register configures the index array used when drawing elements.<br />
<br />
=== GPUREG_NUMVERTICES ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Number of vertices to render<br />
|}<br />
<br />
This register sets the number of vertices to render.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|-<br />
| 9<br />
| 0x0<br />
|-<br />
| 31<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_VERTEX_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Starting vertex offset<br />
|}<br />
<br />
This register sets the offset of the first vertex in an array to render.<br />
<br />
=== GPUREG_POST_VERTEX_CACHE_NUM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)<br />
|}<br />
<br />
This register configures the post-vertex cache.<br />
<br />
=== GPUREG_DRAWARRAYS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw arrays)<br />
|}<br />
<br />
This register triggers drawing vertex arrays.<br />
<br />
=== GPUREG_DRAWELEMENTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw elements)<br />
|}<br />
<br />
This register triggers drawing vertex array elements.<br />
<br />
=== GPUREG_VTX_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)<br />
|}<br />
<br />
This register triggers clearing the post-vertex cache.<br />
<br />
=== GPUREG_FIXEDATTRIB_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)<br />
|}<br />
<br />
This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.<br />
<br />
=== GPUREG_FIXEDATTRIB_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| colspan="2" | '''DATA0:'''<br />
|-<br />
| 0-7<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)<br />
|-<br />
| 8-31<br />
| float1.7.16, Vertex attribute element 4 (W)<br />
|-<br />
| colspan="2" | '''DATA1:'''<br />
|-<br />
| 0-15<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)<br />
|-<br />
| 16-31<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)<br />
|-<br />
| colspan="2" | '''DATA2:'''<br />
|-<br />
| 0-23<br />
| float1.7.16, Vertex attribute element 1 (X)<br />
|-<br />
| 24-31<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)<br />
|}<br />
<br />
Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.<br />
<br />
=== GPUREG_CMDBUF_SIZE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the size of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_SIZE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the size of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the physical address of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the physical address of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)<br />
|}<br />
<br />
This register triggers a jump to the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)<br />
|}<br />
<br />
This register triggers a jump to the second command buffer.<br />
<br />
=== GPUREG_VSH_NUM_ATTR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader input attributes - 1<br />
|}<br />
<br />
This register sets the number of vertex shader input attributes.<br />
<br />
=== GPUREG_VSH_COM_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.<br />
<br />
=== GPUREG_START_DRAW_FUNC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Mode (0 = drawing, 1 = configuration)<br />
|-<br />
| 1-7<br />
| 0x0<br />
|}<br />
<br />
This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_GSH_MISC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)<br />
|}<br />
<br />
This register configures miscellaneous geometry shader properties.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_GSH_MISC1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)<br />
|}<br />
<br />
This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.<br />
<br />
=== GPUREG_PRIMITIVE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|-<br />
| 8-9<br />
| unsigned, Primitive mode<br />
|}<br />
<br />
This register configures primitive drawing.<br />
<br />
Primitive mode value:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Triangles<br />
|-<br />
| 1<br />
| Triangle strip<br />
|-<br />
| 2<br />
| Triangle fan<br />
|-<br />
| 3<br />
| Geometry primitive<br />
|}<br />
<br />
=== GPUREG_RESTART_PRIMITIVE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = reset primitive)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
This register triggers resetting primitive drawing.<br />
<br />
== Shader registers ==<br />
<br />
=== GPUREG_''SH''_BOOLUNIFORM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Boolean register b0 value (0 = false, 1 = true)<br />
|-<br />
| 1<br />
| unsigned, Boolean register b1 value (0 = false, 1 = true)<br />
|-<br />
| 2<br />
| unsigned, Boolean register b2 value (0 = false, 1 = true)<br />
|-<br />
| 3<br />
| unsigned, Boolean register b3 value (0 = false, 1 = true)<br />
|-<br />
| 4<br />
| unsigned, Boolean register b4 value (0 = false, 1 = true)<br />
|-<br />
| 5<br />
| unsigned, Boolean register b5 value (0 = false, 1 = true)<br />
|-<br />
| 6<br />
| unsigned, Boolean register b6 value (0 = false, 1 = true)<br />
|-<br />
| 7<br />
| unsigned, Boolean register b7 value (0 = false, 1 = true)<br />
|-<br />
| 8<br />
| unsigned, Boolean register b8 value (0 = false, 1 = true)<br />
|-<br />
| 9<br />
| unsigned, Boolean register b9 value (0 = false, 1 = true)<br />
|-<br />
| 10<br />
| unsigned, Boolean register b10 value (0 = false, 1 = true)<br />
|-<br />
| 11<br />
| unsigned, Boolean register b11 value (0 = false, 1 = true)<br />
|-<br />
| 12<br />
| unsigned, Boolean register b12 value (0 = false, 1 = true)<br />
|-<br />
| 13<br />
| unsigned, Boolean register b13 value (0 = false, 1 = true)<br />
|-<br />
| 14<br />
| unsigned, Boolean register b14 value (0 = false, 1 = true)<br />
|-<br />
| 15<br />
| unsigned, Boolean register b15 value (0 = false, 1 = true)<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register is used to set a shader unit's boolean registers.<br />
<br />
=== GPUREG_''SH''_INTUNIFORM_I''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Integer register i''i'' X value<br />
|-<br />
| 8-15<br />
| unsigned, Integer register i''i'' Y value<br />
|-<br />
| 16-23<br />
| unsigned, Integer register i''i'' Z value<br />
|-<br />
| 24-31<br />
| unsigned, Integer register i''i'' W value<br />
|}<br />
<br />
These registers are used to set a shader unit's integer registers.<br />
<br />
=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Input vertex attributes - 1<br />
|-<br />
| 8-15<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)<br />
|-<br />
| 16-23<br />
| 0x0<br />
|-<br />
| 24-31<br />
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)<br />
|}<br />
<br />
This register is used to configure a shader unit's input buffer.<br />
<br />
=== GPUREG_''SH''_ENTRYPOINT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Code entry point offset, in 32-bit words<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register sets a shader unit's code entry point.<br />
<br />
For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.<br />
<br />
For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them. <br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 0 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 1 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 2 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 3 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 4 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 5 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 6 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 7 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.<br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 8 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 9 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 10 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 11 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 12 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 13 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 14 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 15 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.<br />
<br />
=== GPUREG_''SH''_OUTMAP_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4<br />
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 5<br />
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 6<br />
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 7<br />
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 8<br />
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 9<br />
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 10<br />
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 11<br />
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 12<br />
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 13<br />
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 14<br />
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 15<br />
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 16-31<br />
| 0x0<br />
|}<br />
<br />
This register toggles a shader unit's output registers.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_END ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Signal transfer end (0 = idle, non-zero = signal)<br />
|}<br />
<br />
This register's value should be set to 1 in order to finalize the transfer of shader code.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)<br />
|-<br />
| 31<br />
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)<br />
|}<br />
<br />
This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| Floating-point register component data<br />
|}<br />
<br />
This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].<br />
<br />
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:<br />
** first word : ZZWWWWWW<br />
** second word : YYYYZZZZ<br />
** third word : XXXXXXYY<br />
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader code offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader instruction data<br />
|}<br />
<br />
This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.<br />
<br />
=== GPUREG_''SH''_OPDESCS_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader operand descriptor offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_OPDESCS_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader operand descriptor data<br />
|}<br />
<br />
This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=GPU/Internal_Registers&diff=19809
GPU/Internal Registers
2017-04-08T10:49:03Z
<p>Plutooo: testing</p>
<hr />
<div>[[Category:GPU]]<br />
<br />
== Overview ==<br />
<br />
GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.<br />
<br />
Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).<br />
<br />
In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.<br />
<br />
For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).<br />
<br />
Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.<br />
<br />
The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.<br />
<br />
=== Command Header ===<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0-15<br />
| Command ID<br />
|-<br />
| 16-19<br />
| Parameter mask<br />
|-<br />
| 20-30<br />
| Number of extra parameters (may be zero)<br />
|-<br />
| 31<br />
| Consecutive writing mode<br />
|}<br />
<br />
=== Parameter masking ===<br />
<br />
Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.<br />
<br />
=== Types ===<br />
<br />
There are three main types of registers :<br />
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])<br />
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])<br />
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])<br />
<br />
=== Aliases ===<br />
<br />
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]<br />
<br />
=== Data Types ===<br />
<br />
{| class="wikitable" border="1"<br />
! Name<br />
! Description<br />
|-<br />
| signed<br />
| Signed integer<br />
|-<br />
| unsigned<br />
| Unsigned integer<br />
|-<br />
| floatX.Y.Z<br />
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits<br />
|-<br />
| fixedX.Y.Z<br />
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits<br />
|}<br />
<br />
== Register list ==<br />
<br />
=== Miscellaneous registers (0x000-0x03F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0000<br />
| [[#GPUREG_0000|GPUREG_0000]]<br />
| <br />
|<br />
|-<br />
| 0001<br />
| [[#GPUREG_0001|GPUREG_0001]]<br />
| <br />
|<br />
|-<br />
| 0002<br />
| [[#GPUREG_0002|GPUREG_0002]]<br />
| <br />
|<br />
|-<br />
| 0003<br />
| [[#GPUREG_0003|GPUREG_0003]]<br />
| <br />
|<br />
|-<br />
| 0004<br />
| [[#GPUREG_0004|GPUREG_0004]]<br />
| <br />
|<br />
|-<br />
| 0005<br />
| [[#GPUREG_0005|GPUREG_0005]]<br />
| <br />
|<br />
|-<br />
| 0006<br />
| [[#GPUREG_0006|GPUREG_0006]]<br />
| <br />
|<br />
|-<br />
| 0007<br />
| [[#GPUREG_0007|GPUREG_0007]]<br />
| <br />
|<br />
|-<br />
| 0008<br />
| [[#GPUREG_0008|GPUREG_0008]]<br />
| <br />
|<br />
|-<br />
| 0009<br />
| [[#GPUREG_0009|GPUREG_0009]]<br />
| <br />
|<br />
|-<br />
| 000A<br />
| [[#GPUREG_000A|GPUREG_000A]]<br />
| <br />
|<br />
|-<br />
| 000B<br />
| [[#GPUREG_000B|GPUREG_000B]]<br />
| <br />
|<br />
|-<br />
| 000C<br />
| [[#GPUREG_000C|GPUREG_000C]]<br />
| <br />
|<br />
|-<br />
| 000D<br />
| [[#GPUREG_000D|GPUREG_000D]]<br />
| <br />
|<br />
|-<br />
| 000E<br />
| [[#GPUREG_000E|GPUREG_000E]]<br />
| <br />
|<br />
|-<br />
| 000F<br />
| [[#GPUREG_000F|GPUREG_000F]]<br />
| <br />
|<br />
|-<br />
| 0010<br />
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]<br />
| <br />
|PICA_REG_INTERRUPT<br />
|-<br />
| 0011<br />
| [[#GPUREG_0011|GPUREG_0011]]<br />
| <br />
|<br />
|-<br />
| 0012<br />
| [[#GPUREG_0012|GPUREG_0012]]<br />
| <br />
|<br />
|-<br />
| 0013<br />
| [[#GPUREG_0013|GPUREG_0013]]<br />
| <br />
|<br />
|-<br />
| 0014<br />
| [[#GPUREG_0014|GPUREG_0014]]<br />
| <br />
|<br />
|-<br />
| 0015<br />
| [[#GPUREG_0015|GPUREG_0015]]<br />
| <br />
|<br />
|-<br />
| 0016<br />
| [[#GPUREG_0016|GPUREG_0016]]<br />
| <br />
|<br />
|-<br />
| 0017<br />
| [[#GPUREG_0017|GPUREG_0017]]<br />
| <br />
|<br />
|-<br />
| 0018<br />
| [[#GPUREG_0018|GPUREG_0018]]<br />
| <br />
|<br />
|-<br />
| 0019<br />
| [[#GPUREG_0019|GPUREG_0019]]<br />
| <br />
|<br />
|-<br />
| 001A<br />
| [[#GPUREG_001A|GPUREG_001A]]<br />
| <br />
|<br />
|-<br />
| 001B<br />
| [[#GPUREG_001B|GPUREG_001B]]<br />
| <br />
|<br />
|-<br />
| 001C<br />
| [[#GPUREG_001C|GPUREG_001C]]<br />
| <br />
|<br />
|-<br />
| 001D<br />
| [[#GPUREG_001D|GPUREG_001D]]<br />
| <br />
|<br />
|-<br />
| 001E<br />
| [[#GPUREG_001E|GPUREG_001E]]<br />
| <br />
|<br />
|-<br />
| 001F<br />
| [[#GPUREG_001F|GPUREG_001F]]<br />
| <br />
|<br />
|-<br />
| 0020<br />
| [[#GPUREG_0020|GPUREG_0020]]<br />
| <br />
|<br />
|-<br />
| 0021<br />
| [[#GPUREG_0021|GPUREG_0021]]<br />
| <br />
|<br />
|-<br />
| 0022<br />
| [[#GPUREG_0022|GPUREG_0022]]<br />
| <br />
|<br />
|-<br />
| 0023<br />
| [[#GPUREG_0023|GPUREG_0023]]<br />
| <br />
|<br />
|-<br />
| 0024<br />
| [[#GPUREG_0024|GPUREG_0024]]<br />
| <br />
|<br />
|-<br />
| 0025<br />
| [[#GPUREG_0025|GPUREG_0025]]<br />
| <br />
|<br />
|-<br />
| 0026<br />
| [[#GPUREG_0026|GPUREG_0026]]<br />
| <br />
|<br />
|-<br />
| 0027<br />
| [[#GPUREG_0027|GPUREG_0027]]<br />
| <br />
|<br />
|-<br />
| 0028<br />
| [[#GPUREG_0028|GPUREG_0028]]<br />
| <br />
|<br />
|-<br />
| 0029<br />
| [[#GPUREG_0029|GPUREG_0029]]<br />
| <br />
|<br />
|-<br />
| 002A<br />
| [[#GPUREG_002A|GPUREG_002A]]<br />
| <br />
|<br />
|-<br />
| 002B<br />
| [[#GPUREG_002B|GPUREG_002B]]<br />
| <br />
|<br />
|-<br />
| 002C<br />
| [[#GPUREG_002C|GPUREG_002C]]<br />
| <br />
|<br />
|-<br />
| 002D<br />
| [[#GPUREG_002D|GPUREG_002D]]<br />
| <br />
|<br />
|-<br />
| 002E<br />
| [[#GPUREG_002E|GPUREG_002E]]<br />
| <br />
|<br />
|-<br />
| 002F<br />
| [[#GPUREG_002F|GPUREG_002F]]<br />
| <br />
|<br />
|-<br />
| 0030<br />
| [[#GPUREG_0030|GPUREG_0030]]<br />
| <br />
|<br />
|-<br />
| 0031<br />
| [[#GPUREG_0031|GPUREG_0031]]<br />
| <br />
|<br />
|-<br />
| 0032<br />
| [[#GPUREG_0032|GPUREG_0032]]<br />
| <br />
|<br />
|-<br />
| 0033<br />
| [[#GPUREG_0033|GPUREG_0033]]<br />
| <br />
|<br />
|-<br />
| 0034<br />
| [[#GPUREG_0034|GPUREG_0034]]<br />
| <br />
|<br />
|-<br />
| 0035<br />
| [[#GPUREG_0035|GPUREG_0035]]<br />
| <br />
|<br />
|-<br />
| 0036<br />
| [[#GPUREG_0036|GPUREG_0036]]<br />
| <br />
|<br />
|-<br />
| 0037<br />
| [[#GPUREG_0037|GPUREG_0037]]<br />
| <br />
|<br />
|-<br />
| 0038<br />
| [[#GPUREG_0038|GPUREG_0038]]<br />
| <br />
|<br />
|-<br />
| 0039<br />
| [[#GPUREG_0039|GPUREG_0039]]<br />
| <br />
|<br />
|-<br />
| 003A<br />
| [[#GPUREG_003A|GPUREG_003A]]<br />
| <br />
|<br />
|-<br />
| 003B<br />
| [[#GPUREG_003B|GPUREG_003B]]<br />
| <br />
|<br />
|-<br />
| 003C<br />
| [[#GPUREG_003C|GPUREG_003C]]<br />
| <br />
|<br />
|-<br />
| 003D<br />
| [[#GPUREG_003D|GPUREG_003D]]<br />
| <br />
|<br />
|-<br />
| 003E<br />
| [[#GPUREG_003E|GPUREG_003E]]<br />
| <br />
|<br />
|-<br />
| 003F<br />
| [[#GPUREG_003F|GPUREG_003F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Rasterizer registers (0x040-0x07F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0040<br />
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]<br />
| <br />
|PICA_REG_CULL_FACE<br />
|-<br />
| 0041<br />
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH1<br />
|-<br />
| 0042<br />
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH2<br />
|-<br />
| 0043<br />
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT1<br />
|-<br />
| 0044<br />
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT2<br />
|-<br />
| 0045<br />
| [[#GPUREG_0045|GPUREG_0045]]<br />
| <br />
|<br />
|-<br />
| 0046<br />
| [[#GPUREG_0046|GPUREG_0046]]<br />
| <br />
|<br />
|-<br />
| 0047<br />
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP<br />
|-<br />
| 0048<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]<br />
|? <br />
|PICA_REG_FRAGOP_CLIP_DATA1<br />
|-<br />
| 0049<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA2<br />
|-<br />
| 004A<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA3<br />
|-<br />
| 004B<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA4<br />
|-<br />
| 004C<br />
| [[#GPUREG_004C|GPUREG_004C]]<br />
| <br />
|<br />
|-<br />
| 004D<br />
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA1<br />
|-<br />
| 004E<br />
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA2<br />
|-<br />
| 004F<br />
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]<br />
| <br />
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0<br />
|-<br />
| 0050<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0<br />
|-<br />
| 0051<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1<br />
|-<br />
| 0052<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2<br />
|-<br />
| 0053<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3<br />
|-<br />
| 0054<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4<br />
|-<br />
| 0055<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5<br />
|-<br />
| 0056<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6<br />
|-<br />
| 0057<br />
| [[#GPUREG_0057|GPUREG_0057]]<br />
| <br />
|<br />
|-<br />
| 0058<br />
| [[#GPUREG_0058|GPUREG_0058]]<br />
| <br />
|<br />
|-<br />
| 0059<br />
| [[#GPUREG_0059|GPUREG_0059]]<br />
| <br />
|<br />
|-<br />
| 005A<br />
| [[#GPUREG_005A|GPUREG_005A]]<br />
| <br />
|<br />
|-<br />
| 005B<br />
| [[#GPUREG_005B|GPUREG_005B]]<br />
| <br />
|<br />
|-<br />
| 005C<br />
| [[#GPUREG_005C|GPUREG_005C]]<br />
| <br />
|<br />
|-<br />
| 005D<br />
| [[#GPUREG_005D|GPUREG_005D]]<br />
| <br />
|<br />
|-<br />
| 005E<br />
| [[#GPUREG_005E|GPUREG_005E]]<br />
| <br />
|<br />
|-<br />
| 005F<br />
| [[#GPUREG_005F|GPUREG_005F]]<br />
| <br />
|<br />
|-<br />
| 0060<br />
| [[#GPUREG_0060|GPUREG_0060]]<br />
| <br />
|<br />
|-<br />
| 0061<br />
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_FUNC<br />
|-<br />
| 0062<br />
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST1<br />
|-<br />
| 0063<br />
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]<br />
| <br />
|PICA_REG_EARLY_DEPTH_CLEAR<br />
|-<br />
| 0064<br />
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE<br />
|-<br />
| 0065<br />
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]<br />
| <br />
|PICA_REG_SCISSOR<br />
|-<br />
| 0066<br />
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]<br />
| <br />
|PICA_REG_SCISSOR_XY<br />
|-<br />
| 0067<br />
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]<br />
| <br />
|PICA_REG_SCISSOR_SIZE<br />
|-<br />
| 0068<br />
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]<br />
|<br />
|PICA_REG_VIEWPORT_XY<br />
|-<br />
| 0069<br />
| [[#GPUREG_0069|GPUREG_0069]]<br />
| <br />
|<br />
|-<br />
| 006A<br />
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]<br />
|<br />
|PICA_REG_EARLY_DEPTH_DATA<br />
|-<br />
| 006B<br />
| [[#GPUREG_006B|GPUREG_006B]]<br />
| <br />
|<br />
|-<br />
| 006C<br />
| [[#GPUREG_006C|GPUREG_006C]]<br />
| <br />
|<br />
|-<br />
| 006D<br />
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]<br />
|?<br />
|PICA_REG_FRAGOP_WSCALE<br />
|-<br />
| 006E<br />
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]<br />
|?<br />
|PICA_REG_RENDER_BUF_RESOLUTION1<br />
|-<br />
| 006F<br />
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK<br />
|-<br />
| 0070<br />
| [[#GPUREG_0070|GPUREG_0070]]<br />
| <br />
|<br />
|-<br />
| 0071<br />
| [[#GPUREG_0071|GPUREG_0071]]<br />
| <br />
|<br />
|-<br />
| 0072<br />
| [[#GPUREG_0072|GPUREG_0072]]<br />
| <br />
|<br />
|-<br />
| 0073<br />
| [[#GPUREG_0073|GPUREG_0073]]<br />
| <br />
|<br />
|-<br />
| 0074<br />
| [[#GPUREG_0074|GPUREG_0074]]<br />
| <br />
|<br />
|-<br />
| 0075<br />
| [[#GPUREG_0075|GPUREG_0075]]<br />
| <br />
|<br />
|-<br />
| 0076<br />
| [[#GPUREG_0076|GPUREG_0076]]<br />
| <br />
|<br />
|-<br />
| 0077<br />
| [[#GPUREG_0077|GPUREG_0077]]<br />
| <br />
|<br />
|-<br />
| 0078<br />
| [[#GPUREG_0078|GPUREG_0078]]<br />
| <br />
|<br />
|-<br />
| 0079<br />
| [[#GPUREG_0079|GPUREG_0079]]<br />
| <br />
|<br />
|-<br />
| 007A<br />
| [[#GPUREG_007A|GPUREG_007A]]<br />
| <br />
|<br />
|-<br />
| 007B<br />
| [[#GPUREG_007B|GPUREG_007B]]<br />
| <br />
|<br />
|-<br />
| 007C<br />
| [[#GPUREG_007C|GPUREG_007C]]<br />
| <br />
|<br />
|-<br />
| 007D<br />
| [[#GPUREG_007D|GPUREG_007D]]<br />
| <br />
|<br />
|-<br />
| 007E<br />
| [[#GPUREG_007E|GPUREG_007E]]<br />
| <br />
|<br />
|-<br />
| 007F<br />
| [[#GPUREG_007F|GPUREG_007F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Texturing registers (0x080-0x0FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0080<br />
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]<br />
|<br />
|PICA_REG_TEXTURE_FUNC<br />
|-<br />
| 0081<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE0_BORDER_COLOR<br />
|-<br />
| 0082<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]<br />
|<br />
|PICA_REG_TEXTURE0_SIZE<br />
|-<br />
| 0083<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE0_WRAP_FILTER<br />
|-<br />
| 0084<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE0_LOD<br />
|-<br />
| 0085<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR1<br />
|-<br />
| 0086<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR2<br />
|-<br />
| 0087<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR3<br />
|-<br />
| 0088<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR4<br />
|-<br />
| 0089<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR5<br />
|-<br />
| 008A<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR6<br />
|-<br />
| 008B<br />
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]<br />
|?<br />
|PICA_REG_TEXTURE0_SHADOW<br />
|-<br />
| 008C<br />
| [[#GPUREG_008C|GPUREG_008C]]<br />
|<br />
|<br />
|-<br />
| 008D<br />
| [[#GPUREG_008D|GPUREG_008D]]<br />
|<br />
|<br />
|-<br />
| 008E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]<br />
|?<br />
|PICA_REG_TEXTURE0_FORMAT<br />
|-<br />
| 008F<br />
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN0<br />
|-<br />
| 0090<br />
| [[#GPUREG_0090|GPUREG_0090]]<br />
| <br />
|<br />
|-<br />
| 0091<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE1_BORDER_COLOR<br />
|-<br />
| 0092<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]<br />
| <br />
|PICA_REG_TEXTURE1_SIZE<br />
|-<br />
| 0093<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE1_WRAP_FILTER<br />
|-<br />
| 0094<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE1_LOD<br />
|-<br />
| 0095<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]<br />
| <br />
|PICA_REG_TEXTURE1_ADDR<br />
|-<br />
| 0096<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE1_FORMAT<br />
|-<br />
| 0097<br />
| [[#GPUREG_0097|GPUREG_0097]]<br />
| <br />
|<br />
|-<br />
| 0098<br />
| [[#GPUREG_0098|GPUREG_0098]]<br />
| <br />
|<br />
|-<br />
| 0099<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE2_BORDER_COLOR<br />
|-<br />
| 009A<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]<br />
| <br />
|PICA_REG_TEXTURE2_SIZE<br />
|-<br />
| 009B<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE2_WRAP_FILTER<br />
|-<br />
| 009C<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE2_LOD<br />
|-<br />
| 009D<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]<br />
|<br />
|PICA_REG_TEXTURE2_ADDR<br />
|-<br />
| 009E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE2_FORMAT<br />
|-<br />
| 009F<br />
| [[#GPUREG_009F|GPUREG_009F]]<br />
| <br />
|<br />
|-<br />
| 00A0<br />
| [[#GPUREG_00A0|GPUREG_00A0]]<br />
| <br />
|<br />
|-<br />
| 00A1<br />
| [[#GPUREG_00A1|GPUREG_00A1]]<br />
| <br />
|<br />
|-<br />
| 00A2<br />
| [[#GPUREG_00A2|GPUREG_00A2]]<br />
| <br />
|<br />
|-<br />
| 00A3<br />
| [[#GPUREG_00A3|GPUREG_00A3]]<br />
| <br />
|<br />
|-<br />
| 00A4<br />
| [[#GPUREG_00A4|GPUREG_00A4]]<br />
| <br />
|<br />
|-<br />
| 00A5<br />
| [[#GPUREG_00A5|GPUREG_00A5]]<br />
| <br />
|<br />
|-<br />
| 00A6<br />
| [[#GPUREG_00A6|GPUREG_00A6]]<br />
| <br />
|<br />
|-<br />
| 00A7<br />
| [[#GPUREG_00A7|GPUREG_00A7]]<br />
| <br />
|<br />
|-<br />
| 00A8<br />
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX0<br />
|-<br />
| 00A9<br />
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX1<br />
|-<br />
| 00AA<br />
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]<br />
|? <br />
|PICA_REG_TEXTURE3_PROCTEX2<br />
|-<br />
| 00AB<br />
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX3<br />
|-<br />
| 00AC<br />
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX4<br />
|-<br />
| 00AD<br />
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX5<br />
|-<br />
| 00AE<br />
| [[#GPUREG_00AE|GPUREG_00AE]]<br />
| <br />
|<br />
|-<br />
| 00AF<br />
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]<br />
|?<br />
|PICA_REG_PROCTEX_LUT<br />
|-<br />
| 00B0<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA0<br />
|-<br />
| 00B1<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA1<br />
|-<br />
| 00B2<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA2<br />
|-<br />
| 00B3<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA3<br />
|-<br />
| 00B4<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA4<br />
|-<br />
| 00B5<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA5<br />
|-<br />
| 00B6<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA6<br />
|-<br />
| 00B7<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA7<br />
|-<br />
| 00B8<br />
| [[#GPUREG_00B8|GPUREG_00B8]]<br />
| <br />
|<br />
|-<br />
| 00B9<br />
| [[#GPUREG_00B9|GPUREG_00B9]]<br />
| <br />
|<br />
|-<br />
| 00BA<br />
| [[#GPUREG_00BA|GPUREG_00BA]]<br />
| <br />
|<br />
|-<br />
| 00BB<br />
| [[#GPUREG_00BB|GPUREG_00BB]]<br />
| <br />
|<br />
|-<br />
| 00BC<br />
| [[#GPUREG_00BC|GPUREG_00BC]]<br />
| <br />
|<br />
|-<br />
| 00BD<br />
| [[#GPUREG_00BD|GPUREG_00BD]]<br />
| <br />
|<br />
|-<br />
| 00BE<br />
| [[#GPUREG_00BE|GPUREG_00BE]]<br />
| <br />
|<br />
|-<br />
| 00BF<br />
| [[#GPUREG_00BF|GPUREG_00BF]]<br />
| <br />
|<br />
|-<br />
| 00C0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_0<br />
|-<br />
| 00C1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_0_OPERAND<br />
|-<br />
| 00C2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COMBINE<br />
|-<br />
| 00C3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COLOR<br />
|-<br />
| 00C4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_0_SCALE<br />
|-<br />
| 00C5<br />
| [[#GPUREG_00C5|GPUREG_00C5]]<br />
| <br />
|<br />
|-<br />
| 00C6<br />
| [[#GPUREG_00C6|GPUREG_00C6]]<br />
| <br />
|<br />
|-<br />
| 00C7<br />
| [[#GPUREG_00C7|GPUREG_00C7]]<br />
| <br />
|<br />
|-<br />
| 00C8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_1<br />
|-<br />
| 00C9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_1_OPERAND<br />
|-<br />
| 00CA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COMBINE<br />
|-<br />
| 00CB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COLOR<br />
|-<br />
| 00CC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_1_SCALE<br />
|-<br />
| 00CD<br />
| [[#GPUREG_00CD|GPUREG_00CD]]<br />
| <br />
|<br />
|-<br />
| 00CE<br />
| [[#GPUREG_00CE|GPUREG_00CE]]<br />
| <br />
|<br />
|-<br />
| 00CF<br />
| [[#GPUREG_00CF|GPUREG_00CF]]<br />
| <br />
|<br />
|-<br />
| 00D0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_2<br />
|-<br />
| 00D1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_2_OPERAND<br />
|-<br />
| 00D2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COMBINE<br />
|-<br />
| 00D3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COLOR<br />
|-<br />
| 00D4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_2_SCALE<br />
|-<br />
| 00D5<br />
| [[#GPUREG_00D5|GPUREG_00D5]]<br />
| <br />
|<br />
|-<br />
| 00D6<br />
| [[#GPUREG_00D6|GPUREG_00D6]]<br />
| <br />
|<br />
|-<br />
| 00D7<br />
| [[#GPUREG_00D7|GPUREG_00D7]]<br />
| <br />
|<br />
|-<br />
| 00D8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_3<br />
|-<br />
| 00D9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_3_OPERAND<br />
|-<br />
| 00DA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COMBINE<br />
|-<br />
| 00DB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COLOR<br />
|-<br />
| 00DC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_3_SCALE<br />
|-<br />
| 00DD<br />
| [[#GPUREG_00DD|GPUREG_00DD]]<br />
| <br />
|<br />
|-<br />
| 00DE<br />
| [[#GPUREG_00DE|GPUREG_00DE]]<br />
| <br />
|<br />
|-<br />
| 00DF<br />
| [[#GPUREG_00DF|GPUREG_00DF]]<br />
| <br />
|<br />
|-<br />
| 00E0<br />
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]<br />
|?<br />
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT<br />
|-<br />
| 00E1<br />
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]<br />
|?<br />
|PICA_REG_FOG_COLOR<br />
|-<br />
| 00E2<br />
| [[#GPUREG_00E2|GPUREG_00E2]]<br />
| <br />
|<br />
|-<br />
| 00E3<br />
| [[#GPUREG_00E3|GPUREG_00E3]]<br />
| <br />
|<br />
|-<br />
| 00E4<br />
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]<br />
|?<br />
|PICA_REG_GAS_ATTENUATION<br />
|-<br />
| 00E5<br />
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]<br />
|?<br />
|PICA_REG_GAS_ACCMAX<br />
|-<br />
| 00E6<br />
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FOG_LUT_INDEX<br />
|-<br />
| 00E7<br />
| [[#GPUREG_00E7|GPUREG_00E7]]<br />
| <br />
|<br />
|-<br />
| 00E8<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA0<br />
|-<br />
| 00E9<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]<br />
|? <br />
|PICA_REG_FOG_LUT_DATA1<br />
|-<br />
| 00EA<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA2<br />
|-<br />
| 00EB<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA3<br />
|-<br />
| 00EC<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA4<br />
|-<br />
| 00ED<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA5<br />
|-<br />
| 00EE<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA6<br />
|-<br />
| 00EF<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA7<br />
|-<br />
| 00F0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_4<br />
|-<br />
| 00F1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_4_OPERAND<br />
|-<br />
| 00F2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COMBINE<br />
|-<br />
| 00F3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COLOR<br />
|-<br />
| 00F4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_4_SCALE<br />
|-<br />
| 00F5<br />
| [[#GPUREG_00F5|GPUREG_00F5]]<br />
| <br />
|<br />
|-<br />
| 00F6<br />
| [[#GPUREG_00F6|GPUREG_00F6]]<br />
| <br />
|<br />
|-<br />
| 00F7<br />
| [[#GPUREG_00F7|GPUREG_00F7]]<br />
| <br />
|<br />
|-<br />
| 00F8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_5<br />
|-<br />
| 00F9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_5_OPERAND<br />
|-<br />
| 00FA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COMBINE<br />
|-<br />
| 00FB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COLOR<br />
|-<br />
| 00FC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_5_SCALE<br />
|-<br />
| 00FD<br />
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]<br />
|?<br />
|PICA_REG_TEX_ENV_BUF_COLOR<br />
|-<br />
| 00FE<br />
| [[#GPUREG_00FE|GPUREG_00FE]]<br />
| <br />
|<br />
|-<br />
| 00FF<br />
| [[#GPUREG_00FF|GPUREG_00FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Framebuffer registers (0x100-0x13F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0100<br />
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]<br />
|<br />
|PICA_REG_COLOR_OPERATION<br />
|-<br />
| 0101<br />
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]<br />
| <br />
|PICA_REG_BLEND_FUNC<br />
|-<br />
| 0102<br />
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]<br />
| <br />
|PICA_REG_LOGIC_OP<br />
|-<br />
| 0103<br />
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]<br />
| <br />
|PICA_REG_BLEND_COLOR<br />
|-<br />
| 0104<br />
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]<br />
| <br />
|PICA_REG_FRAGOP_ALPHA_TEST<br />
|-<br />
| 0105<br />
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]<br />
| <br />
|PICA_REG_STENCIL_TEST<br />
|-<br />
| 0106<br />
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]<br />
| <br />
|PICA_REG_STENCIL_OP<br />
|-<br />
| 0107<br />
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]<br />
| <br />
|PICA_REG_DEPTH_COLOR_MASK<br />
|-<br />
| 0108<br />
| [[#GPUREG_0108|GPUREG_0108]]<br />
| <br />
|<br />
|-<br />
| 0109<br />
| [[#GPUREG_0109|GPUREG_0109]]<br />
| <br />
|<br />
|-<br />
| 010A<br />
| [[#GPUREG_010A|GPUREG_010A]]<br />
| <br />
|<br />
|-<br />
| 010B<br />
| [[#GPUREG_010B|GPUREG_010B]]<br />
| <br />
|<br />
|-<br />
| 010C<br />
| [[#GPUREG_010C|GPUREG_010C]]<br />
| <br />
|<br />
|-<br />
| 010D<br />
| [[#GPUREG_010D|GPUREG_010D]]<br />
| <br />
|<br />
|-<br />
| 010E<br />
| [[#GPUREG_010E|GPUREG_010E]]<br />
| <br />
|<br />
|-<br />
| 010F<br />
| [[#GPUREG_010F|GPUREG_010F]]<br />
| <br />
|<br />
|-<br />
| 0110<br />
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR0<br />
|-<br />
| 0111<br />
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR1<br />
|-<br />
| 0112<br />
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_READ<br />
|-<br />
| 0113<br />
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_WRITE<br />
|-<br />
| 0114<br />
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_READ<br />
|-<br />
| 0115<br />
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_WRITE<br />
|-<br />
| 0116<br />
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_DEPTH_MODE<br />
|-<br />
| 0117<br />
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_MODE<br />
|-<br />
| 0118<br />
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST2<br />
|-<br />
| 0119<br />
| [[#GPUREG_0119|GPUREG_0119]]<br />
| <br />
|<br />
|-<br />
| 011A<br />
| [[#GPUREG_011A|GPUREG_011A]]<br />
| <br />
|<br />
|-<br />
| 011B<br />
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]<br />
|<br />
|PICA_REG_RENDER_BLOCK_FORMAT<br />
|-<br />
| 011C<br />
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]<br />
|<br />
|PICA_REG_RENDER_BUF_DEPTH_ADDR<br />
|-<br />
| 011D<br />
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_ADDR<br />
|-<br />
| 011E<br />
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]<br />
| <br />
|PICA_REG_RENDER_BUF_RESOLUTION0<br />
|-<br />
| 011F<br />
| [[#GPUREG_011F|GPUREG_011F]]<br />
| <br />
|<br />
|-<br />
| 0120<br />
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_XY<br />
|-<br />
| 0121<br />
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z<br />
|-<br />
| 0122<br />
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z_COLOR<br />
|-<br />
| 0123<br />
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]<br />
|?<br />
|PICA_REG_GAS_LUT_INDEX<br />
|-<br />
| 0124<br />
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]<br />
|?<br />
|PICA_REG_GAS_LUT_DATA<br />
|-<br />
| 0125<br />
| [[#GPUREG_0125|GPUREG_0125]]<br />
| <br />
|<br />
|-<br />
| 0126<br />
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]<br />
|?<br />
|PICA_REG_GAS_DELTAZ_DEPTH<br />
|-<br />
| 0127<br />
| [[#GPUREG_0127|GPUREG_0127]]<br />
| <br />
|<br />
|-<br />
| 0128<br />
| [[#GPUREG_0128|GPUREG_0128]]<br />
| <br />
|<br />
|-<br />
| 0129<br />
| [[#GPUREG_0129|GPUREG_0129]]<br />
| <br />
|<br />
|-<br />
| 012A<br />
| [[#GPUREG_012A|GPUREG_012A]]<br />
| <br />
|<br />
|-<br />
| 012B<br />
| [[#GPUREG_012B|GPUREG_012B]]<br />
| <br />
|<br />
|-<br />
| 012C<br />
| [[#GPUREG_012C|GPUREG_012C]]<br />
| <br />
|<br />
|-<br />
| 012D<br />
| [[#GPUREG_012D|GPUREG_012D]]<br />
| <br />
|<br />
|-<br />
| 012E<br />
| [[#GPUREG_012E|GPUREG_012E]]<br />
| <br />
|<br />
|-<br />
| 012F<br />
| [[#GPUREG_012F|GPUREG_012F]]<br />
| <br />
|<br />
|-<br />
| 0130<br />
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]<br />
|?<br />
|PICA_REG_FRAGOP_SHADOW<br />
|-<br />
| 0131<br />
| [[#GPUREG_0131|GPUREG_0131]]<br />
| <br />
|<br />
|-<br />
| 0132<br />
| [[#GPUREG_0132|GPUREG_0132]]<br />
| <br />
|<br />
|-<br />
| 0133<br />
| [[#GPUREG_0133|GPUREG_0133]]<br />
| <br />
|<br />
|-<br />
| 0134<br />
| [[#GPUREG_0134|GPUREG_0134]]<br />
| <br />
|<br />
|-<br />
| 0135<br />
| [[#GPUREG_0135|GPUREG_0135]]<br />
| <br />
|<br />
|-<br />
| 0136<br />
| [[#GPUREG_0136|GPUREG_0136]]<br />
| <br />
|<br />
|-<br />
| 0137<br />
| [[#GPUREG_0137|GPUREG_0137]]<br />
| <br />
|<br />
|-<br />
| 0138<br />
| [[#GPUREG_0138|GPUREG_0138]]<br />
| <br />
|<br />
|-<br />
| 0139<br />
| [[#GPUREG_0139|GPUREG_0139]]<br />
| <br />
|<br />
|-<br />
| 013A<br />
| [[#GPUREG_013A|GPUREG_013A]]<br />
| <br />
|<br />
|-<br />
| 013B<br />
| [[#GPUREG_013B|GPUREG_013B]]<br />
| <br />
|<br />
|-<br />
| 013C<br />
| [[#GPUREG_013C|GPUREG_013C]]<br />
| <br />
|<br />
|-<br />
| 013D<br />
| [[#GPUREG_013D|GPUREG_013D]]<br />
| <br />
|<br />
|-<br />
| 013E<br />
| [[#GPUREG_013E|GPUREG_013E]]<br />
| <br />
|<br />
|-<br />
| 013F<br />
| [[#GPUREG_013F|GPUREG_013F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Fragment lighting registers (0x140-0x1FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0140<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START<br />
|-<br />
| 0141<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR1<br />
|-<br />
| 0142<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIFFUSE<br />
|-<br />
| 0143<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_AMBIENT<br />
|-<br />
| 0144<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_XY<br />
|-<br />
| 0145<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_Z<br />
|-<br />
| 0146<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_XY<br />
|-<br />
| 0147<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_Z<br />
|-<br />
| 0148<br />
| [[#GPUREG_0148|GPUREG_0148]]<br />
| <br />
|<br />
|-<br />
| 0149<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]<br />
| <br />
|PICA_REG_FRAG_LIGHT0_TYPE<br />
|-<br />
| 014A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS<br />
|-<br />
| 014B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE<br />
|-<br />
| 014C<br />
| [[#GPUREG_014C|GPUREG_014C]]<br />
| <br />
|<br />
|-<br />
| 014D<br />
| [[#GPUREG_014D|GPUREG_014D]]<br />
| <br />
|<br />
|-<br />
| 014E<br />
| [[#GPUREG_014E|GPUREG_014E]]<br />
| <br />
|<br />
|-<br />
| 014F<br />
| [[#GPUREG_014F|GPUREG_014F]]<br />
| <br />
|<br />
|-<br />
| 0150<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR0<br />
|-<br />
| 0151<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR1<br />
|-<br />
| 0152<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIFFUSE<br />
|-<br />
| 0153<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_AMBIENT<br />
|-<br />
| 0154<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_XY<br />
|-<br />
| 0155<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_Z<br />
|-<br />
| 0156<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_XY<br />
|-<br />
| 0157<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_Z<br />
|-<br />
| 0158<br />
| [[#GPUREG_0158|GPUREG_0158]]<br />
| <br />
|<br />
|-<br />
| 0159<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_TYPE<br />
|-<br />
| 015A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS<br />
|-<br />
| 015B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE<br />
|-<br />
| 015C<br />
| [[#GPUREG_015C|GPUREG_015C]]<br />
| <br />
|<br />
|-<br />
| 015D<br />
| [[#GPUREG_015D|GPUREG_015D]]<br />
| <br />
|<br />
|-<br />
| 015E<br />
| [[#GPUREG_015E|GPUREG_015E]]<br />
| <br />
|<br />
|-<br />
| 015F<br />
| [[#GPUREG_015F|GPUREG_015F]]<br />
| <br />
|<br />
|-<br />
| 0160<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR0<br />
|-<br />
| 0161<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR1<br />
|-<br />
| 0162<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIFFUSE<br />
|-<br />
| 0163<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_AMBIENT<br />
|-<br />
| 0164<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_XY<br />
|-<br />
| 0165<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_Z<br />
|-<br />
| 0166<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_XY<br />
|-<br />
| 0167<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_Z<br />
|-<br />
| 0168<br />
| [[#GPUREG_0168|GPUREG_0168]]<br />
| <br />
|<br />
|-<br />
| 0169<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_TYPE<br />
|-<br />
| 016A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS<br />
|-<br />
| 016B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE<br />
|-<br />
| 016C<br />
| [[#GPUREG_016C|GPUREG_016C]]<br />
| <br />
|<br />
|-<br />
| 016D<br />
| [[#GPUREG_016D|GPUREG_016D]]<br />
| <br />
|<br />
|-<br />
| 016E<br />
| [[#GPUREG_016E|GPUREG_016E]]<br />
| <br />
|<br />
|-<br />
| 016F<br />
| [[#GPUREG_016F|GPUREG_016F]]<br />
| <br />
|<br />
|-<br />
| 0170<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR0<br />
|-<br />
| 0171<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR1<br />
|-<br />
| 0172<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIFFUSE<br />
|-<br />
| 0173<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_AMBIENT<br />
|-<br />
| 0174<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_XY<br />
|-<br />
| 0175<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_Z<br />
|-<br />
| 0176<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]<br />
|? <br />
|PICA_REG_FRAG_LIGHT3_SPOT_XY<br />
|-<br />
| 0177<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPOT_Z<br />
|-<br />
| 0178<br />
| [[#GPUREG_0178|GPUREG_0178]]<br />
| <br />
|<br />
|-<br />
| 0179<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_TYPE<br />
|-<br />
| 017A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS<br />
|-<br />
| 017B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE<br />
|-<br />
| 017C<br />
| [[#GPUREG_017C|GPUREG_017C]]<br />
| <br />
|<br />
|-<br />
| 017D<br />
| [[#GPUREG_017D|GPUREG_017D]]<br />
| <br />
|<br />
|-<br />
| 017E<br />
| [[#GPUREG_017E|GPUREG_017E]]<br />
| <br />
|<br />
|-<br />
| 017F<br />
| [[#GPUREG_017F|GPUREG_017F]]<br />
| <br />
|<br />
|-<br />
| 0180<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR0<br />
|-<br />
| 0181<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR1<br />
|-<br />
| 0182<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIFFUSE<br />
|-<br />
| 0183<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_AMBIENT<br />
|-<br />
| 0184<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_XY<br />
|-<br />
| 0185<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_Z<br />
|-<br />
| 0186<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_XY<br />
|-<br />
| 0187<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_Z<br />
|-<br />
| 0188<br />
| [[#GPUREG_0188|GPUREG_0188]]<br />
| <br />
|<br />
|-<br />
| 0189<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_TYPE<br />
|-<br />
| 018A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS<br />
|-<br />
| 018B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE<br />
|-<br />
| 018C<br />
| [[#GPUREG_018C|GPUREG_018C]]<br />
| <br />
|<br />
|-<br />
| 018D<br />
| [[#GPUREG_018D|GPUREG_018D]]<br />
| <br />
|<br />
|-<br />
| 018E<br />
| [[#GPUREG_018E|GPUREG_018E]]<br />
| <br />
|<br />
|-<br />
| 018F<br />
| [[#GPUREG_018F|GPUREG_018F]]<br />
| <br />
|<br />
|-<br />
| 0190<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR0<br />
|-<br />
| 0191<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR1<br />
|-<br />
| 0192<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_DIFFUSE<br />
|-<br />
| 0193<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_AMBIENT<br />
|-<br />
| 0194<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_XY<br />
|-<br />
| 0195<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_Z<br />
|-<br />
| 0196<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_XY<br />
|-<br />
| 0197<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_Z<br />
|-<br />
| 0198<br />
| [[#GPUREG_0198|GPUREG_0198]]<br />
| <br />
|<br />
|-<br />
| 0199<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_TYPE<br />
|-<br />
| 019A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS<br />
|-<br />
| 019B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE<br />
|-<br />
| 019C<br />
| [[#GPUREG_019C|GPUREG_019C]]<br />
| <br />
|<br />
|-<br />
| 019D<br />
| [[#GPUREG_019D|GPUREG_019D]]<br />
| <br />
|<br />
|-<br />
| 019E<br />
| [[#GPUREG_019E|GPUREG_019E]]<br />
| <br />
|<br />
|-<br />
| 019F<br />
| [[#GPUREG_019F|GPUREG_019F]]<br />
| <br />
|<br />
|-<br />
| 01A0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR0<br />
|-<br />
| 01A1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR1<br />
|-<br />
| 01A2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIFFUSE<br />
|-<br />
| 01A3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_AMBIENT<br />
|-<br />
| 01A4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_XY<br />
|-<br />
| 01A5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_Z<br />
|-<br />
| 01A6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_XY<br />
|-<br />
| 01A7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_Z<br />
|-<br />
| 01A8<br />
| [[#GPUREG_01A8|GPUREG_01A8]]<br />
| <br />
|<br />
|-<br />
| 01A9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_TYPE<br />
|-<br />
| 01AA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS<br />
|-<br />
| 01AB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE<br />
|-<br />
| 01AC<br />
| [[#GPUREG_01AC|GPUREG_01AC]]<br />
| <br />
|<br />
|-<br />
| 01AD<br />
| [[#GPUREG_01AD|GPUREG_01AD]]<br />
| <br />
|<br />
|-<br />
| 01AE<br />
| [[#GPUREG_01AE|GPUREG_01AE]]<br />
| <br />
|<br />
|-<br />
| 01AF<br />
| [[#GPUREG_01AF|GPUREG_01AF]]<br />
| <br />
|<br />
|-<br />
| 01B0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR0<br />
|-<br />
| 01B1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR1<br />
|-<br />
| 01B2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_DIFFUSE<br />
|-<br />
| 01B3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_AMBIENT<br />
|-<br />
| 01B4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_XY<br />
|-<br />
| 01B5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_Z<br />
|-<br />
| 01B6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_XY<br />
|-<br />
| 01B7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_Z<br />
|-<br />
| 01B8<br />
| [[#GPUREG_01B8|GPUREG_01B8]]<br />
| <br />
|<br />
|-<br />
| 01B9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_TYPE<br />
|-<br />
| 01BA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS<br />
|-<br />
| 01BB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE<br />
|-<br />
| 01BC<br />
| [[#GPUREG_01BC|GPUREG_01BC]]<br />
| <br />
|<br />
|-<br />
| 01BD<br />
| [[#GPUREG_01BD|GPUREG_01BD]]<br />
| <br />
|<br />
|-<br />
| 01BE<br />
| [[#GPUREG_01BE|GPUREG_01BE]]<br />
| <br />
|<br />
|-<br />
| 01BF<br />
| [[#GPUREG_01BF|GPUREG_01BF]]<br />
| <br />
|<br />
|-<br />
| 01C0<br />
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_AMBIENT<br />
|-<br />
| 01C1<br />
| [[#GPUREG_01C1|GPUREG_01C1]]<br />
| <br />
|<br />
|-<br />
| 01C2<br />
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_NUM<br />
|-<br />
| 01C3<br />
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE0<br />
|-<br />
| 01C4<br />
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE1<br />
|-<br />
| 01C5<br />
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT<br />
|-<br />
| 01C6<br />
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN1<br />
|-<br />
| 01C7<br />
| [[#GPUREG_01C7|GPUREG_01C7]]<br />
| <br />
|<br />
|-<br />
| 01C8<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA0<br />
|-<br />
| 01C9<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA1<br />
|-<br />
| 01CA<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA2<br />
|-<br />
| 01CB<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA3<br />
|-<br />
| 01CC<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA4<br />
|-<br />
| 01CD<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA5<br />
|-<br />
| 01CE<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA6<br />
|-<br />
| 01CF<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA7<br />
|-<br />
| 01D0<br />
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT<br />
|-<br />
| 01D1<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTINPUT<br />
|-<br />
| 01D2<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTSCALE<br />
|-<br />
| 01D3<br />
| [[#GPUREG_01D3|GPUREG_01D3]]<br />
| <br />
|<br />
|-<br />
| 01D4<br />
| [[#GPUREG_01D4|GPUREG_01D4]]<br />
| <br />
|<br />
|-<br />
| 01D5<br />
| [[#GPUREG_01D5|GPUREG_01D5]]<br />
| <br />
|<br />
|-<br />
| 01D6<br />
| [[#GPUREG_01D6|GPUREG_01D6]]<br />
| <br />
|<br />
|-<br />
| 01D7<br />
| [[#GPUREG_01D7|GPUREG_01D7]]<br />
| <br />
|<br />
|-<br />
| 01D8<br />
| [[#GPUREG_01D8|GPUREG_01D8]]<br />
| <br />
|<br />
|-<br />
| 01D9<br />
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_EN_ID<br />
|-<br />
| 01DA<br />
| [[#GPUREG_01DA|GPUREG_01DA]]<br />
| <br />
|<br />
|-<br />
| 01DB<br />
| [[#GPUREG_01DB|GPUREG_01DB]]<br />
| <br />
|<br />
|-<br />
| 01DC<br />
| [[#GPUREG_01DC|GPUREG_01DC]]<br />
| <br />
|<br />
|-<br />
| 01DD<br />
| [[#GPUREG_01DD|GPUREG_01DD]]<br />
| <br />
|<br />
|-<br />
| 01DE<br />
| [[#GPUREG_01DE|GPUREG_01DE]]<br />
| <br />
|<br />
|-<br />
| 01DF<br />
| [[#GPUREG_01DF|GPUREG_01DF]]<br />
| <br />
|<br />
|-<br />
| 01E0<br />
| [[#GPUREG_01E0|GPUREG_01E0]]<br />
| <br />
|<br />
|-<br />
| 01E1<br />
| [[#GPUREG_01E1|GPUREG_01E1]]<br />
| <br />
|<br />
|-<br />
| 01E2<br />
| [[#GPUREG_01E2|GPUREG_01E2]]<br />
| <br />
|<br />
|-<br />
| 01E3<br />
| [[#GPUREG_01E3|GPUREG_01E3]]<br />
| <br />
|<br />
|-<br />
| 01E4<br />
| [[#GPUREG_01E4|GPUREG_01E4]]<br />
| <br />
|<br />
|-<br />
| 01E5<br />
| [[#GPUREG_01E5|GPUREG_01E5]]<br />
| <br />
|<br />
|-<br />
| 01E6<br />
| [[#GPUREG_01E6|GPUREG_01E6]]<br />
| <br />
|<br />
|-<br />
| 01E7<br />
| [[#GPUREG_01E7|GPUREG_01E7]]<br />
| <br />
|<br />
|-<br />
| 01E8<br />
| [[#GPUREG_01E8|GPUREG_01E8]]<br />
| <br />
|<br />
|-<br />
| 01E9<br />
| [[#GPUREG_01E9|GPUREG_01E9]]<br />
| <br />
|<br />
|-<br />
| 01EA<br />
| [[#GPUREG_01EA|GPUREG_01EA]]<br />
| <br />
|<br />
|-<br />
| 01EB<br />
| [[#GPUREG_01EB|GPUREG_01EB]]<br />
| <br />
|<br />
|-<br />
| 01EC<br />
| [[#GPUREG_01EC|GPUREG_01EC]]<br />
| <br />
|<br />
|-<br />
| 01ED<br />
| [[#GPUREG_01ED|GPUREG_01ED]]<br />
| <br />
|<br />
|-<br />
| 01EE<br />
| [[#GPUREG_01EE|GPUREG_01EE]]<br />
| <br />
|<br />
|-<br />
| 01EF<br />
| [[#GPUREG_01EF|GPUREG_01EF]]<br />
| <br />
|<br />
|-<br />
| 01F0<br />
| [[#GPUREG_01F0|GPUREG_01F0]]<br />
| <br />
|<br />
|-<br />
| 01F1<br />
| [[#GPUREG_01F1|GPUREG_01F1]]<br />
| <br />
|<br />
|-<br />
| 01F2<br />
| [[#GPUREG_01F2|GPUREG_01F2]]<br />
| <br />
|<br />
|-<br />
| 01F3<br />
| [[#GPUREG_01F3|GPUREG_01F3]]<br />
| <br />
|<br />
|-<br />
| 01F4<br />
| [[#GPUREG_01F4|GPUREG_01F4]]<br />
| <br />
|<br />
|-<br />
| 01F5<br />
| [[#GPUREG_01F5|GPUREG_01F5]]<br />
| <br />
|<br />
|-<br />
| 01F6<br />
| [[#GPUREG_01F6|GPUREG_01F6]]<br />
| <br />
|<br />
|-<br />
| 01F7<br />
| [[#GPUREG_01F7|GPUREG_01F7]]<br />
| <br />
|<br />
|-<br />
| 01F8<br />
| [[#GPUREG_01F8|GPUREG_01F8]]<br />
| <br />
|<br />
|-<br />
| 01F9<br />
| [[#GPUREG_01F9|GPUREG_01F9]]<br />
| <br />
|<br />
|-<br />
| 01FA<br />
| [[#GPUREG_01FA|GPUREG_01FA]]<br />
| <br />
|<br />
|-<br />
| 01FB<br />
| [[#GPUREG_01FB|GPUREG_01FB]]<br />
| <br />
|<br />
|-<br />
| 01FC<br />
| [[#GPUREG_01FC|GPUREG_01FC]]<br />
| <br />
|<br />
|-<br />
| 01FD<br />
| [[#GPUREG_01FD|GPUREG_01FD]]<br />
| <br />
|<br />
|-<br />
| 01FE<br />
| [[#GPUREG_01FE|GPUREG_01FE]]<br />
| <br />
|<br />
|-<br />
| 01FF<br />
| [[#GPUREG_01FF|GPUREG_01FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Geometry pipeline registers (0x200-0x27F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0200<br />
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR<br />
|-<br />
| 0201<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS0<br />
|-<br />
| 0202<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS1<br />
|-<br />
| 0203<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET<br />
|-<br />
| 0204<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT0<br />
|-<br />
| 0205<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT1<br />
|-<br />
| 0206<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0207<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0208<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0209<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020B<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020C<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020E<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020F<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0210<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0211<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0212<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0213<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0214<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0215<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0216<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0217<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0218<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0219<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021B<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021C<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021E<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021F<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0220<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0221<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0222<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0223<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0224<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0225<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0226<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0227<br />
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET<br />
|-<br />
| 0228<br />
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]<br />
| <br />
|PICA_REG_DRAW_VERTEX_NUM<br />
|-<br />
| 0229<br />
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]<br />
| ?<br />
|PICA_REG_DRAW_MODE0<br />
|-<br />
| 022A<br />
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]<br />
|<br />
|PICA_REG_DRAW_VERTEX_OFFSET<br />
|-<br />
| 022B<br />
| [[#GPUREG_022B|GPUREG_022B]]<br />
| <br />
|<br />
|-<br />
| 022C<br />
| [[#GPUREG_022C|GPUREG_022C]]<br />
| <br />
|<br />
|-<br />
| 022D<br />
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]<br />
| <br />
|PICA_REG_POST_VERTEX_CACHE_NUM<br />
|-<br />
| 022E<br />
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]<br />
|<br />
|PICA_REG_START_DRAW_ARRAY<br />
|-<br />
| 022F<br />
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]<br />
|<br />
|PICA_REG_START_DRAW_ELEMENT<br />
|-<br />
| 0230<br />
| [[#GPUREG_0230|GPUREG_0230]]<br />
| <br />
|<br />
|-<br />
| 0231<br />
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]<br />
|?<br />
|PICA_REG_VTX_FUNC<br />
|-<br />
| 0232<br />
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR<br />
|-<br />
| 0233<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA0<br />
|-<br />
| 0234<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA1<br />
|-<br />
| 0235<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA2<br />
|-<br />
| 0236<br />
| [[#GPUREG_0236|GPUREG_0236]]<br />
| <br />
|<br />
|-<br />
| 0237<br />
| [[#GPUREG_0237|GPUREG_0237]]<br />
| <br />
|<br />
|-<br />
| 0238<br />
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH0<br />
|-<br />
| 0239<br />
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH1<br />
|-<br />
| 023A<br />
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH0<br />
|-<br />
| 023B<br />
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH1<br />
|-<br />
| 023C<br />
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH0<br />
|-<br />
| 023D<br />
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH1<br />
|-<br />
| 023E<br />
| [[#GPUREG_023E|GPUREG_023E]]<br />
| <br />
|<br />
|-<br />
| 023F<br />
| [[#GPUREG_023F|GPUREG_023F]]<br />
| <br />
|<br />
|-<br />
| 0240<br />
| [[#GPUREG_0240|GPUREG_0240]]<br />
| <br />
|<br />
|-<br />
| 0241<br />
| [[#GPUREG_0241|GPUREG_0241]]<br />
| <br />
|<br />
|-<br />
| 0242<br />
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]<br />
|?<br />
|PICA_REG_VS_ATTR_NUM1<br />
|-<br />
| 0243<br />
| [[#GPUREG_0243|GPUREG_0243]]<br />
| <br />
|<br />
|-<br />
| 0244<br />
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]<br />
|?<br />
|PICA_REG_VS_COM_MODE<br />
|-<br />
| 0245<br />
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC0<br />
|-<br />
| 0246<br />
| [[#GPUREG_0246|GPUREG_0246]]<br />
| <br />
|<br />
|-<br />
| 0247<br />
| [[#GPUREG_0247|GPUREG_0247]]<br />
| <br />
|<br />
|-<br />
| 0248<br />
| [[#GPUREG_0248|GPUREG_0248]]<br />
| <br />
|<br />
|-<br />
| 0249<br />
| [[#GPUREG_0249|GPUREG_0249]]<br />
| <br />
|<br />
|-<br />
| 024A<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM1<br />
|-<br />
| 024B<br />
| [[#GPUREG_024B|GPUREG_024B]]<br />
|<br />
|<br />
|-<br />
| 024C<br />
| [[#GPUREG_024C|GPUREG_024C]]<br />
| <br />
|<br />
|-<br />
| 024D<br />
| [[#GPUREG_024D|GPUREG_024D]]<br />
| <br />
|<br />
|-<br />
| 024E<br />
| [[#GPUREG_024E|GPUREG_024E]]<br />
| <br />
|<br />
|-<br />
| 024F<br />
| [[#GPUREG_024F|GPUREG_024F]]<br />
| <br />
|<br />
|-<br />
| 0250<br />
| [[#GPUREG_0250|GPUREG_0250]]<br />
| <br />
|<br />
|-<br />
| 0251<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM2<br />
|-<br />
| 0252<br />
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]<br />
|?<br />
|PICA_REG_GS_MISC_REG0<br />
|-<br />
| 0253<br />
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]<br />
|?<br />
|PICA_REG_DRAW_MODE1<br />
|-<br />
| 0254<br />
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]<br />
|?<br />
|PICA_REG_GS_MISC_REG1<br />
|-<br />
| 0255<br />
| [[#GPUREG_0255|GPUREG_0255]]<br />
| <br />
|<br />
|-<br />
| 0256<br />
| [[#GPUREG_0256|GPUREG_0256]]<br />
| <br />
|<br />
|-<br />
| 0257<br />
| [[#GPUREG_0257|GPUREG_0257]]<br />
| <br />
|<br />
|-<br />
| 0258<br />
| [[#GPUREG_0258|GPUREG_0258]]<br />
| <br />
|<br />
|-<br />
| 0259<br />
| [[#GPUREG_0259|GPUREG_0259]]<br />
| <br />
|<br />
|-<br />
| 025A<br />
| [[#GPUREG_025A|GPUREG_025A]]<br />
| <br />
|<br />
|-<br />
| 025B<br />
| [[#GPUREG_025B|GPUREG_025B]]<br />
| <br />
|<br />
|-<br />
| 025C<br />
| [[#GPUREG_025C|GPUREG_025C]]<br />
| <br />
|<br />
|-<br />
| 025D<br />
| [[#GPUREG_025D|GPUREG_025D]]<br />
| <br />
|<br />
|-<br />
| 025E<br />
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]<br />
| ?<br />
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3<br />
|-<br />
| 025F<br />
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC1<br />
|-<br />
| 0260<br />
| [[#GPUREG_0260|GPUREG_0260]]<br />
| <br />
|<br />
|-<br />
| 0261<br />
| [[#GPUREG_0261|GPUREG_0261]]<br />
| <br />
|<br />
|-<br />
| 0262<br />
| [[#GPUREG_0262|GPUREG_0262]]<br />
| <br />
|<br />
|-<br />
| 0263<br />
| [[#GPUREG_0263|GPUREG_0263]]<br />
| <br />
|<br />
|-<br />
| 0264<br />
| [[#GPUREG_0264|GPUREG_0264]]<br />
| <br />
|<br />
|-<br />
| 0265<br />
| [[#GPUREG_0265|GPUREG_0265]]<br />
| <br />
|<br />
|-<br />
| 0266<br />
| [[#GPUREG_0266|GPUREG_0266]]<br />
| <br />
|<br />
|-<br />
| 0267<br />
| [[#GPUREG_0267|GPUREG_0267]]<br />
| <br />
|<br />
|-<br />
| 0268<br />
| [[#GPUREG_0268|GPUREG_0268]]<br />
| <br />
|<br />
|-<br />
| 0269<br />
| [[#GPUREG_0269|GPUREG_0269]]<br />
| <br />
|<br />
|-<br />
| 026A<br />
| [[#GPUREG_026A|GPUREG_026A]]<br />
| <br />
|<br />
|-<br />
| 026B<br />
| [[#GPUREG_026B|GPUREG_026B]]<br />
| <br />
|<br />
|-<br />
| 026C<br />
| [[#GPUREG_026C|GPUREG_026C]]<br />
| <br />
|<br />
|-<br />
| 026D<br />
| [[#GPUREG_026D|GPUREG_026D]]<br />
| <br />
|<br />
|-<br />
| 026E<br />
| [[#GPUREG_026E|GPUREG_026E]]<br />
| <br />
|<br />
|-<br />
| 026F<br />
| [[#GPUREG_026F|GPUREG_026F]]<br />
| <br />
|<br />
|-<br />
| 0270<br />
| [[#GPUREG_0270|GPUREG_0270]]<br />
| <br />
|<br />
|-<br />
| 0271<br />
| [[#GPUREG_0271|GPUREG_0271]]<br />
| <br />
|<br />
|-<br />
| 0272<br />
| [[#GPUREG_0272|GPUREG_0272]]<br />
| <br />
|<br />
|-<br />
| 0273<br />
| [[#GPUREG_0273|GPUREG_0273]]<br />
| <br />
|<br />
|-<br />
| 0274<br />
| [[#GPUREG_0274|GPUREG_0274]]<br />
| <br />
|<br />
|-<br />
| 0275<br />
| [[#GPUREG_0275|GPUREG_0275]]<br />
| <br />
|<br />
|-<br />
| 0276<br />
| [[#GPUREG_0276|GPUREG_0276]]<br />
| <br />
|<br />
|-<br />
| 0277<br />
| [[#GPUREG_0277|GPUREG_0277]]<br />
| <br />
|<br />
|-<br />
| 0278<br />
| [[#GPUREG_0278|GPUREG_0278]]<br />
| <br />
|<br />
|-<br />
| 0279<br />
| [[#GPUREG_0279|GPUREG_0279]]<br />
| <br />
|<br />
|-<br />
| 027A<br />
| [[#GPUREG_027A|GPUREG_027A]]<br />
| <br />
|<br />
|-<br />
| 027B<br />
| [[#GPUREG_027B|GPUREG_027B]]<br />
| <br />
|<br />
|-<br />
| 027C<br />
| [[#GPUREG_027C|GPUREG_027C]]<br />
| <br />
|<br />
|-<br />
| 027D<br />
| [[#GPUREG_027D|GPUREG_027D]]<br />
| <br />
|<br />
|-<br />
| 027E<br />
| [[#GPUREG_027E|GPUREG_027E]]<br />
| <br />
|<br />
|-<br />
| 027F<br />
| [[#GPUREG_027F|GPUREG_027F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Shader registers (0x280-0x2DF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
! colspan=4 | Geometry shader<br />
|-<br />
| 0280<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_GS_BOOL<br />
|-<br />
| 0281<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_GS_INT0<br />
|-<br />
| 0282<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_GS_INT1<br />
|-<br />
| 0283<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_GS_INT2<br />
|-<br />
| 0284<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_GS_INT3<br />
|-<br />
| 0285<br />
| [[#GPUREG_0285|GPUREG_0285]]<br />
| <br />
|<br />
|-<br />
| 0286<br />
| [[#GPUREG_0286|GPUREG_0286]]<br />
| <br />
|<br />
|-<br />
| 0287<br />
| [[#GPUREG_0287|GPUREG_0287]]<br />
| <br />
|<br />
|-<br />
| 0288<br />
| [[#GPUREG_0288|GPUREG_0288]]<br />
| <br />
|<br />
|-<br />
| 0289<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_GS_ATTR_NUM<br />
|-<br />
| 028A<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_GS_START_ADDR<br />
|-<br />
| 028B<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP0<br />
|-<br />
| 028C<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP1<br />
|-<br />
| 028D<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_GS_OUT_REG_MASK<br />
|-<br />
| 028E<br />
| [[#GPUREG_028E|GPUREG_028E]]<br />
| <br />
|<br />
|-<br />
| 028F<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_GS_PROG_RENEWAL_END<br />
|-<br />
| 0290<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_GS_FLOAT_ADDR<br />
|-<br />
| 0291<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA0<br />
|-<br />
| 0292<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA1<br />
|-<br />
| 0293<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA2<br />
|-<br />
| 0294<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA3<br />
|-<br />
| 0295<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA4<br />
|-<br />
| 0296<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA5<br />
|-<br />
| 0297<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA6<br />
|-<br />
| 0298<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA7<br />
|-<br />
| 0299<br />
| [[#GPUREG_0299|GPUREG_0299]]<br />
| <br />
|<br />
|-<br />
| 029A<br />
| [[#GPUREG_029A|GPUREG_029A]]<br />
| <br />
|<br />
|-<br />
| 029B<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_GS_PROG_ADDR<br />
|-<br />
| 029C<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_DATA0<br />
|-<br />
| 029D<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_DATA1<br />
|-<br />
| 029E<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_DATA2<br />
|-<br />
| 029F<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_DATA3<br />
|-<br />
| 02A0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_DATA4<br />
|-<br />
| 02A1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_DATA5<br />
|-<br />
| 02A2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_DATA6<br />
|-<br />
| 02A3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_DATA7<br />
|-<br />
| 02A4<br />
| [[#GPUREG_02A4|GPUREG_02A4]]<br />
| <br />
|<br />
|-<br />
| 02A5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02A6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02A7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02A8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02A9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02AA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02AB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02AC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02AD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02AE<br />
| [[#GPUREG_02AE|GPUREG_02AE]]<br />
| <br />
|<br />
|-<br />
| 02AF<br />
| [[#GPUREG_02AF|GPUREG_02AF]]<br />
| <br />
|<br />
|-<br />
! colspan=4 | Vertex shader<br />
|-<br />
| 02B0<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_VS_BOOL<br />
|-<br />
| 02B1<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_VS_INT0<br />
|-<br />
| 02B2<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_VS_INT1<br />
|-<br />
| 02B3<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_VS_INT2<br />
|-<br />
| 02B4<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_VS_INT3<br />
|-<br />
| 02B5<br />
| [[#GPUREG_02B5|GPUREG_02B5]]<br />
| <br />
|<br />
|-<br />
| 02B6<br />
| [[#GPUREG_02B6|GPUREG_02B6]]<br />
| <br />
|<br />
|-<br />
| 02B7<br />
| [[#GPUREG_02B7|GPUREG_02B7]]<br />
| <br />
|<br />
|-<br />
| 02B8<br />
| [[#GPUREG_02B8|GPUREG_02B8]]<br />
| <br />
|<br />
|-<br />
| 02B9<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_VS_ATTR_NUM0<br />
|-<br />
| 02BA<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_VS_START_ADDR<br />
|-<br />
| 02BB<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP0<br />
|-<br />
| 02BC<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP1<br />
|-<br />
| 02BD<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_VS_OUT_REG_MASK<br />
|-<br />
| 02BE<br />
| [[#GPUREG_02BE|GPUREG_02BE]]<br />
| <br />
|<br />
|-<br />
| 02BF<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_VS_PROG_RENEWAL_END<br />
|-<br />
| 02C0<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_VS_FLOAT_ADDR<br />
|-<br />
| 02C1<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA0<br />
|-<br />
| 02C2<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA1<br />
|-<br />
| 02C3<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA2<br />
|-<br />
| 02C4<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA3<br />
|-<br />
| 02C5<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA4<br />
|-<br />
| 02C6<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA5<br />
|-<br />
| 02C7<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA6<br />
|-<br />
| 02C8<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA7<br />
|-<br />
| 02C9<br />
| [[#GPUREG_02C9|GPUREG_02C9]]<br />
| <br />
|<br />
|-<br />
| 02CA<br />
| [[#GPUREG_02CA|GPUREG_02CA]]<br />
| <br />
|<br />
|-<br />
| 02CB<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_ADDR<br />
|-<br />
| 02CC<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_DATA0<br />
|-<br />
| 02CD<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_DATA1<br />
|-<br />
| 02CE<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_DATA2<br />
|-<br />
| 02CF<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_DATA3<br />
|-<br />
| 02D0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_DATA4<br />
|-<br />
| 02D1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_DATA5<br />
|-<br />
| 02D2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_DATA6<br />
|-<br />
| 02D3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_DATA7<br />
|-<br />
| 02D4<br />
| [[#GPUREG_02D4|GPUREG_02D4]]<br />
| <br />
|<br />
|-<br />
| 02D5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02D6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02D7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02D8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02D9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02DA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02DB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02DC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02DD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02DE<br />
| [[#GPUREG_02DE|GPUREG_02DE]]<br />
| <br />
|<br />
|-<br />
| 02DF<br />
| [[#GPUREG_02DF|GPUREG_02DF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Unknown registers (0x2E0-0x2FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 02E0<br />
| [[#GPUREG_02E0|GPUREG_02E0]]<br />
| <br />
|<br />
|-<br />
| 02E1<br />
| [[#GPUREG_02E1|GPUREG_02E1]]<br />
| <br />
|<br />
|-<br />
| 02E2<br />
| [[#GPUREG_02E2|GPUREG_02E2]]<br />
| <br />
|<br />
|-<br />
| 02E3<br />
| [[#GPUREG_02E3|GPUREG_02E3]]<br />
| <br />
|<br />
|-<br />
| 02E4<br />
| [[#GPUREG_02E4|GPUREG_02E4]]<br />
| <br />
|<br />
|-<br />
| 02E5<br />
| [[#GPUREG_02E5|GPUREG_02E5]]<br />
| <br />
|<br />
|-<br />
| 02E6<br />
| [[#GPUREG_02E6|GPUREG_02E6]]<br />
| <br />
|<br />
|-<br />
| 02E7<br />
| [[#GPUREG_02E7|GPUREG_02E7]]<br />
| <br />
|<br />
|-<br />
| 02E8<br />
| [[#GPUREG_02E8|GPUREG_02E8]]<br />
| <br />
|<br />
|-<br />
| 02E9<br />
| [[#GPUREG_02E9|GPUREG_02E9]]<br />
| <br />
|<br />
|-<br />
| 02EA<br />
| [[#GPUREG_02EA|GPUREG_02EA]]<br />
| <br />
|<br />
|-<br />
| 02EB<br />
| [[#GPUREG_02EB|GPUREG_02EB]]<br />
| <br />
|<br />
|-<br />
| 02EC<br />
| [[#GPUREG_02EC|GPUREG_02EC]]<br />
| <br />
|<br />
|-<br />
| 02ED<br />
| [[#GPUREG_02ED|GPUREG_02ED]]<br />
| <br />
|<br />
|-<br />
| 02EE<br />
| [[#GPUREG_02EE|GPUREG_02EE]]<br />
| <br />
|<br />
|-<br />
| 02EF<br />
| [[#GPUREG_02EF|GPUREG_02EF]]<br />
| <br />
|<br />
|-<br />
| 02F0<br />
| [[#GPUREG_02F0|GPUREG_02F0]]<br />
| <br />
|<br />
|-<br />
| 02F1<br />
| [[#GPUREG_02F1|GPUREG_02F1]]<br />
| <br />
|<br />
|-<br />
| 02F2<br />
| [[#GPUREG_02F2|GPUREG_02F2]]<br />
| <br />
|<br />
|-<br />
| 02F3<br />
| [[#GPUREG_02F3|GPUREG_02F3]]<br />
| <br />
|<br />
|-<br />
| 02F4<br />
| [[#GPUREG_02F4|GPUREG_02F4]]<br />
| <br />
|<br />
|-<br />
| 02F5<br />
| [[#GPUREG_02F5|GPUREG_02F5]]<br />
| <br />
|<br />
|-<br />
| 02F6<br />
| [[#GPUREG_02F6|GPUREG_02F6]]<br />
| <br />
|<br />
|-<br />
| 02F7<br />
| [[#GPUREG_02F7|GPUREG_02F7]]<br />
| <br />
|<br />
|-<br />
| 02F8<br />
| [[#GPUREG_02F8|GPUREG_02F8]]<br />
| <br />
|<br />
|-<br />
| 02F9<br />
| [[#GPUREG_02F9|GPUREG_02F9]]<br />
| <br />
|<br />
|-<br />
| 02FA<br />
| [[#GPUREG_02FA|GPUREG_02FA]]<br />
| <br />
|<br />
|-<br />
| 02FB<br />
| [[#GPUREG_02FB|GPUREG_02FB]]<br />
| <br />
|<br />
|-<br />
| 02FC<br />
| [[#GPUREG_02FC|GPUREG_02FC]]<br />
| <br />
|<br />
|-<br />
| 02FD<br />
| [[#GPUREG_02FD|GPUREG_02FD]]<br />
| <br />
|<br />
|-<br />
| 02FE<br />
| [[#GPUREG_02FE|GPUREG_02FE]]<br />
| <br />
|<br />
|-<br />
| 02FF<br />
| [[#GPUREG_02FF|GPUREG_02FF]]<br />
| <br />
|<br />
|}<br />
<br />
== Miscellaneous registers ==<br />
<br />
=== GPUREG_FINALIZE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)<br />
|}<br />
<br />
Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.<br />
Failure to write to this register in any command buffer will result in the GPU hanging.<br />
<br />
== Rasterizer registers ==<br />
<br />
=== GPUREG_FACECULLING_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Culling mode<br />
|}<br />
<br />
This register is used to configure the face culling mode.<br />
<br />
Culling mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Front Face (Counter Clockwise)<br />
|-<br />
| 2<br />
| Back Face (Counter Clockwise)<br />
|}<br />
<br />
=== GPUREG_VIEWPORT_WIDTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, width / 2<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.<br />
<br />
=== GPUREG_VIEWPORT_INVW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / width<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.<br />
<br />
=== GPUREG_VIEWPORT_HEIGHT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, height / 2<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.<br />
<br />
=== GPUREG_VIEWPORT_INVH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / height<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.<br />
<br />
=== GPUREG_FRAGOP_CLIP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable clipping planes.<br />
<br />
=== GPUREG_FRAGOP_CLIP_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Clipping plane coefficient ''i''<br />
|}<br />
<br />
This register is used to configure clipping plane coefficients.<br />
<br />
=== GPUREG_DEPTHMAP_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near - Far<br />
|}<br />
<br />
This register is used to configure the depth range scale.<br />
<br />
=== GPUREG_DEPTHMAP_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near + Polygon Offset<br />
|}<br />
<br />
This register is used to configure the depth range bias.<br />
<br />
=== GPUREG_SH_OUTMAP_TOTAL ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of following attributes<br />
|}<br />
<br />
This register is used to configure the total shader output map attributes.<br />
<br />
=== GPUREG_SH_OUTMAP_O''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Semantic for the x component of the register.<br />
|-<br />
| 8-12<br />
| unsigned, Semantic for the y component of the register.<br />
|-<br />
| 16-20<br />
| unsigned, Semantic for the z component of the register.<br />
|-<br />
| 24-28<br />
| unsigned, Semantic for the w component of the register.<br />
|}<br />
<br />
These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.<br />
<br />
Semantic values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Semantic<br />
! Description<br />
|-<br />
| 0x00<br />
| position.x<br />
| rowspan="4" | Vertex Position<br />
|-<br />
| 0x01<br />
| position.y<br />
|-<br />
| 0x02<br />
| position.z<br />
|-<br />
| 0x03<br />
| position.w<br />
|-<br />
| 0x04<br />
| normquat.x<br />
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)<br />
|-<br />
| 0x05<br />
| normquat.y<br />
|-<br />
| 0x06<br />
| normquat.z<br />
|-<br />
| 0x07<br />
| normquat.w<br />
|-<br />
| 0x08<br />
| color.r<br />
| rowspan="4" | Vertex color<br />
|-<br />
| 0x09<br />
| color.g<br />
|-<br />
| 0x0A<br />
| color.b<br />
|-<br />
| 0x0B<br />
| color.a<br />
|-<br />
| 0x0C<br />
| texcoord0.u<br />
| rowspan="2" | Texture coordinates for texture 0<br />
|-<br />
| 0x0D<br />
| texcoord0.v<br />
|-<br />
| 0x0E<br />
| texcoord1.u<br />
| rowspan="2" | Texture coordinates for texture 1<br />
|-<br />
| 0x0F<br />
| texcoord1.v<br />
|-<br />
| 0x10<br />
| texcoord0.w<br />
|<br />
<br />
|-<br />
| 0x12<br />
| view.x<br />
| rowspan="3" | View vector (for fragment lighting)<br />
|-<br />
| 0x13<br />
| view.y<br />
|-<br />
| 0x14<br />
| view.z<br />
<br />
|-<br />
| 0x16<br />
| texcoord2.u<br />
| rowspan="2" | Texture coordinates for texture 2<br />
|-<br />
| 0x17<br />
| texcoord2.v<br />
<br />
|-<br />
| 0x1F<br />
| Unused component<br />
| Should be set for unused components of the output register<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Early depth function<br />
|}<br />
<br />
This register configures the early depth test function.<br />
<br />
Early depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| >=<br />
|-<br />
| 1<br />
| ><br />
|-<br />
| 2<br />
| <=<br />
|-<br />
| 3<br />
| <<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether the early depth test is enabled.<br />
<br />
=== GPUREG_EARLYDEPTH_CLEAR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = clear)<br />
|}<br />
<br />
This register triggers clearing the early depth data.<br />
<br />
=== GPUREG_SH_OUTATTR_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Use texture coordinates (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register is used to configure the shader output attribute mode.<br />
<br />
=== GPUREG_SCISSORTEST_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Enabled (0 = disabled, 3 = enabled)<br />
|}<br />
<br />
This register is used to enable scissor testing.<br />
<br />
=== GPUREG_SCISSORTEST_POS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X1<br />
|-<br />
| 16-25<br />
| unsigned, Y1<br />
|}<br />
<br />
This register is used to configure the scissor test start position.<br />
<br />
=== GPUREG_SCISSORTEST_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X2<br />
|-<br />
| 16-25<br />
| unsigned, Y2<br />
|}<br />
<br />
This register is used to configure the scissor test end position.<br />
<br />
=== GPUREG_VIEWPORT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| signed, X<br />
|-<br />
| 16-25<br />
| signed, Y<br />
|}<br />
<br />
This register is used to configure the viewport position.<br />
<br />
=== GPUREG_EARLYDEPTH_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| unsigned, Clear value<br />
|}<br />
<br />
This register is used to configure the early depth clear value.<br />
<br />
=== GPUREG_DEPTHMAP_ENABLE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable depth range.<br />
<br />
=== GPUREG_RENDERBUF_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register is used to configure the output framebuffer dimensions.<br />
<br />
=== GPUREG_SH_OUTATTR_CLOCK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, 'position.z' present (0 = absent, 1 = present)<br />
|-<br />
| 1<br />
| unsigned, 'color' component present (0 = absent, 1 = present)<br />
|-<br />
| 8<br />
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)<br />
|-<br />
| 9<br />
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)<br />
|-<br />
| 10<br />
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)<br />
|-<br />
| 16<br />
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)<br />
|-<br />
| 24<br />
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)<br />
|}<br />
<br />
This register controls the clock supply to parts relating to certain attributes.<br />
<br />
== Texturing registers ==<br />
<br />
=== GPUREG_TEXUNIT_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| 0x0<br />
|-<br />
| 8-9<br />
| unsigned, Texture 3 coordinates<br />
|-<br />
| 10<br />
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| 0x1<br />
|-<br />
| 13<br />
| unsigned, Texture 2 coordinates<br />
|-<br />
| 16<br />
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)<br />
|-<br />
| 17-31<br />
| 0x0<br />
|}<br />
<br />
This register is used to enable texture units.<br />
<br />
Texture 3 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 0<br />
|-<br />
| 1<br />
| Texture 1<br />
|-<br />
| 2<br />
| Texture 2<br />
|}<br />
<br />
Texture 2 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 2<br />
|-<br />
| 1<br />
| Texture 1<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to set a texture unit's border color.<br />
<br />
=== GPUREG_TEXUNIT''i''_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Height<br />
|-<br />
| 16-26<br />
| unsigned, Width<br />
|}<br />
<br />
This register is used to set a texture unit's dimensions.<br />
<br />
=== GPUREG_TEXUNIT''i''_PARAM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, Magnification filter<br />
|-<br />
| 2<br />
| unsigned, Minification filter<br />
|-<br />
| 4-5<br />
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4<br />
|-<br />
| 8-10<br />
| unsigned, Wrap T<br />
|-<br />
| 12-14<br />
| unsigned, Wrap S<br />
|-<br />
| 16-17<br />
| 0x0<br />
|-<br />
| 20<br />
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)<br />
|-<br />
| 24<br />
| unsigned, Mipmap filter<br />
|-<br />
| 28-30<br />
| unsigned, Type (Texture 0 only)<br />
|}<br />
<br />
This register is used to set a texture unit's extra parameters.<br />
<br />
Filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|}<br />
<br />
Wrap values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to edge<br />
|-<br />
| 1<br />
| Clamp to border<br />
|-<br />
| 2<br />
| Repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|}<br />
<br />
Type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 2D<br />
|-<br />
| 1<br />
| Cube map<br />
|-<br />
| 2<br />
| Shadow 2D<br />
|-<br />
| 3<br />
| Projection<br />
|-<br />
| 4<br />
| Shadow cube<br />
|-<br />
| 5<br />
| Disabled<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_LOD ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.4.8, Bias<br />
|-<br />
| 16-19<br />
| unsigned, Max Level<br />
|-<br />
| 24-27<br />
| unsigned, Min Level<br />
|}<br />
<br />
This register is used to configure a texture unit's level of detail.<br />
<br />
=== GPUREG_TEXUNIT''i''_ADDR''i'' ===<br />
<br />
First ADDR register:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Texture physical address >> 3<br />
|}<br />
<br />
Subsequent ADDR registers:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-21<br />
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)<br />
|}<br />
<br />
This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.<br />
<br />
If the texture is a cube:<br />
<br />
{| class="wikitable" border="1"<br />
! Register<br />
! Description<br />
|-<br />
| ADDR1<br />
| Positive X<br />
|-<br />
| ADDR2<br />
| Negative X<br />
|-<br />
| ADDR3<br />
| Positive Y<br />
|-<br />
| ADDR4<br />
| Negative Y<br />
|-<br />
| ADDR5<br />
| Positive Z<br />
|-<br />
| ADDR6<br />
| Negative Z<br />
|}<br />
<br />
Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.<br />
<br />
=== GPUREG_TEXUNIT''i''_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Perspective (0 = perspective, 1 = not perspective)<br />
|-<br />
| 1-23<br />
| fixed0.0.24, Z bias (upper 23 bits)<br />
|}<br />
<br />
This register is used to set a texture unit's shadow texture properties.<br />
<br />
=== GPUREG_TEXUNIT''i''_TYPE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Format<br />
|}<br />
<br />
This register is used to set a texture unit's data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! GL Format<br />
! GL Data Type<br />
|-<br />
| 0x0<br />
| RGBA8888<br />
| GL_RGBA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x1<br />
| RGB888<br />
| GL_RGB<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x2<br />
| RGBA5551<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_5_5_5_1<br />
|-<br />
| 0x3<br />
| RGB565<br />
| GL_RGB<br />
| GL_UNSIGNED_SHORT_5_6_5<br />
|-<br />
| 0x4<br />
| RGBA4444<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_4_4_4_4<br />
|-<br />
| 0x5<br />
| IA8<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x6<br />
| HILO8<br />
| <br />
| <br />
|-<br />
| 0x7<br />
| I8<br />
| GL_LUMINANCE<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x8<br />
| A8<br />
| GL_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x9<br />
| IA44<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE_4_4_EXT<br />
|-<br />
| 0xA<br />
| I4<br />
| <br />
|<br />
|-<br />
| 0xB<br />
| A4<br />
| GL_ALPHA<br />
| GL_UNSIGNED_NIBBLE_EXT<br />
|-<br />
| 0xC<br />
| ETC1<br />
| GL_ETC1_RGB8_OES<br />
| <br />
|-<br />
| 0xD<br />
| ETC1A4<br />
|<br />
| <br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable lighting.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, U-direction clamp<br />
|-<br />
| 3-5<br />
| unsigned, V-direction clamp<br />
|-<br />
| 6-9<br />
| unsigned, RGB mapping function<br />
|-<br />
| 10-13<br />
| unsigned, Alpha mapping function<br />
|-<br />
| 14<br />
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)<br />
|-<br />
| 15<br />
| unsigned, Noise enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 16-17<br />
| unsigned, U-direction shift<br />
|-<br />
| 18-19<br />
| unsigned, V-direction shift<br />
|-<br />
| 20-27<br />
| float1.5.10, Texture bias (lower 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Clamp values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to zero<br />
|-<br />
| 1<br />
| Clamp to edge<br />
|-<br />
| 2<br />
| Symmetrical repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|-<br />
| 4<br />
| Pulse<br />
|}<br />
<br />
Mapping function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| U<br />
|-<br />
| 1<br />
| U²<br />
|-<br />
| 2<br />
| V<br />
|-<br />
| 3<br />
| V²<br />
|-<br />
| 4<br />
| (U + V) / 2<br />
|-<br />
| 5<br />
| (U² + V²) / 2<br />
|-<br />
| 6<br />
| sqrt(U² + V²)<br />
|-<br />
| 7<br />
| Minimum<br />
|-<br />
| 8<br />
| Maximum<br />
|-<br />
| 9<br />
| Rmax<br />
|}<br />
<br />
Shift values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Odd<br />
|-<br />
| 2<br />
| Even<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, U-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, U-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, V-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX3 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, U-direction noise frequency<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise frequency<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX4 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Minification filter<br />
|-<br />
| 3-10<br />
| 0x60<br />
|-<br />
| 11-18<br />
| unsigned, Texture width<br />
|-<br />
| 19-26<br />
| float1.5.10, Texture bias (upper 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Minification filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|-<br />
| 2<br />
| Nearest, Mipmap Nearest<br />
|-<br />
| 3<br />
| Linear, Mipmap Nearest<br />
|-<br />
| 4<br />
| Nearest, Mipmap Linear<br />
|-<br />
| 5<br />
| Linear, Mipmap Linear<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX5 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Texture offset<br />
|-<br />
| 8-31<br />
| 0xE0C080<br />
|}<br />
<br />
This register is used to set the procedural texture unit's offset.<br />
<br />
=== GPUREG_PROCTEX_LUT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Index<br />
|-<br />
| 8-11<br />
| unsigned, Reference table<br />
|}<br />
<br />
This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.<br />
<br />
Reference table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Noise table<br />
|-<br />
| 2<br />
| RGB mapping function table<br />
|-<br />
| 3<br />
| Alpha mapping function table<br />
|-<br />
| 4<br />
| Color table<br />
|-<br />
| 5<br />
| Color difference table<br />
|}<br />
<br />
=== GPUREG_PROCTEX_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.<br />
<br />
==== Noise Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== RGB Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Alpha Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Color Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
==== Color Difference Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| fixed1.0.7, Red difference between current and next color table elements<br />
|-<br />
| 8-15<br />
| fixed1.0.7, Green difference between current and next color table elements<br />
|-<br />
| 16-23<br />
| fixed1.0.7, Blue difference between current and next color table elements<br />
|-<br />
| 24-31<br />
| fixed1.0.7, Alpha difference between current and next color table elements<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_SOURCE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB source 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB source 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB source 2<br />
|-<br />
| 16-19<br />
| unsigned, Alpha source 0<br />
|-<br />
| 20-23<br />
| unsigned, Alpha source 1<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source 2<br />
|}<br />
<br />
This register configures a texture combiner's sources.<br />
<br />
Source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Primary color<br />
|-<br />
| 1<br />
| Fragment primary color<br />
|-<br />
| 2<br />
| Fragment secondary color<br />
|-<br />
| 3<br />
| Texture 0<br />
|-<br />
| 4<br />
| Texture 1<br />
|-<br />
| 5<br />
| Texture 2<br />
|-<br />
| 6<br />
| Texture 3<br />
|-<br />
| 13<br />
| Previous buffer<br />
|-<br />
| 14<br />
| Constant (from GPUREG_TEXENV''i''_COLOR)<br />
|-<br />
| 15<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_OPERAND ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB operand 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB operand 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB operand 2<br />
|-<br />
| 12-14<br />
| unsigned, Alpha operand 0<br />
|-<br />
| 16-18<br />
| unsigned, Alpha operand 1<br />
|-<br />
| 20-22<br />
| unsigned, Alpha operand 2<br />
|}<br />
<br />
This register configures a texture combiner's operands.<br />
<br />
RGB operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source color<br />
|-<br />
| 1<br />
| One minus source color<br />
|-<br />
| 2<br />
| Source alpha<br />
|-<br />
| 3<br />
| One minus source alpha<br />
|-<br />
| 4<br />
| Source red<br />
|-<br />
| 5<br />
| One minus source red<br />
|-<br />
| 8<br />
| Source green<br />
|-<br />
| 9<br />
| One minus source green<br />
|-<br />
| 12<br />
| Source blue<br />
|-<br />
| 13<br />
| One minus source blue<br />
|}<br />
<br />
Alpha operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source alpha<br />
|-<br />
| 1<br />
| One minus source alpha<br />
|-<br />
| 2<br />
| Source red<br />
|-<br />
| 3<br />
| One minus source red<br />
|-<br />
| 4<br />
| Source green<br />
|-<br />
| 5<br />
| One minus source green<br />
|-<br />
| 6<br />
| Source blue<br />
|-<br />
| 7<br />
| One minus source blue<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COMBINER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB combine<br />
|-<br />
| 16-19<br />
| unsigned, Alpha combine<br />
|}<br />
<br />
This register configures a texture combiner's combine mode.<br />
<br />
Combine values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Replace<br />
|-<br />
| 1<br />
| Modulate<br />
|-<br />
| 2<br />
| Add<br />
|-<br />
| 3<br />
| Add signed<br />
|-<br />
| 4<br />
| Interpolate<br />
|-<br />
| 5<br />
| Subtract<br />
|-<br />
| 6<br />
| Dot3 RGB<br />
|-<br />
| 7<br />
| Dot3 RGBA<br />
|-<br />
| 8<br />
| Multiply then add<br />
|-<br />
| 9<br />
| Add then multiply<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register configures a texture combiner's constant color.<br />
<br />
=== GPUREG_TEXENV''i''_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, RGB scale<br />
|-<br />
| 16-17<br />
| unsigned, Alpha scale<br />
|}<br />
<br />
This register configures a texture combiner's scale value.<br />
<br />
Scale values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|}<br />
<br />
=== GPUREG_TEXENV_UPDATE_BUFFER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fog mode<br />
|-<br />
| 3<br />
| unsigned, Shading density source<br />
|-<br />
| 8<br />
| unsigned, TexEnv 1 RGB buffer input<br />
|-<br />
| 9<br />
| unsigned, TexEnv 2 RGB buffer input<br />
|-<br />
| 10<br />
| unsigned, TexEnv 3 RGB buffer input<br />
|-<br />
| 11<br />
| unsigned, TexEnv 4 RGB buffer input<br />
|-<br />
| 12<br />
| unsigned, TexEnv 1 alpha buffer input<br />
|-<br />
| 13<br />
| unsigned, TexEnv 2 alpha buffer input<br />
|-<br />
| 14<br />
| unsigned, TexEnv 3 alpha buffer input<br />
|-<br />
| 15<br />
| unsigned, TexEnv 4 alpha buffer input<br />
|-<br />
| 16<br />
| unsigned, Z flip (0 = don't flip, 1 = flip)<br />
|-<br />
| 24-25<br />
| 0x0<br />
|}<br />
<br />
This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.<br />
<br />
Fog mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Disabled<br />
|-<br />
| 5<br />
| Fog<br />
|-<br />
| 7<br />
| Gas<br />
|}<br />
<br />
Shading density source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Plain density<br />
|-<br />
| 1<br />
| Depth density<br />
|}<br />
<br />
Buffer input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Previous buffer<br />
|-<br />
| 1<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_FOG_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
This register is used to configure the color of fog.<br />
<br />
=== GPUREG_GAS_ATTENUATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas density attenuation<br />
|}<br />
<br />
This register is used to configure the gas density attenuation.<br />
<br />
=== GPUREG_GAS_ACCMAX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas maximum density accumulation<br />
|}<br />
<br />
This register is used to configure the gas maximum density accumulation.<br />
<br />
=== GPUREG_FOG_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.<br />
<br />
=== GPUREG_FOG_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.<br />
<br />
==== Fog Look-Up Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Difference from next element <br />
|-<br />
| 13-23<br />
| fixed0.0.11, Value<br />
|}<br />
<br />
=== GPUREG_TEXENV_BUFFER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the texture combiner buffer color.<br />
<br />
== Framebuffer registers ==<br />
<br />
=== GPUREG_COLOR_OPERATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Fragment operation mode<br />
|-<br />
| 8<br />
| unsigned, Blend mode<br />
|-<br />
| 16-25<br />
| 0x0E4<br />
|}<br />
<br />
This register is used to configure the fragment operation mode and whether to use logic ops or blending.<br />
<br />
Fragment operation mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Default<br />
|-<br />
| 1<br />
| Gas<br />
|-<br />
| 3<br />
| Shadow<br />
|}<br />
<br />
Blend mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Logic op<br />
|-<br />
| 1<br />
| Blend<br />
|}<br />
<br />
=== GPUREG_BLEND_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, RGB equation<br />
|-<br />
| 8-10<br />
| unsigned, Alpha equation<br />
|-<br />
| 16-19<br />
| unsigned, RGB source function<br />
|-<br />
| 20-23<br />
| unsigned, RGB destination function<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source function<br />
|-<br />
| 28-31<br />
| unsigned, Alpha destination function<br />
|}<br />
<br />
This register is used to configure the blending function.<br />
<br />
Equation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Add<br />
|-<br />
| 1<br />
| Subtract<br />
|-<br />
| 2<br />
| Reverse subtract<br />
|-<br />
| 3<br />
| Minimum<br />
|-<br />
| 4<br />
| Maximum<br />
|}<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Zero<br />
|-<br />
| 1<br />
| One<br />
|-<br />
| 2<br />
| Source color<br />
|-<br />
| 3<br />
| One minus source color<br />
|-<br />
| 4<br />
| Destination color<br />
|-<br />
| 5<br />
| One minus destination color<br />
|-<br />
| 6<br />
| Source alpha<br />
|-<br />
| 7<br />
| One minus source alpha<br />
|-<br />
| 8<br />
| Destination alpha<br />
|-<br />
| 9<br />
| One minus destination alpha<br />
|-<br />
| 10<br />
| Constant color<br />
|-<br />
| 11<br />
| One minus constant color<br />
|-<br />
| 12<br />
| Constant alpha<br />
|-<br />
| 13<br />
| One minus constant alpha<br />
|-<br />
| 14<br />
| Source alpha saturate<br />
|}<br />
<br />
=== GPUREG_LOGIC_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Logic op<br />
|}<br />
<br />
This register is used to configure the logic op.<br />
<br />
Logic op values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clear<br />
|-<br />
| 1<br />
| AND<br />
|-<br />
| 2<br />
| Reverse AND<br />
|-<br />
| 3<br />
| Copy<br />
|-<br />
| 4<br />
| Set<br />
|-<br />
| 5<br />
| Inverted copy<br />
|-<br />
| 6<br />
| Noop<br />
|-<br />
| 7<br />
| Invert<br />
|-<br />
| 8<br />
| NAND<br />
|-<br />
| 9<br />
| OR<br />
|-<br />
| 10<br />
| NOR<br />
|-<br />
| 11<br />
| XOR<br />
|-<br />
| 12<br />
| Equivalent<br />
|-<br />
| 13<br />
| Inverted AND<br />
|-<br />
| 14<br />
| Reverse OR<br />
|-<br />
| 15<br />
| Inverted OR<br />
|}<br />
<br />
=== GPUREG_BLEND_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the blending color.<br />
<br />
=== GPUREG_FRAGOP_ALPHA_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Reference value<br />
|}<br />
<br />
This register is used to configure alpha testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Buffer mask<br />
|-<br />
| 16-23<br />
| signed, Reference value<br />
|-<br />
| 24-31<br />
| unsigned, Mask<br />
|}<br />
<br />
This register is used to configure stencil testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fail operation<br />
|-<br />
| 4-6<br />
| unsigned, Z-fail operation<br />
|-<br />
| 8-10<br />
| unsigned, Z-pass operation<br />
|}<br />
<br />
This register is used to configure stencil result operations.<br />
<br />
Operation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Keep<br />
|-<br />
| 1<br />
| Zero<br />
|-<br />
| 2<br />
| Replace<br />
|-<br />
| 3<br />
| Increment<br />
|-<br />
| 4<br />
| Decrement<br />
|-<br />
| 5<br />
| Invert<br />
|-<br />
| 6<br />
| Increment and wrap<br />
|-<br />
| 7<br />
| Decrement and wrap<br />
|}<br />
<br />
=== GPUREG_DEPTH_COLOR_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Depth function<br />
|-<br />
| 8<br />
| unsigned, Red write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 9<br />
| unsigned, Green write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 10<br />
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 11<br />
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to depth testing and framebuffer write masking.<br />
<br />
Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.<br />
<br />
Depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_FRAMEBUFFER_INVALIDATE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = invalidate)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.<br />
<br />
=== GPUREG_FRAMEBUFFER_FLUSH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = flush)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.<br />
<br />
=== GPUREG_COLORBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow read (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures read access from the color buffer.<br />
<br />
=== GPUREG_COLORBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow write (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures write access to the color buffer.<br />
<br />
=== GPUREG_DEPTHBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil read (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth read (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures read access from the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil write (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth write (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures write access to the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the depth buffer data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit depth<br />
|-<br />
| 2<br />
| 24-bit depth<br />
|-<br />
| 3<br />
| 24-bit depth + 8-bit stencil<br />
|}<br />
<br />
=== GPUREG_COLORBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Pixel size<br />
|-<br />
| 16-18<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.<br />
<br />
Pixel size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit color<br />
|-<br />
| 2<br />
| 32-bit color<br />
|}<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| RGBA8/Gas<br />
|-<br />
| 2<br />
| RGB5A1<br />
|-<br />
| 3<br />
| RGB565<br />
|-<br />
| 4<br />
| RGBA4<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register enables the early depth test.<br />
<br />
=== GPUREG_FRAMEBUFFER_BLOCK32 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Render block mode<br />
|}<br />
<br />
This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.<br />
<br />
Render block mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8x8 blocks<br />
|-<br />
| 1<br />
| 32x32 blocks<br />
|}<br />
<br />
=== GPUREG_DEPTHBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Depth buffer physical address >> 3<br />
|}<br />
<br />
This register configures the depth buffer physical address.<br />
<br />
=== GPUREG_COLORBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Color buffer physical address >> 3<br />
|}<br />
<br />
This register configures the color buffer physical address.<br />
<br />
=== GPUREG_FRAMEBUFFER_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register configures the framebuffer dimensions.<br />
<br />
=== GPUREG_GAS_LIGHT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Planar shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, Planar shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, Planar shading density attenuation<br />
|}<br />
<br />
This register configures gas light planar shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, View shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, View shading density attenuation<br />
|}<br />
<br />
This register configures gas light view shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading effect in line-of-sight direction<br />
|-<br />
| 8<br />
| Gas color LUT input<br />
|}<br />
<br />
This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.<br />
<br />
Color LUT input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Gas density<br />
|-<br />
| 1<br />
| Light factor<br />
|}<br />
<br />
=== GPUREG_GAS_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.<br />
<br />
=== GPUREG_GAS_LUT_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.<br />
<br />
==== Gas Look-Up Table ====<br />
<br />
16 elements:<br />
<br />
First 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| signed, Red<br />
|-<br />
| 8-15<br />
| signed, Green<br />
|-<br />
| 16-23<br />
| signed, Blue<br />
|}<br />
<br />
Last 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
=== GPUREG_GAS_DELTAZ_DEPTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| fixed0.16.8, Depth direction attenuation proportion<br />
|}<br />
<br />
This register is used to configure the gas depth direction attenuation proportion.<br />
<br />
=== GPUREG_FRAGOP_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Sum of penumbra scale and penumbra bias<br />
|-<br />
| 16-31<br />
| float1.5.10, Penumbra scale with reversed sign<br />
|}<br />
<br />
This register is used to configure shadow properties.<br />
<br />
== Fragment lighting registers ==<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR1 ===<br />
<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.<br />
<br />
=== GPUREG_LIGHT''i''_DIFFUSE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.<br />
<br />
=== GPUREG_LIGHT''i''_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.<br />
<br />
=== GPUREG_LIGHT''i''_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, X coordinate<br />
|-<br />
| 16-31<br />
| float1.5.10, Y coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Z coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, X coordinate (negated)<br />
|-<br />
| 16-28<br />
| fixed1.1.11, Y coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Z coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Light type (0 = positional light, 1 = directional light)<br />
|-<br />
| 1<br />
| unsigned, Two side diffuse (0 = one side, 1 = both sides)<br />
|-<br />
| 2<br />
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)<br />
|-<br />
| 3<br />
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures a light's properties.<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation bias<br />
|}<br />
<br />
These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation scale<br />
|}<br />
<br />
These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHTING_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.<br />
<br />
=== GPUREG_LIGHTING_NUM_LIGHTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of active lights - 1<br />
|}<br />
<br />
This register configures the number of active lights.<br />
<br />
=== GPUREG_LIGHTING_CONFIG0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)<br />
|-<br />
| 2-3<br />
| unsigned, Fresnel selector<br />
|-<br />
| 4-7<br />
| unsigned, Light environment configuration<br />
|-<br />
| 8-11<br />
| 0x4<br />
|-<br />
| 16<br />
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 17<br />
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 18<br />
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)<br />
|-<br />
| 19<br />
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)<br />
|-<br />
| 22-23<br />
| unsigned, Bump map texture unit<br />
|-<br />
| 24-25<br />
| unsigned, Shadow map texture unit<br />
|-<br />
| 27<br />
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)<br />
|-<br />
| 28-29<br />
| unsigned, Bump mode<br />
|-<br />
| 30<br />
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)<br />
|-<br />
| 31<br />
| 0x1<br />
|}<br />
<br />
This register configures the light environment.<br />
<br />
Fresnel selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Primary alpha<br />
|-<br />
| 2<br />
| Secondary alpha<br />
|-<br />
| 3<br />
| Primary and secondary alpha<br />
|}<br />
<br />
The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.<br />
<br />
Light environment configuration values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! Available LUTs<br />
|-<br />
| 0<br />
| Configuration 0<br />
| D0, RR, SP, DA<br />
|-<br />
| 1<br />
| Configuration 1<br />
| FR, RR, SP, DA<br />
|-<br />
| 2<br />
| Configuration 2<br />
| D0, D1, RR, DA<br />
|-<br />
| 3<br />
| Configuration 3<br />
| D0, D1, FR, DA<br />
|-<br />
| 4<br />
| Configuration 4<br />
| All except for FR<br />
|-<br />
| 5<br />
| Configuration 5<br />
| All except for D1<br />
|-<br />
| 6<br />
| Configuration 6<br />
| All except for RB and RG<br />
|-<br />
| 8<br />
| Configuration 7<br />
| All<br />
|}<br />
<br />
Bump mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Not used<br />
|-<br />
| 1<br />
| Use as bump map<br />
|-<br />
| 2<br />
| Use as tangent map<br />
|}<br />
<br />
=== GPUREG_LIGHTING_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 1<br />
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 2<br />
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 3<br />
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 4<br />
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 6<br />
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 7<br />
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 8<br />
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 10<br />
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 11<br />
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 12<br />
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 14<br />
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 15<br />
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 16<br />
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 18<br />
| 0x1<br />
|-<br />
| 19<br />
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 20-22<br />
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 21<br />
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 22<br />
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 24<br />
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 26<br />
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 27<br />
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 28<br />
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 29<br />
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 30<br />
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 31<br />
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is used to disable various aspects of the light environment.<br />
<br />
=== GPUREG_LIGHTING_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Starting index<br />
|-<br />
| 8-12<br />
| unsigned, Look-up table<br />
|}<br />
<br />
This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.<br />
<br />
Lookup table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| D0<br />
|-<br />
| 1<br />
| D1<br />
|-<br />
| 3<br />
| FR<br />
|-<br />
| 4<br />
| RB<br />
|-<br />
| 5<br />
| RG<br />
|-<br />
| 6<br />
| RR<br />
|-<br />
| 8-15<br />
| SP0-7<br />
|-<br />
| 16-23<br />
| DA0-7<br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.<br />
<br />
=== GPUREG_LIGHTING_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
Lighting LUT data is written here.<br />
<br />
A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.<br />
<br />
DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.<br />
<br />
Format of an entry:<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Entry value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_ABS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)<br />
|-<br />
| 21<br />
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register controls whether the absolute value of the input is taken before using a LUT.<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SELECT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Input selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Input selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Input selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Input selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Input selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Input selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Input selector for RR<br />
|}<br />
<br />
This register selects the input from LUTs.<br />
<br />
Input selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| N·H<br />
|-<br />
| 1<br />
| V·H<br />
|-<br />
| 2<br />
| N·V<br />
|-<br />
| 3<br />
| L·N<br />
|-<br />
| 4<br />
| -L·P (aka Spotlight aka SP)<br />
|-<br />
| 5<br />
| cos φ (aka CP)<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Scaler selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Scaler selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Scaler selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Scaler selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Scaler selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Scaler selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Scaler selector for RR<br />
|}<br />
<br />
This register controls the scaling that is applied to the output of a LUT.<br />
<br />
Scaler selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|-<br />
| 3<br />
| 8x<br />
|-<br />
| 6<br />
| 0.25x<br />
|-<br />
| 7<br />
| 0.5x<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, ID of the 1st enabled light<br />
|-<br />
| 4-6<br />
| unsigned, ID of the 2nd enabled light<br />
|-<br />
| 8-10<br />
| unsigned, ID of the 3rd enabled light<br />
|-<br />
| 12-14<br />
| unsigned, ID of the 4th enabled light<br />
|-<br />
| 16-18<br />
| unsigned, ID of the 5th enabled light<br />
|-<br />
| 20-22<br />
| unsigned, ID of the 6th enabled light<br />
|-<br />
| 24-26<br />
| unsigned, ID of the 7th enabled light<br />
|-<br />
| 28-30<br />
| unsigned, ID of the 8th enabled light<br />
|}<br />
<br />
This register sets the IDs of enabled light sources.<br />
<br />
== Geometry pipeline registers ==<br />
<br />
=== GPUREG_ATTRIBBUFFERS_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-28<br />
| unsigned, Vertex arrays base address<br />
|}<br />
<br />
This register sets the base address of all vertex arrays.<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 0 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 0 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 1 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 1 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 2 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 2 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 3 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 3 size<br />
|-<br />
| 16-17<br />
| unsigned, Vertex attribute 4 type<br />
|-<br />
| 18-19<br />
| unsigned, Vertex attribute 4 size<br />
|-<br />
| 20-21<br />
| unsigned, Vertex attribute 5 type<br />
|-<br />
| 22-23<br />
| unsigned, Vertex attribute 5 size<br />
|-<br />
| 24-25<br />
| unsigned, Vertex attribute 6 type<br />
|-<br />
| 26-27<br />
| unsigned, Vertex attribute 6 size<br />
|-<br />
| 28-29<br />
| unsigned, Vertex attribute 7 type<br />
|-<br />
| 30-31<br />
| unsigned, Vertex attribute 7 size<br />
|}<br />
<br />
This register configures the types and sizes of the first 8 vertex attributes.<br />
<br />
Vertex attribute type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Byte<br />
|-<br />
| 1<br />
| Unsigned byte<br />
|-<br />
| 2<br />
| Short<br />
|-<br />
| 3<br />
| Float<br />
|}<br />
<br />
Vertex attribute size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8 bits<br />
|-<br />
| 1<br />
| 16 bits<br />
|-<br />
| 2<br />
| 24 bits<br />
|-<br />
| 3<br />
| 32 bits<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 8 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 8 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 9 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 9 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 10 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 10 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 11 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 11 size<br />
|-<br />
| 16-27<br />
| unsigned, Fixed vertex attribute mask<br />
|-<br />
| 28-31<br />
| unsigned, Total vertex attribute count - 1<br />
|}<br />
<br />
This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.<br />
<br />
See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|}<br />
<br />
This register configures the offset of a vertex array from the base vertex arrays address.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 1<br />
|-<br />
| 4-7<br />
| unsigned, Component 2<br />
|-<br />
| 8-11<br />
| unsigned, Component 3<br />
|-<br />
| 12-15<br />
| unsigned, Component 4<br />
|-<br />
| 16-19<br />
| unsigned, Component 5<br />
|-<br />
| 20-23<br />
| unsigned, Component 6<br />
|-<br />
| 24-27<br />
| unsigned, Component 7<br />
|-<br />
| 28-31<br />
| unsigned, Component 8<br />
|}<br />
<br />
This register configures the first 8 component types of a vertex array.<br />
<br />
Component values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Vertex attribute 0<br />
|-<br />
| 1<br />
| Vertex attribute 1<br />
|-<br />
| 2<br />
| Vertex attribute 2<br />
|-<br />
| 3<br />
| Vertex attribute 3<br />
|-<br />
| 4<br />
| Vertex attribute 4<br />
|-<br />
| 5<br />
| Vertex attribute 5<br />
|-<br />
| 6<br />
| Vertex attribute 6<br />
|-<br />
| 7<br />
| Vertex attribute 7<br />
|-<br />
| 8<br />
| Vertex attribute 8<br />
|-<br />
| 9<br />
| Vertex attribute 9<br />
|-<br />
| 10<br />
| Vertex attribute 10<br />
|-<br />
| 11<br />
| Vertex attribute 11<br />
|-<br />
| 12<br />
| 4-byte padding<br />
|-<br />
| 13<br />
| 8-byte padding<br />
|-<br />
| 14<br />
| 12-byte padding<br />
|-<br />
| 15<br />
| 16-byte padding<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 9<br />
|-<br />
| 4-7<br />
| unsigned, Component 10<br />
|-<br />
| 8-11<br />
| unsigned, Component 11<br />
|-<br />
| 12-15<br />
| unsigned, Component 12<br />
|-<br />
| 16-23<br />
| unsigned, Bytes per vertex<br />
|-<br />
| 28-31<br />
| unsigned, Total number of components<br />
|}<br />
<br />
This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.<br />
<br />
See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.<br />
<br />
=== GPUREG_INDEXBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|-<br />
| 31<br />
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)<br />
|}<br />
<br />
This register configures the index array used when drawing elements.<br />
<br />
=== GPUREG_NUMVERTICES ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Number of vertices to render<br />
|}<br />
<br />
This register sets the number of vertices to render.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|-<br />
| 9<br />
| 0x0<br />
|-<br />
| 31<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_VERTEX_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Starting vertex offset<br />
|}<br />
<br />
This register sets the offset of the first vertex in an array to render.<br />
<br />
=== GPUREG_POST_VERTEX_CACHE_NUM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)<br />
|}<br />
<br />
This register configures the post-vertex cache.<br />
<br />
=== GPUREG_DRAWARRAYS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw arrays)<br />
|}<br />
<br />
This register triggers drawing vertex arrays.<br />
<br />
=== GPUREG_DRAWELEMENTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw elements)<br />
|}<br />
<br />
This register triggers drawing vertex array elements.<br />
<br />
=== GPUREG_VTX_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)<br />
|}<br />
<br />
This register triggers clearing the post-vertex cache.<br />
<br />
=== GPUREG_FIXEDATTRIB_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)<br />
|}<br />
<br />
This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.<br />
<br />
=== GPUREG_FIXEDATTRIB_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| colspan="2" | '''DATA0:'''<br />
|-<br />
| 0-7<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)<br />
|-<br />
| 8-31<br />
| float1.7.16, Vertex attribute element 4 (W)<br />
|-<br />
| colspan="2" | '''DATA1:'''<br />
|-<br />
| 0-15<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)<br />
|-<br />
| 16-31<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)<br />
|-<br />
| colspan="2" | '''DATA2:'''<br />
|-<br />
| 0-23<br />
| float1.7.16, Vertex attribute element 1 (X)<br />
|-<br />
| 24-31<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)<br />
|}<br />
<br />
Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.<br />
<br />
=== GPUREG_CMDBUF_SIZE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the size of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_SIZE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the size of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the physical address of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the physical address of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)<br />
|}<br />
<br />
This register triggers a jump to the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)<br />
|}<br />
<br />
This register triggers a jump to the second command buffer.<br />
<br />
=== GPUREG_VSH_NUM_ATTR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader input attributes - 1<br />
|}<br />
<br />
This register sets the number of vertex shader input attributes.<br />
<br />
=== GPUREG_VSH_COM_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.<br />
<br />
=== GPUREG_START_DRAW_FUNC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Mode (0 = drawing, 1 = configuration)<br />
|-<br />
| 1-7<br />
| 0x0<br />
|}<br />
<br />
This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_GSH_MISC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)<br />
|}<br />
<br />
This register configures miscellaneous geometry shader properties.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_GSH_MISC1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)<br />
|}<br />
<br />
This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.<br />
<br />
=== GPUREG_PRIMITIVE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|-<br />
| 8-9<br />
| unsigned, Primitive mode<br />
|}<br />
<br />
This register configures primitive drawing.<br />
<br />
Primitive mode value:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Triangles<br />
|-<br />
| 1<br />
| Triangle strip<br />
|-<br />
| 2<br />
| Triangle fan<br />
|-<br />
| 3<br />
| Geometry primitive<br />
|}<br />
<br />
=== GPUREG_RESTART_PRIMITIVE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = reset primitive)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
This register triggers resetting primitive drawing.<br />
<br />
== Shader registers ==<br />
<br />
=== GPUREG_''SH''_BOOLUNIFORM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Boolean register b0 value (0 = false, 1 = true)<br />
|-<br />
| 1<br />
| unsigned, Boolean register b1 value (0 = false, 1 = true)<br />
|-<br />
| 2<br />
| unsigned, Boolean register b2 value (0 = false, 1 = true)<br />
|-<br />
| 3<br />
| unsigned, Boolean register b3 value (0 = false, 1 = true)<br />
|-<br />
| 4<br />
| unsigned, Boolean register b4 value (0 = false, 1 = true)<br />
|-<br />
| 5<br />
| unsigned, Boolean register b5 value (0 = false, 1 = true)<br />
|-<br />
| 6<br />
| unsigned, Boolean register b6 value (0 = false, 1 = true)<br />
|-<br />
| 7<br />
| unsigned, Boolean register b7 value (0 = false, 1 = true)<br />
|-<br />
| 8<br />
| unsigned, Boolean register b8 value (0 = false, 1 = true)<br />
|-<br />
| 9<br />
| unsigned, Boolean register b9 value (0 = false, 1 = true)<br />
|-<br />
| 10<br />
| unsigned, Boolean register b10 value (0 = false, 1 = true)<br />
|-<br />
| 11<br />
| unsigned, Boolean register b11 value (0 = false, 1 = true)<br />
|-<br />
| 12<br />
| unsigned, Boolean register b12 value (0 = false, 1 = true)<br />
|-<br />
| 13<br />
| unsigned, Boolean register b13 value (0 = false, 1 = true)<br />
|-<br />
| 14<br />
| unsigned, Boolean register b14 value (0 = false, 1 = true)<br />
|-<br />
| 15<br />
| unsigned, Boolean register b15 value (0 = false, 1 = true)<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register is used to set a shader unit's boolean registers.<br />
<br />
=== GPUREG_''SH''_INTUNIFORM_I''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Integer register i''i'' X value<br />
|-<br />
| 8-15<br />
| unsigned, Integer register i''i'' Y value<br />
|-<br />
| 16-23<br />
| unsigned, Integer register i''i'' Z value<br />
|-<br />
| 24-31<br />
| unsigned, Integer register i''i'' W value<br />
|}<br />
<br />
These registers are used to set a shader unit's integer registers.<br />
<br />
=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Input vertex attributes - 1<br />
|-<br />
| 8-15<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)<br />
|-<br />
| 16-23<br />
| 0x0<br />
|-<br />
| 24-31<br />
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)<br />
|}<br />
<br />
This register is used to configure a shader unit's input buffer.<br />
<br />
=== GPUREG_''SH''_ENTRYPOINT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Code entry point offset, in 32-bit words<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register sets a shader unit's code entry point.<br />
<br />
For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.<br />
<br />
For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them. <br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 0 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 1 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 2 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 3 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 4 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 5 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 6 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 7 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.<br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 8 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 9 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 10 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 11 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 12 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 13 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 14 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 15 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.<br />
<br />
=== GPUREG_''SH''_OUTMAP_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4<br />
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 5<br />
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 6<br />
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 7<br />
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 8<br />
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 9<br />
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 10<br />
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 11<br />
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 12<br />
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 13<br />
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 14<br />
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 15<br />
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 16-31<br />
| 0x0<br />
|}<br />
<br />
This register toggles a shader unit's output registers.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_END ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Signal transfer end (0 = idle, non-zero = signal)<br />
|}<br />
<br />
This register's value should be set to 1 in order to finalize the transfer of shader code.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)<br />
|-<br />
| 31<br />
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)<br />
|}<br />
<br />
This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| Floating-point register component data<br />
|}<br />
<br />
This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].<br />
<br />
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:<br />
** first word : ZZWWWWWW<br />
** second word : YYYYZZZZ<br />
** third word : XXXXXXYY<br />
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader code offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader instruction data<br />
|}<br />
<br />
This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.<br />
<br />
=== GPUREG_''SH''_OPDESCS_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader operand descriptor offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_OPDESCS_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader operand descriptor data<br />
|}<br />
<br />
This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=GPU/Internal_Registers&diff=19808
GPU/Internal Registers
2017-04-08T10:46:59Z
<p>Plutooo: testing</p>
<hr />
<div>[[Category:GPU]]<br />
<br />
== Overview ==<br />
GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.<br />
<br />
Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).<br />
<br />
In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.<br />
<br />
For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).<br />
<br />
Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.<br />
<br />
The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.<br />
<br />
=== Command Header ===<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0-15<br />
| Command ID<br />
|-<br />
| 16-19<br />
| Parameter mask<br />
|-<br />
| 20-30<br />
| Number of extra parameters (may be zero)<br />
|-<br />
| 31<br />
| Consecutive writing mode<br />
|}<br />
<br />
=== Parameter masking ===<br />
<br />
Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.<br />
<br />
=== Types ===<br />
<br />
There are three main types of registers :<br />
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])<br />
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])<br />
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])<br />
<br />
=== Aliases ===<br />
<br />
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]<br />
<br />
=== Data Types ===<br />
<br />
{| class="wikitable" border="1"<br />
! Name<br />
! Description<br />
|-<br />
| signed<br />
| Signed integer<br />
|-<br />
| unsigned<br />
| Unsigned integer<br />
|-<br />
| floatX.Y.Z<br />
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits<br />
|-<br />
| fixedX.Y.Z<br />
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits<br />
|}<br />
<br />
== Register list ==<br />
<br />
=== Miscellaneous registers (0x000-0x03F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0000<br />
| [[#GPUREG_0000|GPUREG_0000]]<br />
| <br />
|<br />
|-<br />
| 0001<br />
| [[#GPUREG_0001|GPUREG_0001]]<br />
| <br />
|<br />
|-<br />
| 0002<br />
| [[#GPUREG_0002|GPUREG_0002]]<br />
| <br />
|<br />
|-<br />
| 0003<br />
| [[#GPUREG_0003|GPUREG_0003]]<br />
| <br />
|<br />
|-<br />
| 0004<br />
| [[#GPUREG_0004|GPUREG_0004]]<br />
| <br />
|<br />
|-<br />
| 0005<br />
| [[#GPUREG_0005|GPUREG_0005]]<br />
| <br />
|<br />
|-<br />
| 0006<br />
| [[#GPUREG_0006|GPUREG_0006]]<br />
| <br />
|<br />
|-<br />
| 0007<br />
| [[#GPUREG_0007|GPUREG_0007]]<br />
| <br />
|<br />
|-<br />
| 0008<br />
| [[#GPUREG_0008|GPUREG_0008]]<br />
| <br />
|<br />
|-<br />
| 0009<br />
| [[#GPUREG_0009|GPUREG_0009]]<br />
| <br />
|<br />
|-<br />
| 000A<br />
| [[#GPUREG_000A|GPUREG_000A]]<br />
| <br />
|<br />
|-<br />
| 000B<br />
| [[#GPUREG_000B|GPUREG_000B]]<br />
| <br />
|<br />
|-<br />
| 000C<br />
| [[#GPUREG_000C|GPUREG_000C]]<br />
| <br />
|<br />
|-<br />
| 000D<br />
| [[#GPUREG_000D|GPUREG_000D]]<br />
| <br />
|<br />
|-<br />
| 000E<br />
| [[#GPUREG_000E|GPUREG_000E]]<br />
| <br />
|<br />
|-<br />
| 000F<br />
| [[#GPUREG_000F|GPUREG_000F]]<br />
| <br />
|<br />
|-<br />
| 0010<br />
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]<br />
| <br />
|PICA_REG_INTERRUPT<br />
|-<br />
| 0011<br />
| [[#GPUREG_0011|GPUREG_0011]]<br />
| <br />
|<br />
|-<br />
| 0012<br />
| [[#GPUREG_0012|GPUREG_0012]]<br />
| <br />
|<br />
|-<br />
| 0013<br />
| [[#GPUREG_0013|GPUREG_0013]]<br />
| <br />
|<br />
|-<br />
| 0014<br />
| [[#GPUREG_0014|GPUREG_0014]]<br />
| <br />
|<br />
|-<br />
| 0015<br />
| [[#GPUREG_0015|GPUREG_0015]]<br />
| <br />
|<br />
|-<br />
| 0016<br />
| [[#GPUREG_0016|GPUREG_0016]]<br />
| <br />
|<br />
|-<br />
| 0017<br />
| [[#GPUREG_0017|GPUREG_0017]]<br />
| <br />
|<br />
|-<br />
| 0018<br />
| [[#GPUREG_0018|GPUREG_0018]]<br />
| <br />
|<br />
|-<br />
| 0019<br />
| [[#GPUREG_0019|GPUREG_0019]]<br />
| <br />
|<br />
|-<br />
| 001A<br />
| [[#GPUREG_001A|GPUREG_001A]]<br />
| <br />
|<br />
|-<br />
| 001B<br />
| [[#GPUREG_001B|GPUREG_001B]]<br />
| <br />
|<br />
|-<br />
| 001C<br />
| [[#GPUREG_001C|GPUREG_001C]]<br />
| <br />
|<br />
|-<br />
| 001D<br />
| [[#GPUREG_001D|GPUREG_001D]]<br />
| <br />
|<br />
|-<br />
| 001E<br />
| [[#GPUREG_001E|GPUREG_001E]]<br />
| <br />
|<br />
|-<br />
| 001F<br />
| [[#GPUREG_001F|GPUREG_001F]]<br />
| <br />
|<br />
|-<br />
| 0020<br />
| [[#GPUREG_0020|GPUREG_0020]]<br />
| <br />
|<br />
|-<br />
| 0021<br />
| [[#GPUREG_0021|GPUREG_0021]]<br />
| <br />
|<br />
|-<br />
| 0022<br />
| [[#GPUREG_0022|GPUREG_0022]]<br />
| <br />
|<br />
|-<br />
| 0023<br />
| [[#GPUREG_0023|GPUREG_0023]]<br />
| <br />
|<br />
|-<br />
| 0024<br />
| [[#GPUREG_0024|GPUREG_0024]]<br />
| <br />
|<br />
|-<br />
| 0025<br />
| [[#GPUREG_0025|GPUREG_0025]]<br />
| <br />
|<br />
|-<br />
| 0026<br />
| [[#GPUREG_0026|GPUREG_0026]]<br />
| <br />
|<br />
|-<br />
| 0027<br />
| [[#GPUREG_0027|GPUREG_0027]]<br />
| <br />
|<br />
|-<br />
| 0028<br />
| [[#GPUREG_0028|GPUREG_0028]]<br />
| <br />
|<br />
|-<br />
| 0029<br />
| [[#GPUREG_0029|GPUREG_0029]]<br />
| <br />
|<br />
|-<br />
| 002A<br />
| [[#GPUREG_002A|GPUREG_002A]]<br />
| <br />
|<br />
|-<br />
| 002B<br />
| [[#GPUREG_002B|GPUREG_002B]]<br />
| <br />
|<br />
|-<br />
| 002C<br />
| [[#GPUREG_002C|GPUREG_002C]]<br />
| <br />
|<br />
|-<br />
| 002D<br />
| [[#GPUREG_002D|GPUREG_002D]]<br />
| <br />
|<br />
|-<br />
| 002E<br />
| [[#GPUREG_002E|GPUREG_002E]]<br />
| <br />
|<br />
|-<br />
| 002F<br />
| [[#GPUREG_002F|GPUREG_002F]]<br />
| <br />
|<br />
|-<br />
| 0030<br />
| [[#GPUREG_0030|GPUREG_0030]]<br />
| <br />
|<br />
|-<br />
| 0031<br />
| [[#GPUREG_0031|GPUREG_0031]]<br />
| <br />
|<br />
|-<br />
| 0032<br />
| [[#GPUREG_0032|GPUREG_0032]]<br />
| <br />
|<br />
|-<br />
| 0033<br />
| [[#GPUREG_0033|GPUREG_0033]]<br />
| <br />
|<br />
|-<br />
| 0034<br />
| [[#GPUREG_0034|GPUREG_0034]]<br />
| <br />
|<br />
|-<br />
| 0035<br />
| [[#GPUREG_0035|GPUREG_0035]]<br />
| <br />
|<br />
|-<br />
| 0036<br />
| [[#GPUREG_0036|GPUREG_0036]]<br />
| <br />
|<br />
|-<br />
| 0037<br />
| [[#GPUREG_0037|GPUREG_0037]]<br />
| <br />
|<br />
|-<br />
| 0038<br />
| [[#GPUREG_0038|GPUREG_0038]]<br />
| <br />
|<br />
|-<br />
| 0039<br />
| [[#GPUREG_0039|GPUREG_0039]]<br />
| <br />
|<br />
|-<br />
| 003A<br />
| [[#GPUREG_003A|GPUREG_003A]]<br />
| <br />
|<br />
|-<br />
| 003B<br />
| [[#GPUREG_003B|GPUREG_003B]]<br />
| <br />
|<br />
|-<br />
| 003C<br />
| [[#GPUREG_003C|GPUREG_003C]]<br />
| <br />
|<br />
|-<br />
| 003D<br />
| [[#GPUREG_003D|GPUREG_003D]]<br />
| <br />
|<br />
|-<br />
| 003E<br />
| [[#GPUREG_003E|GPUREG_003E]]<br />
| <br />
|<br />
|-<br />
| 003F<br />
| [[#GPUREG_003F|GPUREG_003F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Rasterizer registers (0x040-0x07F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0040<br />
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]<br />
| <br />
|PICA_REG_CULL_FACE<br />
|-<br />
| 0041<br />
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH1<br />
|-<br />
| 0042<br />
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH2<br />
|-<br />
| 0043<br />
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT1<br />
|-<br />
| 0044<br />
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT2<br />
|-<br />
| 0045<br />
| [[#GPUREG_0045|GPUREG_0045]]<br />
| <br />
|<br />
|-<br />
| 0046<br />
| [[#GPUREG_0046|GPUREG_0046]]<br />
| <br />
|<br />
|-<br />
| 0047<br />
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP<br />
|-<br />
| 0048<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]<br />
|? <br />
|PICA_REG_FRAGOP_CLIP_DATA1<br />
|-<br />
| 0049<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA2<br />
|-<br />
| 004A<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA3<br />
|-<br />
| 004B<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA4<br />
|-<br />
| 004C<br />
| [[#GPUREG_004C|GPUREG_004C]]<br />
| <br />
|<br />
|-<br />
| 004D<br />
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA1<br />
|-<br />
| 004E<br />
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA2<br />
|-<br />
| 004F<br />
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]<br />
| <br />
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0<br />
|-<br />
| 0050<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0<br />
|-<br />
| 0051<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1<br />
|-<br />
| 0052<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2<br />
|-<br />
| 0053<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3<br />
|-<br />
| 0054<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4<br />
|-<br />
| 0055<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5<br />
|-<br />
| 0056<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6<br />
|-<br />
| 0057<br />
| [[#GPUREG_0057|GPUREG_0057]]<br />
| <br />
|<br />
|-<br />
| 0058<br />
| [[#GPUREG_0058|GPUREG_0058]]<br />
| <br />
|<br />
|-<br />
| 0059<br />
| [[#GPUREG_0059|GPUREG_0059]]<br />
| <br />
|<br />
|-<br />
| 005A<br />
| [[#GPUREG_005A|GPUREG_005A]]<br />
| <br />
|<br />
|-<br />
| 005B<br />
| [[#GPUREG_005B|GPUREG_005B]]<br />
| <br />
|<br />
|-<br />
| 005C<br />
| [[#GPUREG_005C|GPUREG_005C]]<br />
| <br />
|<br />
|-<br />
| 005D<br />
| [[#GPUREG_005D|GPUREG_005D]]<br />
| <br />
|<br />
|-<br />
| 005E<br />
| [[#GPUREG_005E|GPUREG_005E]]<br />
| <br />
|<br />
|-<br />
| 005F<br />
| [[#GPUREG_005F|GPUREG_005F]]<br />
| <br />
|<br />
|-<br />
| 0060<br />
| [[#GPUREG_0060|GPUREG_0060]]<br />
| <br />
|<br />
|-<br />
| 0061<br />
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_FUNC<br />
|-<br />
| 0062<br />
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST1<br />
|-<br />
| 0063<br />
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]<br />
| <br />
|PICA_REG_EARLY_DEPTH_CLEAR<br />
|-<br />
| 0064<br />
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE<br />
|-<br />
| 0065<br />
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]<br />
| <br />
|PICA_REG_SCISSOR<br />
|-<br />
| 0066<br />
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]<br />
| <br />
|PICA_REG_SCISSOR_XY<br />
|-<br />
| 0067<br />
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]<br />
| <br />
|PICA_REG_SCISSOR_SIZE<br />
|-<br />
| 0068<br />
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]<br />
|<br />
|PICA_REG_VIEWPORT_XY<br />
|-<br />
| 0069<br />
| [[#GPUREG_0069|GPUREG_0069]]<br />
| <br />
|<br />
|-<br />
| 006A<br />
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]<br />
|<br />
|PICA_REG_EARLY_DEPTH_DATA<br />
|-<br />
| 006B<br />
| [[#GPUREG_006B|GPUREG_006B]]<br />
| <br />
|<br />
|-<br />
| 006C<br />
| [[#GPUREG_006C|GPUREG_006C]]<br />
| <br />
|<br />
|-<br />
| 006D<br />
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]<br />
|?<br />
|PICA_REG_FRAGOP_WSCALE<br />
|-<br />
| 006E<br />
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]<br />
|?<br />
|PICA_REG_RENDER_BUF_RESOLUTION1<br />
|-<br />
| 006F<br />
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK<br />
|-<br />
| 0070<br />
| [[#GPUREG_0070|GPUREG_0070]]<br />
| <br />
|<br />
|-<br />
| 0071<br />
| [[#GPUREG_0071|GPUREG_0071]]<br />
| <br />
|<br />
|-<br />
| 0072<br />
| [[#GPUREG_0072|GPUREG_0072]]<br />
| <br />
|<br />
|-<br />
| 0073<br />
| [[#GPUREG_0073|GPUREG_0073]]<br />
| <br />
|<br />
|-<br />
| 0074<br />
| [[#GPUREG_0074|GPUREG_0074]]<br />
| <br />
|<br />
|-<br />
| 0075<br />
| [[#GPUREG_0075|GPUREG_0075]]<br />
| <br />
|<br />
|-<br />
| 0076<br />
| [[#GPUREG_0076|GPUREG_0076]]<br />
| <br />
|<br />
|-<br />
| 0077<br />
| [[#GPUREG_0077|GPUREG_0077]]<br />
| <br />
|<br />
|-<br />
| 0078<br />
| [[#GPUREG_0078|GPUREG_0078]]<br />
| <br />
|<br />
|-<br />
| 0079<br />
| [[#GPUREG_0079|GPUREG_0079]]<br />
| <br />
|<br />
|-<br />
| 007A<br />
| [[#GPUREG_007A|GPUREG_007A]]<br />
| <br />
|<br />
|-<br />
| 007B<br />
| [[#GPUREG_007B|GPUREG_007B]]<br />
| <br />
|<br />
|-<br />
| 007C<br />
| [[#GPUREG_007C|GPUREG_007C]]<br />
| <br />
|<br />
|-<br />
| 007D<br />
| [[#GPUREG_007D|GPUREG_007D]]<br />
| <br />
|<br />
|-<br />
| 007E<br />
| [[#GPUREG_007E|GPUREG_007E]]<br />
| <br />
|<br />
|-<br />
| 007F<br />
| [[#GPUREG_007F|GPUREG_007F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Texturing registers (0x080-0x0FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0080<br />
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]<br />
|<br />
|PICA_REG_TEXTURE_FUNC<br />
|-<br />
| 0081<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE0_BORDER_COLOR<br />
|-<br />
| 0082<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]<br />
|<br />
|PICA_REG_TEXTURE0_SIZE<br />
|-<br />
| 0083<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE0_WRAP_FILTER<br />
|-<br />
| 0084<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE0_LOD<br />
|-<br />
| 0085<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR1<br />
|-<br />
| 0086<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR2<br />
|-<br />
| 0087<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR3<br />
|-<br />
| 0088<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR4<br />
|-<br />
| 0089<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR5<br />
|-<br />
| 008A<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR6<br />
|-<br />
| 008B<br />
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]<br />
|?<br />
|PICA_REG_TEXTURE0_SHADOW<br />
|-<br />
| 008C<br />
| [[#GPUREG_008C|GPUREG_008C]]<br />
|<br />
|<br />
|-<br />
| 008D<br />
| [[#GPUREG_008D|GPUREG_008D]]<br />
|<br />
|<br />
|-<br />
| 008E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]<br />
|?<br />
|PICA_REG_TEXTURE0_FORMAT<br />
|-<br />
| 008F<br />
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN0<br />
|-<br />
| 0090<br />
| [[#GPUREG_0090|GPUREG_0090]]<br />
| <br />
|<br />
|-<br />
| 0091<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE1_BORDER_COLOR<br />
|-<br />
| 0092<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]<br />
| <br />
|PICA_REG_TEXTURE1_SIZE<br />
|-<br />
| 0093<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE1_WRAP_FILTER<br />
|-<br />
| 0094<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE1_LOD<br />
|-<br />
| 0095<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]<br />
| <br />
|PICA_REG_TEXTURE1_ADDR<br />
|-<br />
| 0096<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE1_FORMAT<br />
|-<br />
| 0097<br />
| [[#GPUREG_0097|GPUREG_0097]]<br />
| <br />
|<br />
|-<br />
| 0098<br />
| [[#GPUREG_0098|GPUREG_0098]]<br />
| <br />
|<br />
|-<br />
| 0099<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE2_BORDER_COLOR<br />
|-<br />
| 009A<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]<br />
| <br />
|PICA_REG_TEXTURE2_SIZE<br />
|-<br />
| 009B<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE2_WRAP_FILTER<br />
|-<br />
| 009C<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE2_LOD<br />
|-<br />
| 009D<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]<br />
|<br />
|PICA_REG_TEXTURE2_ADDR<br />
|-<br />
| 009E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE2_FORMAT<br />
|-<br />
| 009F<br />
| [[#GPUREG_009F|GPUREG_009F]]<br />
| <br />
|<br />
|-<br />
| 00A0<br />
| [[#GPUREG_00A0|GPUREG_00A0]]<br />
| <br />
|<br />
|-<br />
| 00A1<br />
| [[#GPUREG_00A1|GPUREG_00A1]]<br />
| <br />
|<br />
|-<br />
| 00A2<br />
| [[#GPUREG_00A2|GPUREG_00A2]]<br />
| <br />
|<br />
|-<br />
| 00A3<br />
| [[#GPUREG_00A3|GPUREG_00A3]]<br />
| <br />
|<br />
|-<br />
| 00A4<br />
| [[#GPUREG_00A4|GPUREG_00A4]]<br />
| <br />
|<br />
|-<br />
| 00A5<br />
| [[#GPUREG_00A5|GPUREG_00A5]]<br />
| <br />
|<br />
|-<br />
| 00A6<br />
| [[#GPUREG_00A6|GPUREG_00A6]]<br />
| <br />
|<br />
|-<br />
| 00A7<br />
| [[#GPUREG_00A7|GPUREG_00A7]]<br />
| <br />
|<br />
|-<br />
| 00A8<br />
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX0<br />
|-<br />
| 00A9<br />
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX1<br />
|-<br />
| 00AA<br />
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]<br />
|? <br />
|PICA_REG_TEXTURE3_PROCTEX2<br />
|-<br />
| 00AB<br />
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX3<br />
|-<br />
| 00AC<br />
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX4<br />
|-<br />
| 00AD<br />
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX5<br />
|-<br />
| 00AE<br />
| [[#GPUREG_00AE|GPUREG_00AE]]<br />
| <br />
|<br />
|-<br />
| 00AF<br />
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]<br />
|?<br />
|PICA_REG_PROCTEX_LUT<br />
|-<br />
| 00B0<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA0<br />
|-<br />
| 00B1<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA1<br />
|-<br />
| 00B2<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA2<br />
|-<br />
| 00B3<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA3<br />
|-<br />
| 00B4<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA4<br />
|-<br />
| 00B5<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA5<br />
|-<br />
| 00B6<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA6<br />
|-<br />
| 00B7<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA7<br />
|-<br />
| 00B8<br />
| [[#GPUREG_00B8|GPUREG_00B8]]<br />
| <br />
|<br />
|-<br />
| 00B9<br />
| [[#GPUREG_00B9|GPUREG_00B9]]<br />
| <br />
|<br />
|-<br />
| 00BA<br />
| [[#GPUREG_00BA|GPUREG_00BA]]<br />
| <br />
|<br />
|-<br />
| 00BB<br />
| [[#GPUREG_00BB|GPUREG_00BB]]<br />
| <br />
|<br />
|-<br />
| 00BC<br />
| [[#GPUREG_00BC|GPUREG_00BC]]<br />
| <br />
|<br />
|-<br />
| 00BD<br />
| [[#GPUREG_00BD|GPUREG_00BD]]<br />
| <br />
|<br />
|-<br />
| 00BE<br />
| [[#GPUREG_00BE|GPUREG_00BE]]<br />
| <br />
|<br />
|-<br />
| 00BF<br />
| [[#GPUREG_00BF|GPUREG_00BF]]<br />
| <br />
|<br />
|-<br />
| 00C0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_0<br />
|-<br />
| 00C1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_0_OPERAND<br />
|-<br />
| 00C2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COMBINE<br />
|-<br />
| 00C3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COLOR<br />
|-<br />
| 00C4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_0_SCALE<br />
|-<br />
| 00C5<br />
| [[#GPUREG_00C5|GPUREG_00C5]]<br />
| <br />
|<br />
|-<br />
| 00C6<br />
| [[#GPUREG_00C6|GPUREG_00C6]]<br />
| <br />
|<br />
|-<br />
| 00C7<br />
| [[#GPUREG_00C7|GPUREG_00C7]]<br />
| <br />
|<br />
|-<br />
| 00C8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_1<br />
|-<br />
| 00C9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_1_OPERAND<br />
|-<br />
| 00CA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COMBINE<br />
|-<br />
| 00CB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COLOR<br />
|-<br />
| 00CC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_1_SCALE<br />
|-<br />
| 00CD<br />
| [[#GPUREG_00CD|GPUREG_00CD]]<br />
| <br />
|<br />
|-<br />
| 00CE<br />
| [[#GPUREG_00CE|GPUREG_00CE]]<br />
| <br />
|<br />
|-<br />
| 00CF<br />
| [[#GPUREG_00CF|GPUREG_00CF]]<br />
| <br />
|<br />
|-<br />
| 00D0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_2<br />
|-<br />
| 00D1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_2_OPERAND<br />
|-<br />
| 00D2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COMBINE<br />
|-<br />
| 00D3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COLOR<br />
|-<br />
| 00D4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_2_SCALE<br />
|-<br />
| 00D5<br />
| [[#GPUREG_00D5|GPUREG_00D5]]<br />
| <br />
|<br />
|-<br />
| 00D6<br />
| [[#GPUREG_00D6|GPUREG_00D6]]<br />
| <br />
|<br />
|-<br />
| 00D7<br />
| [[#GPUREG_00D7|GPUREG_00D7]]<br />
| <br />
|<br />
|-<br />
| 00D8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_3<br />
|-<br />
| 00D9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_3_OPERAND<br />
|-<br />
| 00DA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COMBINE<br />
|-<br />
| 00DB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COLOR<br />
|-<br />
| 00DC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_3_SCALE<br />
|-<br />
| 00DD<br />
| [[#GPUREG_00DD|GPUREG_00DD]]<br />
| <br />
|<br />
|-<br />
| 00DE<br />
| [[#GPUREG_00DE|GPUREG_00DE]]<br />
| <br />
|<br />
|-<br />
| 00DF<br />
| [[#GPUREG_00DF|GPUREG_00DF]]<br />
| <br />
|<br />
|-<br />
| 00E0<br />
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]<br />
|?<br />
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT<br />
|-<br />
| 00E1<br />
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]<br />
|?<br />
|PICA_REG_FOG_COLOR<br />
|-<br />
| 00E2<br />
| [[#GPUREG_00E2|GPUREG_00E2]]<br />
| <br />
|<br />
|-<br />
| 00E3<br />
| [[#GPUREG_00E3|GPUREG_00E3]]<br />
| <br />
|<br />
|-<br />
| 00E4<br />
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]<br />
|?<br />
|PICA_REG_GAS_ATTENUATION<br />
|-<br />
| 00E5<br />
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]<br />
|?<br />
|PICA_REG_GAS_ACCMAX<br />
|-<br />
| 00E6<br />
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FOG_LUT_INDEX<br />
|-<br />
| 00E7<br />
| [[#GPUREG_00E7|GPUREG_00E7]]<br />
| <br />
|<br />
|-<br />
| 00E8<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA0<br />
|-<br />
| 00E9<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]<br />
|? <br />
|PICA_REG_FOG_LUT_DATA1<br />
|-<br />
| 00EA<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA2<br />
|-<br />
| 00EB<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA3<br />
|-<br />
| 00EC<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA4<br />
|-<br />
| 00ED<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA5<br />
|-<br />
| 00EE<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA6<br />
|-<br />
| 00EF<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA7<br />
|-<br />
| 00F0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_4<br />
|-<br />
| 00F1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_4_OPERAND<br />
|-<br />
| 00F2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COMBINE<br />
|-<br />
| 00F3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COLOR<br />
|-<br />
| 00F4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_4_SCALE<br />
|-<br />
| 00F5<br />
| [[#GPUREG_00F5|GPUREG_00F5]]<br />
| <br />
|<br />
|-<br />
| 00F6<br />
| [[#GPUREG_00F6|GPUREG_00F6]]<br />
| <br />
|<br />
|-<br />
| 00F7<br />
| [[#GPUREG_00F7|GPUREG_00F7]]<br />
| <br />
|<br />
|-<br />
| 00F8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_5<br />
|-<br />
| 00F9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_5_OPERAND<br />
|-<br />
| 00FA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COMBINE<br />
|-<br />
| 00FB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COLOR<br />
|-<br />
| 00FC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_5_SCALE<br />
|-<br />
| 00FD<br />
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]<br />
|?<br />
|PICA_REG_TEX_ENV_BUF_COLOR<br />
|-<br />
| 00FE<br />
| [[#GPUREG_00FE|GPUREG_00FE]]<br />
| <br />
|<br />
|-<br />
| 00FF<br />
| [[#GPUREG_00FF|GPUREG_00FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Framebuffer registers (0x100-0x13F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0100<br />
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]<br />
|<br />
|PICA_REG_COLOR_OPERATION<br />
|-<br />
| 0101<br />
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]<br />
| <br />
|PICA_REG_BLEND_FUNC<br />
|-<br />
| 0102<br />
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]<br />
| <br />
|PICA_REG_LOGIC_OP<br />
|-<br />
| 0103<br />
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]<br />
| <br />
|PICA_REG_BLEND_COLOR<br />
|-<br />
| 0104<br />
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]<br />
| <br />
|PICA_REG_FRAGOP_ALPHA_TEST<br />
|-<br />
| 0105<br />
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]<br />
| <br />
|PICA_REG_STENCIL_TEST<br />
|-<br />
| 0106<br />
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]<br />
| <br />
|PICA_REG_STENCIL_OP<br />
|-<br />
| 0107<br />
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]<br />
| <br />
|PICA_REG_DEPTH_COLOR_MASK<br />
|-<br />
| 0108<br />
| [[#GPUREG_0108|GPUREG_0108]]<br />
| <br />
|<br />
|-<br />
| 0109<br />
| [[#GPUREG_0109|GPUREG_0109]]<br />
| <br />
|<br />
|-<br />
| 010A<br />
| [[#GPUREG_010A|GPUREG_010A]]<br />
| <br />
|<br />
|-<br />
| 010B<br />
| [[#GPUREG_010B|GPUREG_010B]]<br />
| <br />
|<br />
|-<br />
| 010C<br />
| [[#GPUREG_010C|GPUREG_010C]]<br />
| <br />
|<br />
|-<br />
| 010D<br />
| [[#GPUREG_010D|GPUREG_010D]]<br />
| <br />
|<br />
|-<br />
| 010E<br />
| [[#GPUREG_010E|GPUREG_010E]]<br />
| <br />
|<br />
|-<br />
| 010F<br />
| [[#GPUREG_010F|GPUREG_010F]]<br />
| <br />
|<br />
|-<br />
| 0110<br />
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR0<br />
|-<br />
| 0111<br />
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR1<br />
|-<br />
| 0112<br />
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_READ<br />
|-<br />
| 0113<br />
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_WRITE<br />
|-<br />
| 0114<br />
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_READ<br />
|-<br />
| 0115<br />
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_WRITE<br />
|-<br />
| 0116<br />
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_DEPTH_MODE<br />
|-<br />
| 0117<br />
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_MODE<br />
|-<br />
| 0118<br />
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST2<br />
|-<br />
| 0119<br />
| [[#GPUREG_0119|GPUREG_0119]]<br />
| <br />
|<br />
|-<br />
| 011A<br />
| [[#GPUREG_011A|GPUREG_011A]]<br />
| <br />
|<br />
|-<br />
| 011B<br />
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]<br />
|<br />
|PICA_REG_RENDER_BLOCK_FORMAT<br />
|-<br />
| 011C<br />
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]<br />
|<br />
|PICA_REG_RENDER_BUF_DEPTH_ADDR<br />
|-<br />
| 011D<br />
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_ADDR<br />
|-<br />
| 011E<br />
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]<br />
| <br />
|PICA_REG_RENDER_BUF_RESOLUTION0<br />
|-<br />
| 011F<br />
| [[#GPUREG_011F|GPUREG_011F]]<br />
| <br />
|<br />
|-<br />
| 0120<br />
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_XY<br />
|-<br />
| 0121<br />
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z<br />
|-<br />
| 0122<br />
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z_COLOR<br />
|-<br />
| 0123<br />
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]<br />
|?<br />
|PICA_REG_GAS_LUT_INDEX<br />
|-<br />
| 0124<br />
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]<br />
|?<br />
|PICA_REG_GAS_LUT_DATA<br />
|-<br />
| 0125<br />
| [[#GPUREG_0125|GPUREG_0125]]<br />
| <br />
|<br />
|-<br />
| 0126<br />
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]<br />
|?<br />
|PICA_REG_GAS_DELTAZ_DEPTH<br />
|-<br />
| 0127<br />
| [[#GPUREG_0127|GPUREG_0127]]<br />
| <br />
|<br />
|-<br />
| 0128<br />
| [[#GPUREG_0128|GPUREG_0128]]<br />
| <br />
|<br />
|-<br />
| 0129<br />
| [[#GPUREG_0129|GPUREG_0129]]<br />
| <br />
|<br />
|-<br />
| 012A<br />
| [[#GPUREG_012A|GPUREG_012A]]<br />
| <br />
|<br />
|-<br />
| 012B<br />
| [[#GPUREG_012B|GPUREG_012B]]<br />
| <br />
|<br />
|-<br />
| 012C<br />
| [[#GPUREG_012C|GPUREG_012C]]<br />
| <br />
|<br />
|-<br />
| 012D<br />
| [[#GPUREG_012D|GPUREG_012D]]<br />
| <br />
|<br />
|-<br />
| 012E<br />
| [[#GPUREG_012E|GPUREG_012E]]<br />
| <br />
|<br />
|-<br />
| 012F<br />
| [[#GPUREG_012F|GPUREG_012F]]<br />
| <br />
|<br />
|-<br />
| 0130<br />
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]<br />
|?<br />
|PICA_REG_FRAGOP_SHADOW<br />
|-<br />
| 0131<br />
| [[#GPUREG_0131|GPUREG_0131]]<br />
| <br />
|<br />
|-<br />
| 0132<br />
| [[#GPUREG_0132|GPUREG_0132]]<br />
| <br />
|<br />
|-<br />
| 0133<br />
| [[#GPUREG_0133|GPUREG_0133]]<br />
| <br />
|<br />
|-<br />
| 0134<br />
| [[#GPUREG_0134|GPUREG_0134]]<br />
| <br />
|<br />
|-<br />
| 0135<br />
| [[#GPUREG_0135|GPUREG_0135]]<br />
| <br />
|<br />
|-<br />
| 0136<br />
| [[#GPUREG_0136|GPUREG_0136]]<br />
| <br />
|<br />
|-<br />
| 0137<br />
| [[#GPUREG_0137|GPUREG_0137]]<br />
| <br />
|<br />
|-<br />
| 0138<br />
| [[#GPUREG_0138|GPUREG_0138]]<br />
| <br />
|<br />
|-<br />
| 0139<br />
| [[#GPUREG_0139|GPUREG_0139]]<br />
| <br />
|<br />
|-<br />
| 013A<br />
| [[#GPUREG_013A|GPUREG_013A]]<br />
| <br />
|<br />
|-<br />
| 013B<br />
| [[#GPUREG_013B|GPUREG_013B]]<br />
| <br />
|<br />
|-<br />
| 013C<br />
| [[#GPUREG_013C|GPUREG_013C]]<br />
| <br />
|<br />
|-<br />
| 013D<br />
| [[#GPUREG_013D|GPUREG_013D]]<br />
| <br />
|<br />
|-<br />
| 013E<br />
| [[#GPUREG_013E|GPUREG_013E]]<br />
| <br />
|<br />
|-<br />
| 013F<br />
| [[#GPUREG_013F|GPUREG_013F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Fragment lighting registers (0x140-0x1FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0140<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START<br />
|-<br />
| 0141<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR1<br />
|-<br />
| 0142<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIFFUSE<br />
|-<br />
| 0143<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_AMBIENT<br />
|-<br />
| 0144<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_XY<br />
|-<br />
| 0145<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_Z<br />
|-<br />
| 0146<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_XY<br />
|-<br />
| 0147<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_Z<br />
|-<br />
| 0148<br />
| [[#GPUREG_0148|GPUREG_0148]]<br />
| <br />
|<br />
|-<br />
| 0149<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]<br />
| <br />
|PICA_REG_FRAG_LIGHT0_TYPE<br />
|-<br />
| 014A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS<br />
|-<br />
| 014B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE<br />
|-<br />
| 014C<br />
| [[#GPUREG_014C|GPUREG_014C]]<br />
| <br />
|<br />
|-<br />
| 014D<br />
| [[#GPUREG_014D|GPUREG_014D]]<br />
| <br />
|<br />
|-<br />
| 014E<br />
| [[#GPUREG_014E|GPUREG_014E]]<br />
| <br />
|<br />
|-<br />
| 014F<br />
| [[#GPUREG_014F|GPUREG_014F]]<br />
| <br />
|<br />
|-<br />
| 0150<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR0<br />
|-<br />
| 0151<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR1<br />
|-<br />
| 0152<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIFFUSE<br />
|-<br />
| 0153<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_AMBIENT<br />
|-<br />
| 0154<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_XY<br />
|-<br />
| 0155<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_Z<br />
|-<br />
| 0156<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_XY<br />
|-<br />
| 0157<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_Z<br />
|-<br />
| 0158<br />
| [[#GPUREG_0158|GPUREG_0158]]<br />
| <br />
|<br />
|-<br />
| 0159<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_TYPE<br />
|-<br />
| 015A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS<br />
|-<br />
| 015B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE<br />
|-<br />
| 015C<br />
| [[#GPUREG_015C|GPUREG_015C]]<br />
| <br />
|<br />
|-<br />
| 015D<br />
| [[#GPUREG_015D|GPUREG_015D]]<br />
| <br />
|<br />
|-<br />
| 015E<br />
| [[#GPUREG_015E|GPUREG_015E]]<br />
| <br />
|<br />
|-<br />
| 015F<br />
| [[#GPUREG_015F|GPUREG_015F]]<br />
| <br />
|<br />
|-<br />
| 0160<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR0<br />
|-<br />
| 0161<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR1<br />
|-<br />
| 0162<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIFFUSE<br />
|-<br />
| 0163<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_AMBIENT<br />
|-<br />
| 0164<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_XY<br />
|-<br />
| 0165<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_Z<br />
|-<br />
| 0166<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_XY<br />
|-<br />
| 0167<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_Z<br />
|-<br />
| 0168<br />
| [[#GPUREG_0168|GPUREG_0168]]<br />
| <br />
|<br />
|-<br />
| 0169<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_TYPE<br />
|-<br />
| 016A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS<br />
|-<br />
| 016B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE<br />
|-<br />
| 016C<br />
| [[#GPUREG_016C|GPUREG_016C]]<br />
| <br />
|<br />
|-<br />
| 016D<br />
| [[#GPUREG_016D|GPUREG_016D]]<br />
| <br />
|<br />
|-<br />
| 016E<br />
| [[#GPUREG_016E|GPUREG_016E]]<br />
| <br />
|<br />
|-<br />
| 016F<br />
| [[#GPUREG_016F|GPUREG_016F]]<br />
| <br />
|<br />
|-<br />
| 0170<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR0<br />
|-<br />
| 0171<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR1<br />
|-<br />
| 0172<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIFFUSE<br />
|-<br />
| 0173<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_AMBIENT<br />
|-<br />
| 0174<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_XY<br />
|-<br />
| 0175<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_Z<br />
|-<br />
| 0176<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]<br />
|? <br />
|PICA_REG_FRAG_LIGHT3_SPOT_XY<br />
|-<br />
| 0177<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPOT_Z<br />
|-<br />
| 0178<br />
| [[#GPUREG_0178|GPUREG_0178]]<br />
| <br />
|<br />
|-<br />
| 0179<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_TYPE<br />
|-<br />
| 017A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS<br />
|-<br />
| 017B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE<br />
|-<br />
| 017C<br />
| [[#GPUREG_017C|GPUREG_017C]]<br />
| <br />
|<br />
|-<br />
| 017D<br />
| [[#GPUREG_017D|GPUREG_017D]]<br />
| <br />
|<br />
|-<br />
| 017E<br />
| [[#GPUREG_017E|GPUREG_017E]]<br />
| <br />
|<br />
|-<br />
| 017F<br />
| [[#GPUREG_017F|GPUREG_017F]]<br />
| <br />
|<br />
|-<br />
| 0180<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR0<br />
|-<br />
| 0181<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR1<br />
|-<br />
| 0182<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIFFUSE<br />
|-<br />
| 0183<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_AMBIENT<br />
|-<br />
| 0184<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_XY<br />
|-<br />
| 0185<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_Z<br />
|-<br />
| 0186<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_XY<br />
|-<br />
| 0187<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_Z<br />
|-<br />
| 0188<br />
| [[#GPUREG_0188|GPUREG_0188]]<br />
| <br />
|<br />
|-<br />
| 0189<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_TYPE<br />
|-<br />
| 018A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS<br />
|-<br />
| 018B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE<br />
|-<br />
| 018C<br />
| [[#GPUREG_018C|GPUREG_018C]]<br />
| <br />
|<br />
|-<br />
| 018D<br />
| [[#GPUREG_018D|GPUREG_018D]]<br />
| <br />
|<br />
|-<br />
| 018E<br />
| [[#GPUREG_018E|GPUREG_018E]]<br />
| <br />
|<br />
|-<br />
| 018F<br />
| [[#GPUREG_018F|GPUREG_018F]]<br />
| <br />
|<br />
|-<br />
| 0190<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR0<br />
|-<br />
| 0191<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR1<br />
|-<br />
| 0192<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_DIFFUSE<br />
|-<br />
| 0193<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_AMBIENT<br />
|-<br />
| 0194<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_XY<br />
|-<br />
| 0195<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_Z<br />
|-<br />
| 0196<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_XY<br />
|-<br />
| 0197<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_Z<br />
|-<br />
| 0198<br />
| [[#GPUREG_0198|GPUREG_0198]]<br />
| <br />
|<br />
|-<br />
| 0199<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_TYPE<br />
|-<br />
| 019A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS<br />
|-<br />
| 019B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE<br />
|-<br />
| 019C<br />
| [[#GPUREG_019C|GPUREG_019C]]<br />
| <br />
|<br />
|-<br />
| 019D<br />
| [[#GPUREG_019D|GPUREG_019D]]<br />
| <br />
|<br />
|-<br />
| 019E<br />
| [[#GPUREG_019E|GPUREG_019E]]<br />
| <br />
|<br />
|-<br />
| 019F<br />
| [[#GPUREG_019F|GPUREG_019F]]<br />
| <br />
|<br />
|-<br />
| 01A0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR0<br />
|-<br />
| 01A1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR1<br />
|-<br />
| 01A2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIFFUSE<br />
|-<br />
| 01A3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_AMBIENT<br />
|-<br />
| 01A4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_XY<br />
|-<br />
| 01A5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_Z<br />
|-<br />
| 01A6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_XY<br />
|-<br />
| 01A7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_Z<br />
|-<br />
| 01A8<br />
| [[#GPUREG_01A8|GPUREG_01A8]]<br />
| <br />
|<br />
|-<br />
| 01A9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_TYPE<br />
|-<br />
| 01AA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS<br />
|-<br />
| 01AB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE<br />
|-<br />
| 01AC<br />
| [[#GPUREG_01AC|GPUREG_01AC]]<br />
| <br />
|<br />
|-<br />
| 01AD<br />
| [[#GPUREG_01AD|GPUREG_01AD]]<br />
| <br />
|<br />
|-<br />
| 01AE<br />
| [[#GPUREG_01AE|GPUREG_01AE]]<br />
| <br />
|<br />
|-<br />
| 01AF<br />
| [[#GPUREG_01AF|GPUREG_01AF]]<br />
| <br />
|<br />
|-<br />
| 01B0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR0<br />
|-<br />
| 01B1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR1<br />
|-<br />
| 01B2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_DIFFUSE<br />
|-<br />
| 01B3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_AMBIENT<br />
|-<br />
| 01B4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_XY<br />
|-<br />
| 01B5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_Z<br />
|-<br />
| 01B6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_XY<br />
|-<br />
| 01B7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_Z<br />
|-<br />
| 01B8<br />
| [[#GPUREG_01B8|GPUREG_01B8]]<br />
| <br />
|<br />
|-<br />
| 01B9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_TYPE<br />
|-<br />
| 01BA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS<br />
|-<br />
| 01BB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE<br />
|-<br />
| 01BC<br />
| [[#GPUREG_01BC|GPUREG_01BC]]<br />
| <br />
|<br />
|-<br />
| 01BD<br />
| [[#GPUREG_01BD|GPUREG_01BD]]<br />
| <br />
|<br />
|-<br />
| 01BE<br />
| [[#GPUREG_01BE|GPUREG_01BE]]<br />
| <br />
|<br />
|-<br />
| 01BF<br />
| [[#GPUREG_01BF|GPUREG_01BF]]<br />
| <br />
|<br />
|-<br />
| 01C0<br />
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_AMBIENT<br />
|-<br />
| 01C1<br />
| [[#GPUREG_01C1|GPUREG_01C1]]<br />
| <br />
|<br />
|-<br />
| 01C2<br />
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_NUM<br />
|-<br />
| 01C3<br />
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE0<br />
|-<br />
| 01C4<br />
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE1<br />
|-<br />
| 01C5<br />
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT<br />
|-<br />
| 01C6<br />
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN1<br />
|-<br />
| 01C7<br />
| [[#GPUREG_01C7|GPUREG_01C7]]<br />
| <br />
|<br />
|-<br />
| 01C8<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA0<br />
|-<br />
| 01C9<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA1<br />
|-<br />
| 01CA<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA2<br />
|-<br />
| 01CB<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA3<br />
|-<br />
| 01CC<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA4<br />
|-<br />
| 01CD<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA5<br />
|-<br />
| 01CE<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA6<br />
|-<br />
| 01CF<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA7<br />
|-<br />
| 01D0<br />
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT<br />
|-<br />
| 01D1<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTINPUT<br />
|-<br />
| 01D2<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTSCALE<br />
|-<br />
| 01D3<br />
| [[#GPUREG_01D3|GPUREG_01D3]]<br />
| <br />
|<br />
|-<br />
| 01D4<br />
| [[#GPUREG_01D4|GPUREG_01D4]]<br />
| <br />
|<br />
|-<br />
| 01D5<br />
| [[#GPUREG_01D5|GPUREG_01D5]]<br />
| <br />
|<br />
|-<br />
| 01D6<br />
| [[#GPUREG_01D6|GPUREG_01D6]]<br />
| <br />
|<br />
|-<br />
| 01D7<br />
| [[#GPUREG_01D7|GPUREG_01D7]]<br />
| <br />
|<br />
|-<br />
| 01D8<br />
| [[#GPUREG_01D8|GPUREG_01D8]]<br />
| <br />
|<br />
|-<br />
| 01D9<br />
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_EN_ID<br />
|-<br />
| 01DA<br />
| [[#GPUREG_01DA|GPUREG_01DA]]<br />
| <br />
|<br />
|-<br />
| 01DB<br />
| [[#GPUREG_01DB|GPUREG_01DB]]<br />
| <br />
|<br />
|-<br />
| 01DC<br />
| [[#GPUREG_01DC|GPUREG_01DC]]<br />
| <br />
|<br />
|-<br />
| 01DD<br />
| [[#GPUREG_01DD|GPUREG_01DD]]<br />
| <br />
|<br />
|-<br />
| 01DE<br />
| [[#GPUREG_01DE|GPUREG_01DE]]<br />
| <br />
|<br />
|-<br />
| 01DF<br />
| [[#GPUREG_01DF|GPUREG_01DF]]<br />
| <br />
|<br />
|-<br />
| 01E0<br />
| [[#GPUREG_01E0|GPUREG_01E0]]<br />
| <br />
|<br />
|-<br />
| 01E1<br />
| [[#GPUREG_01E1|GPUREG_01E1]]<br />
| <br />
|<br />
|-<br />
| 01E2<br />
| [[#GPUREG_01E2|GPUREG_01E2]]<br />
| <br />
|<br />
|-<br />
| 01E3<br />
| [[#GPUREG_01E3|GPUREG_01E3]]<br />
| <br />
|<br />
|-<br />
| 01E4<br />
| [[#GPUREG_01E4|GPUREG_01E4]]<br />
| <br />
|<br />
|-<br />
| 01E5<br />
| [[#GPUREG_01E5|GPUREG_01E5]]<br />
| <br />
|<br />
|-<br />
| 01E6<br />
| [[#GPUREG_01E6|GPUREG_01E6]]<br />
| <br />
|<br />
|-<br />
| 01E7<br />
| [[#GPUREG_01E7|GPUREG_01E7]]<br />
| <br />
|<br />
|-<br />
| 01E8<br />
| [[#GPUREG_01E8|GPUREG_01E8]]<br />
| <br />
|<br />
|-<br />
| 01E9<br />
| [[#GPUREG_01E9|GPUREG_01E9]]<br />
| <br />
|<br />
|-<br />
| 01EA<br />
| [[#GPUREG_01EA|GPUREG_01EA]]<br />
| <br />
|<br />
|-<br />
| 01EB<br />
| [[#GPUREG_01EB|GPUREG_01EB]]<br />
| <br />
|<br />
|-<br />
| 01EC<br />
| [[#GPUREG_01EC|GPUREG_01EC]]<br />
| <br />
|<br />
|-<br />
| 01ED<br />
| [[#GPUREG_01ED|GPUREG_01ED]]<br />
| <br />
|<br />
|-<br />
| 01EE<br />
| [[#GPUREG_01EE|GPUREG_01EE]]<br />
| <br />
|<br />
|-<br />
| 01EF<br />
| [[#GPUREG_01EF|GPUREG_01EF]]<br />
| <br />
|<br />
|-<br />
| 01F0<br />
| [[#GPUREG_01F0|GPUREG_01F0]]<br />
| <br />
|<br />
|-<br />
| 01F1<br />
| [[#GPUREG_01F1|GPUREG_01F1]]<br />
| <br />
|<br />
|-<br />
| 01F2<br />
| [[#GPUREG_01F2|GPUREG_01F2]]<br />
| <br />
|<br />
|-<br />
| 01F3<br />
| [[#GPUREG_01F3|GPUREG_01F3]]<br />
| <br />
|<br />
|-<br />
| 01F4<br />
| [[#GPUREG_01F4|GPUREG_01F4]]<br />
| <br />
|<br />
|-<br />
| 01F5<br />
| [[#GPUREG_01F5|GPUREG_01F5]]<br />
| <br />
|<br />
|-<br />
| 01F6<br />
| [[#GPUREG_01F6|GPUREG_01F6]]<br />
| <br />
|<br />
|-<br />
| 01F7<br />
| [[#GPUREG_01F7|GPUREG_01F7]]<br />
| <br />
|<br />
|-<br />
| 01F8<br />
| [[#GPUREG_01F8|GPUREG_01F8]]<br />
| <br />
|<br />
|-<br />
| 01F9<br />
| [[#GPUREG_01F9|GPUREG_01F9]]<br />
| <br />
|<br />
|-<br />
| 01FA<br />
| [[#GPUREG_01FA|GPUREG_01FA]]<br />
| <br />
|<br />
|-<br />
| 01FB<br />
| [[#GPUREG_01FB|GPUREG_01FB]]<br />
| <br />
|<br />
|-<br />
| 01FC<br />
| [[#GPUREG_01FC|GPUREG_01FC]]<br />
| <br />
|<br />
|-<br />
| 01FD<br />
| [[#GPUREG_01FD|GPUREG_01FD]]<br />
| <br />
|<br />
|-<br />
| 01FE<br />
| [[#GPUREG_01FE|GPUREG_01FE]]<br />
| <br />
|<br />
|-<br />
| 01FF<br />
| [[#GPUREG_01FF|GPUREG_01FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Geometry pipeline registers (0x200-0x27F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0200<br />
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR<br />
|-<br />
| 0201<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS0<br />
|-<br />
| 0202<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS1<br />
|-<br />
| 0203<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET<br />
|-<br />
| 0204<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT0<br />
|-<br />
| 0205<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT1<br />
|-<br />
| 0206<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0207<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0208<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0209<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020B<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020C<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020E<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020F<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0210<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0211<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0212<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0213<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0214<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0215<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0216<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0217<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0218<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0219<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021B<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021C<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021E<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021F<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0220<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0221<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0222<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0223<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0224<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0225<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0226<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0227<br />
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET<br />
|-<br />
| 0228<br />
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]<br />
| <br />
|PICA_REG_DRAW_VERTEX_NUM<br />
|-<br />
| 0229<br />
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]<br />
| ?<br />
|PICA_REG_DRAW_MODE0<br />
|-<br />
| 022A<br />
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]<br />
|<br />
|PICA_REG_DRAW_VERTEX_OFFSET<br />
|-<br />
| 022B<br />
| [[#GPUREG_022B|GPUREG_022B]]<br />
| <br />
|<br />
|-<br />
| 022C<br />
| [[#GPUREG_022C|GPUREG_022C]]<br />
| <br />
|<br />
|-<br />
| 022D<br />
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]<br />
| <br />
|PICA_REG_POST_VERTEX_CACHE_NUM<br />
|-<br />
| 022E<br />
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]<br />
|<br />
|PICA_REG_START_DRAW_ARRAY<br />
|-<br />
| 022F<br />
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]<br />
|<br />
|PICA_REG_START_DRAW_ELEMENT<br />
|-<br />
| 0230<br />
| [[#GPUREG_0230|GPUREG_0230]]<br />
| <br />
|<br />
|-<br />
| 0231<br />
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]<br />
|?<br />
|PICA_REG_VTX_FUNC<br />
|-<br />
| 0232<br />
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR<br />
|-<br />
| 0233<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA0<br />
|-<br />
| 0234<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA1<br />
|-<br />
| 0235<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA2<br />
|-<br />
| 0236<br />
| [[#GPUREG_0236|GPUREG_0236]]<br />
| <br />
|<br />
|-<br />
| 0237<br />
| [[#GPUREG_0237|GPUREG_0237]]<br />
| <br />
|<br />
|-<br />
| 0238<br />
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH0<br />
|-<br />
| 0239<br />
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH1<br />
|-<br />
| 023A<br />
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH0<br />
|-<br />
| 023B<br />
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH1<br />
|-<br />
| 023C<br />
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH0<br />
|-<br />
| 023D<br />
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH1<br />
|-<br />
| 023E<br />
| [[#GPUREG_023E|GPUREG_023E]]<br />
| <br />
|<br />
|-<br />
| 023F<br />
| [[#GPUREG_023F|GPUREG_023F]]<br />
| <br />
|<br />
|-<br />
| 0240<br />
| [[#GPUREG_0240|GPUREG_0240]]<br />
| <br />
|<br />
|-<br />
| 0241<br />
| [[#GPUREG_0241|GPUREG_0241]]<br />
| <br />
|<br />
|-<br />
| 0242<br />
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]<br />
|?<br />
|PICA_REG_VS_ATTR_NUM1<br />
|-<br />
| 0243<br />
| [[#GPUREG_0243|GPUREG_0243]]<br />
| <br />
|<br />
|-<br />
| 0244<br />
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]<br />
|?<br />
|PICA_REG_VS_COM_MODE<br />
|-<br />
| 0245<br />
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC0<br />
|-<br />
| 0246<br />
| [[#GPUREG_0246|GPUREG_0246]]<br />
| <br />
|<br />
|-<br />
| 0247<br />
| [[#GPUREG_0247|GPUREG_0247]]<br />
| <br />
|<br />
|-<br />
| 0248<br />
| [[#GPUREG_0248|GPUREG_0248]]<br />
| <br />
|<br />
|-<br />
| 0249<br />
| [[#GPUREG_0249|GPUREG_0249]]<br />
| <br />
|<br />
|-<br />
| 024A<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM1<br />
|-<br />
| 024B<br />
| [[#GPUREG_024B|GPUREG_024B]]<br />
|<br />
|<br />
|-<br />
| 024C<br />
| [[#GPUREG_024C|GPUREG_024C]]<br />
| <br />
|<br />
|-<br />
| 024D<br />
| [[#GPUREG_024D|GPUREG_024D]]<br />
| <br />
|<br />
|-<br />
| 024E<br />
| [[#GPUREG_024E|GPUREG_024E]]<br />
| <br />
|<br />
|-<br />
| 024F<br />
| [[#GPUREG_024F|GPUREG_024F]]<br />
| <br />
|<br />
|-<br />
| 0250<br />
| [[#GPUREG_0250|GPUREG_0250]]<br />
| <br />
|<br />
|-<br />
| 0251<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM2<br />
|-<br />
| 0252<br />
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]<br />
|?<br />
|PICA_REG_GS_MISC_REG0<br />
|-<br />
| 0253<br />
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]<br />
|?<br />
|PICA_REG_DRAW_MODE1<br />
|-<br />
| 0254<br />
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]<br />
|?<br />
|PICA_REG_GS_MISC_REG1<br />
|-<br />
| 0255<br />
| [[#GPUREG_0255|GPUREG_0255]]<br />
| <br />
|<br />
|-<br />
| 0256<br />
| [[#GPUREG_0256|GPUREG_0256]]<br />
| <br />
|<br />
|-<br />
| 0257<br />
| [[#GPUREG_0257|GPUREG_0257]]<br />
| <br />
|<br />
|-<br />
| 0258<br />
| [[#GPUREG_0258|GPUREG_0258]]<br />
| <br />
|<br />
|-<br />
| 0259<br />
| [[#GPUREG_0259|GPUREG_0259]]<br />
| <br />
|<br />
|-<br />
| 025A<br />
| [[#GPUREG_025A|GPUREG_025A]]<br />
| <br />
|<br />
|-<br />
| 025B<br />
| [[#GPUREG_025B|GPUREG_025B]]<br />
| <br />
|<br />
|-<br />
| 025C<br />
| [[#GPUREG_025C|GPUREG_025C]]<br />
| <br />
|<br />
|-<br />
| 025D<br />
| [[#GPUREG_025D|GPUREG_025D]]<br />
| <br />
|<br />
|-<br />
| 025E<br />
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]<br />
| ?<br />
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3<br />
|-<br />
| 025F<br />
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC1<br />
|-<br />
| 0260<br />
| [[#GPUREG_0260|GPUREG_0260]]<br />
| <br />
|<br />
|-<br />
| 0261<br />
| [[#GPUREG_0261|GPUREG_0261]]<br />
| <br />
|<br />
|-<br />
| 0262<br />
| [[#GPUREG_0262|GPUREG_0262]]<br />
| <br />
|<br />
|-<br />
| 0263<br />
| [[#GPUREG_0263|GPUREG_0263]]<br />
| <br />
|<br />
|-<br />
| 0264<br />
| [[#GPUREG_0264|GPUREG_0264]]<br />
| <br />
|<br />
|-<br />
| 0265<br />
| [[#GPUREG_0265|GPUREG_0265]]<br />
| <br />
|<br />
|-<br />
| 0266<br />
| [[#GPUREG_0266|GPUREG_0266]]<br />
| <br />
|<br />
|-<br />
| 0267<br />
| [[#GPUREG_0267|GPUREG_0267]]<br />
| <br />
|<br />
|-<br />
| 0268<br />
| [[#GPUREG_0268|GPUREG_0268]]<br />
| <br />
|<br />
|-<br />
| 0269<br />
| [[#GPUREG_0269|GPUREG_0269]]<br />
| <br />
|<br />
|-<br />
| 026A<br />
| [[#GPUREG_026A|GPUREG_026A]]<br />
| <br />
|<br />
|-<br />
| 026B<br />
| [[#GPUREG_026B|GPUREG_026B]]<br />
| <br />
|<br />
|-<br />
| 026C<br />
| [[#GPUREG_026C|GPUREG_026C]]<br />
| <br />
|<br />
|-<br />
| 026D<br />
| [[#GPUREG_026D|GPUREG_026D]]<br />
| <br />
|<br />
|-<br />
| 026E<br />
| [[#GPUREG_026E|GPUREG_026E]]<br />
| <br />
|<br />
|-<br />
| 026F<br />
| [[#GPUREG_026F|GPUREG_026F]]<br />
| <br />
|<br />
|-<br />
| 0270<br />
| [[#GPUREG_0270|GPUREG_0270]]<br />
| <br />
|<br />
|-<br />
| 0271<br />
| [[#GPUREG_0271|GPUREG_0271]]<br />
| <br />
|<br />
|-<br />
| 0272<br />
| [[#GPUREG_0272|GPUREG_0272]]<br />
| <br />
|<br />
|-<br />
| 0273<br />
| [[#GPUREG_0273|GPUREG_0273]]<br />
| <br />
|<br />
|-<br />
| 0274<br />
| [[#GPUREG_0274|GPUREG_0274]]<br />
| <br />
|<br />
|-<br />
| 0275<br />
| [[#GPUREG_0275|GPUREG_0275]]<br />
| <br />
|<br />
|-<br />
| 0276<br />
| [[#GPUREG_0276|GPUREG_0276]]<br />
| <br />
|<br />
|-<br />
| 0277<br />
| [[#GPUREG_0277|GPUREG_0277]]<br />
| <br />
|<br />
|-<br />
| 0278<br />
| [[#GPUREG_0278|GPUREG_0278]]<br />
| <br />
|<br />
|-<br />
| 0279<br />
| [[#GPUREG_0279|GPUREG_0279]]<br />
| <br />
|<br />
|-<br />
| 027A<br />
| [[#GPUREG_027A|GPUREG_027A]]<br />
| <br />
|<br />
|-<br />
| 027B<br />
| [[#GPUREG_027B|GPUREG_027B]]<br />
| <br />
|<br />
|-<br />
| 027C<br />
| [[#GPUREG_027C|GPUREG_027C]]<br />
| <br />
|<br />
|-<br />
| 027D<br />
| [[#GPUREG_027D|GPUREG_027D]]<br />
| <br />
|<br />
|-<br />
| 027E<br />
| [[#GPUREG_027E|GPUREG_027E]]<br />
| <br />
|<br />
|-<br />
| 027F<br />
| [[#GPUREG_027F|GPUREG_027F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Shader registers (0x280-0x2DF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
! colspan=4 | Geometry shader<br />
|-<br />
| 0280<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_GS_BOOL<br />
|-<br />
| 0281<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_GS_INT0<br />
|-<br />
| 0282<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_GS_INT1<br />
|-<br />
| 0283<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_GS_INT2<br />
|-<br />
| 0284<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_GS_INT3<br />
|-<br />
| 0285<br />
| [[#GPUREG_0285|GPUREG_0285]]<br />
| <br />
|<br />
|-<br />
| 0286<br />
| [[#GPUREG_0286|GPUREG_0286]]<br />
| <br />
|<br />
|-<br />
| 0287<br />
| [[#GPUREG_0287|GPUREG_0287]]<br />
| <br />
|<br />
|-<br />
| 0288<br />
| [[#GPUREG_0288|GPUREG_0288]]<br />
| <br />
|<br />
|-<br />
| 0289<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_GS_ATTR_NUM<br />
|-<br />
| 028A<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_GS_START_ADDR<br />
|-<br />
| 028B<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP0<br />
|-<br />
| 028C<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP1<br />
|-<br />
| 028D<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_GS_OUT_REG_MASK<br />
|-<br />
| 028E<br />
| [[#GPUREG_028E|GPUREG_028E]]<br />
| <br />
|<br />
|-<br />
| 028F<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_GS_PROG_RENEWAL_END<br />
|-<br />
| 0290<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_GS_FLOAT_ADDR<br />
|-<br />
| 0291<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA0<br />
|-<br />
| 0292<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA1<br />
|-<br />
| 0293<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA2<br />
|-<br />
| 0294<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA3<br />
|-<br />
| 0295<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA4<br />
|-<br />
| 0296<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA5<br />
|-<br />
| 0297<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA6<br />
|-<br />
| 0298<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA7<br />
|-<br />
| 0299<br />
| [[#GPUREG_0299|GPUREG_0299]]<br />
| <br />
|<br />
|-<br />
| 029A<br />
| [[#GPUREG_029A|GPUREG_029A]]<br />
| <br />
|<br />
|-<br />
| 029B<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_GS_PROG_ADDR<br />
|-<br />
| 029C<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_DATA0<br />
|-<br />
| 029D<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_DATA1<br />
|-<br />
| 029E<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_DATA2<br />
|-<br />
| 029F<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_DATA3<br />
|-<br />
| 02A0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_DATA4<br />
|-<br />
| 02A1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_DATA5<br />
|-<br />
| 02A2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_DATA6<br />
|-<br />
| 02A3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_DATA7<br />
|-<br />
| 02A4<br />
| [[#GPUREG_02A4|GPUREG_02A4]]<br />
| <br />
|<br />
|-<br />
| 02A5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02A6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02A7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02A8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02A9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02AA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02AB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02AC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02AD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02AE<br />
| [[#GPUREG_02AE|GPUREG_02AE]]<br />
| <br />
|<br />
|-<br />
| 02AF<br />
| [[#GPUREG_02AF|GPUREG_02AF]]<br />
| <br />
|<br />
|-<br />
! colspan=4 | Vertex shader<br />
|-<br />
| 02B0<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_VS_BOOL<br />
|-<br />
| 02B1<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_VS_INT0<br />
|-<br />
| 02B2<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_VS_INT1<br />
|-<br />
| 02B3<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_VS_INT2<br />
|-<br />
| 02B4<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_VS_INT3<br />
|-<br />
| 02B5<br />
| [[#GPUREG_02B5|GPUREG_02B5]]<br />
| <br />
|<br />
|-<br />
| 02B6<br />
| [[#GPUREG_02B6|GPUREG_02B6]]<br />
| <br />
|<br />
|-<br />
| 02B7<br />
| [[#GPUREG_02B7|GPUREG_02B7]]<br />
| <br />
|<br />
|-<br />
| 02B8<br />
| [[#GPUREG_02B8|GPUREG_02B8]]<br />
| <br />
|<br />
|-<br />
| 02B9<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_VS_ATTR_NUM0<br />
|-<br />
| 02BA<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_VS_START_ADDR<br />
|-<br />
| 02BB<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP0<br />
|-<br />
| 02BC<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP1<br />
|-<br />
| 02BD<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_VS_OUT_REG_MASK<br />
|-<br />
| 02BE<br />
| [[#GPUREG_02BE|GPUREG_02BE]]<br />
| <br />
|<br />
|-<br />
| 02BF<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_VS_PROG_RENEWAL_END<br />
|-<br />
| 02C0<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_VS_FLOAT_ADDR<br />
|-<br />
| 02C1<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA0<br />
|-<br />
| 02C2<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA1<br />
|-<br />
| 02C3<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA2<br />
|-<br />
| 02C4<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA3<br />
|-<br />
| 02C5<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA4<br />
|-<br />
| 02C6<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA5<br />
|-<br />
| 02C7<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA6<br />
|-<br />
| 02C8<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA7<br />
|-<br />
| 02C9<br />
| [[#GPUREG_02C9|GPUREG_02C9]]<br />
| <br />
|<br />
|-<br />
| 02CA<br />
| [[#GPUREG_02CA|GPUREG_02CA]]<br />
| <br />
|<br />
|-<br />
| 02CB<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_ADDR<br />
|-<br />
| 02CC<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_DATA0<br />
|-<br />
| 02CD<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_DATA1<br />
|-<br />
| 02CE<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_DATA2<br />
|-<br />
| 02CF<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_DATA3<br />
|-<br />
| 02D0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_DATA4<br />
|-<br />
| 02D1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_DATA5<br />
|-<br />
| 02D2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_DATA6<br />
|-<br />
| 02D3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_DATA7<br />
|-<br />
| 02D4<br />
| [[#GPUREG_02D4|GPUREG_02D4]]<br />
| <br />
|<br />
|-<br />
| 02D5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02D6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02D7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02D8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02D9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02DA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02DB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02DC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02DD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02DE<br />
| [[#GPUREG_02DE|GPUREG_02DE]]<br />
| <br />
|<br />
|-<br />
| 02DF<br />
| [[#GPUREG_02DF|GPUREG_02DF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Unknown registers (0x2E0-0x2FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 02E0<br />
| [[#GPUREG_02E0|GPUREG_02E0]]<br />
| <br />
|<br />
|-<br />
| 02E1<br />
| [[#GPUREG_02E1|GPUREG_02E1]]<br />
| <br />
|<br />
|-<br />
| 02E2<br />
| [[#GPUREG_02E2|GPUREG_02E2]]<br />
| <br />
|<br />
|-<br />
| 02E3<br />
| [[#GPUREG_02E3|GPUREG_02E3]]<br />
| <br />
|<br />
|-<br />
| 02E4<br />
| [[#GPUREG_02E4|GPUREG_02E4]]<br />
| <br />
|<br />
|-<br />
| 02E5<br />
| [[#GPUREG_02E5|GPUREG_02E5]]<br />
| <br />
|<br />
|-<br />
| 02E6<br />
| [[#GPUREG_02E6|GPUREG_02E6]]<br />
| <br />
|<br />
|-<br />
| 02E7<br />
| [[#GPUREG_02E7|GPUREG_02E7]]<br />
| <br />
|<br />
|-<br />
| 02E8<br />
| [[#GPUREG_02E8|GPUREG_02E8]]<br />
| <br />
|<br />
|-<br />
| 02E9<br />
| [[#GPUREG_02E9|GPUREG_02E9]]<br />
| <br />
|<br />
|-<br />
| 02EA<br />
| [[#GPUREG_02EA|GPUREG_02EA]]<br />
| <br />
|<br />
|-<br />
| 02EB<br />
| [[#GPUREG_02EB|GPUREG_02EB]]<br />
| <br />
|<br />
|-<br />
| 02EC<br />
| [[#GPUREG_02EC|GPUREG_02EC]]<br />
| <br />
|<br />
|-<br />
| 02ED<br />
| [[#GPUREG_02ED|GPUREG_02ED]]<br />
| <br />
|<br />
|-<br />
| 02EE<br />
| [[#GPUREG_02EE|GPUREG_02EE]]<br />
| <br />
|<br />
|-<br />
| 02EF<br />
| [[#GPUREG_02EF|GPUREG_02EF]]<br />
| <br />
|<br />
|-<br />
| 02F0<br />
| [[#GPUREG_02F0|GPUREG_02F0]]<br />
| <br />
|<br />
|-<br />
| 02F1<br />
| [[#GPUREG_02F1|GPUREG_02F1]]<br />
| <br />
|<br />
|-<br />
| 02F2<br />
| [[#GPUREG_02F2|GPUREG_02F2]]<br />
| <br />
|<br />
|-<br />
| 02F3<br />
| [[#GPUREG_02F3|GPUREG_02F3]]<br />
| <br />
|<br />
|-<br />
| 02F4<br />
| [[#GPUREG_02F4|GPUREG_02F4]]<br />
| <br />
|<br />
|-<br />
| 02F5<br />
| [[#GPUREG_02F5|GPUREG_02F5]]<br />
| <br />
|<br />
|-<br />
| 02F6<br />
| [[#GPUREG_02F6|GPUREG_02F6]]<br />
| <br />
|<br />
|-<br />
| 02F7<br />
| [[#GPUREG_02F7|GPUREG_02F7]]<br />
| <br />
|<br />
|-<br />
| 02F8<br />
| [[#GPUREG_02F8|GPUREG_02F8]]<br />
| <br />
|<br />
|-<br />
| 02F9<br />
| [[#GPUREG_02F9|GPUREG_02F9]]<br />
| <br />
|<br />
|-<br />
| 02FA<br />
| [[#GPUREG_02FA|GPUREG_02FA]]<br />
| <br />
|<br />
|-<br />
| 02FB<br />
| [[#GPUREG_02FB|GPUREG_02FB]]<br />
| <br />
|<br />
|-<br />
| 02FC<br />
| [[#GPUREG_02FC|GPUREG_02FC]]<br />
| <br />
|<br />
|-<br />
| 02FD<br />
| [[#GPUREG_02FD|GPUREG_02FD]]<br />
| <br />
|<br />
|-<br />
| 02FE<br />
| [[#GPUREG_02FE|GPUREG_02FE]]<br />
| <br />
|<br />
|-<br />
| 02FF<br />
| [[#GPUREG_02FF|GPUREG_02FF]]<br />
| <br />
|<br />
|}<br />
<br />
== Miscellaneous registers ==<br />
<br />
=== GPUREG_FINALIZE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)<br />
|}<br />
<br />
Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.<br />
Failure to write to this register in any command buffer will result in the GPU hanging.<br />
<br />
== Rasterizer registers ==<br />
<br />
=== GPUREG_FACECULLING_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Culling mode<br />
|}<br />
<br />
This register is used to configure the face culling mode.<br />
<br />
Culling mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Front Face (Counter Clockwise)<br />
|-<br />
| 2<br />
| Back Face (Counter Clockwise)<br />
|}<br />
<br />
=== GPUREG_VIEWPORT_WIDTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, width / 2<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.<br />
<br />
=== GPUREG_VIEWPORT_INVW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / width<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.<br />
<br />
=== GPUREG_VIEWPORT_HEIGHT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, height / 2<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.<br />
<br />
=== GPUREG_VIEWPORT_INVH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / height<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.<br />
<br />
=== GPUREG_FRAGOP_CLIP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable clipping planes.<br />
<br />
=== GPUREG_FRAGOP_CLIP_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Clipping plane coefficient ''i''<br />
|}<br />
<br />
This register is used to configure clipping plane coefficients.<br />
<br />
=== GPUREG_DEPTHMAP_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near - Far<br />
|}<br />
<br />
This register is used to configure the depth range scale.<br />
<br />
=== GPUREG_DEPTHMAP_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near + Polygon Offset<br />
|}<br />
<br />
This register is used to configure the depth range bias.<br />
<br />
=== GPUREG_SH_OUTMAP_TOTAL ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of following attributes<br />
|}<br />
<br />
This register is used to configure the total shader output map attributes.<br />
<br />
=== GPUREG_SH_OUTMAP_O''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Semantic for the x component of the register.<br />
|-<br />
| 8-12<br />
| unsigned, Semantic for the y component of the register.<br />
|-<br />
| 16-20<br />
| unsigned, Semantic for the z component of the register.<br />
|-<br />
| 24-28<br />
| unsigned, Semantic for the w component of the register.<br />
|}<br />
<br />
These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.<br />
<br />
Semantic values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Semantic<br />
! Description<br />
|-<br />
| 0x00<br />
| position.x<br />
| rowspan="4" | Vertex Position<br />
|-<br />
| 0x01<br />
| position.y<br />
|-<br />
| 0x02<br />
| position.z<br />
|-<br />
| 0x03<br />
| position.w<br />
|-<br />
| 0x04<br />
| normquat.x<br />
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)<br />
|-<br />
| 0x05<br />
| normquat.y<br />
|-<br />
| 0x06<br />
| normquat.z<br />
|-<br />
| 0x07<br />
| normquat.w<br />
|-<br />
| 0x08<br />
| color.r<br />
| rowspan="4" | Vertex color<br />
|-<br />
| 0x09<br />
| color.g<br />
|-<br />
| 0x0A<br />
| color.b<br />
|-<br />
| 0x0B<br />
| color.a<br />
|-<br />
| 0x0C<br />
| texcoord0.u<br />
| rowspan="2" | Texture coordinates for texture 0<br />
|-<br />
| 0x0D<br />
| texcoord0.v<br />
|-<br />
| 0x0E<br />
| texcoord1.u<br />
| rowspan="2" | Texture coordinates for texture 1<br />
|-<br />
| 0x0F<br />
| texcoord1.v<br />
|-<br />
| 0x10<br />
| texcoord0.w<br />
|<br />
<br />
|-<br />
| 0x12<br />
| view.x<br />
| rowspan="3" | View vector (for fragment lighting)<br />
|-<br />
| 0x13<br />
| view.y<br />
|-<br />
| 0x14<br />
| view.z<br />
<br />
|-<br />
| 0x16<br />
| texcoord2.u<br />
| rowspan="2" | Texture coordinates for texture 2<br />
|-<br />
| 0x17<br />
| texcoord2.v<br />
<br />
|-<br />
| 0x1F<br />
| Unused component<br />
| Should be set for unused components of the output register<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Early depth function<br />
|}<br />
<br />
This register configures the early depth test function.<br />
<br />
Early depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| >=<br />
|-<br />
| 1<br />
| ><br />
|-<br />
| 2<br />
| <=<br />
|-<br />
| 3<br />
| <<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether the early depth test is enabled.<br />
<br />
=== GPUREG_EARLYDEPTH_CLEAR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = clear)<br />
|}<br />
<br />
This register triggers clearing the early depth data.<br />
<br />
=== GPUREG_SH_OUTATTR_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Use texture coordinates (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register is used to configure the shader output attribute mode.<br />
<br />
=== GPUREG_SCISSORTEST_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Enabled (0 = disabled, 3 = enabled)<br />
|}<br />
<br />
This register is used to enable scissor testing.<br />
<br />
=== GPUREG_SCISSORTEST_POS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X1<br />
|-<br />
| 16-25<br />
| unsigned, Y1<br />
|}<br />
<br />
This register is used to configure the scissor test start position.<br />
<br />
=== GPUREG_SCISSORTEST_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X2<br />
|-<br />
| 16-25<br />
| unsigned, Y2<br />
|}<br />
<br />
This register is used to configure the scissor test end position.<br />
<br />
=== GPUREG_VIEWPORT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| signed, X<br />
|-<br />
| 16-25<br />
| signed, Y<br />
|}<br />
<br />
This register is used to configure the viewport position.<br />
<br />
=== GPUREG_EARLYDEPTH_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| unsigned, Clear value<br />
|}<br />
<br />
This register is used to configure the early depth clear value.<br />
<br />
=== GPUREG_DEPTHMAP_ENABLE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable depth range.<br />
<br />
=== GPUREG_RENDERBUF_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register is used to configure the output framebuffer dimensions.<br />
<br />
=== GPUREG_SH_OUTATTR_CLOCK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, 'position.z' present (0 = absent, 1 = present)<br />
|-<br />
| 1<br />
| unsigned, 'color' component present (0 = absent, 1 = present)<br />
|-<br />
| 8<br />
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)<br />
|-<br />
| 9<br />
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)<br />
|-<br />
| 10<br />
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)<br />
|-<br />
| 16<br />
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)<br />
|-<br />
| 24<br />
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)<br />
|}<br />
<br />
This register controls the clock supply to parts relating to certain attributes.<br />
<br />
== Texturing registers ==<br />
<br />
=== GPUREG_TEXUNIT_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| 0x0<br />
|-<br />
| 8-9<br />
| unsigned, Texture 3 coordinates<br />
|-<br />
| 10<br />
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| 0x1<br />
|-<br />
| 13<br />
| unsigned, Texture 2 coordinates<br />
|-<br />
| 16<br />
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)<br />
|-<br />
| 17-31<br />
| 0x0<br />
|}<br />
<br />
This register is used to enable texture units.<br />
<br />
Texture 3 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 0<br />
|-<br />
| 1<br />
| Texture 1<br />
|-<br />
| 2<br />
| Texture 2<br />
|}<br />
<br />
Texture 2 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 2<br />
|-<br />
| 1<br />
| Texture 1<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to set a texture unit's border color.<br />
<br />
=== GPUREG_TEXUNIT''i''_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Height<br />
|-<br />
| 16-26<br />
| unsigned, Width<br />
|}<br />
<br />
This register is used to set a texture unit's dimensions.<br />
<br />
=== GPUREG_TEXUNIT''i''_PARAM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, Magnification filter<br />
|-<br />
| 2<br />
| unsigned, Minification filter<br />
|-<br />
| 4-5<br />
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4<br />
|-<br />
| 8-10<br />
| unsigned, Wrap T<br />
|-<br />
| 12-14<br />
| unsigned, Wrap S<br />
|-<br />
| 16-17<br />
| 0x0<br />
|-<br />
| 20<br />
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)<br />
|-<br />
| 24<br />
| unsigned, Mipmap filter<br />
|-<br />
| 28-30<br />
| unsigned, Type (Texture 0 only)<br />
|}<br />
<br />
This register is used to set a texture unit's extra parameters.<br />
<br />
Filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|}<br />
<br />
Wrap values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to edge<br />
|-<br />
| 1<br />
| Clamp to border<br />
|-<br />
| 2<br />
| Repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|}<br />
<br />
Type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 2D<br />
|-<br />
| 1<br />
| Cube map<br />
|-<br />
| 2<br />
| Shadow 2D<br />
|-<br />
| 3<br />
| Projection<br />
|-<br />
| 4<br />
| Shadow cube<br />
|-<br />
| 5<br />
| Disabled<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_LOD ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.4.8, Bias<br />
|-<br />
| 16-19<br />
| unsigned, Max Level<br />
|-<br />
| 24-27<br />
| unsigned, Min Level<br />
|}<br />
<br />
This register is used to configure a texture unit's level of detail.<br />
<br />
=== GPUREG_TEXUNIT''i''_ADDR''i'' ===<br />
<br />
First ADDR register:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Texture physical address >> 3<br />
|}<br />
<br />
Subsequent ADDR registers:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-21<br />
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)<br />
|}<br />
<br />
This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.<br />
<br />
If the texture is a cube:<br />
<br />
{| class="wikitable" border="1"<br />
! Register<br />
! Description<br />
|-<br />
| ADDR1<br />
| Positive X<br />
|-<br />
| ADDR2<br />
| Negative X<br />
|-<br />
| ADDR3<br />
| Positive Y<br />
|-<br />
| ADDR4<br />
| Negative Y<br />
|-<br />
| ADDR5<br />
| Positive Z<br />
|-<br />
| ADDR6<br />
| Negative Z<br />
|}<br />
<br />
Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.<br />
<br />
=== GPUREG_TEXUNIT''i''_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Perspective (0 = perspective, 1 = not perspective)<br />
|-<br />
| 1-23<br />
| fixed0.0.24, Z bias (upper 23 bits)<br />
|}<br />
<br />
This register is used to set a texture unit's shadow texture properties.<br />
<br />
=== GPUREG_TEXUNIT''i''_TYPE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Format<br />
|}<br />
<br />
This register is used to set a texture unit's data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! GL Format<br />
! GL Data Type<br />
|-<br />
| 0x0<br />
| RGBA8888<br />
| GL_RGBA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x1<br />
| RGB888<br />
| GL_RGB<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x2<br />
| RGBA5551<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_5_5_5_1<br />
|-<br />
| 0x3<br />
| RGB565<br />
| GL_RGB<br />
| GL_UNSIGNED_SHORT_5_6_5<br />
|-<br />
| 0x4<br />
| RGBA4444<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_4_4_4_4<br />
|-<br />
| 0x5<br />
| IA8<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x6<br />
| HILO8<br />
| <br />
| <br />
|-<br />
| 0x7<br />
| I8<br />
| GL_LUMINANCE<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x8<br />
| A8<br />
| GL_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x9<br />
| IA44<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE_4_4_EXT<br />
|-<br />
| 0xA<br />
| I4<br />
| <br />
|<br />
|-<br />
| 0xB<br />
| A4<br />
| GL_ALPHA<br />
| GL_UNSIGNED_NIBBLE_EXT<br />
|-<br />
| 0xC<br />
| ETC1<br />
| GL_ETC1_RGB8_OES<br />
| <br />
|-<br />
| 0xD<br />
| ETC1A4<br />
|<br />
| <br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable lighting.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, U-direction clamp<br />
|-<br />
| 3-5<br />
| unsigned, V-direction clamp<br />
|-<br />
| 6-9<br />
| unsigned, RGB mapping function<br />
|-<br />
| 10-13<br />
| unsigned, Alpha mapping function<br />
|-<br />
| 14<br />
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)<br />
|-<br />
| 15<br />
| unsigned, Noise enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 16-17<br />
| unsigned, U-direction shift<br />
|-<br />
| 18-19<br />
| unsigned, V-direction shift<br />
|-<br />
| 20-27<br />
| float1.5.10, Texture bias (lower 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Clamp values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to zero<br />
|-<br />
| 1<br />
| Clamp to edge<br />
|-<br />
| 2<br />
| Symmetrical repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|-<br />
| 4<br />
| Pulse<br />
|}<br />
<br />
Mapping function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| U<br />
|-<br />
| 1<br />
| U²<br />
|-<br />
| 2<br />
| V<br />
|-<br />
| 3<br />
| V²<br />
|-<br />
| 4<br />
| (U + V) / 2<br />
|-<br />
| 5<br />
| (U² + V²) / 2<br />
|-<br />
| 6<br />
| sqrt(U² + V²)<br />
|-<br />
| 7<br />
| Minimum<br />
|-<br />
| 8<br />
| Maximum<br />
|-<br />
| 9<br />
| Rmax<br />
|}<br />
<br />
Shift values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Odd<br />
|-<br />
| 2<br />
| Even<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, U-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, U-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, V-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX3 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, U-direction noise frequency<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise frequency<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX4 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Minification filter<br />
|-<br />
| 3-10<br />
| 0x60<br />
|-<br />
| 11-18<br />
| unsigned, Texture width<br />
|-<br />
| 19-26<br />
| float1.5.10, Texture bias (upper 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Minification filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|-<br />
| 2<br />
| Nearest, Mipmap Nearest<br />
|-<br />
| 3<br />
| Linear, Mipmap Nearest<br />
|-<br />
| 4<br />
| Nearest, Mipmap Linear<br />
|-<br />
| 5<br />
| Linear, Mipmap Linear<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX5 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Texture offset<br />
|-<br />
| 8-31<br />
| 0xE0C080<br />
|}<br />
<br />
This register is used to set the procedural texture unit's offset.<br />
<br />
=== GPUREG_PROCTEX_LUT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Index<br />
|-<br />
| 8-11<br />
| unsigned, Reference table<br />
|}<br />
<br />
This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.<br />
<br />
Reference table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Noise table<br />
|-<br />
| 2<br />
| RGB mapping function table<br />
|-<br />
| 3<br />
| Alpha mapping function table<br />
|-<br />
| 4<br />
| Color table<br />
|-<br />
| 5<br />
| Color difference table<br />
|}<br />
<br />
=== GPUREG_PROCTEX_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.<br />
<br />
==== Noise Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== RGB Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Alpha Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Color Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
==== Color Difference Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| fixed1.0.7, Red difference between current and next color table elements<br />
|-<br />
| 8-15<br />
| fixed1.0.7, Green difference between current and next color table elements<br />
|-<br />
| 16-23<br />
| fixed1.0.7, Blue difference between current and next color table elements<br />
|-<br />
| 24-31<br />
| fixed1.0.7, Alpha difference between current and next color table elements<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_SOURCE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB source 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB source 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB source 2<br />
|-<br />
| 16-19<br />
| unsigned, Alpha source 0<br />
|-<br />
| 20-23<br />
| unsigned, Alpha source 1<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source 2<br />
|}<br />
<br />
This register configures a texture combiner's sources.<br />
<br />
Source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Primary color<br />
|-<br />
| 1<br />
| Fragment primary color<br />
|-<br />
| 2<br />
| Fragment secondary color<br />
|-<br />
| 3<br />
| Texture 0<br />
|-<br />
| 4<br />
| Texture 1<br />
|-<br />
| 5<br />
| Texture 2<br />
|-<br />
| 6<br />
| Texture 3<br />
|-<br />
| 13<br />
| Previous buffer<br />
|-<br />
| 14<br />
| Constant (from GPUREG_TEXENV''i''_COLOR)<br />
|-<br />
| 15<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_OPERAND ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB operand 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB operand 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB operand 2<br />
|-<br />
| 12-14<br />
| unsigned, Alpha operand 0<br />
|-<br />
| 16-18<br />
| unsigned, Alpha operand 1<br />
|-<br />
| 20-22<br />
| unsigned, Alpha operand 2<br />
|}<br />
<br />
This register configures a texture combiner's operands.<br />
<br />
RGB operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source color<br />
|-<br />
| 1<br />
| One minus source color<br />
|-<br />
| 2<br />
| Source alpha<br />
|-<br />
| 3<br />
| One minus source alpha<br />
|-<br />
| 4<br />
| Source red<br />
|-<br />
| 5<br />
| One minus source red<br />
|-<br />
| 8<br />
| Source green<br />
|-<br />
| 9<br />
| One minus source green<br />
|-<br />
| 12<br />
| Source blue<br />
|-<br />
| 13<br />
| One minus source blue<br />
|}<br />
<br />
Alpha operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source alpha<br />
|-<br />
| 1<br />
| One minus source alpha<br />
|-<br />
| 2<br />
| Source red<br />
|-<br />
| 3<br />
| One minus source red<br />
|-<br />
| 4<br />
| Source green<br />
|-<br />
| 5<br />
| One minus source green<br />
|-<br />
| 6<br />
| Source blue<br />
|-<br />
| 7<br />
| One minus source blue<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COMBINER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB combine<br />
|-<br />
| 16-19<br />
| unsigned, Alpha combine<br />
|}<br />
<br />
This register configures a texture combiner's combine mode.<br />
<br />
Combine values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Replace<br />
|-<br />
| 1<br />
| Modulate<br />
|-<br />
| 2<br />
| Add<br />
|-<br />
| 3<br />
| Add signed<br />
|-<br />
| 4<br />
| Interpolate<br />
|-<br />
| 5<br />
| Subtract<br />
|-<br />
| 6<br />
| Dot3 RGB<br />
|-<br />
| 7<br />
| Dot3 RGBA<br />
|-<br />
| 8<br />
| Multiply then add<br />
|-<br />
| 9<br />
| Add then multiply<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register configures a texture combiner's constant color.<br />
<br />
=== GPUREG_TEXENV''i''_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, RGB scale<br />
|-<br />
| 16-17<br />
| unsigned, Alpha scale<br />
|}<br />
<br />
This register configures a texture combiner's scale value.<br />
<br />
Scale values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|}<br />
<br />
=== GPUREG_TEXENV_UPDATE_BUFFER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fog mode<br />
|-<br />
| 3<br />
| unsigned, Shading density source<br />
|-<br />
| 8<br />
| unsigned, TexEnv 1 RGB buffer input<br />
|-<br />
| 9<br />
| unsigned, TexEnv 2 RGB buffer input<br />
|-<br />
| 10<br />
| unsigned, TexEnv 3 RGB buffer input<br />
|-<br />
| 11<br />
| unsigned, TexEnv 4 RGB buffer input<br />
|-<br />
| 12<br />
| unsigned, TexEnv 1 alpha buffer input<br />
|-<br />
| 13<br />
| unsigned, TexEnv 2 alpha buffer input<br />
|-<br />
| 14<br />
| unsigned, TexEnv 3 alpha buffer input<br />
|-<br />
| 15<br />
| unsigned, TexEnv 4 alpha buffer input<br />
|-<br />
| 16<br />
| unsigned, Z flip (0 = don't flip, 1 = flip)<br />
|-<br />
| 24-25<br />
| 0x0<br />
|}<br />
<br />
This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.<br />
<br />
Fog mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Disabled<br />
|-<br />
| 5<br />
| Fog<br />
|-<br />
| 7<br />
| Gas<br />
|}<br />
<br />
Shading density source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Plain density<br />
|-<br />
| 1<br />
| Depth density<br />
|}<br />
<br />
Buffer input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Previous buffer<br />
|-<br />
| 1<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_FOG_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
This register is used to configure the color of fog.<br />
<br />
=== GPUREG_GAS_ATTENUATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas density attenuation<br />
|}<br />
<br />
This register is used to configure the gas density attenuation.<br />
<br />
=== GPUREG_GAS_ACCMAX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas maximum density accumulation<br />
|}<br />
<br />
This register is used to configure the gas maximum density accumulation.<br />
<br />
=== GPUREG_FOG_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.<br />
<br />
=== GPUREG_FOG_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.<br />
<br />
==== Fog Look-Up Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Difference from next element <br />
|-<br />
| 13-23<br />
| fixed0.0.11, Value<br />
|}<br />
<br />
=== GPUREG_TEXENV_BUFFER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the texture combiner buffer color.<br />
<br />
== Framebuffer registers ==<br />
<br />
=== GPUREG_COLOR_OPERATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Fragment operation mode<br />
|-<br />
| 8<br />
| unsigned, Blend mode<br />
|-<br />
| 16-25<br />
| 0x0E4<br />
|}<br />
<br />
This register is used to configure the fragment operation mode and whether to use logic ops or blending.<br />
<br />
Fragment operation mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Default<br />
|-<br />
| 1<br />
| Gas<br />
|-<br />
| 3<br />
| Shadow<br />
|}<br />
<br />
Blend mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Logic op<br />
|-<br />
| 1<br />
| Blend<br />
|}<br />
<br />
=== GPUREG_BLEND_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, RGB equation<br />
|-<br />
| 8-10<br />
| unsigned, Alpha equation<br />
|-<br />
| 16-19<br />
| unsigned, RGB source function<br />
|-<br />
| 20-23<br />
| unsigned, RGB destination function<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source function<br />
|-<br />
| 28-31<br />
| unsigned, Alpha destination function<br />
|}<br />
<br />
This register is used to configure the blending function.<br />
<br />
Equation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Add<br />
|-<br />
| 1<br />
| Subtract<br />
|-<br />
| 2<br />
| Reverse subtract<br />
|-<br />
| 3<br />
| Minimum<br />
|-<br />
| 4<br />
| Maximum<br />
|}<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Zero<br />
|-<br />
| 1<br />
| One<br />
|-<br />
| 2<br />
| Source color<br />
|-<br />
| 3<br />
| One minus source color<br />
|-<br />
| 4<br />
| Destination color<br />
|-<br />
| 5<br />
| One minus destination color<br />
|-<br />
| 6<br />
| Source alpha<br />
|-<br />
| 7<br />
| One minus source alpha<br />
|-<br />
| 8<br />
| Destination alpha<br />
|-<br />
| 9<br />
| One minus destination alpha<br />
|-<br />
| 10<br />
| Constant color<br />
|-<br />
| 11<br />
| One minus constant color<br />
|-<br />
| 12<br />
| Constant alpha<br />
|-<br />
| 13<br />
| One minus constant alpha<br />
|-<br />
| 14<br />
| Source alpha saturate<br />
|}<br />
<br />
=== GPUREG_LOGIC_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Logic op<br />
|}<br />
<br />
This register is used to configure the logic op.<br />
<br />
Logic op values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clear<br />
|-<br />
| 1<br />
| AND<br />
|-<br />
| 2<br />
| Reverse AND<br />
|-<br />
| 3<br />
| Copy<br />
|-<br />
| 4<br />
| Set<br />
|-<br />
| 5<br />
| Inverted copy<br />
|-<br />
| 6<br />
| Noop<br />
|-<br />
| 7<br />
| Invert<br />
|-<br />
| 8<br />
| NAND<br />
|-<br />
| 9<br />
| OR<br />
|-<br />
| 10<br />
| NOR<br />
|-<br />
| 11<br />
| XOR<br />
|-<br />
| 12<br />
| Equivalent<br />
|-<br />
| 13<br />
| Inverted AND<br />
|-<br />
| 14<br />
| Reverse OR<br />
|-<br />
| 15<br />
| Inverted OR<br />
|}<br />
<br />
=== GPUREG_BLEND_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the blending color.<br />
<br />
=== GPUREG_FRAGOP_ALPHA_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Reference value<br />
|}<br />
<br />
This register is used to configure alpha testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Buffer mask<br />
|-<br />
| 16-23<br />
| signed, Reference value<br />
|-<br />
| 24-31<br />
| unsigned, Mask<br />
|}<br />
<br />
This register is used to configure stencil testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fail operation<br />
|-<br />
| 4-6<br />
| unsigned, Z-fail operation<br />
|-<br />
| 8-10<br />
| unsigned, Z-pass operation<br />
|}<br />
<br />
This register is used to configure stencil result operations.<br />
<br />
Operation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Keep<br />
|-<br />
| 1<br />
| Zero<br />
|-<br />
| 2<br />
| Replace<br />
|-<br />
| 3<br />
| Increment<br />
|-<br />
| 4<br />
| Decrement<br />
|-<br />
| 5<br />
| Invert<br />
|-<br />
| 6<br />
| Increment and wrap<br />
|-<br />
| 7<br />
| Decrement and wrap<br />
|}<br />
<br />
=== GPUREG_DEPTH_COLOR_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Depth function<br />
|-<br />
| 8<br />
| unsigned, Red write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 9<br />
| unsigned, Green write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 10<br />
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 11<br />
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to depth testing and framebuffer write masking.<br />
<br />
Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.<br />
<br />
Depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_FRAMEBUFFER_INVALIDATE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = invalidate)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.<br />
<br />
=== GPUREG_FRAMEBUFFER_FLUSH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = flush)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.<br />
<br />
=== GPUREG_COLORBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow read (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures read access from the color buffer.<br />
<br />
=== GPUREG_COLORBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow write (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures write access to the color buffer.<br />
<br />
=== GPUREG_DEPTHBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil read (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth read (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures read access from the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil write (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth write (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures write access to the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the depth buffer data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit depth<br />
|-<br />
| 2<br />
| 24-bit depth<br />
|-<br />
| 3<br />
| 24-bit depth + 8-bit stencil<br />
|}<br />
<br />
=== GPUREG_COLORBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Pixel size<br />
|-<br />
| 16-18<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.<br />
<br />
Pixel size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit color<br />
|-<br />
| 2<br />
| 32-bit color<br />
|}<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| RGBA8/Gas<br />
|-<br />
| 2<br />
| RGB5A1<br />
|-<br />
| 3<br />
| RGB565<br />
|-<br />
| 4<br />
| RGBA4<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register enables the early depth test.<br />
<br />
=== GPUREG_FRAMEBUFFER_BLOCK32 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Render block mode<br />
|}<br />
<br />
This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.<br />
<br />
Render block mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8x8 blocks<br />
|-<br />
| 1<br />
| 32x32 blocks<br />
|}<br />
<br />
=== GPUREG_DEPTHBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Depth buffer physical address >> 3<br />
|}<br />
<br />
This register configures the depth buffer physical address.<br />
<br />
=== GPUREG_COLORBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Color buffer physical address >> 3<br />
|}<br />
<br />
This register configures the color buffer physical address.<br />
<br />
=== GPUREG_FRAMEBUFFER_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register configures the framebuffer dimensions.<br />
<br />
=== GPUREG_GAS_LIGHT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Planar shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, Planar shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, Planar shading density attenuation<br />
|}<br />
<br />
This register configures gas light planar shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, View shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, View shading density attenuation<br />
|}<br />
<br />
This register configures gas light view shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading effect in line-of-sight direction<br />
|-<br />
| 8<br />
| Gas color LUT input<br />
|}<br />
<br />
This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.<br />
<br />
Color LUT input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Gas density<br />
|-<br />
| 1<br />
| Light factor<br />
|}<br />
<br />
=== GPUREG_GAS_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.<br />
<br />
=== GPUREG_GAS_LUT_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.<br />
<br />
==== Gas Look-Up Table ====<br />
<br />
16 elements:<br />
<br />
First 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| signed, Red<br />
|-<br />
| 8-15<br />
| signed, Green<br />
|-<br />
| 16-23<br />
| signed, Blue<br />
|}<br />
<br />
Last 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
=== GPUREG_GAS_DELTAZ_DEPTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| fixed0.16.8, Depth direction attenuation proportion<br />
|}<br />
<br />
This register is used to configure the gas depth direction attenuation proportion.<br />
<br />
=== GPUREG_FRAGOP_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Sum of penumbra scale and penumbra bias<br />
|-<br />
| 16-31<br />
| float1.5.10, Penumbra scale with reversed sign<br />
|}<br />
<br />
This register is used to configure shadow properties.<br />
<br />
== Fragment lighting registers ==<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR1 ===<br />
<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.<br />
<br />
=== GPUREG_LIGHT''i''_DIFFUSE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.<br />
<br />
=== GPUREG_LIGHT''i''_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.<br />
<br />
=== GPUREG_LIGHT''i''_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, X coordinate<br />
|-<br />
| 16-31<br />
| float1.5.10, Y coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Z coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, X coordinate (negated)<br />
|-<br />
| 16-28<br />
| fixed1.1.11, Y coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Z coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Light type (0 = positional light, 1 = directional light)<br />
|-<br />
| 1<br />
| unsigned, Two side diffuse (0 = one side, 1 = both sides)<br />
|-<br />
| 2<br />
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)<br />
|-<br />
| 3<br />
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures a light's properties.<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation bias<br />
|}<br />
<br />
These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation scale<br />
|}<br />
<br />
These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHTING_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.<br />
<br />
=== GPUREG_LIGHTING_NUM_LIGHTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of active lights - 1<br />
|}<br />
<br />
This register configures the number of active lights.<br />
<br />
=== GPUREG_LIGHTING_CONFIG0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)<br />
|-<br />
| 2-3<br />
| unsigned, Fresnel selector<br />
|-<br />
| 4-7<br />
| unsigned, Light environment configuration<br />
|-<br />
| 8-11<br />
| 0x4<br />
|-<br />
| 16<br />
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 17<br />
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 18<br />
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)<br />
|-<br />
| 19<br />
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)<br />
|-<br />
| 22-23<br />
| unsigned, Bump map texture unit<br />
|-<br />
| 24-25<br />
| unsigned, Shadow map texture unit<br />
|-<br />
| 27<br />
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)<br />
|-<br />
| 28-29<br />
| unsigned, Bump mode<br />
|-<br />
| 30<br />
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)<br />
|-<br />
| 31<br />
| 0x1<br />
|}<br />
<br />
This register configures the light environment.<br />
<br />
Fresnel selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Primary alpha<br />
|-<br />
| 2<br />
| Secondary alpha<br />
|-<br />
| 3<br />
| Primary and secondary alpha<br />
|}<br />
<br />
The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.<br />
<br />
Light environment configuration values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! Available LUTs<br />
|-<br />
| 0<br />
| Configuration 0<br />
| D0, RR, SP, DA<br />
|-<br />
| 1<br />
| Configuration 1<br />
| FR, RR, SP, DA<br />
|-<br />
| 2<br />
| Configuration 2<br />
| D0, D1, RR, DA<br />
|-<br />
| 3<br />
| Configuration 3<br />
| D0, D1, FR, DA<br />
|-<br />
| 4<br />
| Configuration 4<br />
| All except for FR<br />
|-<br />
| 5<br />
| Configuration 5<br />
| All except for D1<br />
|-<br />
| 6<br />
| Configuration 6<br />
| All except for RB and RG<br />
|-<br />
| 8<br />
| Configuration 7<br />
| All<br />
|}<br />
<br />
Bump mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Not used<br />
|-<br />
| 1<br />
| Use as bump map<br />
|-<br />
| 2<br />
| Use as tangent map<br />
|}<br />
<br />
=== GPUREG_LIGHTING_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 1<br />
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 2<br />
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 3<br />
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 4<br />
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 6<br />
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 7<br />
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 8<br />
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 10<br />
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 11<br />
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 12<br />
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 14<br />
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 15<br />
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 16<br />
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 18<br />
| 0x1<br />
|-<br />
| 19<br />
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 20-22<br />
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 21<br />
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 22<br />
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 24<br />
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 26<br />
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 27<br />
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 28<br />
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 29<br />
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 30<br />
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 31<br />
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is used to disable various aspects of the light environment.<br />
<br />
=== GPUREG_LIGHTING_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Starting index<br />
|-<br />
| 8-12<br />
| unsigned, Look-up table<br />
|}<br />
<br />
This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.<br />
<br />
Lookup table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| D0<br />
|-<br />
| 1<br />
| D1<br />
|-<br />
| 3<br />
| FR<br />
|-<br />
| 4<br />
| RB<br />
|-<br />
| 5<br />
| RG<br />
|-<br />
| 6<br />
| RR<br />
|-<br />
| 8-15<br />
| SP0-7<br />
|-<br />
| 16-23<br />
| DA0-7<br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.<br />
<br />
=== GPUREG_LIGHTING_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
Lighting LUT data is written here.<br />
<br />
A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.<br />
<br />
DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.<br />
<br />
Format of an entry:<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Entry value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_ABS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)<br />
|-<br />
| 21<br />
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register controls whether the absolute value of the input is taken before using a LUT.<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SELECT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Input selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Input selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Input selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Input selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Input selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Input selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Input selector for RR<br />
|}<br />
<br />
This register selects the input from LUTs.<br />
<br />
Input selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| N·H<br />
|-<br />
| 1<br />
| V·H<br />
|-<br />
| 2<br />
| N·V<br />
|-<br />
| 3<br />
| L·N<br />
|-<br />
| 4<br />
| -L·P (aka Spotlight aka SP)<br />
|-<br />
| 5<br />
| cos φ (aka CP)<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Scaler selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Scaler selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Scaler selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Scaler selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Scaler selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Scaler selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Scaler selector for RR<br />
|}<br />
<br />
This register controls the scaling that is applied to the output of a LUT.<br />
<br />
Scaler selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|-<br />
| 3<br />
| 8x<br />
|-<br />
| 6<br />
| 0.25x<br />
|-<br />
| 7<br />
| 0.5x<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, ID of the 1st enabled light<br />
|-<br />
| 4-6<br />
| unsigned, ID of the 2nd enabled light<br />
|-<br />
| 8-10<br />
| unsigned, ID of the 3rd enabled light<br />
|-<br />
| 12-14<br />
| unsigned, ID of the 4th enabled light<br />
|-<br />
| 16-18<br />
| unsigned, ID of the 5th enabled light<br />
|-<br />
| 20-22<br />
| unsigned, ID of the 6th enabled light<br />
|-<br />
| 24-26<br />
| unsigned, ID of the 7th enabled light<br />
|-<br />
| 28-30<br />
| unsigned, ID of the 8th enabled light<br />
|}<br />
<br />
This register sets the IDs of enabled light sources.<br />
<br />
== Geometry pipeline registers ==<br />
<br />
=== GPUREG_ATTRIBBUFFERS_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-28<br />
| unsigned, Vertex arrays base address<br />
|}<br />
<br />
This register sets the base address of all vertex arrays.<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 0 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 0 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 1 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 1 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 2 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 2 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 3 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 3 size<br />
|-<br />
| 16-17<br />
| unsigned, Vertex attribute 4 type<br />
|-<br />
| 18-19<br />
| unsigned, Vertex attribute 4 size<br />
|-<br />
| 20-21<br />
| unsigned, Vertex attribute 5 type<br />
|-<br />
| 22-23<br />
| unsigned, Vertex attribute 5 size<br />
|-<br />
| 24-25<br />
| unsigned, Vertex attribute 6 type<br />
|-<br />
| 26-27<br />
| unsigned, Vertex attribute 6 size<br />
|-<br />
| 28-29<br />
| unsigned, Vertex attribute 7 type<br />
|-<br />
| 30-31<br />
| unsigned, Vertex attribute 7 size<br />
|}<br />
<br />
This register configures the types and sizes of the first 8 vertex attributes.<br />
<br />
Vertex attribute type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Byte<br />
|-<br />
| 1<br />
| Unsigned byte<br />
|-<br />
| 2<br />
| Short<br />
|-<br />
| 3<br />
| Float<br />
|}<br />
<br />
Vertex attribute size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8 bits<br />
|-<br />
| 1<br />
| 16 bits<br />
|-<br />
| 2<br />
| 24 bits<br />
|-<br />
| 3<br />
| 32 bits<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 8 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 8 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 9 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 9 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 10 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 10 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 11 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 11 size<br />
|-<br />
| 16-27<br />
| unsigned, Fixed vertex attribute mask<br />
|-<br />
| 28-31<br />
| unsigned, Total vertex attribute count - 1<br />
|}<br />
<br />
This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.<br />
<br />
See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|}<br />
<br />
This register configures the offset of a vertex array from the base vertex arrays address.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 1<br />
|-<br />
| 4-7<br />
| unsigned, Component 2<br />
|-<br />
| 8-11<br />
| unsigned, Component 3<br />
|-<br />
| 12-15<br />
| unsigned, Component 4<br />
|-<br />
| 16-19<br />
| unsigned, Component 5<br />
|-<br />
| 20-23<br />
| unsigned, Component 6<br />
|-<br />
| 24-27<br />
| unsigned, Component 7<br />
|-<br />
| 28-31<br />
| unsigned, Component 8<br />
|}<br />
<br />
This register configures the first 8 component types of a vertex array.<br />
<br />
Component values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Vertex attribute 0<br />
|-<br />
| 1<br />
| Vertex attribute 1<br />
|-<br />
| 2<br />
| Vertex attribute 2<br />
|-<br />
| 3<br />
| Vertex attribute 3<br />
|-<br />
| 4<br />
| Vertex attribute 4<br />
|-<br />
| 5<br />
| Vertex attribute 5<br />
|-<br />
| 6<br />
| Vertex attribute 6<br />
|-<br />
| 7<br />
| Vertex attribute 7<br />
|-<br />
| 8<br />
| Vertex attribute 8<br />
|-<br />
| 9<br />
| Vertex attribute 9<br />
|-<br />
| 10<br />
| Vertex attribute 10<br />
|-<br />
| 11<br />
| Vertex attribute 11<br />
|-<br />
| 12<br />
| 4-byte padding<br />
|-<br />
| 13<br />
| 8-byte padding<br />
|-<br />
| 14<br />
| 12-byte padding<br />
|-<br />
| 15<br />
| 16-byte padding<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 9<br />
|-<br />
| 4-7<br />
| unsigned, Component 10<br />
|-<br />
| 8-11<br />
| unsigned, Component 11<br />
|-<br />
| 12-15<br />
| unsigned, Component 12<br />
|-<br />
| 16-23<br />
| unsigned, Bytes per vertex<br />
|-<br />
| 28-31<br />
| unsigned, Total number of components<br />
|}<br />
<br />
This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.<br />
<br />
See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.<br />
<br />
=== GPUREG_INDEXBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|-<br />
| 31<br />
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)<br />
|}<br />
<br />
This register configures the index array used when drawing elements.<br />
<br />
=== GPUREG_NUMVERTICES ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Number of vertices to render<br />
|}<br />
<br />
This register sets the number of vertices to render.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|-<br />
| 9<br />
| 0x0<br />
|-<br />
| 31<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_VERTEX_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Starting vertex offset<br />
|}<br />
<br />
This register sets the offset of the first vertex in an array to render.<br />
<br />
=== GPUREG_POST_VERTEX_CACHE_NUM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)<br />
|}<br />
<br />
This register configures the post-vertex cache.<br />
<br />
=== GPUREG_DRAWARRAYS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw arrays)<br />
|}<br />
<br />
This register triggers drawing vertex arrays.<br />
<br />
=== GPUREG_DRAWELEMENTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw elements)<br />
|}<br />
<br />
This register triggers drawing vertex array elements.<br />
<br />
=== GPUREG_VTX_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)<br />
|}<br />
<br />
This register triggers clearing the post-vertex cache.<br />
<br />
=== GPUREG_FIXEDATTRIB_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)<br />
|}<br />
<br />
This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.<br />
<br />
=== GPUREG_FIXEDATTRIB_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| colspan="2" | '''DATA0:'''<br />
|-<br />
| 0-7<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)<br />
|-<br />
| 8-31<br />
| float1.7.16, Vertex attribute element 4 (W)<br />
|-<br />
| colspan="2" | '''DATA1:'''<br />
|-<br />
| 0-15<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)<br />
|-<br />
| 16-31<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)<br />
|-<br />
| colspan="2" | '''DATA2:'''<br />
|-<br />
| 0-23<br />
| float1.7.16, Vertex attribute element 1 (X)<br />
|-<br />
| 24-31<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)<br />
|}<br />
<br />
Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.<br />
<br />
=== GPUREG_CMDBUF_SIZE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the size of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_SIZE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the size of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the physical address of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the physical address of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)<br />
|}<br />
<br />
This register triggers a jump to the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)<br />
|}<br />
<br />
This register triggers a jump to the second command buffer.<br />
<br />
=== GPUREG_VSH_NUM_ATTR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader input attributes - 1<br />
|}<br />
<br />
This register sets the number of vertex shader input attributes.<br />
<br />
=== GPUREG_VSH_COM_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.<br />
<br />
=== GPUREG_START_DRAW_FUNC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Mode (0 = drawing, 1 = configuration)<br />
|-<br />
| 1-7<br />
| 0x0<br />
|}<br />
<br />
This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_GSH_MISC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)<br />
|}<br />
<br />
This register configures miscellaneous geometry shader properties.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_GSH_MISC1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)<br />
|}<br />
<br />
This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.<br />
<br />
=== GPUREG_PRIMITIVE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|-<br />
| 8-9<br />
| unsigned, Primitive mode<br />
|}<br />
<br />
This register configures primitive drawing.<br />
<br />
Primitive mode value:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Triangles<br />
|-<br />
| 1<br />
| Triangle strip<br />
|-<br />
| 2<br />
| Triangle fan<br />
|-<br />
| 3<br />
| Geometry primitive<br />
|}<br />
<br />
=== GPUREG_RESTART_PRIMITIVE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = reset primitive)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
This register triggers resetting primitive drawing.<br />
<br />
== Shader registers ==<br />
<br />
=== GPUREG_''SH''_BOOLUNIFORM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Boolean register b0 value (0 = false, 1 = true)<br />
|-<br />
| 1<br />
| unsigned, Boolean register b1 value (0 = false, 1 = true)<br />
|-<br />
| 2<br />
| unsigned, Boolean register b2 value (0 = false, 1 = true)<br />
|-<br />
| 3<br />
| unsigned, Boolean register b3 value (0 = false, 1 = true)<br />
|-<br />
| 4<br />
| unsigned, Boolean register b4 value (0 = false, 1 = true)<br />
|-<br />
| 5<br />
| unsigned, Boolean register b5 value (0 = false, 1 = true)<br />
|-<br />
| 6<br />
| unsigned, Boolean register b6 value (0 = false, 1 = true)<br />
|-<br />
| 7<br />
| unsigned, Boolean register b7 value (0 = false, 1 = true)<br />
|-<br />
| 8<br />
| unsigned, Boolean register b8 value (0 = false, 1 = true)<br />
|-<br />
| 9<br />
| unsigned, Boolean register b9 value (0 = false, 1 = true)<br />
|-<br />
| 10<br />
| unsigned, Boolean register b10 value (0 = false, 1 = true)<br />
|-<br />
| 11<br />
| unsigned, Boolean register b11 value (0 = false, 1 = true)<br />
|-<br />
| 12<br />
| unsigned, Boolean register b12 value (0 = false, 1 = true)<br />
|-<br />
| 13<br />
| unsigned, Boolean register b13 value (0 = false, 1 = true)<br />
|-<br />
| 14<br />
| unsigned, Boolean register b14 value (0 = false, 1 = true)<br />
|-<br />
| 15<br />
| unsigned, Boolean register b15 value (0 = false, 1 = true)<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register is used to set a shader unit's boolean registers.<br />
<br />
=== GPUREG_''SH''_INTUNIFORM_I''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Integer register i''i'' X value<br />
|-<br />
| 8-15<br />
| unsigned, Integer register i''i'' Y value<br />
|-<br />
| 16-23<br />
| unsigned, Integer register i''i'' Z value<br />
|-<br />
| 24-31<br />
| unsigned, Integer register i''i'' W value<br />
|}<br />
<br />
These registers are used to set a shader unit's integer registers.<br />
<br />
=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Input vertex attributes - 1<br />
|-<br />
| 8-15<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)<br />
|-<br />
| 16-23<br />
| 0x0<br />
|-<br />
| 24-31<br />
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)<br />
|}<br />
<br />
This register is used to configure a shader unit's input buffer.<br />
<br />
=== GPUREG_''SH''_ENTRYPOINT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Code entry point offset, in 32-bit words<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register sets a shader unit's code entry point.<br />
<br />
For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.<br />
<br />
For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them. <br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 0 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 1 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 2 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 3 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 4 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 5 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 6 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 7 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.<br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 8 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 9 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 10 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 11 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 12 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 13 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 14 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 15 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.<br />
<br />
=== GPUREG_''SH''_OUTMAP_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4<br />
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 5<br />
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 6<br />
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 7<br />
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 8<br />
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 9<br />
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 10<br />
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 11<br />
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 12<br />
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 13<br />
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 14<br />
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 15<br />
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 16-31<br />
| 0x0<br />
|}<br />
<br />
This register toggles a shader unit's output registers.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_END ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Signal transfer end (0 = idle, non-zero = signal)<br />
|}<br />
<br />
This register's value should be set to 1 in order to finalize the transfer of shader code.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)<br />
|-<br />
| 31<br />
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)<br />
|}<br />
<br />
This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| Floating-point register component data<br />
|}<br />
<br />
This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].<br />
<br />
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:<br />
** first word : ZZWWWWWW<br />
** second word : YYYYZZZZ<br />
** third word : XXXXXXYY<br />
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader code offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader instruction data<br />
|}<br />
<br />
This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.<br />
<br />
=== GPUREG_''SH''_OPDESCS_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader operand descriptor offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_OPDESCS_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader operand descriptor data<br />
|}<br />
<br />
This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=GPU/Internal_Registers&diff=19807
GPU/Internal Registers
2017-04-08T10:45:42Z
<p>Plutooo: Reverted edits by Plutooo (talk) to last revision by Fincs</p>
<hr />
<div>[[Category:GPU]]<br />
<br />
== Overview ==<br />
<br />
GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.<br />
<br />
Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).<br />
<br />
In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.<br />
<br />
For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).<br />
<br />
Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.<br />
<br />
The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.<br />
<br />
=== Command Header ===<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0-15<br />
| Command ID<br />
|-<br />
| 16-19<br />
| Parameter mask<br />
|-<br />
| 20-30<br />
| Number of extra parameters (may be zero)<br />
|-<br />
| 31<br />
| Consecutive writing mode<br />
|}<br />
<br />
=== Parameter masking ===<br />
<br />
Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.<br />
<br />
=== Types ===<br />
<br />
There are three main types of registers :<br />
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])<br />
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])<br />
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])<br />
<br />
=== Aliases ===<br />
<br />
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]<br />
<br />
=== Data Types ===<br />
<br />
{| class="wikitable" border="1"<br />
! Name<br />
! Description<br />
|-<br />
| signed<br />
| Signed integer<br />
|-<br />
| unsigned<br />
| Unsigned integer<br />
|-<br />
| floatX.Y.Z<br />
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits<br />
|-<br />
| fixedX.Y.Z<br />
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits<br />
|}<br />
<br />
== Register list ==<br />
<br />
=== Miscellaneous registers (0x000-0x03F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0000<br />
| [[#GPUREG_0000|GPUREG_0000]]<br />
| <br />
|<br />
|-<br />
| 0001<br />
| [[#GPUREG_0001|GPUREG_0001]]<br />
| <br />
|<br />
|-<br />
| 0002<br />
| [[#GPUREG_0002|GPUREG_0002]]<br />
| <br />
|<br />
|-<br />
| 0003<br />
| [[#GPUREG_0003|GPUREG_0003]]<br />
| <br />
|<br />
|-<br />
| 0004<br />
| [[#GPUREG_0004|GPUREG_0004]]<br />
| <br />
|<br />
|-<br />
| 0005<br />
| [[#GPUREG_0005|GPUREG_0005]]<br />
| <br />
|<br />
|-<br />
| 0006<br />
| [[#GPUREG_0006|GPUREG_0006]]<br />
| <br />
|<br />
|-<br />
| 0007<br />
| [[#GPUREG_0007|GPUREG_0007]]<br />
| <br />
|<br />
|-<br />
| 0008<br />
| [[#GPUREG_0008|GPUREG_0008]]<br />
| <br />
|<br />
|-<br />
| 0009<br />
| [[#GPUREG_0009|GPUREG_0009]]<br />
| <br />
|<br />
|-<br />
| 000A<br />
| [[#GPUREG_000A|GPUREG_000A]]<br />
| <br />
|<br />
|-<br />
| 000B<br />
| [[#GPUREG_000B|GPUREG_000B]]<br />
| <br />
|<br />
|-<br />
| 000C<br />
| [[#GPUREG_000C|GPUREG_000C]]<br />
| <br />
|<br />
|-<br />
| 000D<br />
| [[#GPUREG_000D|GPUREG_000D]]<br />
| <br />
|<br />
|-<br />
| 000E<br />
| [[#GPUREG_000E|GPUREG_000E]]<br />
| <br />
|<br />
|-<br />
| 000F<br />
| [[#GPUREG_000F|GPUREG_000F]]<br />
| <br />
|<br />
|-<br />
| 0010<br />
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]<br />
| <br />
|PICA_REG_INTERRUPT<br />
|-<br />
| 0011<br />
| [[#GPUREG_0011|GPUREG_0011]]<br />
| <br />
|<br />
|-<br />
| 0012<br />
| [[#GPUREG_0012|GPUREG_0012]]<br />
| <br />
|<br />
|-<br />
| 0013<br />
| [[#GPUREG_0013|GPUREG_0013]]<br />
| <br />
|<br />
|-<br />
| 0014<br />
| [[#GPUREG_0014|GPUREG_0014]]<br />
| <br />
|<br />
|-<br />
| 0015<br />
| [[#GPUREG_0015|GPUREG_0015]]<br />
| <br />
|<br />
|-<br />
| 0016<br />
| [[#GPUREG_0016|GPUREG_0016]]<br />
| <br />
|<br />
|-<br />
| 0017<br />
| [[#GPUREG_0017|GPUREG_0017]]<br />
| <br />
|<br />
|-<br />
| 0018<br />
| [[#GPUREG_0018|GPUREG_0018]]<br />
| <br />
|<br />
|-<br />
| 0019<br />
| [[#GPUREG_0019|GPUREG_0019]]<br />
| <br />
|<br />
|-<br />
| 001A<br />
| [[#GPUREG_001A|GPUREG_001A]]<br />
| <br />
|<br />
|-<br />
| 001B<br />
| [[#GPUREG_001B|GPUREG_001B]]<br />
| <br />
|<br />
|-<br />
| 001C<br />
| [[#GPUREG_001C|GPUREG_001C]]<br />
| <br />
|<br />
|-<br />
| 001D<br />
| [[#GPUREG_001D|GPUREG_001D]]<br />
| <br />
|<br />
|-<br />
| 001E<br />
| [[#GPUREG_001E|GPUREG_001E]]<br />
| <br />
|<br />
|-<br />
| 001F<br />
| [[#GPUREG_001F|GPUREG_001F]]<br />
| <br />
|<br />
|-<br />
| 0020<br />
| [[#GPUREG_0020|GPUREG_0020]]<br />
| <br />
|<br />
|-<br />
| 0021<br />
| [[#GPUREG_0021|GPUREG_0021]]<br />
| <br />
|<br />
|-<br />
| 0022<br />
| [[#GPUREG_0022|GPUREG_0022]]<br />
| <br />
|<br />
|-<br />
| 0023<br />
| [[#GPUREG_0023|GPUREG_0023]]<br />
| <br />
|<br />
|-<br />
| 0024<br />
| [[#GPUREG_0024|GPUREG_0024]]<br />
| <br />
|<br />
|-<br />
| 0025<br />
| [[#GPUREG_0025|GPUREG_0025]]<br />
| <br />
|<br />
|-<br />
| 0026<br />
| [[#GPUREG_0026|GPUREG_0026]]<br />
| <br />
|<br />
|-<br />
| 0027<br />
| [[#GPUREG_0027|GPUREG_0027]]<br />
| <br />
|<br />
|-<br />
| 0028<br />
| [[#GPUREG_0028|GPUREG_0028]]<br />
| <br />
|<br />
|-<br />
| 0029<br />
| [[#GPUREG_0029|GPUREG_0029]]<br />
| <br />
|<br />
|-<br />
| 002A<br />
| [[#GPUREG_002A|GPUREG_002A]]<br />
| <br />
|<br />
|-<br />
| 002B<br />
| [[#GPUREG_002B|GPUREG_002B]]<br />
| <br />
|<br />
|-<br />
| 002C<br />
| [[#GPUREG_002C|GPUREG_002C]]<br />
| <br />
|<br />
|-<br />
| 002D<br />
| [[#GPUREG_002D|GPUREG_002D]]<br />
| <br />
|<br />
|-<br />
| 002E<br />
| [[#GPUREG_002E|GPUREG_002E]]<br />
| <br />
|<br />
|-<br />
| 002F<br />
| [[#GPUREG_002F|GPUREG_002F]]<br />
| <br />
|<br />
|-<br />
| 0030<br />
| [[#GPUREG_0030|GPUREG_0030]]<br />
| <br />
|<br />
|-<br />
| 0031<br />
| [[#GPUREG_0031|GPUREG_0031]]<br />
| <br />
|<br />
|-<br />
| 0032<br />
| [[#GPUREG_0032|GPUREG_0032]]<br />
| <br />
|<br />
|-<br />
| 0033<br />
| [[#GPUREG_0033|GPUREG_0033]]<br />
| <br />
|<br />
|-<br />
| 0034<br />
| [[#GPUREG_0034|GPUREG_0034]]<br />
| <br />
|<br />
|-<br />
| 0035<br />
| [[#GPUREG_0035|GPUREG_0035]]<br />
| <br />
|<br />
|-<br />
| 0036<br />
| [[#GPUREG_0036|GPUREG_0036]]<br />
| <br />
|<br />
|-<br />
| 0037<br />
| [[#GPUREG_0037|GPUREG_0037]]<br />
| <br />
|<br />
|-<br />
| 0038<br />
| [[#GPUREG_0038|GPUREG_0038]]<br />
| <br />
|<br />
|-<br />
| 0039<br />
| [[#GPUREG_0039|GPUREG_0039]]<br />
| <br />
|<br />
|-<br />
| 003A<br />
| [[#GPUREG_003A|GPUREG_003A]]<br />
| <br />
|<br />
|-<br />
| 003B<br />
| [[#GPUREG_003B|GPUREG_003B]]<br />
| <br />
|<br />
|-<br />
| 003C<br />
| [[#GPUREG_003C|GPUREG_003C]]<br />
| <br />
|<br />
|-<br />
| 003D<br />
| [[#GPUREG_003D|GPUREG_003D]]<br />
| <br />
|<br />
|-<br />
| 003E<br />
| [[#GPUREG_003E|GPUREG_003E]]<br />
| <br />
|<br />
|-<br />
| 003F<br />
| [[#GPUREG_003F|GPUREG_003F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Rasterizer registers (0x040-0x07F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0040<br />
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]<br />
| <br />
|PICA_REG_CULL_FACE<br />
|-<br />
| 0041<br />
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH1<br />
|-<br />
| 0042<br />
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH2<br />
|-<br />
| 0043<br />
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT1<br />
|-<br />
| 0044<br />
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT2<br />
|-<br />
| 0045<br />
| [[#GPUREG_0045|GPUREG_0045]]<br />
| <br />
|<br />
|-<br />
| 0046<br />
| [[#GPUREG_0046|GPUREG_0046]]<br />
| <br />
|<br />
|-<br />
| 0047<br />
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP<br />
|-<br />
| 0048<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]<br />
|? <br />
|PICA_REG_FRAGOP_CLIP_DATA1<br />
|-<br />
| 0049<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA2<br />
|-<br />
| 004A<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA3<br />
|-<br />
| 004B<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA4<br />
|-<br />
| 004C<br />
| [[#GPUREG_004C|GPUREG_004C]]<br />
| <br />
|<br />
|-<br />
| 004D<br />
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA1<br />
|-<br />
| 004E<br />
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA2<br />
|-<br />
| 004F<br />
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]<br />
| <br />
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0<br />
|-<br />
| 0050<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0<br />
|-<br />
| 0051<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1<br />
|-<br />
| 0052<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2<br />
|-<br />
| 0053<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3<br />
|-<br />
| 0054<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4<br />
|-<br />
| 0055<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5<br />
|-<br />
| 0056<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6<br />
|-<br />
| 0057<br />
| [[#GPUREG_0057|GPUREG_0057]]<br />
| <br />
|<br />
|-<br />
| 0058<br />
| [[#GPUREG_0058|GPUREG_0058]]<br />
| <br />
|<br />
|-<br />
| 0059<br />
| [[#GPUREG_0059|GPUREG_0059]]<br />
| <br />
|<br />
|-<br />
| 005A<br />
| [[#GPUREG_005A|GPUREG_005A]]<br />
| <br />
|<br />
|-<br />
| 005B<br />
| [[#GPUREG_005B|GPUREG_005B]]<br />
| <br />
|<br />
|-<br />
| 005C<br />
| [[#GPUREG_005C|GPUREG_005C]]<br />
| <br />
|<br />
|-<br />
| 005D<br />
| [[#GPUREG_005D|GPUREG_005D]]<br />
| <br />
|<br />
|-<br />
| 005E<br />
| [[#GPUREG_005E|GPUREG_005E]]<br />
| <br />
|<br />
|-<br />
| 005F<br />
| [[#GPUREG_005F|GPUREG_005F]]<br />
| <br />
|<br />
|-<br />
| 0060<br />
| [[#GPUREG_0060|GPUREG_0060]]<br />
| <br />
|<br />
|-<br />
| 0061<br />
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_FUNC<br />
|-<br />
| 0062<br />
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST1<br />
|-<br />
| 0063<br />
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]<br />
| <br />
|PICA_REG_EARLY_DEPTH_CLEAR<br />
|-<br />
| 0064<br />
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE<br />
|-<br />
| 0065<br />
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]<br />
| <br />
|PICA_REG_SCISSOR<br />
|-<br />
| 0066<br />
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]<br />
| <br />
|PICA_REG_SCISSOR_XY<br />
|-<br />
| 0067<br />
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]<br />
| <br />
|PICA_REG_SCISSOR_SIZE<br />
|-<br />
| 0068<br />
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]<br />
|<br />
|PICA_REG_VIEWPORT_XY<br />
|-<br />
| 0069<br />
| [[#GPUREG_0069|GPUREG_0069]]<br />
| <br />
|<br />
|-<br />
| 006A<br />
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]<br />
|<br />
|PICA_REG_EARLY_DEPTH_DATA<br />
|-<br />
| 006B<br />
| [[#GPUREG_006B|GPUREG_006B]]<br />
| <br />
|<br />
|-<br />
| 006C<br />
| [[#GPUREG_006C|GPUREG_006C]]<br />
| <br />
|<br />
|-<br />
| 006D<br />
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]<br />
|?<br />
|PICA_REG_FRAGOP_WSCALE<br />
|-<br />
| 006E<br />
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]<br />
|?<br />
|PICA_REG_RENDER_BUF_RESOLUTION1<br />
|-<br />
| 006F<br />
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK<br />
|-<br />
| 0070<br />
| [[#GPUREG_0070|GPUREG_0070]]<br />
| <br />
|<br />
|-<br />
| 0071<br />
| [[#GPUREG_0071|GPUREG_0071]]<br />
| <br />
|<br />
|-<br />
| 0072<br />
| [[#GPUREG_0072|GPUREG_0072]]<br />
| <br />
|<br />
|-<br />
| 0073<br />
| [[#GPUREG_0073|GPUREG_0073]]<br />
| <br />
|<br />
|-<br />
| 0074<br />
| [[#GPUREG_0074|GPUREG_0074]]<br />
| <br />
|<br />
|-<br />
| 0075<br />
| [[#GPUREG_0075|GPUREG_0075]]<br />
| <br />
|<br />
|-<br />
| 0076<br />
| [[#GPUREG_0076|GPUREG_0076]]<br />
| <br />
|<br />
|-<br />
| 0077<br />
| [[#GPUREG_0077|GPUREG_0077]]<br />
| <br />
|<br />
|-<br />
| 0078<br />
| [[#GPUREG_0078|GPUREG_0078]]<br />
| <br />
|<br />
|-<br />
| 0079<br />
| [[#GPUREG_0079|GPUREG_0079]]<br />
| <br />
|<br />
|-<br />
| 007A<br />
| [[#GPUREG_007A|GPUREG_007A]]<br />
| <br />
|<br />
|-<br />
| 007B<br />
| [[#GPUREG_007B|GPUREG_007B]]<br />
| <br />
|<br />
|-<br />
| 007C<br />
| [[#GPUREG_007C|GPUREG_007C]]<br />
| <br />
|<br />
|-<br />
| 007D<br />
| [[#GPUREG_007D|GPUREG_007D]]<br />
| <br />
|<br />
|-<br />
| 007E<br />
| [[#GPUREG_007E|GPUREG_007E]]<br />
| <br />
|<br />
|-<br />
| 007F<br />
| [[#GPUREG_007F|GPUREG_007F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Texturing registers (0x080-0x0FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0080<br />
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]<br />
|<br />
|PICA_REG_TEXTURE_FUNC<br />
|-<br />
| 0081<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE0_BORDER_COLOR<br />
|-<br />
| 0082<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]<br />
|<br />
|PICA_REG_TEXTURE0_SIZE<br />
|-<br />
| 0083<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE0_WRAP_FILTER<br />
|-<br />
| 0084<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE0_LOD<br />
|-<br />
| 0085<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR1<br />
|-<br />
| 0086<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR2<br />
|-<br />
| 0087<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR3<br />
|-<br />
| 0088<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR4<br />
|-<br />
| 0089<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR5<br />
|-<br />
| 008A<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR6<br />
|-<br />
| 008B<br />
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]<br />
|?<br />
|PICA_REG_TEXTURE0_SHADOW<br />
|-<br />
| 008C<br />
| [[#GPUREG_008C|GPUREG_008C]]<br />
|<br />
|<br />
|-<br />
| 008D<br />
| [[#GPUREG_008D|GPUREG_008D]]<br />
|<br />
|<br />
|-<br />
| 008E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]<br />
|?<br />
|PICA_REG_TEXTURE0_FORMAT<br />
|-<br />
| 008F<br />
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN0<br />
|-<br />
| 0090<br />
| [[#GPUREG_0090|GPUREG_0090]]<br />
| <br />
|<br />
|-<br />
| 0091<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE1_BORDER_COLOR<br />
|-<br />
| 0092<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]<br />
| <br />
|PICA_REG_TEXTURE1_SIZE<br />
|-<br />
| 0093<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE1_WRAP_FILTER<br />
|-<br />
| 0094<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE1_LOD<br />
|-<br />
| 0095<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]<br />
| <br />
|PICA_REG_TEXTURE1_ADDR<br />
|-<br />
| 0096<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE1_FORMAT<br />
|-<br />
| 0097<br />
| [[#GPUREG_0097|GPUREG_0097]]<br />
| <br />
|<br />
|-<br />
| 0098<br />
| [[#GPUREG_0098|GPUREG_0098]]<br />
| <br />
|<br />
|-<br />
| 0099<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE2_BORDER_COLOR<br />
|-<br />
| 009A<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]<br />
| <br />
|PICA_REG_TEXTURE2_SIZE<br />
|-<br />
| 009B<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE2_WRAP_FILTER<br />
|-<br />
| 009C<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE2_LOD<br />
|-<br />
| 009D<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]<br />
|<br />
|PICA_REG_TEXTURE2_ADDR<br />
|-<br />
| 009E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE2_FORMAT<br />
|-<br />
| 009F<br />
| [[#GPUREG_009F|GPUREG_009F]]<br />
| <br />
|<br />
|-<br />
| 00A0<br />
| [[#GPUREG_00A0|GPUREG_00A0]]<br />
| <br />
|<br />
|-<br />
| 00A1<br />
| [[#GPUREG_00A1|GPUREG_00A1]]<br />
| <br />
|<br />
|-<br />
| 00A2<br />
| [[#GPUREG_00A2|GPUREG_00A2]]<br />
| <br />
|<br />
|-<br />
| 00A3<br />
| [[#GPUREG_00A3|GPUREG_00A3]]<br />
| <br />
|<br />
|-<br />
| 00A4<br />
| [[#GPUREG_00A4|GPUREG_00A4]]<br />
| <br />
|<br />
|-<br />
| 00A5<br />
| [[#GPUREG_00A5|GPUREG_00A5]]<br />
| <br />
|<br />
|-<br />
| 00A6<br />
| [[#GPUREG_00A6|GPUREG_00A6]]<br />
| <br />
|<br />
|-<br />
| 00A7<br />
| [[#GPUREG_00A7|GPUREG_00A7]]<br />
| <br />
|<br />
|-<br />
| 00A8<br />
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX0<br />
|-<br />
| 00A9<br />
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX1<br />
|-<br />
| 00AA<br />
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]<br />
|? <br />
|PICA_REG_TEXTURE3_PROCTEX2<br />
|-<br />
| 00AB<br />
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX3<br />
|-<br />
| 00AC<br />
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX4<br />
|-<br />
| 00AD<br />
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX5<br />
|-<br />
| 00AE<br />
| [[#GPUREG_00AE|GPUREG_00AE]]<br />
| <br />
|<br />
|-<br />
| 00AF<br />
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]<br />
|?<br />
|PICA_REG_PROCTEX_LUT<br />
|-<br />
| 00B0<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA0<br />
|-<br />
| 00B1<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA1<br />
|-<br />
| 00B2<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA2<br />
|-<br />
| 00B3<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA3<br />
|-<br />
| 00B4<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA4<br />
|-<br />
| 00B5<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA5<br />
|-<br />
| 00B6<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA6<br />
|-<br />
| 00B7<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA7<br />
|-<br />
| 00B8<br />
| [[#GPUREG_00B8|GPUREG_00B8]]<br />
| <br />
|<br />
|-<br />
| 00B9<br />
| [[#GPUREG_00B9|GPUREG_00B9]]<br />
| <br />
|<br />
|-<br />
| 00BA<br />
| [[#GPUREG_00BA|GPUREG_00BA]]<br />
| <br />
|<br />
|-<br />
| 00BB<br />
| [[#GPUREG_00BB|GPUREG_00BB]]<br />
| <br />
|<br />
|-<br />
| 00BC<br />
| [[#GPUREG_00BC|GPUREG_00BC]]<br />
| <br />
|<br />
|-<br />
| 00BD<br />
| [[#GPUREG_00BD|GPUREG_00BD]]<br />
| <br />
|<br />
|-<br />
| 00BE<br />
| [[#GPUREG_00BE|GPUREG_00BE]]<br />
| <br />
|<br />
|-<br />
| 00BF<br />
| [[#GPUREG_00BF|GPUREG_00BF]]<br />
| <br />
|<br />
|-<br />
| 00C0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_0<br />
|-<br />
| 00C1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_0_OPERAND<br />
|-<br />
| 00C2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COMBINE<br />
|-<br />
| 00C3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COLOR<br />
|-<br />
| 00C4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_0_SCALE<br />
|-<br />
| 00C5<br />
| [[#GPUREG_00C5|GPUREG_00C5]]<br />
| <br />
|<br />
|-<br />
| 00C6<br />
| [[#GPUREG_00C6|GPUREG_00C6]]<br />
| <br />
|<br />
|-<br />
| 00C7<br />
| [[#GPUREG_00C7|GPUREG_00C7]]<br />
| <br />
|<br />
|-<br />
| 00C8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_1<br />
|-<br />
| 00C9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_1_OPERAND<br />
|-<br />
| 00CA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COMBINE<br />
|-<br />
| 00CB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COLOR<br />
|-<br />
| 00CC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_1_SCALE<br />
|-<br />
| 00CD<br />
| [[#GPUREG_00CD|GPUREG_00CD]]<br />
| <br />
|<br />
|-<br />
| 00CE<br />
| [[#GPUREG_00CE|GPUREG_00CE]]<br />
| <br />
|<br />
|-<br />
| 00CF<br />
| [[#GPUREG_00CF|GPUREG_00CF]]<br />
| <br />
|<br />
|-<br />
| 00D0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_2<br />
|-<br />
| 00D1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_2_OPERAND<br />
|-<br />
| 00D2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COMBINE<br />
|-<br />
| 00D3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COLOR<br />
|-<br />
| 00D4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_2_SCALE<br />
|-<br />
| 00D5<br />
| [[#GPUREG_00D5|GPUREG_00D5]]<br />
| <br />
|<br />
|-<br />
| 00D6<br />
| [[#GPUREG_00D6|GPUREG_00D6]]<br />
| <br />
|<br />
|-<br />
| 00D7<br />
| [[#GPUREG_00D7|GPUREG_00D7]]<br />
| <br />
|<br />
|-<br />
| 00D8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_3<br />
|-<br />
| 00D9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_3_OPERAND<br />
|-<br />
| 00DA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COMBINE<br />
|-<br />
| 00DB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COLOR<br />
|-<br />
| 00DC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_3_SCALE<br />
|-<br />
| 00DD<br />
| [[#GPUREG_00DD|GPUREG_00DD]]<br />
| <br />
|<br />
|-<br />
| 00DE<br />
| [[#GPUREG_00DE|GPUREG_00DE]]<br />
| <br />
|<br />
|-<br />
| 00DF<br />
| [[#GPUREG_00DF|GPUREG_00DF]]<br />
| <br />
|<br />
|-<br />
| 00E0<br />
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]<br />
|?<br />
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT<br />
|-<br />
| 00E1<br />
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]<br />
|?<br />
|PICA_REG_FOG_COLOR<br />
|-<br />
| 00E2<br />
| [[#GPUREG_00E2|GPUREG_00E2]]<br />
| <br />
|<br />
|-<br />
| 00E3<br />
| [[#GPUREG_00E3|GPUREG_00E3]]<br />
| <br />
|<br />
|-<br />
| 00E4<br />
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]<br />
|?<br />
|PICA_REG_GAS_ATTENUATION<br />
|-<br />
| 00E5<br />
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]<br />
|?<br />
|PICA_REG_GAS_ACCMAX<br />
|-<br />
| 00E6<br />
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FOG_LUT_INDEX<br />
|-<br />
| 00E7<br />
| [[#GPUREG_00E7|GPUREG_00E7]]<br />
| <br />
|<br />
|-<br />
| 00E8<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA0<br />
|-<br />
| 00E9<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]<br />
|? <br />
|PICA_REG_FOG_LUT_DATA1<br />
|-<br />
| 00EA<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA2<br />
|-<br />
| 00EB<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA3<br />
|-<br />
| 00EC<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA4<br />
|-<br />
| 00ED<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA5<br />
|-<br />
| 00EE<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA6<br />
|-<br />
| 00EF<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA7<br />
|-<br />
| 00F0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_4<br />
|-<br />
| 00F1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_4_OPERAND<br />
|-<br />
| 00F2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COMBINE<br />
|-<br />
| 00F3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COLOR<br />
|-<br />
| 00F4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_4_SCALE<br />
|-<br />
| 00F5<br />
| [[#GPUREG_00F5|GPUREG_00F5]]<br />
| <br />
|<br />
|-<br />
| 00F6<br />
| [[#GPUREG_00F6|GPUREG_00F6]]<br />
| <br />
|<br />
|-<br />
| 00F7<br />
| [[#GPUREG_00F7|GPUREG_00F7]]<br />
| <br />
|<br />
|-<br />
| 00F8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_5<br />
|-<br />
| 00F9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_5_OPERAND<br />
|-<br />
| 00FA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COMBINE<br />
|-<br />
| 00FB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COLOR<br />
|-<br />
| 00FC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_5_SCALE<br />
|-<br />
| 00FD<br />
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]<br />
|?<br />
|PICA_REG_TEX_ENV_BUF_COLOR<br />
|-<br />
| 00FE<br />
| [[#GPUREG_00FE|GPUREG_00FE]]<br />
| <br />
|<br />
|-<br />
| 00FF<br />
| [[#GPUREG_00FF|GPUREG_00FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Framebuffer registers (0x100-0x13F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0100<br />
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]<br />
|<br />
|PICA_REG_COLOR_OPERATION<br />
|-<br />
| 0101<br />
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]<br />
| <br />
|PICA_REG_BLEND_FUNC<br />
|-<br />
| 0102<br />
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]<br />
| <br />
|PICA_REG_LOGIC_OP<br />
|-<br />
| 0103<br />
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]<br />
| <br />
|PICA_REG_BLEND_COLOR<br />
|-<br />
| 0104<br />
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]<br />
| <br />
|PICA_REG_FRAGOP_ALPHA_TEST<br />
|-<br />
| 0105<br />
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]<br />
| <br />
|PICA_REG_STENCIL_TEST<br />
|-<br />
| 0106<br />
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]<br />
| <br />
|PICA_REG_STENCIL_OP<br />
|-<br />
| 0107<br />
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]<br />
| <br />
|PICA_REG_DEPTH_COLOR_MASK<br />
|-<br />
| 0108<br />
| [[#GPUREG_0108|GPUREG_0108]]<br />
| <br />
|<br />
|-<br />
| 0109<br />
| [[#GPUREG_0109|GPUREG_0109]]<br />
| <br />
|<br />
|-<br />
| 010A<br />
| [[#GPUREG_010A|GPUREG_010A]]<br />
| <br />
|<br />
|-<br />
| 010B<br />
| [[#GPUREG_010B|GPUREG_010B]]<br />
| <br />
|<br />
|-<br />
| 010C<br />
| [[#GPUREG_010C|GPUREG_010C]]<br />
| <br />
|<br />
|-<br />
| 010D<br />
| [[#GPUREG_010D|GPUREG_010D]]<br />
| <br />
|<br />
|-<br />
| 010E<br />
| [[#GPUREG_010E|GPUREG_010E]]<br />
| <br />
|<br />
|-<br />
| 010F<br />
| [[#GPUREG_010F|GPUREG_010F]]<br />
| <br />
|<br />
|-<br />
| 0110<br />
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR0<br />
|-<br />
| 0111<br />
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR1<br />
|-<br />
| 0112<br />
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_READ<br />
|-<br />
| 0113<br />
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_WRITE<br />
|-<br />
| 0114<br />
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_READ<br />
|-<br />
| 0115<br />
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_WRITE<br />
|-<br />
| 0116<br />
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_DEPTH_MODE<br />
|-<br />
| 0117<br />
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_MODE<br />
|-<br />
| 0118<br />
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST2<br />
|-<br />
| 0119<br />
| [[#GPUREG_0119|GPUREG_0119]]<br />
| <br />
|<br />
|-<br />
| 011A<br />
| [[#GPUREG_011A|GPUREG_011A]]<br />
| <br />
|<br />
|-<br />
| 011B<br />
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]<br />
|<br />
|PICA_REG_RENDER_BLOCK_FORMAT<br />
|-<br />
| 011C<br />
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]<br />
|<br />
|PICA_REG_RENDER_BUF_DEPTH_ADDR<br />
|-<br />
| 011D<br />
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_ADDR<br />
|-<br />
| 011E<br />
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]<br />
| <br />
|PICA_REG_RENDER_BUF_RESOLUTION0<br />
|-<br />
| 011F<br />
| [[#GPUREG_011F|GPUREG_011F]]<br />
| <br />
|<br />
|-<br />
| 0120<br />
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_XY<br />
|-<br />
| 0121<br />
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z<br />
|-<br />
| 0122<br />
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z_COLOR<br />
|-<br />
| 0123<br />
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]<br />
|?<br />
|PICA_REG_GAS_LUT_INDEX<br />
|-<br />
| 0124<br />
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]<br />
|?<br />
|PICA_REG_GAS_LUT_DATA<br />
|-<br />
| 0125<br />
| [[#GPUREG_0125|GPUREG_0125]]<br />
| <br />
|<br />
|-<br />
| 0126<br />
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]<br />
|?<br />
|PICA_REG_GAS_DELTAZ_DEPTH<br />
|-<br />
| 0127<br />
| [[#GPUREG_0127|GPUREG_0127]]<br />
| <br />
|<br />
|-<br />
| 0128<br />
| [[#GPUREG_0128|GPUREG_0128]]<br />
| <br />
|<br />
|-<br />
| 0129<br />
| [[#GPUREG_0129|GPUREG_0129]]<br />
| <br />
|<br />
|-<br />
| 012A<br />
| [[#GPUREG_012A|GPUREG_012A]]<br />
| <br />
|<br />
|-<br />
| 012B<br />
| [[#GPUREG_012B|GPUREG_012B]]<br />
| <br />
|<br />
|-<br />
| 012C<br />
| [[#GPUREG_012C|GPUREG_012C]]<br />
| <br />
|<br />
|-<br />
| 012D<br />
| [[#GPUREG_012D|GPUREG_012D]]<br />
| <br />
|<br />
|-<br />
| 012E<br />
| [[#GPUREG_012E|GPUREG_012E]]<br />
| <br />
|<br />
|-<br />
| 012F<br />
| [[#GPUREG_012F|GPUREG_012F]]<br />
| <br />
|<br />
|-<br />
| 0130<br />
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]<br />
|?<br />
|PICA_REG_FRAGOP_SHADOW<br />
|-<br />
| 0131<br />
| [[#GPUREG_0131|GPUREG_0131]]<br />
| <br />
|<br />
|-<br />
| 0132<br />
| [[#GPUREG_0132|GPUREG_0132]]<br />
| <br />
|<br />
|-<br />
| 0133<br />
| [[#GPUREG_0133|GPUREG_0133]]<br />
| <br />
|<br />
|-<br />
| 0134<br />
| [[#GPUREG_0134|GPUREG_0134]]<br />
| <br />
|<br />
|-<br />
| 0135<br />
| [[#GPUREG_0135|GPUREG_0135]]<br />
| <br />
|<br />
|-<br />
| 0136<br />
| [[#GPUREG_0136|GPUREG_0136]]<br />
| <br />
|<br />
|-<br />
| 0137<br />
| [[#GPUREG_0137|GPUREG_0137]]<br />
| <br />
|<br />
|-<br />
| 0138<br />
| [[#GPUREG_0138|GPUREG_0138]]<br />
| <br />
|<br />
|-<br />
| 0139<br />
| [[#GPUREG_0139|GPUREG_0139]]<br />
| <br />
|<br />
|-<br />
| 013A<br />
| [[#GPUREG_013A|GPUREG_013A]]<br />
| <br />
|<br />
|-<br />
| 013B<br />
| [[#GPUREG_013B|GPUREG_013B]]<br />
| <br />
|<br />
|-<br />
| 013C<br />
| [[#GPUREG_013C|GPUREG_013C]]<br />
| <br />
|<br />
|-<br />
| 013D<br />
| [[#GPUREG_013D|GPUREG_013D]]<br />
| <br />
|<br />
|-<br />
| 013E<br />
| [[#GPUREG_013E|GPUREG_013E]]<br />
| <br />
|<br />
|-<br />
| 013F<br />
| [[#GPUREG_013F|GPUREG_013F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Fragment lighting registers (0x140-0x1FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0140<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START<br />
|-<br />
| 0141<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR1<br />
|-<br />
| 0142<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIFFUSE<br />
|-<br />
| 0143<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_AMBIENT<br />
|-<br />
| 0144<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_XY<br />
|-<br />
| 0145<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_Z<br />
|-<br />
| 0146<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_XY<br />
|-<br />
| 0147<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_Z<br />
|-<br />
| 0148<br />
| [[#GPUREG_0148|GPUREG_0148]]<br />
| <br />
|<br />
|-<br />
| 0149<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]<br />
| <br />
|PICA_REG_FRAG_LIGHT0_TYPE<br />
|-<br />
| 014A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS<br />
|-<br />
| 014B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE<br />
|-<br />
| 014C<br />
| [[#GPUREG_014C|GPUREG_014C]]<br />
| <br />
|<br />
|-<br />
| 014D<br />
| [[#GPUREG_014D|GPUREG_014D]]<br />
| <br />
|<br />
|-<br />
| 014E<br />
| [[#GPUREG_014E|GPUREG_014E]]<br />
| <br />
|<br />
|-<br />
| 014F<br />
| [[#GPUREG_014F|GPUREG_014F]]<br />
| <br />
|<br />
|-<br />
| 0150<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR0<br />
|-<br />
| 0151<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR1<br />
|-<br />
| 0152<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIFFUSE<br />
|-<br />
| 0153<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_AMBIENT<br />
|-<br />
| 0154<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_XY<br />
|-<br />
| 0155<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_Z<br />
|-<br />
| 0156<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_XY<br />
|-<br />
| 0157<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_Z<br />
|-<br />
| 0158<br />
| [[#GPUREG_0158|GPUREG_0158]]<br />
| <br />
|<br />
|-<br />
| 0159<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_TYPE<br />
|-<br />
| 015A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS<br />
|-<br />
| 015B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE<br />
|-<br />
| 015C<br />
| [[#GPUREG_015C|GPUREG_015C]]<br />
| <br />
|<br />
|-<br />
| 015D<br />
| [[#GPUREG_015D|GPUREG_015D]]<br />
| <br />
|<br />
|-<br />
| 015E<br />
| [[#GPUREG_015E|GPUREG_015E]]<br />
| <br />
|<br />
|-<br />
| 015F<br />
| [[#GPUREG_015F|GPUREG_015F]]<br />
| <br />
|<br />
|-<br />
| 0160<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR0<br />
|-<br />
| 0161<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR1<br />
|-<br />
| 0162<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIFFUSE<br />
|-<br />
| 0163<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_AMBIENT<br />
|-<br />
| 0164<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_XY<br />
|-<br />
| 0165<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_Z<br />
|-<br />
| 0166<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_XY<br />
|-<br />
| 0167<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_Z<br />
|-<br />
| 0168<br />
| [[#GPUREG_0168|GPUREG_0168]]<br />
| <br />
|<br />
|-<br />
| 0169<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_TYPE<br />
|-<br />
| 016A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS<br />
|-<br />
| 016B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE<br />
|-<br />
| 016C<br />
| [[#GPUREG_016C|GPUREG_016C]]<br />
| <br />
|<br />
|-<br />
| 016D<br />
| [[#GPUREG_016D|GPUREG_016D]]<br />
| <br />
|<br />
|-<br />
| 016E<br />
| [[#GPUREG_016E|GPUREG_016E]]<br />
| <br />
|<br />
|-<br />
| 016F<br />
| [[#GPUREG_016F|GPUREG_016F]]<br />
| <br />
|<br />
|-<br />
| 0170<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR0<br />
|-<br />
| 0171<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR1<br />
|-<br />
| 0172<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIFFUSE<br />
|-<br />
| 0173<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_AMBIENT<br />
|-<br />
| 0174<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_XY<br />
|-<br />
| 0175<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_Z<br />
|-<br />
| 0176<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]<br />
|? <br />
|PICA_REG_FRAG_LIGHT3_SPOT_XY<br />
|-<br />
| 0177<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPOT_Z<br />
|-<br />
| 0178<br />
| [[#GPUREG_0178|GPUREG_0178]]<br />
| <br />
|<br />
|-<br />
| 0179<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_TYPE<br />
|-<br />
| 017A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS<br />
|-<br />
| 017B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE<br />
|-<br />
| 017C<br />
| [[#GPUREG_017C|GPUREG_017C]]<br />
| <br />
|<br />
|-<br />
| 017D<br />
| [[#GPUREG_017D|GPUREG_017D]]<br />
| <br />
|<br />
|-<br />
| 017E<br />
| [[#GPUREG_017E|GPUREG_017E]]<br />
| <br />
|<br />
|-<br />
| 017F<br />
| [[#GPUREG_017F|GPUREG_017F]]<br />
| <br />
|<br />
|-<br />
| 0180<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR0<br />
|-<br />
| 0181<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR1<br />
|-<br />
| 0182<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIFFUSE<br />
|-<br />
| 0183<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_AMBIENT<br />
|-<br />
| 0184<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_XY<br />
|-<br />
| 0185<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_Z<br />
|-<br />
| 0186<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_XY<br />
|-<br />
| 0187<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_Z<br />
|-<br />
| 0188<br />
| [[#GPUREG_0188|GPUREG_0188]]<br />
| <br />
|<br />
|-<br />
| 0189<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_TYPE<br />
|-<br />
| 018A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS<br />
|-<br />
| 018B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE<br />
|-<br />
| 018C<br />
| [[#GPUREG_018C|GPUREG_018C]]<br />
| <br />
|<br />
|-<br />
| 018D<br />
| [[#GPUREG_018D|GPUREG_018D]]<br />
| <br />
|<br />
|-<br />
| 018E<br />
| [[#GPUREG_018E|GPUREG_018E]]<br />
| <br />
|<br />
|-<br />
| 018F<br />
| [[#GPUREG_018F|GPUREG_018F]]<br />
| <br />
|<br />
|-<br />
| 0190<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR0<br />
|-<br />
| 0191<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR1<br />
|-<br />
| 0192<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_DIFFUSE<br />
|-<br />
| 0193<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_AMBIENT<br />
|-<br />
| 0194<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_XY<br />
|-<br />
| 0195<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_Z<br />
|-<br />
| 0196<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_XY<br />
|-<br />
| 0197<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_Z<br />
|-<br />
| 0198<br />
| [[#GPUREG_0198|GPUREG_0198]]<br />
| <br />
|<br />
|-<br />
| 0199<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_TYPE<br />
|-<br />
| 019A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS<br />
|-<br />
| 019B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE<br />
|-<br />
| 019C<br />
| [[#GPUREG_019C|GPUREG_019C]]<br />
| <br />
|<br />
|-<br />
| 019D<br />
| [[#GPUREG_019D|GPUREG_019D]]<br />
| <br />
|<br />
|-<br />
| 019E<br />
| [[#GPUREG_019E|GPUREG_019E]]<br />
| <br />
|<br />
|-<br />
| 019F<br />
| [[#GPUREG_019F|GPUREG_019F]]<br />
| <br />
|<br />
|-<br />
| 01A0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR0<br />
|-<br />
| 01A1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR1<br />
|-<br />
| 01A2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIFFUSE<br />
|-<br />
| 01A3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_AMBIENT<br />
|-<br />
| 01A4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_XY<br />
|-<br />
| 01A5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_Z<br />
|-<br />
| 01A6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_XY<br />
|-<br />
| 01A7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_Z<br />
|-<br />
| 01A8<br />
| [[#GPUREG_01A8|GPUREG_01A8]]<br />
| <br />
|<br />
|-<br />
| 01A9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_TYPE<br />
|-<br />
| 01AA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS<br />
|-<br />
| 01AB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE<br />
|-<br />
| 01AC<br />
| [[#GPUREG_01AC|GPUREG_01AC]]<br />
| <br />
|<br />
|-<br />
| 01AD<br />
| [[#GPUREG_01AD|GPUREG_01AD]]<br />
| <br />
|<br />
|-<br />
| 01AE<br />
| [[#GPUREG_01AE|GPUREG_01AE]]<br />
| <br />
|<br />
|-<br />
| 01AF<br />
| [[#GPUREG_01AF|GPUREG_01AF]]<br />
| <br />
|<br />
|-<br />
| 01B0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR0<br />
|-<br />
| 01B1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR1<br />
|-<br />
| 01B2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_DIFFUSE<br />
|-<br />
| 01B3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_AMBIENT<br />
|-<br />
| 01B4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_XY<br />
|-<br />
| 01B5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_Z<br />
|-<br />
| 01B6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_XY<br />
|-<br />
| 01B7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_Z<br />
|-<br />
| 01B8<br />
| [[#GPUREG_01B8|GPUREG_01B8]]<br />
| <br />
|<br />
|-<br />
| 01B9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_TYPE<br />
|-<br />
| 01BA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS<br />
|-<br />
| 01BB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE<br />
|-<br />
| 01BC<br />
| [[#GPUREG_01BC|GPUREG_01BC]]<br />
| <br />
|<br />
|-<br />
| 01BD<br />
| [[#GPUREG_01BD|GPUREG_01BD]]<br />
| <br />
|<br />
|-<br />
| 01BE<br />
| [[#GPUREG_01BE|GPUREG_01BE]]<br />
| <br />
|<br />
|-<br />
| 01BF<br />
| [[#GPUREG_01BF|GPUREG_01BF]]<br />
| <br />
|<br />
|-<br />
| 01C0<br />
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_AMBIENT<br />
|-<br />
| 01C1<br />
| [[#GPUREG_01C1|GPUREG_01C1]]<br />
| <br />
|<br />
|-<br />
| 01C2<br />
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_NUM<br />
|-<br />
| 01C3<br />
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE0<br />
|-<br />
| 01C4<br />
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE1<br />
|-<br />
| 01C5<br />
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT<br />
|-<br />
| 01C6<br />
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN1<br />
|-<br />
| 01C7<br />
| [[#GPUREG_01C7|GPUREG_01C7]]<br />
| <br />
|<br />
|-<br />
| 01C8<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA0<br />
|-<br />
| 01C9<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA1<br />
|-<br />
| 01CA<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA2<br />
|-<br />
| 01CB<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA3<br />
|-<br />
| 01CC<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA4<br />
|-<br />
| 01CD<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA5<br />
|-<br />
| 01CE<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA6<br />
|-<br />
| 01CF<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA7<br />
|-<br />
| 01D0<br />
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT<br />
|-<br />
| 01D1<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTINPUT<br />
|-<br />
| 01D2<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTSCALE<br />
|-<br />
| 01D3<br />
| [[#GPUREG_01D3|GPUREG_01D3]]<br />
| <br />
|<br />
|-<br />
| 01D4<br />
| [[#GPUREG_01D4|GPUREG_01D4]]<br />
| <br />
|<br />
|-<br />
| 01D5<br />
| [[#GPUREG_01D5|GPUREG_01D5]]<br />
| <br />
|<br />
|-<br />
| 01D6<br />
| [[#GPUREG_01D6|GPUREG_01D6]]<br />
| <br />
|<br />
|-<br />
| 01D7<br />
| [[#GPUREG_01D7|GPUREG_01D7]]<br />
| <br />
|<br />
|-<br />
| 01D8<br />
| [[#GPUREG_01D8|GPUREG_01D8]]<br />
| <br />
|<br />
|-<br />
| 01D9<br />
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_EN_ID<br />
|-<br />
| 01DA<br />
| [[#GPUREG_01DA|GPUREG_01DA]]<br />
| <br />
|<br />
|-<br />
| 01DB<br />
| [[#GPUREG_01DB|GPUREG_01DB]]<br />
| <br />
|<br />
|-<br />
| 01DC<br />
| [[#GPUREG_01DC|GPUREG_01DC]]<br />
| <br />
|<br />
|-<br />
| 01DD<br />
| [[#GPUREG_01DD|GPUREG_01DD]]<br />
| <br />
|<br />
|-<br />
| 01DE<br />
| [[#GPUREG_01DE|GPUREG_01DE]]<br />
| <br />
|<br />
|-<br />
| 01DF<br />
| [[#GPUREG_01DF|GPUREG_01DF]]<br />
| <br />
|<br />
|-<br />
| 01E0<br />
| [[#GPUREG_01E0|GPUREG_01E0]]<br />
| <br />
|<br />
|-<br />
| 01E1<br />
| [[#GPUREG_01E1|GPUREG_01E1]]<br />
| <br />
|<br />
|-<br />
| 01E2<br />
| [[#GPUREG_01E2|GPUREG_01E2]]<br />
| <br />
|<br />
|-<br />
| 01E3<br />
| [[#GPUREG_01E3|GPUREG_01E3]]<br />
| <br />
|<br />
|-<br />
| 01E4<br />
| [[#GPUREG_01E4|GPUREG_01E4]]<br />
| <br />
|<br />
|-<br />
| 01E5<br />
| [[#GPUREG_01E5|GPUREG_01E5]]<br />
| <br />
|<br />
|-<br />
| 01E6<br />
| [[#GPUREG_01E6|GPUREG_01E6]]<br />
| <br />
|<br />
|-<br />
| 01E7<br />
| [[#GPUREG_01E7|GPUREG_01E7]]<br />
| <br />
|<br />
|-<br />
| 01E8<br />
| [[#GPUREG_01E8|GPUREG_01E8]]<br />
| <br />
|<br />
|-<br />
| 01E9<br />
| [[#GPUREG_01E9|GPUREG_01E9]]<br />
| <br />
|<br />
|-<br />
| 01EA<br />
| [[#GPUREG_01EA|GPUREG_01EA]]<br />
| <br />
|<br />
|-<br />
| 01EB<br />
| [[#GPUREG_01EB|GPUREG_01EB]]<br />
| <br />
|<br />
|-<br />
| 01EC<br />
| [[#GPUREG_01EC|GPUREG_01EC]]<br />
| <br />
|<br />
|-<br />
| 01ED<br />
| [[#GPUREG_01ED|GPUREG_01ED]]<br />
| <br />
|<br />
|-<br />
| 01EE<br />
| [[#GPUREG_01EE|GPUREG_01EE]]<br />
| <br />
|<br />
|-<br />
| 01EF<br />
| [[#GPUREG_01EF|GPUREG_01EF]]<br />
| <br />
|<br />
|-<br />
| 01F0<br />
| [[#GPUREG_01F0|GPUREG_01F0]]<br />
| <br />
|<br />
|-<br />
| 01F1<br />
| [[#GPUREG_01F1|GPUREG_01F1]]<br />
| <br />
|<br />
|-<br />
| 01F2<br />
| [[#GPUREG_01F2|GPUREG_01F2]]<br />
| <br />
|<br />
|-<br />
| 01F3<br />
| [[#GPUREG_01F3|GPUREG_01F3]]<br />
| <br />
|<br />
|-<br />
| 01F4<br />
| [[#GPUREG_01F4|GPUREG_01F4]]<br />
| <br />
|<br />
|-<br />
| 01F5<br />
| [[#GPUREG_01F5|GPUREG_01F5]]<br />
| <br />
|<br />
|-<br />
| 01F6<br />
| [[#GPUREG_01F6|GPUREG_01F6]]<br />
| <br />
|<br />
|-<br />
| 01F7<br />
| [[#GPUREG_01F7|GPUREG_01F7]]<br />
| <br />
|<br />
|-<br />
| 01F8<br />
| [[#GPUREG_01F8|GPUREG_01F8]]<br />
| <br />
|<br />
|-<br />
| 01F9<br />
| [[#GPUREG_01F9|GPUREG_01F9]]<br />
| <br />
|<br />
|-<br />
| 01FA<br />
| [[#GPUREG_01FA|GPUREG_01FA]]<br />
| <br />
|<br />
|-<br />
| 01FB<br />
| [[#GPUREG_01FB|GPUREG_01FB]]<br />
| <br />
|<br />
|-<br />
| 01FC<br />
| [[#GPUREG_01FC|GPUREG_01FC]]<br />
| <br />
|<br />
|-<br />
| 01FD<br />
| [[#GPUREG_01FD|GPUREG_01FD]]<br />
| <br />
|<br />
|-<br />
| 01FE<br />
| [[#GPUREG_01FE|GPUREG_01FE]]<br />
| <br />
|<br />
|-<br />
| 01FF<br />
| [[#GPUREG_01FF|GPUREG_01FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Geometry pipeline registers (0x200-0x27F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0200<br />
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR<br />
|-<br />
| 0201<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS0<br />
|-<br />
| 0202<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS1<br />
|-<br />
| 0203<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET<br />
|-<br />
| 0204<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT0<br />
|-<br />
| 0205<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT1<br />
|-<br />
| 0206<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0207<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0208<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0209<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020B<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020C<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020E<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020F<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0210<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0211<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0212<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0213<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0214<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0215<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0216<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0217<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0218<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0219<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021B<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021C<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021E<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021F<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0220<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0221<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0222<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0223<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0224<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0225<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0226<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0227<br />
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET<br />
|-<br />
| 0228<br />
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]<br />
| <br />
|PICA_REG_DRAW_VERTEX_NUM<br />
|-<br />
| 0229<br />
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]<br />
| ?<br />
|PICA_REG_DRAW_MODE0<br />
|-<br />
| 022A<br />
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]<br />
|<br />
|PICA_REG_DRAW_VERTEX_OFFSET<br />
|-<br />
| 022B<br />
| [[#GPUREG_022B|GPUREG_022B]]<br />
| <br />
|<br />
|-<br />
| 022C<br />
| [[#GPUREG_022C|GPUREG_022C]]<br />
| <br />
|<br />
|-<br />
| 022D<br />
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]<br />
| <br />
|PICA_REG_POST_VERTEX_CACHE_NUM<br />
|-<br />
| 022E<br />
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]<br />
|<br />
|PICA_REG_START_DRAW_ARRAY<br />
|-<br />
| 022F<br />
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]<br />
|<br />
|PICA_REG_START_DRAW_ELEMENT<br />
|-<br />
| 0230<br />
| [[#GPUREG_0230|GPUREG_0230]]<br />
| <br />
|<br />
|-<br />
| 0231<br />
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]<br />
|?<br />
|PICA_REG_VTX_FUNC<br />
|-<br />
| 0232<br />
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR<br />
|-<br />
| 0233<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA0<br />
|-<br />
| 0234<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA1<br />
|-<br />
| 0235<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA2<br />
|-<br />
| 0236<br />
| [[#GPUREG_0236|GPUREG_0236]]<br />
| <br />
|<br />
|-<br />
| 0237<br />
| [[#GPUREG_0237|GPUREG_0237]]<br />
| <br />
|<br />
|-<br />
| 0238<br />
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH0<br />
|-<br />
| 0239<br />
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH1<br />
|-<br />
| 023A<br />
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH0<br />
|-<br />
| 023B<br />
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH1<br />
|-<br />
| 023C<br />
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH0<br />
|-<br />
| 023D<br />
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH1<br />
|-<br />
| 023E<br />
| [[#GPUREG_023E|GPUREG_023E]]<br />
| <br />
|<br />
|-<br />
| 023F<br />
| [[#GPUREG_023F|GPUREG_023F]]<br />
| <br />
|<br />
|-<br />
| 0240<br />
| [[#GPUREG_0240|GPUREG_0240]]<br />
| <br />
|<br />
|-<br />
| 0241<br />
| [[#GPUREG_0241|GPUREG_0241]]<br />
| <br />
|<br />
|-<br />
| 0242<br />
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]<br />
|?<br />
|PICA_REG_VS_ATTR_NUM1<br />
|-<br />
| 0243<br />
| [[#GPUREG_0243|GPUREG_0243]]<br />
| <br />
|<br />
|-<br />
| 0244<br />
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]<br />
|?<br />
|PICA_REG_VS_COM_MODE<br />
|-<br />
| 0245<br />
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC0<br />
|-<br />
| 0246<br />
| [[#GPUREG_0246|GPUREG_0246]]<br />
| <br />
|<br />
|-<br />
| 0247<br />
| [[#GPUREG_0247|GPUREG_0247]]<br />
| <br />
|<br />
|-<br />
| 0248<br />
| [[#GPUREG_0248|GPUREG_0248]]<br />
| <br />
|<br />
|-<br />
| 0249<br />
| [[#GPUREG_0249|GPUREG_0249]]<br />
| <br />
|<br />
|-<br />
| 024A<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM1<br />
|-<br />
| 024B<br />
| [[#GPUREG_024B|GPUREG_024B]]<br />
|<br />
|<br />
|-<br />
| 024C<br />
| [[#GPUREG_024C|GPUREG_024C]]<br />
| <br />
|<br />
|-<br />
| 024D<br />
| [[#GPUREG_024D|GPUREG_024D]]<br />
| <br />
|<br />
|-<br />
| 024E<br />
| [[#GPUREG_024E|GPUREG_024E]]<br />
| <br />
|<br />
|-<br />
| 024F<br />
| [[#GPUREG_024F|GPUREG_024F]]<br />
| <br />
|<br />
|-<br />
| 0250<br />
| [[#GPUREG_0250|GPUREG_0250]]<br />
| <br />
|<br />
|-<br />
| 0251<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM2<br />
|-<br />
| 0252<br />
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]<br />
|?<br />
|PICA_REG_GS_MISC_REG0<br />
|-<br />
| 0253<br />
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]<br />
|?<br />
|PICA_REG_DRAW_MODE1<br />
|-<br />
| 0254<br />
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]<br />
|?<br />
|PICA_REG_GS_MISC_REG1<br />
|-<br />
| 0255<br />
| [[#GPUREG_0255|GPUREG_0255]]<br />
| <br />
|<br />
|-<br />
| 0256<br />
| [[#GPUREG_0256|GPUREG_0256]]<br />
| <br />
|<br />
|-<br />
| 0257<br />
| [[#GPUREG_0257|GPUREG_0257]]<br />
| <br />
|<br />
|-<br />
| 0258<br />
| [[#GPUREG_0258|GPUREG_0258]]<br />
| <br />
|<br />
|-<br />
| 0259<br />
| [[#GPUREG_0259|GPUREG_0259]]<br />
| <br />
|<br />
|-<br />
| 025A<br />
| [[#GPUREG_025A|GPUREG_025A]]<br />
| <br />
|<br />
|-<br />
| 025B<br />
| [[#GPUREG_025B|GPUREG_025B]]<br />
| <br />
|<br />
|-<br />
| 025C<br />
| [[#GPUREG_025C|GPUREG_025C]]<br />
| <br />
|<br />
|-<br />
| 025D<br />
| [[#GPUREG_025D|GPUREG_025D]]<br />
| <br />
|<br />
|-<br />
| 025E<br />
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]<br />
| ?<br />
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3<br />
|-<br />
| 025F<br />
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC1<br />
|-<br />
| 0260<br />
| [[#GPUREG_0260|GPUREG_0260]]<br />
| <br />
|<br />
|-<br />
| 0261<br />
| [[#GPUREG_0261|GPUREG_0261]]<br />
| <br />
|<br />
|-<br />
| 0262<br />
| [[#GPUREG_0262|GPUREG_0262]]<br />
| <br />
|<br />
|-<br />
| 0263<br />
| [[#GPUREG_0263|GPUREG_0263]]<br />
| <br />
|<br />
|-<br />
| 0264<br />
| [[#GPUREG_0264|GPUREG_0264]]<br />
| <br />
|<br />
|-<br />
| 0265<br />
| [[#GPUREG_0265|GPUREG_0265]]<br />
| <br />
|<br />
|-<br />
| 0266<br />
| [[#GPUREG_0266|GPUREG_0266]]<br />
| <br />
|<br />
|-<br />
| 0267<br />
| [[#GPUREG_0267|GPUREG_0267]]<br />
| <br />
|<br />
|-<br />
| 0268<br />
| [[#GPUREG_0268|GPUREG_0268]]<br />
| <br />
|<br />
|-<br />
| 0269<br />
| [[#GPUREG_0269|GPUREG_0269]]<br />
| <br />
|<br />
|-<br />
| 026A<br />
| [[#GPUREG_026A|GPUREG_026A]]<br />
| <br />
|<br />
|-<br />
| 026B<br />
| [[#GPUREG_026B|GPUREG_026B]]<br />
| <br />
|<br />
|-<br />
| 026C<br />
| [[#GPUREG_026C|GPUREG_026C]]<br />
| <br />
|<br />
|-<br />
| 026D<br />
| [[#GPUREG_026D|GPUREG_026D]]<br />
| <br />
|<br />
|-<br />
| 026E<br />
| [[#GPUREG_026E|GPUREG_026E]]<br />
| <br />
|<br />
|-<br />
| 026F<br />
| [[#GPUREG_026F|GPUREG_026F]]<br />
| <br />
|<br />
|-<br />
| 0270<br />
| [[#GPUREG_0270|GPUREG_0270]]<br />
| <br />
|<br />
|-<br />
| 0271<br />
| [[#GPUREG_0271|GPUREG_0271]]<br />
| <br />
|<br />
|-<br />
| 0272<br />
| [[#GPUREG_0272|GPUREG_0272]]<br />
| <br />
|<br />
|-<br />
| 0273<br />
| [[#GPUREG_0273|GPUREG_0273]]<br />
| <br />
|<br />
|-<br />
| 0274<br />
| [[#GPUREG_0274|GPUREG_0274]]<br />
| <br />
|<br />
|-<br />
| 0275<br />
| [[#GPUREG_0275|GPUREG_0275]]<br />
| <br />
|<br />
|-<br />
| 0276<br />
| [[#GPUREG_0276|GPUREG_0276]]<br />
| <br />
|<br />
|-<br />
| 0277<br />
| [[#GPUREG_0277|GPUREG_0277]]<br />
| <br />
|<br />
|-<br />
| 0278<br />
| [[#GPUREG_0278|GPUREG_0278]]<br />
| <br />
|<br />
|-<br />
| 0279<br />
| [[#GPUREG_0279|GPUREG_0279]]<br />
| <br />
|<br />
|-<br />
| 027A<br />
| [[#GPUREG_027A|GPUREG_027A]]<br />
| <br />
|<br />
|-<br />
| 027B<br />
| [[#GPUREG_027B|GPUREG_027B]]<br />
| <br />
|<br />
|-<br />
| 027C<br />
| [[#GPUREG_027C|GPUREG_027C]]<br />
| <br />
|<br />
|-<br />
| 027D<br />
| [[#GPUREG_027D|GPUREG_027D]]<br />
| <br />
|<br />
|-<br />
| 027E<br />
| [[#GPUREG_027E|GPUREG_027E]]<br />
| <br />
|<br />
|-<br />
| 027F<br />
| [[#GPUREG_027F|GPUREG_027F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Shader registers (0x280-0x2DF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
! colspan=4 | Geometry shader<br />
|-<br />
| 0280<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_GS_BOOL<br />
|-<br />
| 0281<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_GS_INT0<br />
|-<br />
| 0282<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_GS_INT1<br />
|-<br />
| 0283<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_GS_INT2<br />
|-<br />
| 0284<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_GS_INT3<br />
|-<br />
| 0285<br />
| [[#GPUREG_0285|GPUREG_0285]]<br />
| <br />
|<br />
|-<br />
| 0286<br />
| [[#GPUREG_0286|GPUREG_0286]]<br />
| <br />
|<br />
|-<br />
| 0287<br />
| [[#GPUREG_0287|GPUREG_0287]]<br />
| <br />
|<br />
|-<br />
| 0288<br />
| [[#GPUREG_0288|GPUREG_0288]]<br />
| <br />
|<br />
|-<br />
| 0289<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_GS_ATTR_NUM<br />
|-<br />
| 028A<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_GS_START_ADDR<br />
|-<br />
| 028B<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP0<br />
|-<br />
| 028C<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP1<br />
|-<br />
| 028D<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_GS_OUT_REG_MASK<br />
|-<br />
| 028E<br />
| [[#GPUREG_028E|GPUREG_028E]]<br />
| <br />
|<br />
|-<br />
| 028F<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_GS_PROG_RENEWAL_END<br />
|-<br />
| 0290<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_GS_FLOAT_ADDR<br />
|-<br />
| 0291<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA0<br />
|-<br />
| 0292<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA1<br />
|-<br />
| 0293<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA2<br />
|-<br />
| 0294<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA3<br />
|-<br />
| 0295<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA4<br />
|-<br />
| 0296<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA5<br />
|-<br />
| 0297<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA6<br />
|-<br />
| 0298<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA7<br />
|-<br />
| 0299<br />
| [[#GPUREG_0299|GPUREG_0299]]<br />
| <br />
|<br />
|-<br />
| 029A<br />
| [[#GPUREG_029A|GPUREG_029A]]<br />
| <br />
|<br />
|-<br />
| 029B<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_GS_PROG_ADDR<br />
|-<br />
| 029C<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_DATA0<br />
|-<br />
| 029D<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_DATA1<br />
|-<br />
| 029E<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_DATA2<br />
|-<br />
| 029F<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_DATA3<br />
|-<br />
| 02A0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_DATA4<br />
|-<br />
| 02A1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_DATA5<br />
|-<br />
| 02A2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_DATA6<br />
|-<br />
| 02A3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_DATA7<br />
|-<br />
| 02A4<br />
| [[#GPUREG_02A4|GPUREG_02A4]]<br />
| <br />
|<br />
|-<br />
| 02A5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02A6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02A7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02A8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02A9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02AA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02AB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02AC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02AD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02AE<br />
| [[#GPUREG_02AE|GPUREG_02AE]]<br />
| <br />
|<br />
|-<br />
| 02AF<br />
| [[#GPUREG_02AF|GPUREG_02AF]]<br />
| <br />
|<br />
|-<br />
! colspan=4 | Vertex shader<br />
|-<br />
| 02B0<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_VS_BOOL<br />
|-<br />
| 02B1<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_VS_INT0<br />
|-<br />
| 02B2<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_VS_INT1<br />
|-<br />
| 02B3<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_VS_INT2<br />
|-<br />
| 02B4<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_VS_INT3<br />
|-<br />
| 02B5<br />
| [[#GPUREG_02B5|GPUREG_02B5]]<br />
| <br />
|<br />
|-<br />
| 02B6<br />
| [[#GPUREG_02B6|GPUREG_02B6]]<br />
| <br />
|<br />
|-<br />
| 02B7<br />
| [[#GPUREG_02B7|GPUREG_02B7]]<br />
| <br />
|<br />
|-<br />
| 02B8<br />
| [[#GPUREG_02B8|GPUREG_02B8]]<br />
| <br />
|<br />
|-<br />
| 02B9<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_VS_ATTR_NUM0<br />
|-<br />
| 02BA<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_VS_START_ADDR<br />
|-<br />
| 02BB<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP0<br />
|-<br />
| 02BC<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP1<br />
|-<br />
| 02BD<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_VS_OUT_REG_MASK<br />
|-<br />
| 02BE<br />
| [[#GPUREG_02BE|GPUREG_02BE]]<br />
| <br />
|<br />
|-<br />
| 02BF<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_VS_PROG_RENEWAL_END<br />
|-<br />
| 02C0<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_VS_FLOAT_ADDR<br />
|-<br />
| 02C1<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA0<br />
|-<br />
| 02C2<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA1<br />
|-<br />
| 02C3<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA2<br />
|-<br />
| 02C4<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA3<br />
|-<br />
| 02C5<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA4<br />
|-<br />
| 02C6<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA5<br />
|-<br />
| 02C7<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA6<br />
|-<br />
| 02C8<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA7<br />
|-<br />
| 02C9<br />
| [[#GPUREG_02C9|GPUREG_02C9]]<br />
| <br />
|<br />
|-<br />
| 02CA<br />
| [[#GPUREG_02CA|GPUREG_02CA]]<br />
| <br />
|<br />
|-<br />
| 02CB<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_ADDR<br />
|-<br />
| 02CC<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_DATA0<br />
|-<br />
| 02CD<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_DATA1<br />
|-<br />
| 02CE<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_DATA2<br />
|-<br />
| 02CF<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_DATA3<br />
|-<br />
| 02D0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_DATA4<br />
|-<br />
| 02D1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_DATA5<br />
|-<br />
| 02D2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_DATA6<br />
|-<br />
| 02D3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_DATA7<br />
|-<br />
| 02D4<br />
| [[#GPUREG_02D4|GPUREG_02D4]]<br />
| <br />
|<br />
|-<br />
| 02D5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02D6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02D7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02D8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02D9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02DA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02DB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02DC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02DD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02DE<br />
| [[#GPUREG_02DE|GPUREG_02DE]]<br />
| <br />
|<br />
|-<br />
| 02DF<br />
| [[#GPUREG_02DF|GPUREG_02DF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Unknown registers (0x2E0-0x2FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 02E0<br />
| [[#GPUREG_02E0|GPUREG_02E0]]<br />
| <br />
|<br />
|-<br />
| 02E1<br />
| [[#GPUREG_02E1|GPUREG_02E1]]<br />
| <br />
|<br />
|-<br />
| 02E2<br />
| [[#GPUREG_02E2|GPUREG_02E2]]<br />
| <br />
|<br />
|-<br />
| 02E3<br />
| [[#GPUREG_02E3|GPUREG_02E3]]<br />
| <br />
|<br />
|-<br />
| 02E4<br />
| [[#GPUREG_02E4|GPUREG_02E4]]<br />
| <br />
|<br />
|-<br />
| 02E5<br />
| [[#GPUREG_02E5|GPUREG_02E5]]<br />
| <br />
|<br />
|-<br />
| 02E6<br />
| [[#GPUREG_02E6|GPUREG_02E6]]<br />
| <br />
|<br />
|-<br />
| 02E7<br />
| [[#GPUREG_02E7|GPUREG_02E7]]<br />
| <br />
|<br />
|-<br />
| 02E8<br />
| [[#GPUREG_02E8|GPUREG_02E8]]<br />
| <br />
|<br />
|-<br />
| 02E9<br />
| [[#GPUREG_02E9|GPUREG_02E9]]<br />
| <br />
|<br />
|-<br />
| 02EA<br />
| [[#GPUREG_02EA|GPUREG_02EA]]<br />
| <br />
|<br />
|-<br />
| 02EB<br />
| [[#GPUREG_02EB|GPUREG_02EB]]<br />
| <br />
|<br />
|-<br />
| 02EC<br />
| [[#GPUREG_02EC|GPUREG_02EC]]<br />
| <br />
|<br />
|-<br />
| 02ED<br />
| [[#GPUREG_02ED|GPUREG_02ED]]<br />
| <br />
|<br />
|-<br />
| 02EE<br />
| [[#GPUREG_02EE|GPUREG_02EE]]<br />
| <br />
|<br />
|-<br />
| 02EF<br />
| [[#GPUREG_02EF|GPUREG_02EF]]<br />
| <br />
|<br />
|-<br />
| 02F0<br />
| [[#GPUREG_02F0|GPUREG_02F0]]<br />
| <br />
|<br />
|-<br />
| 02F1<br />
| [[#GPUREG_02F1|GPUREG_02F1]]<br />
| <br />
|<br />
|-<br />
| 02F2<br />
| [[#GPUREG_02F2|GPUREG_02F2]]<br />
| <br />
|<br />
|-<br />
| 02F3<br />
| [[#GPUREG_02F3|GPUREG_02F3]]<br />
| <br />
|<br />
|-<br />
| 02F4<br />
| [[#GPUREG_02F4|GPUREG_02F4]]<br />
| <br />
|<br />
|-<br />
| 02F5<br />
| [[#GPUREG_02F5|GPUREG_02F5]]<br />
| <br />
|<br />
|-<br />
| 02F6<br />
| [[#GPUREG_02F6|GPUREG_02F6]]<br />
| <br />
|<br />
|-<br />
| 02F7<br />
| [[#GPUREG_02F7|GPUREG_02F7]]<br />
| <br />
|<br />
|-<br />
| 02F8<br />
| [[#GPUREG_02F8|GPUREG_02F8]]<br />
| <br />
|<br />
|-<br />
| 02F9<br />
| [[#GPUREG_02F9|GPUREG_02F9]]<br />
| <br />
|<br />
|-<br />
| 02FA<br />
| [[#GPUREG_02FA|GPUREG_02FA]]<br />
| <br />
|<br />
|-<br />
| 02FB<br />
| [[#GPUREG_02FB|GPUREG_02FB]]<br />
| <br />
|<br />
|-<br />
| 02FC<br />
| [[#GPUREG_02FC|GPUREG_02FC]]<br />
| <br />
|<br />
|-<br />
| 02FD<br />
| [[#GPUREG_02FD|GPUREG_02FD]]<br />
| <br />
|<br />
|-<br />
| 02FE<br />
| [[#GPUREG_02FE|GPUREG_02FE]]<br />
| <br />
|<br />
|-<br />
| 02FF<br />
| [[#GPUREG_02FF|GPUREG_02FF]]<br />
| <br />
|<br />
|}<br />
<br />
== Miscellaneous registers ==<br />
<br />
=== GPUREG_FINALIZE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)<br />
|}<br />
<br />
Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.<br />
Failure to write to this register in any command buffer will result in the GPU hanging.<br />
<br />
== Rasterizer registers ==<br />
<br />
=== GPUREG_FACECULLING_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Culling mode<br />
|}<br />
<br />
This register is used to configure the face culling mode.<br />
<br />
Culling mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Front Face (Counter Clockwise)<br />
|-<br />
| 2<br />
| Back Face (Counter Clockwise)<br />
|}<br />
<br />
=== GPUREG_VIEWPORT_WIDTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, width / 2<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.<br />
<br />
=== GPUREG_VIEWPORT_INVW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / width<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.<br />
<br />
=== GPUREG_VIEWPORT_HEIGHT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, height / 2<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.<br />
<br />
=== GPUREG_VIEWPORT_INVH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / height<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.<br />
<br />
=== GPUREG_FRAGOP_CLIP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable clipping planes.<br />
<br />
=== GPUREG_FRAGOP_CLIP_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Clipping plane coefficient ''i''<br />
|}<br />
<br />
This register is used to configure clipping plane coefficients.<br />
<br />
=== GPUREG_DEPTHMAP_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near - Far<br />
|}<br />
<br />
This register is used to configure the depth range scale.<br />
<br />
=== GPUREG_DEPTHMAP_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near + Polygon Offset<br />
|}<br />
<br />
This register is used to configure the depth range bias.<br />
<br />
=== GPUREG_SH_OUTMAP_TOTAL ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of following attributes<br />
|}<br />
<br />
This register is used to configure the total shader output map attributes.<br />
<br />
=== GPUREG_SH_OUTMAP_O''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Semantic for the x component of the register.<br />
|-<br />
| 8-12<br />
| unsigned, Semantic for the y component of the register.<br />
|-<br />
| 16-20<br />
| unsigned, Semantic for the z component of the register.<br />
|-<br />
| 24-28<br />
| unsigned, Semantic for the w component of the register.<br />
|}<br />
<br />
These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.<br />
<br />
Semantic values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Semantic<br />
! Description<br />
|-<br />
| 0x00<br />
| position.x<br />
| rowspan="4" | Vertex Position<br />
|-<br />
| 0x01<br />
| position.y<br />
|-<br />
| 0x02<br />
| position.z<br />
|-<br />
| 0x03<br />
| position.w<br />
|-<br />
| 0x04<br />
| normquat.x<br />
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)<br />
|-<br />
| 0x05<br />
| normquat.y<br />
|-<br />
| 0x06<br />
| normquat.z<br />
|-<br />
| 0x07<br />
| normquat.w<br />
|-<br />
| 0x08<br />
| color.r<br />
| rowspan="4" | Vertex color<br />
|-<br />
| 0x09<br />
| color.g<br />
|-<br />
| 0x0A<br />
| color.b<br />
|-<br />
| 0x0B<br />
| color.a<br />
|-<br />
| 0x0C<br />
| texcoord0.u<br />
| rowspan="2" | Texture coordinates for texture 0<br />
|-<br />
| 0x0D<br />
| texcoord0.v<br />
|-<br />
| 0x0E<br />
| texcoord1.u<br />
| rowspan="2" | Texture coordinates for texture 1<br />
|-<br />
| 0x0F<br />
| texcoord1.v<br />
|-<br />
| 0x10<br />
| texcoord0.w<br />
|<br />
<br />
|-<br />
| 0x12<br />
| view.x<br />
| rowspan="3" | View vector (for fragment lighting)<br />
|-<br />
| 0x13<br />
| view.y<br />
|-<br />
| 0x14<br />
| view.z<br />
<br />
|-<br />
| 0x16<br />
| texcoord2.u<br />
| rowspan="2" | Texture coordinates for texture 2<br />
|-<br />
| 0x17<br />
| texcoord2.v<br />
<br />
|-<br />
| 0x1F<br />
| Unused component<br />
| Should be set for unused components of the output register<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Early depth function<br />
|}<br />
<br />
This register configures the early depth test function.<br />
<br />
Early depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| >=<br />
|-<br />
| 1<br />
| ><br />
|-<br />
| 2<br />
| <=<br />
|-<br />
| 3<br />
| <<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether the early depth test is enabled.<br />
<br />
=== GPUREG_EARLYDEPTH_CLEAR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = clear)<br />
|}<br />
<br />
This register triggers clearing the early depth data.<br />
<br />
=== GPUREG_SH_OUTATTR_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Use texture coordinates (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register is used to configure the shader output attribute mode.<br />
<br />
=== GPUREG_SCISSORTEST_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Enabled (0 = disabled, 3 = enabled)<br />
|}<br />
<br />
This register is used to enable scissor testing.<br />
<br />
=== GPUREG_SCISSORTEST_POS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X1<br />
|-<br />
| 16-25<br />
| unsigned, Y1<br />
|}<br />
<br />
This register is used to configure the scissor test start position.<br />
<br />
=== GPUREG_SCISSORTEST_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X2<br />
|-<br />
| 16-25<br />
| unsigned, Y2<br />
|}<br />
<br />
This register is used to configure the scissor test end position.<br />
<br />
=== GPUREG_VIEWPORT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| signed, X<br />
|-<br />
| 16-25<br />
| signed, Y<br />
|}<br />
<br />
This register is used to configure the viewport position.<br />
<br />
=== GPUREG_EARLYDEPTH_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| unsigned, Clear value<br />
|}<br />
<br />
This register is used to configure the early depth clear value.<br />
<br />
=== GPUREG_DEPTHMAP_ENABLE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable depth range.<br />
<br />
=== GPUREG_RENDERBUF_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register is used to configure the output framebuffer dimensions.<br />
<br />
=== GPUREG_SH_OUTATTR_CLOCK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, 'position.z' present (0 = absent, 1 = present)<br />
|-<br />
| 1<br />
| unsigned, 'color' component present (0 = absent, 1 = present)<br />
|-<br />
| 8<br />
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)<br />
|-<br />
| 9<br />
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)<br />
|-<br />
| 10<br />
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)<br />
|-<br />
| 16<br />
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)<br />
|-<br />
| 24<br />
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)<br />
|}<br />
<br />
This register controls the clock supply to parts relating to certain attributes.<br />
<br />
== Texturing registers ==<br />
<br />
=== GPUREG_TEXUNIT_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| 0x0<br />
|-<br />
| 8-9<br />
| unsigned, Texture 3 coordinates<br />
|-<br />
| 10<br />
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| 0x1<br />
|-<br />
| 13<br />
| unsigned, Texture 2 coordinates<br />
|-<br />
| 16<br />
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)<br />
|-<br />
| 17-31<br />
| 0x0<br />
|}<br />
<br />
This register is used to enable texture units.<br />
<br />
Texture 3 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 0<br />
|-<br />
| 1<br />
| Texture 1<br />
|-<br />
| 2<br />
| Texture 2<br />
|}<br />
<br />
Texture 2 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 2<br />
|-<br />
| 1<br />
| Texture 1<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to set a texture unit's border color.<br />
<br />
=== GPUREG_TEXUNIT''i''_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Height<br />
|-<br />
| 16-26<br />
| unsigned, Width<br />
|}<br />
<br />
This register is used to set a texture unit's dimensions.<br />
<br />
=== GPUREG_TEXUNIT''i''_PARAM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, Magnification filter<br />
|-<br />
| 2<br />
| unsigned, Minification filter<br />
|-<br />
| 4-5<br />
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4<br />
|-<br />
| 8-10<br />
| unsigned, Wrap T<br />
|-<br />
| 12-14<br />
| unsigned, Wrap S<br />
|-<br />
| 16-17<br />
| 0x0<br />
|-<br />
| 20<br />
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)<br />
|-<br />
| 24<br />
| unsigned, Mipmap filter<br />
|-<br />
| 28-30<br />
| unsigned, Type (Texture 0 only)<br />
|}<br />
<br />
This register is used to set a texture unit's extra parameters.<br />
<br />
Filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|}<br />
<br />
Wrap values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to edge<br />
|-<br />
| 1<br />
| Clamp to border<br />
|-<br />
| 2<br />
| Repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|}<br />
<br />
Type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 2D<br />
|-<br />
| 1<br />
| Cube map<br />
|-<br />
| 2<br />
| Shadow 2D<br />
|-<br />
| 3<br />
| Projection<br />
|-<br />
| 4<br />
| Shadow cube<br />
|-<br />
| 5<br />
| Disabled<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_LOD ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.4.8, Bias<br />
|-<br />
| 16-19<br />
| unsigned, Max Level<br />
|-<br />
| 24-27<br />
| unsigned, Min Level<br />
|}<br />
<br />
This register is used to configure a texture unit's level of detail.<br />
<br />
=== GPUREG_TEXUNIT''i''_ADDR''i'' ===<br />
<br />
First ADDR register:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Texture physical address >> 3<br />
|}<br />
<br />
Subsequent ADDR registers:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-21<br />
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)<br />
|}<br />
<br />
This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.<br />
<br />
If the texture is a cube:<br />
<br />
{| class="wikitable" border="1"<br />
! Register<br />
! Description<br />
|-<br />
| ADDR1<br />
| Positive X<br />
|-<br />
| ADDR2<br />
| Negative X<br />
|-<br />
| ADDR3<br />
| Positive Y<br />
|-<br />
| ADDR4<br />
| Negative Y<br />
|-<br />
| ADDR5<br />
| Positive Z<br />
|-<br />
| ADDR6<br />
| Negative Z<br />
|}<br />
<br />
Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.<br />
<br />
=== GPUREG_TEXUNIT''i''_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Perspective (0 = perspective, 1 = not perspective)<br />
|-<br />
| 1-23<br />
| fixed0.0.24, Z bias (upper 23 bits)<br />
|}<br />
<br />
This register is used to set a texture unit's shadow texture properties.<br />
<br />
=== GPUREG_TEXUNIT''i''_TYPE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Format<br />
|}<br />
<br />
This register is used to set a texture unit's data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! GL Format<br />
! GL Data Type<br />
|-<br />
| 0x0<br />
| RGBA8888<br />
| GL_RGBA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x1<br />
| RGB888<br />
| GL_RGB<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x2<br />
| RGBA5551<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_5_5_5_1<br />
|-<br />
| 0x3<br />
| RGB565<br />
| GL_RGB<br />
| GL_UNSIGNED_SHORT_5_6_5<br />
|-<br />
| 0x4<br />
| RGBA4444<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_4_4_4_4<br />
|-<br />
| 0x5<br />
| IA8<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x6<br />
| HILO8<br />
| <br />
| <br />
|-<br />
| 0x7<br />
| I8<br />
| GL_LUMINANCE<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x8<br />
| A8<br />
| GL_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x9<br />
| IA44<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE_4_4_EXT<br />
|-<br />
| 0xA<br />
| I4<br />
| <br />
|<br />
|-<br />
| 0xB<br />
| A4<br />
| GL_ALPHA<br />
| GL_UNSIGNED_NIBBLE_EXT<br />
|-<br />
| 0xC<br />
| ETC1<br />
| GL_ETC1_RGB8_OES<br />
| <br />
|-<br />
| 0xD<br />
| ETC1A4<br />
|<br />
| <br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable lighting.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, U-direction clamp<br />
|-<br />
| 3-5<br />
| unsigned, V-direction clamp<br />
|-<br />
| 6-9<br />
| unsigned, RGB mapping function<br />
|-<br />
| 10-13<br />
| unsigned, Alpha mapping function<br />
|-<br />
| 14<br />
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)<br />
|-<br />
| 15<br />
| unsigned, Noise enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 16-17<br />
| unsigned, U-direction shift<br />
|-<br />
| 18-19<br />
| unsigned, V-direction shift<br />
|-<br />
| 20-27<br />
| float1.5.10, Texture bias (lower 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Clamp values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to zero<br />
|-<br />
| 1<br />
| Clamp to edge<br />
|-<br />
| 2<br />
| Symmetrical repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|-<br />
| 4<br />
| Pulse<br />
|}<br />
<br />
Mapping function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| U<br />
|-<br />
| 1<br />
| U²<br />
|-<br />
| 2<br />
| V<br />
|-<br />
| 3<br />
| V²<br />
|-<br />
| 4<br />
| (U + V) / 2<br />
|-<br />
| 5<br />
| (U² + V²) / 2<br />
|-<br />
| 6<br />
| sqrt(U² + V²)<br />
|-<br />
| 7<br />
| Minimum<br />
|-<br />
| 8<br />
| Maximum<br />
|-<br />
| 9<br />
| Rmax<br />
|}<br />
<br />
Shift values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Odd<br />
|-<br />
| 2<br />
| Even<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, U-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, U-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, V-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX3 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, U-direction noise frequency<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise frequency<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX4 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Minification filter<br />
|-<br />
| 3-10<br />
| 0x60<br />
|-<br />
| 11-18<br />
| unsigned, Texture width<br />
|-<br />
| 19-26<br />
| float1.5.10, Texture bias (upper 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Minification filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|-<br />
| 2<br />
| Nearest, Mipmap Nearest<br />
|-<br />
| 3<br />
| Linear, Mipmap Nearest<br />
|-<br />
| 4<br />
| Nearest, Mipmap Linear<br />
|-<br />
| 5<br />
| Linear, Mipmap Linear<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX5 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Texture offset<br />
|-<br />
| 8-31<br />
| 0xE0C080<br />
|}<br />
<br />
This register is used to set the procedural texture unit's offset.<br />
<br />
=== GPUREG_PROCTEX_LUT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Index<br />
|-<br />
| 8-11<br />
| unsigned, Reference table<br />
|}<br />
<br />
This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.<br />
<br />
Reference table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Noise table<br />
|-<br />
| 2<br />
| RGB mapping function table<br />
|-<br />
| 3<br />
| Alpha mapping function table<br />
|-<br />
| 4<br />
| Color table<br />
|-<br />
| 5<br />
| Color difference table<br />
|}<br />
<br />
=== GPUREG_PROCTEX_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.<br />
<br />
==== Noise Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== RGB Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Alpha Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Color Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
==== Color Difference Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| fixed1.0.7, Red difference between current and next color table elements<br />
|-<br />
| 8-15<br />
| fixed1.0.7, Green difference between current and next color table elements<br />
|-<br />
| 16-23<br />
| fixed1.0.7, Blue difference between current and next color table elements<br />
|-<br />
| 24-31<br />
| fixed1.0.7, Alpha difference between current and next color table elements<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_SOURCE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB source 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB source 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB source 2<br />
|-<br />
| 16-19<br />
| unsigned, Alpha source 0<br />
|-<br />
| 20-23<br />
| unsigned, Alpha source 1<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source 2<br />
|}<br />
<br />
This register configures a texture combiner's sources.<br />
<br />
Source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Primary color<br />
|-<br />
| 1<br />
| Fragment primary color<br />
|-<br />
| 2<br />
| Fragment secondary color<br />
|-<br />
| 3<br />
| Texture 0<br />
|-<br />
| 4<br />
| Texture 1<br />
|-<br />
| 5<br />
| Texture 2<br />
|-<br />
| 6<br />
| Texture 3<br />
|-<br />
| 13<br />
| Previous buffer<br />
|-<br />
| 14<br />
| Constant (from GPUREG_TEXENV''i''_COLOR)<br />
|-<br />
| 15<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_OPERAND ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB operand 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB operand 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB operand 2<br />
|-<br />
| 12-14<br />
| unsigned, Alpha operand 0<br />
|-<br />
| 16-18<br />
| unsigned, Alpha operand 1<br />
|-<br />
| 20-22<br />
| unsigned, Alpha operand 2<br />
|}<br />
<br />
This register configures a texture combiner's operands.<br />
<br />
RGB operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source color<br />
|-<br />
| 1<br />
| One minus source color<br />
|-<br />
| 2<br />
| Source alpha<br />
|-<br />
| 3<br />
| One minus source alpha<br />
|-<br />
| 4<br />
| Source red<br />
|-<br />
| 5<br />
| One minus source red<br />
|-<br />
| 8<br />
| Source green<br />
|-<br />
| 9<br />
| One minus source green<br />
|-<br />
| 12<br />
| Source blue<br />
|-<br />
| 13<br />
| One minus source blue<br />
|}<br />
<br />
Alpha operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source alpha<br />
|-<br />
| 1<br />
| One minus source alpha<br />
|-<br />
| 2<br />
| Source red<br />
|-<br />
| 3<br />
| One minus source red<br />
|-<br />
| 4<br />
| Source green<br />
|-<br />
| 5<br />
| One minus source green<br />
|-<br />
| 6<br />
| Source blue<br />
|-<br />
| 7<br />
| One minus source blue<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COMBINER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB combine<br />
|-<br />
| 16-19<br />
| unsigned, Alpha combine<br />
|}<br />
<br />
This register configures a texture combiner's combine mode.<br />
<br />
Combine values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Replace<br />
|-<br />
| 1<br />
| Modulate<br />
|-<br />
| 2<br />
| Add<br />
|-<br />
| 3<br />
| Add signed<br />
|-<br />
| 4<br />
| Interpolate<br />
|-<br />
| 5<br />
| Subtract<br />
|-<br />
| 6<br />
| Dot3 RGB<br />
|-<br />
| 7<br />
| Dot3 RGBA<br />
|-<br />
| 8<br />
| Multiply then add<br />
|-<br />
| 9<br />
| Add then multiply<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register configures a texture combiner's constant color.<br />
<br />
=== GPUREG_TEXENV''i''_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, RGB scale<br />
|-<br />
| 16-17<br />
| unsigned, Alpha scale<br />
|}<br />
<br />
This register configures a texture combiner's scale value.<br />
<br />
Scale values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|}<br />
<br />
=== GPUREG_TEXENV_UPDATE_BUFFER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fog mode<br />
|-<br />
| 3<br />
| unsigned, Shading density source<br />
|-<br />
| 8<br />
| unsigned, TexEnv 1 RGB buffer input<br />
|-<br />
| 9<br />
| unsigned, TexEnv 2 RGB buffer input<br />
|-<br />
| 10<br />
| unsigned, TexEnv 3 RGB buffer input<br />
|-<br />
| 11<br />
| unsigned, TexEnv 4 RGB buffer input<br />
|-<br />
| 12<br />
| unsigned, TexEnv 1 alpha buffer input<br />
|-<br />
| 13<br />
| unsigned, TexEnv 2 alpha buffer input<br />
|-<br />
| 14<br />
| unsigned, TexEnv 3 alpha buffer input<br />
|-<br />
| 15<br />
| unsigned, TexEnv 4 alpha buffer input<br />
|-<br />
| 16<br />
| unsigned, Z flip (0 = don't flip, 1 = flip)<br />
|-<br />
| 24-25<br />
| 0x0<br />
|}<br />
<br />
This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.<br />
<br />
Fog mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Disabled<br />
|-<br />
| 5<br />
| Fog<br />
|-<br />
| 7<br />
| Gas<br />
|}<br />
<br />
Shading density source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Plain density<br />
|-<br />
| 1<br />
| Depth density<br />
|}<br />
<br />
Buffer input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Previous buffer<br />
|-<br />
| 1<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_FOG_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
This register is used to configure the color of fog.<br />
<br />
=== GPUREG_GAS_ATTENUATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas density attenuation<br />
|}<br />
<br />
This register is used to configure the gas density attenuation.<br />
<br />
=== GPUREG_GAS_ACCMAX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas maximum density accumulation<br />
|}<br />
<br />
This register is used to configure the gas maximum density accumulation.<br />
<br />
=== GPUREG_FOG_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.<br />
<br />
=== GPUREG_FOG_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.<br />
<br />
==== Fog Look-Up Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Difference from next element <br />
|-<br />
| 13-23<br />
| fixed0.0.11, Value<br />
|}<br />
<br />
=== GPUREG_TEXENV_BUFFER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the texture combiner buffer color.<br />
<br />
== Framebuffer registers ==<br />
<br />
=== GPUREG_COLOR_OPERATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Fragment operation mode<br />
|-<br />
| 8<br />
| unsigned, Blend mode<br />
|-<br />
| 16-25<br />
| 0x0E4<br />
|}<br />
<br />
This register is used to configure the fragment operation mode and whether to use logic ops or blending.<br />
<br />
Fragment operation mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Default<br />
|-<br />
| 1<br />
| Gas<br />
|-<br />
| 3<br />
| Shadow<br />
|}<br />
<br />
Blend mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Logic op<br />
|-<br />
| 1<br />
| Blend<br />
|}<br />
<br />
=== GPUREG_BLEND_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, RGB equation<br />
|-<br />
| 8-10<br />
| unsigned, Alpha equation<br />
|-<br />
| 16-19<br />
| unsigned, RGB source function<br />
|-<br />
| 20-23<br />
| unsigned, RGB destination function<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source function<br />
|-<br />
| 28-31<br />
| unsigned, Alpha destination function<br />
|}<br />
<br />
This register is used to configure the blending function.<br />
<br />
Equation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Add<br />
|-<br />
| 1<br />
| Subtract<br />
|-<br />
| 2<br />
| Reverse subtract<br />
|-<br />
| 3<br />
| Minimum<br />
|-<br />
| 4<br />
| Maximum<br />
|}<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Zero<br />
|-<br />
| 1<br />
| One<br />
|-<br />
| 2<br />
| Source color<br />
|-<br />
| 3<br />
| One minus source color<br />
|-<br />
| 4<br />
| Destination color<br />
|-<br />
| 5<br />
| One minus destination color<br />
|-<br />
| 6<br />
| Source alpha<br />
|-<br />
| 7<br />
| One minus source alpha<br />
|-<br />
| 8<br />
| Destination alpha<br />
|-<br />
| 9<br />
| One minus destination alpha<br />
|-<br />
| 10<br />
| Constant color<br />
|-<br />
| 11<br />
| One minus constant color<br />
|-<br />
| 12<br />
| Constant alpha<br />
|-<br />
| 13<br />
| One minus constant alpha<br />
|-<br />
| 14<br />
| Source alpha saturate<br />
|}<br />
<br />
=== GPUREG_LOGIC_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Logic op<br />
|}<br />
<br />
This register is used to configure the logic op.<br />
<br />
Logic op values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clear<br />
|-<br />
| 1<br />
| AND<br />
|-<br />
| 2<br />
| Reverse AND<br />
|-<br />
| 3<br />
| Copy<br />
|-<br />
| 4<br />
| Set<br />
|-<br />
| 5<br />
| Inverted copy<br />
|-<br />
| 6<br />
| Noop<br />
|-<br />
| 7<br />
| Invert<br />
|-<br />
| 8<br />
| NAND<br />
|-<br />
| 9<br />
| OR<br />
|-<br />
| 10<br />
| NOR<br />
|-<br />
| 11<br />
| XOR<br />
|-<br />
| 12<br />
| Equivalent<br />
|-<br />
| 13<br />
| Inverted AND<br />
|-<br />
| 14<br />
| Reverse OR<br />
|-<br />
| 15<br />
| Inverted OR<br />
|}<br />
<br />
=== GPUREG_BLEND_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the blending color.<br />
<br />
=== GPUREG_FRAGOP_ALPHA_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Reference value<br />
|}<br />
<br />
This register is used to configure alpha testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Buffer mask<br />
|-<br />
| 16-23<br />
| signed, Reference value<br />
|-<br />
| 24-31<br />
| unsigned, Mask<br />
|}<br />
<br />
This register is used to configure stencil testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fail operation<br />
|-<br />
| 4-6<br />
| unsigned, Z-fail operation<br />
|-<br />
| 8-10<br />
| unsigned, Z-pass operation<br />
|}<br />
<br />
This register is used to configure stencil result operations.<br />
<br />
Operation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Keep<br />
|-<br />
| 1<br />
| Zero<br />
|-<br />
| 2<br />
| Replace<br />
|-<br />
| 3<br />
| Increment<br />
|-<br />
| 4<br />
| Decrement<br />
|-<br />
| 5<br />
| Invert<br />
|-<br />
| 6<br />
| Increment and wrap<br />
|-<br />
| 7<br />
| Decrement and wrap<br />
|}<br />
<br />
=== GPUREG_DEPTH_COLOR_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Depth function<br />
|-<br />
| 8<br />
| unsigned, Red write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 9<br />
| unsigned, Green write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 10<br />
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 11<br />
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to depth testing and framebuffer write masking.<br />
<br />
Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.<br />
<br />
Depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_FRAMEBUFFER_INVALIDATE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = invalidate)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.<br />
<br />
=== GPUREG_FRAMEBUFFER_FLUSH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = flush)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.<br />
<br />
=== GPUREG_COLORBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow read (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures read access from the color buffer.<br />
<br />
=== GPUREG_COLORBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow write (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures write access to the color buffer.<br />
<br />
=== GPUREG_DEPTHBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil read (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth read (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures read access from the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil write (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth write (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures write access to the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the depth buffer data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit depth<br />
|-<br />
| 2<br />
| 24-bit depth<br />
|-<br />
| 3<br />
| 24-bit depth + 8-bit stencil<br />
|}<br />
<br />
=== GPUREG_COLORBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Pixel size<br />
|-<br />
| 16-18<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.<br />
<br />
Pixel size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit color<br />
|-<br />
| 2<br />
| 32-bit color<br />
|}<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| RGBA8/Gas<br />
|-<br />
| 2<br />
| RGB5A1<br />
|-<br />
| 3<br />
| RGB565<br />
|-<br />
| 4<br />
| RGBA4<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register enables the early depth test.<br />
<br />
=== GPUREG_FRAMEBUFFER_BLOCK32 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Render block mode<br />
|}<br />
<br />
This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.<br />
<br />
Render block mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8x8 blocks<br />
|-<br />
| 1<br />
| 32x32 blocks<br />
|}<br />
<br />
=== GPUREG_DEPTHBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Depth buffer physical address >> 3<br />
|}<br />
<br />
This register configures the depth buffer physical address.<br />
<br />
=== GPUREG_COLORBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Color buffer physical address >> 3<br />
|}<br />
<br />
This register configures the color buffer physical address.<br />
<br />
=== GPUREG_FRAMEBUFFER_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register configures the framebuffer dimensions.<br />
<br />
=== GPUREG_GAS_LIGHT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Planar shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, Planar shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, Planar shading density attenuation<br />
|}<br />
<br />
This register configures gas light planar shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, View shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, View shading density attenuation<br />
|}<br />
<br />
This register configures gas light view shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading effect in line-of-sight direction<br />
|-<br />
| 8<br />
| Gas color LUT input<br />
|}<br />
<br />
This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.<br />
<br />
Color LUT input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Gas density<br />
|-<br />
| 1<br />
| Light factor<br />
|}<br />
<br />
=== GPUREG_GAS_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.<br />
<br />
=== GPUREG_GAS_LUT_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.<br />
<br />
==== Gas Look-Up Table ====<br />
<br />
16 elements:<br />
<br />
First 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| signed, Red<br />
|-<br />
| 8-15<br />
| signed, Green<br />
|-<br />
| 16-23<br />
| signed, Blue<br />
|}<br />
<br />
Last 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
=== GPUREG_GAS_DELTAZ_DEPTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| fixed0.16.8, Depth direction attenuation proportion<br />
|}<br />
<br />
This register is used to configure the gas depth direction attenuation proportion.<br />
<br />
=== GPUREG_FRAGOP_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Sum of penumbra scale and penumbra bias<br />
|-<br />
| 16-31<br />
| float1.5.10, Penumbra scale with reversed sign<br />
|}<br />
<br />
This register is used to configure shadow properties.<br />
<br />
== Fragment lighting registers ==<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR1 ===<br />
<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.<br />
<br />
=== GPUREG_LIGHT''i''_DIFFUSE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.<br />
<br />
=== GPUREG_LIGHT''i''_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.<br />
<br />
=== GPUREG_LIGHT''i''_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, X coordinate<br />
|-<br />
| 16-31<br />
| float1.5.10, Y coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Z coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, X coordinate (negated)<br />
|-<br />
| 16-28<br />
| fixed1.1.11, Y coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Z coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Light type (0 = positional light, 1 = directional light)<br />
|-<br />
| 1<br />
| unsigned, Two side diffuse (0 = one side, 1 = both sides)<br />
|-<br />
| 2<br />
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)<br />
|-<br />
| 3<br />
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures a light's properties.<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation bias<br />
|}<br />
<br />
These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation scale<br />
|}<br />
<br />
These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHTING_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.<br />
<br />
=== GPUREG_LIGHTING_NUM_LIGHTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of active lights - 1<br />
|}<br />
<br />
This register configures the number of active lights.<br />
<br />
=== GPUREG_LIGHTING_CONFIG0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)<br />
|-<br />
| 2-3<br />
| unsigned, Fresnel selector<br />
|-<br />
| 4-7<br />
| unsigned, Light environment configuration<br />
|-<br />
| 8-11<br />
| 0x4<br />
|-<br />
| 16<br />
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 17<br />
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 18<br />
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)<br />
|-<br />
| 19<br />
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)<br />
|-<br />
| 22-23<br />
| unsigned, Bump map texture unit<br />
|-<br />
| 24-25<br />
| unsigned, Shadow map texture unit<br />
|-<br />
| 27<br />
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)<br />
|-<br />
| 28-29<br />
| unsigned, Bump mode<br />
|-<br />
| 30<br />
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)<br />
|-<br />
| 31<br />
| 0x1<br />
|}<br />
<br />
This register configures the light environment.<br />
<br />
Fresnel selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Primary alpha<br />
|-<br />
| 2<br />
| Secondary alpha<br />
|-<br />
| 3<br />
| Primary and secondary alpha<br />
|}<br />
<br />
The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.<br />
<br />
Light environment configuration values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! Available LUTs<br />
|-<br />
| 0<br />
| Configuration 0<br />
| D0, RR, SP, DA<br />
|-<br />
| 1<br />
| Configuration 1<br />
| FR, RR, SP, DA<br />
|-<br />
| 2<br />
| Configuration 2<br />
| D0, D1, RR, DA<br />
|-<br />
| 3<br />
| Configuration 3<br />
| D0, D1, FR, DA<br />
|-<br />
| 4<br />
| Configuration 4<br />
| All except for FR<br />
|-<br />
| 5<br />
| Configuration 5<br />
| All except for D1<br />
|-<br />
| 6<br />
| Configuration 6<br />
| All except for RB and RG<br />
|-<br />
| 8<br />
| Configuration 7<br />
| All<br />
|}<br />
<br />
Bump mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Not used<br />
|-<br />
| 1<br />
| Use as bump map<br />
|-<br />
| 2<br />
| Use as tangent map<br />
|}<br />
<br />
=== GPUREG_LIGHTING_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 1<br />
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 2<br />
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 3<br />
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 4<br />
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 6<br />
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 7<br />
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 8<br />
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 10<br />
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 11<br />
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 12<br />
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 14<br />
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 15<br />
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 16<br />
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 18<br />
| 0x1<br />
|-<br />
| 19<br />
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 20-22<br />
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 21<br />
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 22<br />
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 24<br />
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 26<br />
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 27<br />
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 28<br />
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 29<br />
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 30<br />
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 31<br />
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is used to disable various aspects of the light environment.<br />
<br />
=== GPUREG_LIGHTING_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Starting index<br />
|-<br />
| 8-12<br />
| unsigned, Look-up table<br />
|}<br />
<br />
This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.<br />
<br />
Lookup table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| D0<br />
|-<br />
| 1<br />
| D1<br />
|-<br />
| 3<br />
| FR<br />
|-<br />
| 4<br />
| RB<br />
|-<br />
| 5<br />
| RG<br />
|-<br />
| 6<br />
| RR<br />
|-<br />
| 8-15<br />
| SP0-7<br />
|-<br />
| 16-23<br />
| DA0-7<br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.<br />
<br />
=== GPUREG_LIGHTING_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
Lighting LUT data is written here.<br />
<br />
A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.<br />
<br />
DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.<br />
<br />
Format of an entry:<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Entry value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_ABS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)<br />
|-<br />
| 21<br />
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register controls whether the absolute value of the input is taken before using a LUT.<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SELECT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Input selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Input selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Input selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Input selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Input selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Input selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Input selector for RR<br />
|}<br />
<br />
This register selects the input from LUTs.<br />
<br />
Input selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| N·H<br />
|-<br />
| 1<br />
| V·H<br />
|-<br />
| 2<br />
| N·V<br />
|-<br />
| 3<br />
| L·N<br />
|-<br />
| 4<br />
| -L·P (aka Spotlight aka SP)<br />
|-<br />
| 5<br />
| cos φ (aka CP)<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Scaler selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Scaler selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Scaler selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Scaler selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Scaler selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Scaler selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Scaler selector for RR<br />
|}<br />
<br />
This register controls the scaling that is applied to the output of a LUT.<br />
<br />
Scaler selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|-<br />
| 3<br />
| 8x<br />
|-<br />
| 6<br />
| 0.25x<br />
|-<br />
| 7<br />
| 0.5x<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, ID of the 1st enabled light<br />
|-<br />
| 4-6<br />
| unsigned, ID of the 2nd enabled light<br />
|-<br />
| 8-10<br />
| unsigned, ID of the 3rd enabled light<br />
|-<br />
| 12-14<br />
| unsigned, ID of the 4th enabled light<br />
|-<br />
| 16-18<br />
| unsigned, ID of the 5th enabled light<br />
|-<br />
| 20-22<br />
| unsigned, ID of the 6th enabled light<br />
|-<br />
| 24-26<br />
| unsigned, ID of the 7th enabled light<br />
|-<br />
| 28-30<br />
| unsigned, ID of the 8th enabled light<br />
|}<br />
<br />
This register sets the IDs of enabled light sources.<br />
<br />
== Geometry pipeline registers ==<br />
<br />
=== GPUREG_ATTRIBBUFFERS_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-28<br />
| unsigned, Vertex arrays base address<br />
|}<br />
<br />
This register sets the base address of all vertex arrays.<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 0 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 0 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 1 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 1 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 2 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 2 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 3 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 3 size<br />
|-<br />
| 16-17<br />
| unsigned, Vertex attribute 4 type<br />
|-<br />
| 18-19<br />
| unsigned, Vertex attribute 4 size<br />
|-<br />
| 20-21<br />
| unsigned, Vertex attribute 5 type<br />
|-<br />
| 22-23<br />
| unsigned, Vertex attribute 5 size<br />
|-<br />
| 24-25<br />
| unsigned, Vertex attribute 6 type<br />
|-<br />
| 26-27<br />
| unsigned, Vertex attribute 6 size<br />
|-<br />
| 28-29<br />
| unsigned, Vertex attribute 7 type<br />
|-<br />
| 30-31<br />
| unsigned, Vertex attribute 7 size<br />
|}<br />
<br />
This register configures the types and sizes of the first 8 vertex attributes.<br />
<br />
Vertex attribute type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Byte<br />
|-<br />
| 1<br />
| Unsigned byte<br />
|-<br />
| 2<br />
| Short<br />
|-<br />
| 3<br />
| Float<br />
|}<br />
<br />
Vertex attribute size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8 bits<br />
|-<br />
| 1<br />
| 16 bits<br />
|-<br />
| 2<br />
| 24 bits<br />
|-<br />
| 3<br />
| 32 bits<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 8 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 8 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 9 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 9 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 10 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 10 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 11 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 11 size<br />
|-<br />
| 16-27<br />
| unsigned, Fixed vertex attribute mask<br />
|-<br />
| 28-31<br />
| unsigned, Total vertex attribute count - 1<br />
|}<br />
<br />
This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.<br />
<br />
See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|}<br />
<br />
This register configures the offset of a vertex array from the base vertex arrays address.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 1<br />
|-<br />
| 4-7<br />
| unsigned, Component 2<br />
|-<br />
| 8-11<br />
| unsigned, Component 3<br />
|-<br />
| 12-15<br />
| unsigned, Component 4<br />
|-<br />
| 16-19<br />
| unsigned, Component 5<br />
|-<br />
| 20-23<br />
| unsigned, Component 6<br />
|-<br />
| 24-27<br />
| unsigned, Component 7<br />
|-<br />
| 28-31<br />
| unsigned, Component 8<br />
|}<br />
<br />
This register configures the first 8 component types of a vertex array.<br />
<br />
Component values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Vertex attribute 0<br />
|-<br />
| 1<br />
| Vertex attribute 1<br />
|-<br />
| 2<br />
| Vertex attribute 2<br />
|-<br />
| 3<br />
| Vertex attribute 3<br />
|-<br />
| 4<br />
| Vertex attribute 4<br />
|-<br />
| 5<br />
| Vertex attribute 5<br />
|-<br />
| 6<br />
| Vertex attribute 6<br />
|-<br />
| 7<br />
| Vertex attribute 7<br />
|-<br />
| 8<br />
| Vertex attribute 8<br />
|-<br />
| 9<br />
| Vertex attribute 9<br />
|-<br />
| 10<br />
| Vertex attribute 10<br />
|-<br />
| 11<br />
| Vertex attribute 11<br />
|-<br />
| 12<br />
| 4-byte padding<br />
|-<br />
| 13<br />
| 8-byte padding<br />
|-<br />
| 14<br />
| 12-byte padding<br />
|-<br />
| 15<br />
| 16-byte padding<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 9<br />
|-<br />
| 4-7<br />
| unsigned, Component 10<br />
|-<br />
| 8-11<br />
| unsigned, Component 11<br />
|-<br />
| 12-15<br />
| unsigned, Component 12<br />
|-<br />
| 16-23<br />
| unsigned, Bytes per vertex<br />
|-<br />
| 28-31<br />
| unsigned, Total number of components<br />
|}<br />
<br />
This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.<br />
<br />
See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.<br />
<br />
=== GPUREG_INDEXBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|-<br />
| 31<br />
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)<br />
|}<br />
<br />
This register configures the index array used when drawing elements.<br />
<br />
=== GPUREG_NUMVERTICES ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Number of vertices to render<br />
|}<br />
<br />
This register sets the number of vertices to render.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|-<br />
| 9<br />
| 0x0<br />
|-<br />
| 31<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_VERTEX_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Starting vertex offset<br />
|}<br />
<br />
This register sets the offset of the first vertex in an array to render.<br />
<br />
=== GPUREG_POST_VERTEX_CACHE_NUM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)<br />
|}<br />
<br />
This register configures the post-vertex cache.<br />
<br />
=== GPUREG_DRAWARRAYS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw arrays)<br />
|}<br />
<br />
This register triggers drawing vertex arrays.<br />
<br />
=== GPUREG_DRAWELEMENTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw elements)<br />
|}<br />
<br />
This register triggers drawing vertex array elements.<br />
<br />
=== GPUREG_VTX_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)<br />
|}<br />
<br />
This register triggers clearing the post-vertex cache.<br />
<br />
=== GPUREG_FIXEDATTRIB_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)<br />
|}<br />
<br />
This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.<br />
<br />
=== GPUREG_FIXEDATTRIB_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| colspan="2" | '''DATA0:'''<br />
|-<br />
| 0-7<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)<br />
|-<br />
| 8-31<br />
| float1.7.16, Vertex attribute element 4 (W)<br />
|-<br />
| colspan="2" | '''DATA1:'''<br />
|-<br />
| 0-15<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)<br />
|-<br />
| 16-31<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)<br />
|-<br />
| colspan="2" | '''DATA2:'''<br />
|-<br />
| 0-23<br />
| float1.7.16, Vertex attribute element 1 (X)<br />
|-<br />
| 24-31<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)<br />
|}<br />
<br />
Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.<br />
<br />
=== GPUREG_CMDBUF_SIZE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the size of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_SIZE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the size of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the physical address of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the physical address of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)<br />
|}<br />
<br />
This register triggers a jump to the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)<br />
|}<br />
<br />
This register triggers a jump to the second command buffer.<br />
<br />
=== GPUREG_VSH_NUM_ATTR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader input attributes - 1<br />
|}<br />
<br />
This register sets the number of vertex shader input attributes.<br />
<br />
=== GPUREG_VSH_COM_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.<br />
<br />
=== GPUREG_START_DRAW_FUNC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Mode (0 = drawing, 1 = configuration)<br />
|-<br />
| 1-7<br />
| 0x0<br />
|}<br />
<br />
This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_GSH_MISC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)<br />
|}<br />
<br />
This register configures miscellaneous geometry shader properties.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_GSH_MISC1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)<br />
|}<br />
<br />
This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.<br />
<br />
=== GPUREG_PRIMITIVE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|-<br />
| 8-9<br />
| unsigned, Primitive mode<br />
|}<br />
<br />
This register configures primitive drawing.<br />
<br />
Primitive mode value:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Triangles<br />
|-<br />
| 1<br />
| Triangle strip<br />
|-<br />
| 2<br />
| Triangle fan<br />
|-<br />
| 3<br />
| Geometry primitive<br />
|}<br />
<br />
=== GPUREG_RESTART_PRIMITIVE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = reset primitive)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
This register triggers resetting primitive drawing.<br />
<br />
== Shader registers ==<br />
<br />
=== GPUREG_''SH''_BOOLUNIFORM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Boolean register b0 value (0 = false, 1 = true)<br />
|-<br />
| 1<br />
| unsigned, Boolean register b1 value (0 = false, 1 = true)<br />
|-<br />
| 2<br />
| unsigned, Boolean register b2 value (0 = false, 1 = true)<br />
|-<br />
| 3<br />
| unsigned, Boolean register b3 value (0 = false, 1 = true)<br />
|-<br />
| 4<br />
| unsigned, Boolean register b4 value (0 = false, 1 = true)<br />
|-<br />
| 5<br />
| unsigned, Boolean register b5 value (0 = false, 1 = true)<br />
|-<br />
| 6<br />
| unsigned, Boolean register b6 value (0 = false, 1 = true)<br />
|-<br />
| 7<br />
| unsigned, Boolean register b7 value (0 = false, 1 = true)<br />
|-<br />
| 8<br />
| unsigned, Boolean register b8 value (0 = false, 1 = true)<br />
|-<br />
| 9<br />
| unsigned, Boolean register b9 value (0 = false, 1 = true)<br />
|-<br />
| 10<br />
| unsigned, Boolean register b10 value (0 = false, 1 = true)<br />
|-<br />
| 11<br />
| unsigned, Boolean register b11 value (0 = false, 1 = true)<br />
|-<br />
| 12<br />
| unsigned, Boolean register b12 value (0 = false, 1 = true)<br />
|-<br />
| 13<br />
| unsigned, Boolean register b13 value (0 = false, 1 = true)<br />
|-<br />
| 14<br />
| unsigned, Boolean register b14 value (0 = false, 1 = true)<br />
|-<br />
| 15<br />
| unsigned, Boolean register b15 value (0 = false, 1 = true)<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register is used to set a shader unit's boolean registers.<br />
<br />
=== GPUREG_''SH''_INTUNIFORM_I''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Integer register i''i'' X value<br />
|-<br />
| 8-15<br />
| unsigned, Integer register i''i'' Y value<br />
|-<br />
| 16-23<br />
| unsigned, Integer register i''i'' Z value<br />
|-<br />
| 24-31<br />
| unsigned, Integer register i''i'' W value<br />
|}<br />
<br />
These registers are used to set a shader unit's integer registers.<br />
<br />
=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Input vertex attributes - 1<br />
|-<br />
| 8-15<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)<br />
|-<br />
| 16-23<br />
| 0x0<br />
|-<br />
| 24-31<br />
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)<br />
|}<br />
<br />
This register is used to configure a shader unit's input buffer.<br />
<br />
=== GPUREG_''SH''_ENTRYPOINT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Code entry point offset, in 32-bit words<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register sets a shader unit's code entry point.<br />
<br />
For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.<br />
<br />
For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them. <br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 0 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 1 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 2 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 3 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 4 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 5 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 6 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 7 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.<br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 8 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 9 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 10 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 11 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 12 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 13 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 14 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 15 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.<br />
<br />
=== GPUREG_''SH''_OUTMAP_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4<br />
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 5<br />
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 6<br />
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 7<br />
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 8<br />
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 9<br />
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 10<br />
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 11<br />
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 12<br />
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 13<br />
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 14<br />
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 15<br />
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 16-31<br />
| 0x0<br />
|}<br />
<br />
This register toggles a shader unit's output registers.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_END ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Signal transfer end (0 = idle, non-zero = signal)<br />
|}<br />
<br />
This register's value should be set to 1 in order to finalize the transfer of shader code.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)<br />
|-<br />
| 31<br />
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)<br />
|}<br />
<br />
This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| Floating-point register component data<br />
|}<br />
<br />
This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].<br />
<br />
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:<br />
** first word : ZZWWWWWW<br />
** second word : YYYYZZZZ<br />
** third word : XXXXXXYY<br />
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader code offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader instruction data<br />
|}<br />
<br />
This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.<br />
<br />
=== GPUREG_''SH''_OPDESCS_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader operand descriptor offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_OPDESCS_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader operand descriptor data<br />
|}<br />
<br />
This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=GPU/Internal_Registers&diff=19806
GPU/Internal Registers
2017-04-08T10:44:34Z
<p>Plutooo: test</p>
<hr />
<div>[[Category:GPU]]<br />
<br />
== Overview ==<br />
GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.<br />
<br />
Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).<br />
<br />
In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.<br />
<br />
For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).<br />
<br />
Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.<br />
<br />
The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.<br />
<br />
=== Command Header ===<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0-15<br />
| Command ID<br />
|-<br />
| 16-19<br />
| Parameter mask<br />
|-<br />
| 20-30<br />
| Number of extra parameters (may be zero)<br />
|-<br />
| 31<br />
| Consecutive writing mode<br />
|}<br />
<br />
=== Parameter masking ===<br />
<br />
Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.<br />
<br />
=== Types ===<br />
<br />
There are three main types of registers :<br />
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])<br />
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])<br />
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])<br />
<br />
=== Aliases ===<br />
<br />
It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]<br />
<br />
=== Data Types ===<br />
<br />
{| class="wikitable" border="1"<br />
! Name<br />
! Description<br />
|-<br />
| signed<br />
| Signed integer<br />
|-<br />
| unsigned<br />
| Unsigned integer<br />
|-<br />
| floatX.Y.Z<br />
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits<br />
|-<br />
| fixedX.Y.Z<br />
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits<br />
|}<br />
<br />
== Register list ==<br />
<br />
=== Miscellaneous registers (0x000-0x03F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0000<br />
| [[#GPUREG_0000|GPUREG_0000]]<br />
| <br />
|<br />
|-<br />
| 0001<br />
| [[#GPUREG_0001|GPUREG_0001]]<br />
| <br />
|<br />
|-<br />
| 0002<br />
| [[#GPUREG_0002|GPUREG_0002]]<br />
| <br />
|<br />
|-<br />
| 0003<br />
| [[#GPUREG_0003|GPUREG_0003]]<br />
| <br />
|<br />
|-<br />
| 0004<br />
| [[#GPUREG_0004|GPUREG_0004]]<br />
| <br />
|<br />
|-<br />
| 0005<br />
| [[#GPUREG_0005|GPUREG_0005]]<br />
| <br />
|<br />
|-<br />
| 0006<br />
| [[#GPUREG_0006|GPUREG_0006]]<br />
| <br />
|<br />
|-<br />
| 0007<br />
| [[#GPUREG_0007|GPUREG_0007]]<br />
| <br />
|<br />
|-<br />
| 0008<br />
| [[#GPUREG_0008|GPUREG_0008]]<br />
| <br />
|<br />
|-<br />
| 0009<br />
| [[#GPUREG_0009|GPUREG_0009]]<br />
| <br />
|<br />
|-<br />
| 000A<br />
| [[#GPUREG_000A|GPUREG_000A]]<br />
| <br />
|<br />
|-<br />
| 000B<br />
| [[#GPUREG_000B|GPUREG_000B]]<br />
| <br />
|<br />
|-<br />
| 000C<br />
| [[#GPUREG_000C|GPUREG_000C]]<br />
| <br />
|<br />
|-<br />
| 000D<br />
| [[#GPUREG_000D|GPUREG_000D]]<br />
| <br />
|<br />
|-<br />
| 000E<br />
| [[#GPUREG_000E|GPUREG_000E]]<br />
| <br />
|<br />
|-<br />
| 000F<br />
| [[#GPUREG_000F|GPUREG_000F]]<br />
| <br />
|<br />
|-<br />
| 0010<br />
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]<br />
| <br />
|PICA_REG_INTERRUPT<br />
|-<br />
| 0011<br />
| [[#GPUREG_0011|GPUREG_0011]]<br />
| <br />
|<br />
|-<br />
| 0012<br />
| [[#GPUREG_0012|GPUREG_0012]]<br />
| <br />
|<br />
|-<br />
| 0013<br />
| [[#GPUREG_0013|GPUREG_0013]]<br />
| <br />
|<br />
|-<br />
| 0014<br />
| [[#GPUREG_0014|GPUREG_0014]]<br />
| <br />
|<br />
|-<br />
| 0015<br />
| [[#GPUREG_0015|GPUREG_0015]]<br />
| <br />
|<br />
|-<br />
| 0016<br />
| [[#GPUREG_0016|GPUREG_0016]]<br />
| <br />
|<br />
|-<br />
| 0017<br />
| [[#GPUREG_0017|GPUREG_0017]]<br />
| <br />
|<br />
|-<br />
| 0018<br />
| [[#GPUREG_0018|GPUREG_0018]]<br />
| <br />
|<br />
|-<br />
| 0019<br />
| [[#GPUREG_0019|GPUREG_0019]]<br />
| <br />
|<br />
|-<br />
| 001A<br />
| [[#GPUREG_001A|GPUREG_001A]]<br />
| <br />
|<br />
|-<br />
| 001B<br />
| [[#GPUREG_001B|GPUREG_001B]]<br />
| <br />
|<br />
|-<br />
| 001C<br />
| [[#GPUREG_001C|GPUREG_001C]]<br />
| <br />
|<br />
|-<br />
| 001D<br />
| [[#GPUREG_001D|GPUREG_001D]]<br />
| <br />
|<br />
|-<br />
| 001E<br />
| [[#GPUREG_001E|GPUREG_001E]]<br />
| <br />
|<br />
|-<br />
| 001F<br />
| [[#GPUREG_001F|GPUREG_001F]]<br />
| <br />
|<br />
|-<br />
| 0020<br />
| [[#GPUREG_0020|GPUREG_0020]]<br />
| <br />
|<br />
|-<br />
| 0021<br />
| [[#GPUREG_0021|GPUREG_0021]]<br />
| <br />
|<br />
|-<br />
| 0022<br />
| [[#GPUREG_0022|GPUREG_0022]]<br />
| <br />
|<br />
|-<br />
| 0023<br />
| [[#GPUREG_0023|GPUREG_0023]]<br />
| <br />
|<br />
|-<br />
| 0024<br />
| [[#GPUREG_0024|GPUREG_0024]]<br />
| <br />
|<br />
|-<br />
| 0025<br />
| [[#GPUREG_0025|GPUREG_0025]]<br />
| <br />
|<br />
|-<br />
| 0026<br />
| [[#GPUREG_0026|GPUREG_0026]]<br />
| <br />
|<br />
|-<br />
| 0027<br />
| [[#GPUREG_0027|GPUREG_0027]]<br />
| <br />
|<br />
|-<br />
| 0028<br />
| [[#GPUREG_0028|GPUREG_0028]]<br />
| <br />
|<br />
|-<br />
| 0029<br />
| [[#GPUREG_0029|GPUREG_0029]]<br />
| <br />
|<br />
|-<br />
| 002A<br />
| [[#GPUREG_002A|GPUREG_002A]]<br />
| <br />
|<br />
|-<br />
| 002B<br />
| [[#GPUREG_002B|GPUREG_002B]]<br />
| <br />
|<br />
|-<br />
| 002C<br />
| [[#GPUREG_002C|GPUREG_002C]]<br />
| <br />
|<br />
|-<br />
| 002D<br />
| [[#GPUREG_002D|GPUREG_002D]]<br />
| <br />
|<br />
|-<br />
| 002E<br />
| [[#GPUREG_002E|GPUREG_002E]]<br />
| <br />
|<br />
|-<br />
| 002F<br />
| [[#GPUREG_002F|GPUREG_002F]]<br />
| <br />
|<br />
|-<br />
| 0030<br />
| [[#GPUREG_0030|GPUREG_0030]]<br />
| <br />
|<br />
|-<br />
| 0031<br />
| [[#GPUREG_0031|GPUREG_0031]]<br />
| <br />
|<br />
|-<br />
| 0032<br />
| [[#GPUREG_0032|GPUREG_0032]]<br />
| <br />
|<br />
|-<br />
| 0033<br />
| [[#GPUREG_0033|GPUREG_0033]]<br />
| <br />
|<br />
|-<br />
| 0034<br />
| [[#GPUREG_0034|GPUREG_0034]]<br />
| <br />
|<br />
|-<br />
| 0035<br />
| [[#GPUREG_0035|GPUREG_0035]]<br />
| <br />
|<br />
|-<br />
| 0036<br />
| [[#GPUREG_0036|GPUREG_0036]]<br />
| <br />
|<br />
|-<br />
| 0037<br />
| [[#GPUREG_0037|GPUREG_0037]]<br />
| <br />
|<br />
|-<br />
| 0038<br />
| [[#GPUREG_0038|GPUREG_0038]]<br />
| <br />
|<br />
|-<br />
| 0039<br />
| [[#GPUREG_0039|GPUREG_0039]]<br />
| <br />
|<br />
|-<br />
| 003A<br />
| [[#GPUREG_003A|GPUREG_003A]]<br />
| <br />
|<br />
|-<br />
| 003B<br />
| [[#GPUREG_003B|GPUREG_003B]]<br />
| <br />
|<br />
|-<br />
| 003C<br />
| [[#GPUREG_003C|GPUREG_003C]]<br />
| <br />
|<br />
|-<br />
| 003D<br />
| [[#GPUREG_003D|GPUREG_003D]]<br />
| <br />
|<br />
|-<br />
| 003E<br />
| [[#GPUREG_003E|GPUREG_003E]]<br />
| <br />
|<br />
|-<br />
| 003F<br />
| [[#GPUREG_003F|GPUREG_003F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Rasterizer registers (0x040-0x07F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0040<br />
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]<br />
| <br />
|PICA_REG_CULL_FACE<br />
|-<br />
| 0041<br />
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH1<br />
|-<br />
| 0042<br />
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]<br />
|<br />
|PICA_REG_VIEWPORT_WIDTH2<br />
|-<br />
| 0043<br />
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT1<br />
|-<br />
| 0044<br />
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]<br />
|<br />
|PICA_REG_VIEWPORT_HEIGHT2<br />
|-<br />
| 0045<br />
| [[#GPUREG_0045|GPUREG_0045]]<br />
| <br />
|<br />
|-<br />
| 0046<br />
| [[#GPUREG_0046|GPUREG_0046]]<br />
| <br />
|<br />
|-<br />
| 0047<br />
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP<br />
|-<br />
| 0048<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]<br />
|? <br />
|PICA_REG_FRAGOP_CLIP_DATA1<br />
|-<br />
| 0049<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA2<br />
|-<br />
| 004A<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA3<br />
|-<br />
| 004B<br />
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]<br />
|?<br />
|PICA_REG_FRAGOP_CLIP_DATA4<br />
|-<br />
| 004C<br />
| [[#GPUREG_004C|GPUREG_004C]]<br />
| <br />
|<br />
|-<br />
| 004D<br />
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA1<br />
|-<br />
| 004E<br />
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]<br />
| As f24<br />
|PICA_REG_FRAGOP_WSCALE_DATA2<br />
|-<br />
| 004F<br />
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]<br />
| <br />
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0<br />
|-<br />
| 0050<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0<br />
|-<br />
| 0051<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1<br />
|-<br />
| 0052<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2<br />
|-<br />
| 0053<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3<br />
|-<br />
| 0054<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4<br />
|-<br />
| 0055<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5<br />
|-<br />
| 0056<br />
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]<br />
| <br />
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6<br />
|-<br />
| 0057<br />
| [[#GPUREG_0057|GPUREG_0057]]<br />
| <br />
|<br />
|-<br />
| 0058<br />
| [[#GPUREG_0058|GPUREG_0058]]<br />
| <br />
|<br />
|-<br />
| 0059<br />
| [[#GPUREG_0059|GPUREG_0059]]<br />
| <br />
|<br />
|-<br />
| 005A<br />
| [[#GPUREG_005A|GPUREG_005A]]<br />
| <br />
|<br />
|-<br />
| 005B<br />
| [[#GPUREG_005B|GPUREG_005B]]<br />
| <br />
|<br />
|-<br />
| 005C<br />
| [[#GPUREG_005C|GPUREG_005C]]<br />
| <br />
|<br />
|-<br />
| 005D<br />
| [[#GPUREG_005D|GPUREG_005D]]<br />
| <br />
|<br />
|-<br />
| 005E<br />
| [[#GPUREG_005E|GPUREG_005E]]<br />
| <br />
|<br />
|-<br />
| 005F<br />
| [[#GPUREG_005F|GPUREG_005F]]<br />
| <br />
|<br />
|-<br />
| 0060<br />
| [[#GPUREG_0060|GPUREG_0060]]<br />
| <br />
|<br />
|-<br />
| 0061<br />
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_FUNC<br />
|-<br />
| 0062<br />
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST1<br />
|-<br />
| 0063<br />
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]<br />
| <br />
|PICA_REG_EARLY_DEPTH_CLEAR<br />
|-<br />
| 0064<br />
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE<br />
|-<br />
| 0065<br />
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]<br />
| <br />
|PICA_REG_SCISSOR<br />
|-<br />
| 0066<br />
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]<br />
| <br />
|PICA_REG_SCISSOR_XY<br />
|-<br />
| 0067<br />
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]<br />
| <br />
|PICA_REG_SCISSOR_SIZE<br />
|-<br />
| 0068<br />
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]<br />
|<br />
|PICA_REG_VIEWPORT_XY<br />
|-<br />
| 0069<br />
| [[#GPUREG_0069|GPUREG_0069]]<br />
| <br />
|<br />
|-<br />
| 006A<br />
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]<br />
|<br />
|PICA_REG_EARLY_DEPTH_DATA<br />
|-<br />
| 006B<br />
| [[#GPUREG_006B|GPUREG_006B]]<br />
| <br />
|<br />
|-<br />
| 006C<br />
| [[#GPUREG_006C|GPUREG_006C]]<br />
| <br />
|<br />
|-<br />
| 006D<br />
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]<br />
|?<br />
|PICA_REG_FRAGOP_WSCALE<br />
|-<br />
| 006E<br />
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]<br />
|?<br />
|PICA_REG_RENDER_BUF_RESOLUTION1<br />
|-<br />
| 006F<br />
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]<br />
|?<br />
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK<br />
|-<br />
| 0070<br />
| [[#GPUREG_0070|GPUREG_0070]]<br />
| <br />
|<br />
|-<br />
| 0071<br />
| [[#GPUREG_0071|GPUREG_0071]]<br />
| <br />
|<br />
|-<br />
| 0072<br />
| [[#GPUREG_0072|GPUREG_0072]]<br />
| <br />
|<br />
|-<br />
| 0073<br />
| [[#GPUREG_0073|GPUREG_0073]]<br />
| <br />
|<br />
|-<br />
| 0074<br />
| [[#GPUREG_0074|GPUREG_0074]]<br />
| <br />
|<br />
|-<br />
| 0075<br />
| [[#GPUREG_0075|GPUREG_0075]]<br />
| <br />
|<br />
|-<br />
| 0076<br />
| [[#GPUREG_0076|GPUREG_0076]]<br />
| <br />
|<br />
|-<br />
| 0077<br />
| [[#GPUREG_0077|GPUREG_0077]]<br />
| <br />
|<br />
|-<br />
| 0078<br />
| [[#GPUREG_0078|GPUREG_0078]]<br />
| <br />
|<br />
|-<br />
| 0079<br />
| [[#GPUREG_0079|GPUREG_0079]]<br />
| <br />
|<br />
|-<br />
| 007A<br />
| [[#GPUREG_007A|GPUREG_007A]]<br />
| <br />
|<br />
|-<br />
| 007B<br />
| [[#GPUREG_007B|GPUREG_007B]]<br />
| <br />
|<br />
|-<br />
| 007C<br />
| [[#GPUREG_007C|GPUREG_007C]]<br />
| <br />
|<br />
|-<br />
| 007D<br />
| [[#GPUREG_007D|GPUREG_007D]]<br />
| <br />
|<br />
|-<br />
| 007E<br />
| [[#GPUREG_007E|GPUREG_007E]]<br />
| <br />
|<br />
|-<br />
| 007F<br />
| [[#GPUREG_007F|GPUREG_007F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Texturing registers (0x080-0x0FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0080<br />
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]<br />
|<br />
|PICA_REG_TEXTURE_FUNC<br />
|-<br />
| 0081<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE0_BORDER_COLOR<br />
|-<br />
| 0082<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]<br />
|<br />
|PICA_REG_TEXTURE0_SIZE<br />
|-<br />
| 0083<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE0_WRAP_FILTER<br />
|-<br />
| 0084<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE0_LOD<br />
|-<br />
| 0085<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR1<br />
|-<br />
| 0086<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR2<br />
|-<br />
| 0087<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR3<br />
|-<br />
| 0088<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR4<br />
|-<br />
| 0089<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR5<br />
|-<br />
| 008A<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]<br />
| <br />
|PICA_REG_TEXTURE0_ADDR6<br />
|-<br />
| 008B<br />
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]<br />
|?<br />
|PICA_REG_TEXTURE0_SHADOW<br />
|-<br />
| 008C<br />
| [[#GPUREG_008C|GPUREG_008C]]<br />
|<br />
|<br />
|-<br />
| 008D<br />
| [[#GPUREG_008D|GPUREG_008D]]<br />
|<br />
|<br />
|-<br />
| 008E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]<br />
|?<br />
|PICA_REG_TEXTURE0_FORMAT<br />
|-<br />
| 008F<br />
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN0<br />
|-<br />
| 0090<br />
| [[#GPUREG_0090|GPUREG_0090]]<br />
| <br />
|<br />
|-<br />
| 0091<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE1_BORDER_COLOR<br />
|-<br />
| 0092<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]<br />
| <br />
|PICA_REG_TEXTURE1_SIZE<br />
|-<br />
| 0093<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE1_WRAP_FILTER<br />
|-<br />
| 0094<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE1_LOD<br />
|-<br />
| 0095<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]<br />
| <br />
|PICA_REG_TEXTURE1_ADDR<br />
|-<br />
| 0096<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE1_FORMAT<br />
|-<br />
| 0097<br />
| [[#GPUREG_0097|GPUREG_0097]]<br />
| <br />
|<br />
|-<br />
| 0098<br />
| [[#GPUREG_0098|GPUREG_0098]]<br />
| <br />
|<br />
|-<br />
| 0099<br />
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]<br />
|<br />
|PICA_REG_TEXTURE2_BORDER_COLOR<br />
|-<br />
| 009A<br />
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]<br />
| <br />
|PICA_REG_TEXTURE2_SIZE<br />
|-<br />
| 009B<br />
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]<br />
| <br />
|PICA_REG_TEXTURE2_WRAP_FILTER<br />
|-<br />
| 009C<br />
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]<br />
|?<br />
|PICA_REG_TEXTURE2_LOD<br />
|-<br />
| 009D<br />
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]<br />
|<br />
|PICA_REG_TEXTURE2_ADDR<br />
|-<br />
| 009E<br />
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]<br />
| <br />
|PICA_REG_TEXTURE2_FORMAT<br />
|-<br />
| 009F<br />
| [[#GPUREG_009F|GPUREG_009F]]<br />
| <br />
|<br />
|-<br />
| 00A0<br />
| [[#GPUREG_00A0|GPUREG_00A0]]<br />
| <br />
|<br />
|-<br />
| 00A1<br />
| [[#GPUREG_00A1|GPUREG_00A1]]<br />
| <br />
|<br />
|-<br />
| 00A2<br />
| [[#GPUREG_00A2|GPUREG_00A2]]<br />
| <br />
|<br />
|-<br />
| 00A3<br />
| [[#GPUREG_00A3|GPUREG_00A3]]<br />
| <br />
|<br />
|-<br />
| 00A4<br />
| [[#GPUREG_00A4|GPUREG_00A4]]<br />
| <br />
|<br />
|-<br />
| 00A5<br />
| [[#GPUREG_00A5|GPUREG_00A5]]<br />
| <br />
|<br />
|-<br />
| 00A6<br />
| [[#GPUREG_00A6|GPUREG_00A6]]<br />
| <br />
|<br />
|-<br />
| 00A7<br />
| [[#GPUREG_00A7|GPUREG_00A7]]<br />
| <br />
|<br />
|-<br />
| 00A8<br />
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX0<br />
|-<br />
| 00A9<br />
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX1<br />
|-<br />
| 00AA<br />
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]<br />
|? <br />
|PICA_REG_TEXTURE3_PROCTEX2<br />
|-<br />
| 00AB<br />
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX3<br />
|-<br />
| 00AC<br />
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX4<br />
|-<br />
| 00AD<br />
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]<br />
|?<br />
|PICA_REG_TEXTURE3_PROCTEX5<br />
|-<br />
| 00AE<br />
| [[#GPUREG_00AE|GPUREG_00AE]]<br />
| <br />
|<br />
|-<br />
| 00AF<br />
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]<br />
|?<br />
|PICA_REG_PROCTEX_LUT<br />
|-<br />
| 00B0<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA0<br />
|-<br />
| 00B1<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA1<br />
|-<br />
| 00B2<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA2<br />
|-<br />
| 00B3<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA3<br />
|-<br />
| 00B4<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA4<br />
|-<br />
| 00B5<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA5<br />
|-<br />
| 00B6<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA6<br />
|-<br />
| 00B7<br />
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]<br />
| ?<br />
|PICA_REG_PROCTEX_LUT_DATA7<br />
|-<br />
| 00B8<br />
| [[#GPUREG_00B8|GPUREG_00B8]]<br />
| <br />
|<br />
|-<br />
| 00B9<br />
| [[#GPUREG_00B9|GPUREG_00B9]]<br />
| <br />
|<br />
|-<br />
| 00BA<br />
| [[#GPUREG_00BA|GPUREG_00BA]]<br />
| <br />
|<br />
|-<br />
| 00BB<br />
| [[#GPUREG_00BB|GPUREG_00BB]]<br />
| <br />
|<br />
|-<br />
| 00BC<br />
| [[#GPUREG_00BC|GPUREG_00BC]]<br />
| <br />
|<br />
|-<br />
| 00BD<br />
| [[#GPUREG_00BD|GPUREG_00BD]]<br />
| <br />
|<br />
|-<br />
| 00BE<br />
| [[#GPUREG_00BE|GPUREG_00BE]]<br />
| <br />
|<br />
|-<br />
| 00BF<br />
| [[#GPUREG_00BF|GPUREG_00BF]]<br />
| <br />
|<br />
|-<br />
| 00C0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_0<br />
|-<br />
| 00C1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_0_OPERAND<br />
|-<br />
| 00C2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COMBINE<br />
|-<br />
| 00C3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_0_COLOR<br />
|-<br />
| 00C4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_0_SCALE<br />
|-<br />
| 00C5<br />
| [[#GPUREG_00C5|GPUREG_00C5]]<br />
| <br />
|<br />
|-<br />
| 00C6<br />
| [[#GPUREG_00C6|GPUREG_00C6]]<br />
| <br />
|<br />
|-<br />
| 00C7<br />
| [[#GPUREG_00C7|GPUREG_00C7]]<br />
| <br />
|<br />
|-<br />
| 00C8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_1<br />
|-<br />
| 00C9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_1_OPERAND<br />
|-<br />
| 00CA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COMBINE<br />
|-<br />
| 00CB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_1_COLOR<br />
|-<br />
| 00CC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_1_SCALE<br />
|-<br />
| 00CD<br />
| [[#GPUREG_00CD|GPUREG_00CD]]<br />
| <br />
|<br />
|-<br />
| 00CE<br />
| [[#GPUREG_00CE|GPUREG_00CE]]<br />
| <br />
|<br />
|-<br />
| 00CF<br />
| [[#GPUREG_00CF|GPUREG_00CF]]<br />
| <br />
|<br />
|-<br />
| 00D0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_2<br />
|-<br />
| 00D1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_2_OPERAND<br />
|-<br />
| 00D2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COMBINE<br />
|-<br />
| 00D3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_2_COLOR<br />
|-<br />
| 00D4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_2_SCALE<br />
|-<br />
| 00D5<br />
| [[#GPUREG_00D5|GPUREG_00D5]]<br />
| <br />
|<br />
|-<br />
| 00D6<br />
| [[#GPUREG_00D6|GPUREG_00D6]]<br />
| <br />
|<br />
|-<br />
| 00D7<br />
| [[#GPUREG_00D7|GPUREG_00D7]]<br />
| <br />
|<br />
|-<br />
| 00D8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_3<br />
|-<br />
| 00D9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_3_OPERAND<br />
|-<br />
| 00DA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COMBINE<br />
|-<br />
| 00DB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_3_COLOR<br />
|-<br />
| 00DC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_3_SCALE<br />
|-<br />
| 00DD<br />
| [[#GPUREG_00DD|GPUREG_00DD]]<br />
| <br />
|<br />
|-<br />
| 00DE<br />
| [[#GPUREG_00DE|GPUREG_00DE]]<br />
| <br />
|<br />
|-<br />
| 00DF<br />
| [[#GPUREG_00DF|GPUREG_00DF]]<br />
| <br />
|<br />
|-<br />
| 00E0<br />
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]<br />
|?<br />
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT<br />
|-<br />
| 00E1<br />
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]<br />
|?<br />
|PICA_REG_FOG_COLOR<br />
|-<br />
| 00E2<br />
| [[#GPUREG_00E2|GPUREG_00E2]]<br />
| <br />
|<br />
|-<br />
| 00E3<br />
| [[#GPUREG_00E3|GPUREG_00E3]]<br />
| <br />
|<br />
|-<br />
| 00E4<br />
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]<br />
|?<br />
|PICA_REG_GAS_ATTENUATION<br />
|-<br />
| 00E5<br />
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]<br />
|?<br />
|PICA_REG_GAS_ACCMAX<br />
|-<br />
| 00E6<br />
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FOG_LUT_INDEX<br />
|-<br />
| 00E7<br />
| [[#GPUREG_00E7|GPUREG_00E7]]<br />
| <br />
|<br />
|-<br />
| 00E8<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA0<br />
|-<br />
| 00E9<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]<br />
|? <br />
|PICA_REG_FOG_LUT_DATA1<br />
|-<br />
| 00EA<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA2<br />
|-<br />
| 00EB<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA3<br />
|-<br />
| 00EC<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA4<br />
|-<br />
| 00ED<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA5<br />
|-<br />
| 00EE<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA6<br />
|-<br />
| 00EF<br />
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FOG_LUT_DATA7<br />
|-<br />
| 00F0<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_4<br />
|-<br />
| 00F1<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_4_OPERAND<br />
|-<br />
| 00F2<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COMBINE<br />
|-<br />
| 00F3<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_4_COLOR<br />
|-<br />
| 00F4<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_4_SCALE<br />
|-<br />
| 00F5<br />
| [[#GPUREG_00F5|GPUREG_00F5]]<br />
| <br />
|<br />
|-<br />
| 00F6<br />
| [[#GPUREG_00F6|GPUREG_00F6]]<br />
| <br />
|<br />
|-<br />
| 00F7<br />
| [[#GPUREG_00F7|GPUREG_00F7]]<br />
| <br />
|<br />
|-<br />
| 00F8<br />
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]<br />
| <br />
|PICA_REG_TEX_ENV_5<br />
|-<br />
| 00F9<br />
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]<br />
| <br />
|PICA_REG_TEX_ENV_5_OPERAND<br />
|-<br />
| 00FA<br />
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COMBINE<br />
|-<br />
| 00FB<br />
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]<br />
| <br />
|PICA_REG_TEX_ENV_5_COLOR<br />
|-<br />
| 00FC<br />
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]<br />
| <br />
|PICA_REG_TEX_ENV_5_SCALE<br />
|-<br />
| 00FD<br />
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]<br />
|?<br />
|PICA_REG_TEX_ENV_BUF_COLOR<br />
|-<br />
| 00FE<br />
| [[#GPUREG_00FE|GPUREG_00FE]]<br />
| <br />
|<br />
|-<br />
| 00FF<br />
| [[#GPUREG_00FF|GPUREG_00FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Framebuffer registers (0x100-0x13F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0100<br />
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]<br />
|<br />
|PICA_REG_COLOR_OPERATION<br />
|-<br />
| 0101<br />
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]<br />
| <br />
|PICA_REG_BLEND_FUNC<br />
|-<br />
| 0102<br />
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]<br />
| <br />
|PICA_REG_LOGIC_OP<br />
|-<br />
| 0103<br />
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]<br />
| <br />
|PICA_REG_BLEND_COLOR<br />
|-<br />
| 0104<br />
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]<br />
| <br />
|PICA_REG_FRAGOP_ALPHA_TEST<br />
|-<br />
| 0105<br />
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]<br />
| <br />
|PICA_REG_STENCIL_TEST<br />
|-<br />
| 0106<br />
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]<br />
| <br />
|PICA_REG_STENCIL_OP<br />
|-<br />
| 0107<br />
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]<br />
| <br />
|PICA_REG_DEPTH_COLOR_MASK<br />
|-<br />
| 0108<br />
| [[#GPUREG_0108|GPUREG_0108]]<br />
| <br />
|<br />
|-<br />
| 0109<br />
| [[#GPUREG_0109|GPUREG_0109]]<br />
| <br />
|<br />
|-<br />
| 010A<br />
| [[#GPUREG_010A|GPUREG_010A]]<br />
| <br />
|<br />
|-<br />
| 010B<br />
| [[#GPUREG_010B|GPUREG_010B]]<br />
| <br />
|<br />
|-<br />
| 010C<br />
| [[#GPUREG_010C|GPUREG_010C]]<br />
| <br />
|<br />
|-<br />
| 010D<br />
| [[#GPUREG_010D|GPUREG_010D]]<br />
| <br />
|<br />
|-<br />
| 010E<br />
| [[#GPUREG_010E|GPUREG_010E]]<br />
| <br />
|<br />
|-<br />
| 010F<br />
| [[#GPUREG_010F|GPUREG_010F]]<br />
| <br />
|<br />
|-<br />
| 0110<br />
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR0<br />
|-<br />
| 0111<br />
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]<br />
|<br />
|PICA_REG_COLOR_BUFFER_CLEAR1<br />
|-<br />
| 0112<br />
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_READ<br />
|-<br />
| 0113<br />
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]<br />
| <br />
|PICA_REG_COLOR_BUFFER_WRITE<br />
|-<br />
| 0114<br />
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_READ<br />
|-<br />
| 0115<br />
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]<br />
| <br />
|PICA_REG_DEPTH_STENCIL_WRITE<br />
|-<br />
| 0116<br />
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_DEPTH_MODE<br />
|-<br />
| 0117<br />
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_MODE<br />
|-<br />
| 0118<br />
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]<br />
|?<br />
|PICA_REG_EARLY_DEPTH_TEST2<br />
|-<br />
| 0119<br />
| [[#GPUREG_0119|GPUREG_0119]]<br />
| <br />
|<br />
|-<br />
| 011A<br />
| [[#GPUREG_011A|GPUREG_011A]]<br />
| <br />
|<br />
|-<br />
| 011B<br />
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]<br />
|<br />
|PICA_REG_RENDER_BLOCK_FORMAT<br />
|-<br />
| 011C<br />
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]<br />
|<br />
|PICA_REG_RENDER_BUF_DEPTH_ADDR<br />
|-<br />
| 011D<br />
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]<br />
| <br />
|PICA_REG_RENDER_BUF_COLOR_ADDR<br />
|-<br />
| 011E<br />
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]<br />
| <br />
|PICA_REG_RENDER_BUF_RESOLUTION0<br />
|-<br />
| 011F<br />
| [[#GPUREG_011F|GPUREG_011F]]<br />
| <br />
|<br />
|-<br />
| 0120<br />
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_XY<br />
|-<br />
| 0121<br />
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z<br />
|-<br />
| 0122<br />
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]<br />
|?<br />
|PICA_REG_GAS_LIGHT_Z_COLOR<br />
|-<br />
| 0123<br />
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]<br />
|?<br />
|PICA_REG_GAS_LUT_INDEX<br />
|-<br />
| 0124<br />
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]<br />
|?<br />
|PICA_REG_GAS_LUT_DATA<br />
|-<br />
| 0125<br />
| [[#GPUREG_0125|GPUREG_0125]]<br />
| <br />
|<br />
|-<br />
| 0126<br />
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]<br />
|?<br />
|PICA_REG_GAS_DELTAZ_DEPTH<br />
|-<br />
| 0127<br />
| [[#GPUREG_0127|GPUREG_0127]]<br />
| <br />
|<br />
|-<br />
| 0128<br />
| [[#GPUREG_0128|GPUREG_0128]]<br />
| <br />
|<br />
|-<br />
| 0129<br />
| [[#GPUREG_0129|GPUREG_0129]]<br />
| <br />
|<br />
|-<br />
| 012A<br />
| [[#GPUREG_012A|GPUREG_012A]]<br />
| <br />
|<br />
|-<br />
| 012B<br />
| [[#GPUREG_012B|GPUREG_012B]]<br />
| <br />
|<br />
|-<br />
| 012C<br />
| [[#GPUREG_012C|GPUREG_012C]]<br />
| <br />
|<br />
|-<br />
| 012D<br />
| [[#GPUREG_012D|GPUREG_012D]]<br />
| <br />
|<br />
|-<br />
| 012E<br />
| [[#GPUREG_012E|GPUREG_012E]]<br />
| <br />
|<br />
|-<br />
| 012F<br />
| [[#GPUREG_012F|GPUREG_012F]]<br />
| <br />
|<br />
|-<br />
| 0130<br />
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]<br />
|?<br />
|PICA_REG_FRAGOP_SHADOW<br />
|-<br />
| 0131<br />
| [[#GPUREG_0131|GPUREG_0131]]<br />
| <br />
|<br />
|-<br />
| 0132<br />
| [[#GPUREG_0132|GPUREG_0132]]<br />
| <br />
|<br />
|-<br />
| 0133<br />
| [[#GPUREG_0133|GPUREG_0133]]<br />
| <br />
|<br />
|-<br />
| 0134<br />
| [[#GPUREG_0134|GPUREG_0134]]<br />
| <br />
|<br />
|-<br />
| 0135<br />
| [[#GPUREG_0135|GPUREG_0135]]<br />
| <br />
|<br />
|-<br />
| 0136<br />
| [[#GPUREG_0136|GPUREG_0136]]<br />
| <br />
|<br />
|-<br />
| 0137<br />
| [[#GPUREG_0137|GPUREG_0137]]<br />
| <br />
|<br />
|-<br />
| 0138<br />
| [[#GPUREG_0138|GPUREG_0138]]<br />
| <br />
|<br />
|-<br />
| 0139<br />
| [[#GPUREG_0139|GPUREG_0139]]<br />
| <br />
|<br />
|-<br />
| 013A<br />
| [[#GPUREG_013A|GPUREG_013A]]<br />
| <br />
|<br />
|-<br />
| 013B<br />
| [[#GPUREG_013B|GPUREG_013B]]<br />
| <br />
|<br />
|-<br />
| 013C<br />
| [[#GPUREG_013C|GPUREG_013C]]<br />
| <br />
|<br />
|-<br />
| 013D<br />
| [[#GPUREG_013D|GPUREG_013D]]<br />
| <br />
|<br />
|-<br />
| 013E<br />
| [[#GPUREG_013E|GPUREG_013E]]<br />
| <br />
|<br />
|-<br />
| 013F<br />
| [[#GPUREG_013F|GPUREG_013F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Fragment lighting registers (0x140-0x1FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0140<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START<br />
|-<br />
| 0141<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPECULAR1<br />
|-<br />
| 0142<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIFFUSE<br />
|-<br />
| 0143<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_AMBIENT<br />
|-<br />
| 0144<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_XY<br />
|-<br />
| 0145<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_POSITION_Z<br />
|-<br />
| 0146<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_XY<br />
|-<br />
| 0147<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_SPOT_Z<br />
|-<br />
| 0148<br />
| [[#GPUREG_0148|GPUREG_0148]]<br />
| <br />
|<br />
|-<br />
| 0149<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]<br />
| <br />
|PICA_REG_FRAG_LIGHT0_TYPE<br />
|-<br />
| 014A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS<br />
|-<br />
| 014B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE<br />
|-<br />
| 014C<br />
| [[#GPUREG_014C|GPUREG_014C]]<br />
| <br />
|<br />
|-<br />
| 014D<br />
| [[#GPUREG_014D|GPUREG_014D]]<br />
| <br />
|<br />
|-<br />
| 014E<br />
| [[#GPUREG_014E|GPUREG_014E]]<br />
| <br />
|<br />
|-<br />
| 014F<br />
| [[#GPUREG_014F|GPUREG_014F]]<br />
| <br />
|<br />
|-<br />
| 0150<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR0<br />
|-<br />
| 0151<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPECULAR1<br />
|-<br />
| 0152<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIFFUSE<br />
|-<br />
| 0153<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_AMBIENT<br />
|-<br />
| 0154<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_XY<br />
|-<br />
| 0155<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_POSITION_Z<br />
|-<br />
| 0156<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_XY<br />
|-<br />
| 0157<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_SPOT_Z<br />
|-<br />
| 0158<br />
| [[#GPUREG_0158|GPUREG_0158]]<br />
| <br />
|<br />
|-<br />
| 0159<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_TYPE<br />
|-<br />
| 015A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS<br />
|-<br />
| 015B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE<br />
|-<br />
| 015C<br />
| [[#GPUREG_015C|GPUREG_015C]]<br />
| <br />
|<br />
|-<br />
| 015D<br />
| [[#GPUREG_015D|GPUREG_015D]]<br />
| <br />
|<br />
|-<br />
| 015E<br />
| [[#GPUREG_015E|GPUREG_015E]]<br />
| <br />
|<br />
|-<br />
| 015F<br />
| [[#GPUREG_015F|GPUREG_015F]]<br />
| <br />
|<br />
|-<br />
| 0160<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR0<br />
|-<br />
| 0161<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPECULAR1<br />
|-<br />
| 0162<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIFFUSE<br />
|-<br />
| 0163<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_AMBIENT<br />
|-<br />
| 0164<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_XY<br />
|-<br />
| 0165<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_POSITION_Z<br />
|-<br />
| 0166<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_XY<br />
|-<br />
| 0167<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_SPOT_Z<br />
|-<br />
| 0168<br />
| [[#GPUREG_0168|GPUREG_0168]]<br />
| <br />
|<br />
|-<br />
| 0169<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_TYPE<br />
|-<br />
| 016A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS<br />
|-<br />
| 016B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE<br />
|-<br />
| 016C<br />
| [[#GPUREG_016C|GPUREG_016C]]<br />
| <br />
|<br />
|-<br />
| 016D<br />
| [[#GPUREG_016D|GPUREG_016D]]<br />
| <br />
|<br />
|-<br />
| 016E<br />
| [[#GPUREG_016E|GPUREG_016E]]<br />
| <br />
|<br />
|-<br />
| 016F<br />
| [[#GPUREG_016F|GPUREG_016F]]<br />
| <br />
|<br />
|-<br />
| 0170<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR0<br />
|-<br />
| 0171<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPECULAR1<br />
|-<br />
| 0172<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIFFUSE<br />
|-<br />
| 0173<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_AMBIENT<br />
|-<br />
| 0174<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_XY<br />
|-<br />
| 0175<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_POSITION_Z<br />
|-<br />
| 0176<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]<br />
|? <br />
|PICA_REG_FRAG_LIGHT3_SPOT_XY<br />
|-<br />
| 0177<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_SPOT_Z<br />
|-<br />
| 0178<br />
| [[#GPUREG_0178|GPUREG_0178]]<br />
| <br />
|<br />
|-<br />
| 0179<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_TYPE<br />
|-<br />
| 017A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS<br />
|-<br />
| 017B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE<br />
|-<br />
| 017C<br />
| [[#GPUREG_017C|GPUREG_017C]]<br />
| <br />
|<br />
|-<br />
| 017D<br />
| [[#GPUREG_017D|GPUREG_017D]]<br />
| <br />
|<br />
|-<br />
| 017E<br />
| [[#GPUREG_017E|GPUREG_017E]]<br />
| <br />
|<br />
|-<br />
| 017F<br />
| [[#GPUREG_017F|GPUREG_017F]]<br />
| <br />
|<br />
|-<br />
| 0180<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR0<br />
|-<br />
| 0181<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPECULAR1<br />
|-<br />
| 0182<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIFFUSE<br />
|-<br />
| 0183<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_AMBIENT<br />
|-<br />
| 0184<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_XY<br />
|-<br />
| 0185<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_POSITION_Z<br />
|-<br />
| 0186<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_XY<br />
|-<br />
| 0187<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_SPOT_Z<br />
|-<br />
| 0188<br />
| [[#GPUREG_0188|GPUREG_0188]]<br />
| <br />
|<br />
|-<br />
| 0189<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_TYPE<br />
|-<br />
| 018A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS<br />
|-<br />
| 018B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE<br />
|-<br />
| 018C<br />
| [[#GPUREG_018C|GPUREG_018C]]<br />
| <br />
|<br />
|-<br />
| 018D<br />
| [[#GPUREG_018D|GPUREG_018D]]<br />
| <br />
|<br />
|-<br />
| 018E<br />
| [[#GPUREG_018E|GPUREG_018E]]<br />
| <br />
|<br />
|-<br />
| 018F<br />
| [[#GPUREG_018F|GPUREG_018F]]<br />
| <br />
|<br />
|-<br />
| 0190<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR0<br />
|-<br />
| 0191<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPECULAR1<br />
|-<br />
| 0192<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_DIFFUSE<br />
|-<br />
| 0193<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_AMBIENT<br />
|-<br />
| 0194<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_XY<br />
|-<br />
| 0195<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_POSITION_Z<br />
|-<br />
| 0196<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_XY<br />
|-<br />
| 0197<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_SPOT_Z<br />
|-<br />
| 0198<br />
| [[#GPUREG_0198|GPUREG_0198]]<br />
| <br />
|<br />
|-<br />
| 0199<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT5_TYPE<br />
|-<br />
| 019A<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS<br />
|-<br />
| 019B<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE<br />
|-<br />
| 019C<br />
| [[#GPUREG_019C|GPUREG_019C]]<br />
| <br />
|<br />
|-<br />
| 019D<br />
| [[#GPUREG_019D|GPUREG_019D]]<br />
| <br />
|<br />
|-<br />
| 019E<br />
| [[#GPUREG_019E|GPUREG_019E]]<br />
| <br />
|<br />
|-<br />
| 019F<br />
| [[#GPUREG_019F|GPUREG_019F]]<br />
| <br />
|<br />
|-<br />
| 01A0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR0<br />
|-<br />
| 01A1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPECULAR1<br />
|-<br />
| 01A2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIFFUSE<br />
|-<br />
| 01A3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_AMBIENT<br />
|-<br />
| 01A4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_XY<br />
|-<br />
| 01A5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_POSITION_Z<br />
|-<br />
| 01A6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_XY<br />
|-<br />
| 01A7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_SPOT_Z<br />
|-<br />
| 01A8<br />
| [[#GPUREG_01A8|GPUREG_01A8]]<br />
| <br />
|<br />
|-<br />
| 01A9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT6_TYPE<br />
|-<br />
| 01AA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS<br />
|-<br />
| 01AB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE<br />
|-<br />
| 01AC<br />
| [[#GPUREG_01AC|GPUREG_01AC]]<br />
| <br />
|<br />
|-<br />
| 01AD<br />
| [[#GPUREG_01AD|GPUREG_01AD]]<br />
| <br />
|<br />
|-<br />
| 01AE<br />
| [[#GPUREG_01AE|GPUREG_01AE]]<br />
| <br />
|<br />
|-<br />
| 01AF<br />
| [[#GPUREG_01AF|GPUREG_01AF]]<br />
| <br />
|<br />
|-<br />
| 01B0<br />
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR0<br />
|-<br />
| 01B1<br />
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPECULAR1<br />
|-<br />
| 01B2<br />
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_DIFFUSE<br />
|-<br />
| 01B3<br />
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_AMBIENT<br />
|-<br />
| 01B4<br />
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_XY<br />
|-<br />
| 01B5<br />
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_POSITION_Z<br />
|-<br />
| 01B6<br />
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_XY<br />
|-<br />
| 01B7<br />
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_SPOT_Z<br />
|-<br />
| 01B8<br />
| [[#GPUREG_01B8|GPUREG_01B8]]<br />
| <br />
|<br />
|-<br />
| 01B9<br />
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT7_TYPE<br />
|-<br />
| 01BA<br />
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS<br />
|-<br />
| 01BB<br />
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]<br />
| <br />
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE<br />
|-<br />
| 01BC<br />
| [[#GPUREG_01BC|GPUREG_01BC]]<br />
| <br />
|<br />
|-<br />
| 01BD<br />
| [[#GPUREG_01BD|GPUREG_01BD]]<br />
| <br />
|<br />
|-<br />
| 01BE<br />
| [[#GPUREG_01BE|GPUREG_01BE]]<br />
| <br />
|<br />
|-<br />
| 01BF<br />
| [[#GPUREG_01BF|GPUREG_01BF]]<br />
| <br />
|<br />
|-<br />
| 01C0<br />
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_AMBIENT<br />
|-<br />
| 01C1<br />
| [[#GPUREG_01C1|GPUREG_01C1]]<br />
| <br />
|<br />
|-<br />
| 01C2<br />
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_NUM<br />
|-<br />
| 01C3<br />
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE0<br />
|-<br />
| 01C4<br />
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_FUNC_MODE1<br />
|-<br />
| 01C5<br />
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT<br />
|-<br />
| 01C6<br />
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_EN1<br />
|-<br />
| 01C7<br />
| [[#GPUREG_01C7|GPUREG_01C7]]<br />
| <br />
|<br />
|-<br />
| 01C8<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA0<br />
|-<br />
| 01C9<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA1<br />
|-<br />
| 01CA<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA2<br />
|-<br />
| 01CB<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA3<br />
|-<br />
| 01CC<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA4<br />
|-<br />
| 01CD<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA5<br />
|-<br />
| 01CE<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA6<br />
|-<br />
| 01CF<br />
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUT_DATA7<br />
|-<br />
| 01D0<br />
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT<br />
|-<br />
| 01D1<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTINPUT<br />
|-<br />
| 01D2<br />
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_LUTSCALE<br />
|-<br />
| 01D3<br />
| [[#GPUREG_01D3|GPUREG_01D3]]<br />
| <br />
|<br />
|-<br />
| 01D4<br />
| [[#GPUREG_01D4|GPUREG_01D4]]<br />
| <br />
|<br />
|-<br />
| 01D5<br />
| [[#GPUREG_01D5|GPUREG_01D5]]<br />
| <br />
|<br />
|-<br />
| 01D6<br />
| [[#GPUREG_01D6|GPUREG_01D6]]<br />
| <br />
|<br />
|-<br />
| 01D7<br />
| [[#GPUREG_01D7|GPUREG_01D7]]<br />
| <br />
|<br />
|-<br />
| 01D8<br />
| [[#GPUREG_01D8|GPUREG_01D8]]<br />
| <br />
|<br />
|-<br />
| 01D9<br />
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]<br />
|?<br />
|PICA_REG_FRAG_LIGHT_SRC_EN_ID<br />
|-<br />
| 01DA<br />
| [[#GPUREG_01DA|GPUREG_01DA]]<br />
| <br />
|<br />
|-<br />
| 01DB<br />
| [[#GPUREG_01DB|GPUREG_01DB]]<br />
| <br />
|<br />
|-<br />
| 01DC<br />
| [[#GPUREG_01DC|GPUREG_01DC]]<br />
| <br />
|<br />
|-<br />
| 01DD<br />
| [[#GPUREG_01DD|GPUREG_01DD]]<br />
| <br />
|<br />
|-<br />
| 01DE<br />
| [[#GPUREG_01DE|GPUREG_01DE]]<br />
| <br />
|<br />
|-<br />
| 01DF<br />
| [[#GPUREG_01DF|GPUREG_01DF]]<br />
| <br />
|<br />
|-<br />
| 01E0<br />
| [[#GPUREG_01E0|GPUREG_01E0]]<br />
| <br />
|<br />
|-<br />
| 01E1<br />
| [[#GPUREG_01E1|GPUREG_01E1]]<br />
| <br />
|<br />
|-<br />
| 01E2<br />
| [[#GPUREG_01E2|GPUREG_01E2]]<br />
| <br />
|<br />
|-<br />
| 01E3<br />
| [[#GPUREG_01E3|GPUREG_01E3]]<br />
| <br />
|<br />
|-<br />
| 01E4<br />
| [[#GPUREG_01E4|GPUREG_01E4]]<br />
| <br />
|<br />
|-<br />
| 01E5<br />
| [[#GPUREG_01E5|GPUREG_01E5]]<br />
| <br />
|<br />
|-<br />
| 01E6<br />
| [[#GPUREG_01E6|GPUREG_01E6]]<br />
| <br />
|<br />
|-<br />
| 01E7<br />
| [[#GPUREG_01E7|GPUREG_01E7]]<br />
| <br />
|<br />
|-<br />
| 01E8<br />
| [[#GPUREG_01E8|GPUREG_01E8]]<br />
| <br />
|<br />
|-<br />
| 01E9<br />
| [[#GPUREG_01E9|GPUREG_01E9]]<br />
| <br />
|<br />
|-<br />
| 01EA<br />
| [[#GPUREG_01EA|GPUREG_01EA]]<br />
| <br />
|<br />
|-<br />
| 01EB<br />
| [[#GPUREG_01EB|GPUREG_01EB]]<br />
| <br />
|<br />
|-<br />
| 01EC<br />
| [[#GPUREG_01EC|GPUREG_01EC]]<br />
| <br />
|<br />
|-<br />
| 01ED<br />
| [[#GPUREG_01ED|GPUREG_01ED]]<br />
| <br />
|<br />
|-<br />
| 01EE<br />
| [[#GPUREG_01EE|GPUREG_01EE]]<br />
| <br />
|<br />
|-<br />
| 01EF<br />
| [[#GPUREG_01EF|GPUREG_01EF]]<br />
| <br />
|<br />
|-<br />
| 01F0<br />
| [[#GPUREG_01F0|GPUREG_01F0]]<br />
| <br />
|<br />
|-<br />
| 01F1<br />
| [[#GPUREG_01F1|GPUREG_01F1]]<br />
| <br />
|<br />
|-<br />
| 01F2<br />
| [[#GPUREG_01F2|GPUREG_01F2]]<br />
| <br />
|<br />
|-<br />
| 01F3<br />
| [[#GPUREG_01F3|GPUREG_01F3]]<br />
| <br />
|<br />
|-<br />
| 01F4<br />
| [[#GPUREG_01F4|GPUREG_01F4]]<br />
| <br />
|<br />
|-<br />
| 01F5<br />
| [[#GPUREG_01F5|GPUREG_01F5]]<br />
| <br />
|<br />
|-<br />
| 01F6<br />
| [[#GPUREG_01F6|GPUREG_01F6]]<br />
| <br />
|<br />
|-<br />
| 01F7<br />
| [[#GPUREG_01F7|GPUREG_01F7]]<br />
| <br />
|<br />
|-<br />
| 01F8<br />
| [[#GPUREG_01F8|GPUREG_01F8]]<br />
| <br />
|<br />
|-<br />
| 01F9<br />
| [[#GPUREG_01F9|GPUREG_01F9]]<br />
| <br />
|<br />
|-<br />
| 01FA<br />
| [[#GPUREG_01FA|GPUREG_01FA]]<br />
| <br />
|<br />
|-<br />
| 01FB<br />
| [[#GPUREG_01FB|GPUREG_01FB]]<br />
| <br />
|<br />
|-<br />
| 01FC<br />
| [[#GPUREG_01FC|GPUREG_01FC]]<br />
| <br />
|<br />
|-<br />
| 01FD<br />
| [[#GPUREG_01FD|GPUREG_01FD]]<br />
| <br />
|<br />
|-<br />
| 01FE<br />
| [[#GPUREG_01FE|GPUREG_01FE]]<br />
| <br />
|<br />
|-<br />
| 01FF<br />
| [[#GPUREG_01FF|GPUREG_01FF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Geometry pipeline registers (0x200-0x27F) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 0200<br />
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR<br />
|-<br />
| 0201<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS0<br />
|-<br />
| 0202<br />
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]<br />
| <br />
|PICA_REG_VTX_ATTR_ARRAYS1<br />
|-<br />
| 0203<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET<br />
|-<br />
| 0204<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT0<br />
|-<br />
| 0205<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]<br />
| <br />
|PICA_REG_LOAD_ARRAY0_ELEMENT1<br />
|-<br />
| 0206<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0207<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0208<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0209<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020B<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020C<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 020D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 020E<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 020F<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0210<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0211<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0212<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0213<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0214<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0215<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0216<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0217<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0218<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0219<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021A<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021B<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021C<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 021D<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 021E<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 021F<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0220<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0221<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0222<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0223<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0224<br />
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]<br />
| <br />
|<br />
|-<br />
| 0225<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]<br />
| <br />
|<br />
|-<br />
| 0226<br />
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]<br />
| <br />
|<br />
|-<br />
| 0227<br />
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET<br />
|-<br />
| 0228<br />
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]<br />
| <br />
|PICA_REG_DRAW_VERTEX_NUM<br />
|-<br />
| 0229<br />
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]<br />
| ?<br />
|PICA_REG_DRAW_MODE0<br />
|-<br />
| 022A<br />
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]<br />
|<br />
|PICA_REG_DRAW_VERTEX_OFFSET<br />
|-<br />
| 022B<br />
| [[#GPUREG_022B|GPUREG_022B]]<br />
| <br />
|<br />
|-<br />
| 022C<br />
| [[#GPUREG_022C|GPUREG_022C]]<br />
| <br />
|<br />
|-<br />
| 022D<br />
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]<br />
| <br />
|PICA_REG_POST_VERTEX_CACHE_NUM<br />
|-<br />
| 022E<br />
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]<br />
|<br />
|PICA_REG_START_DRAW_ARRAY<br />
|-<br />
| 022F<br />
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]<br />
|<br />
|PICA_REG_START_DRAW_ELEMENT<br />
|-<br />
| 0230<br />
| [[#GPUREG_0230|GPUREG_0230]]<br />
| <br />
|<br />
|-<br />
| 0231<br />
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]<br />
|?<br />
|PICA_REG_VTX_FUNC<br />
|-<br />
| 0232<br />
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR<br />
|-<br />
| 0233<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA0<br />
|-<br />
| 0234<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA1<br />
|-<br />
| 0235<br />
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]<br />
|?<br />
|PICA_REG_VS_FIXED_ATTR_DATA2<br />
|-<br />
| 0236<br />
| [[#GPUREG_0236|GPUREG_0236]]<br />
| <br />
|<br />
|-<br />
| 0237<br />
| [[#GPUREG_0237|GPUREG_0237]]<br />
| <br />
|<br />
|-<br />
| 0238<br />
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH0<br />
|-<br />
| 0239<br />
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_SIZE_CH1<br />
|-<br />
| 023A<br />
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH0<br />
|-<br />
| 023B<br />
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_ADDR_CH1<br />
|-<br />
| 023C<br />
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH0<br />
|-<br />
| 023D<br />
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]<br />
| <br />
|PICA_REG_COMMAND_BUF_KICK_CH1<br />
|-<br />
| 023E<br />
| [[#GPUREG_023E|GPUREG_023E]]<br />
| <br />
|<br />
|-<br />
| 023F<br />
| [[#GPUREG_023F|GPUREG_023F]]<br />
| <br />
|<br />
|-<br />
| 0240<br />
| [[#GPUREG_0240|GPUREG_0240]]<br />
| <br />
|<br />
|-<br />
| 0241<br />
| [[#GPUREG_0241|GPUREG_0241]]<br />
| <br />
|<br />
|-<br />
| 0242<br />
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]<br />
|?<br />
|PICA_REG_VS_ATTR_NUM1<br />
|-<br />
| 0243<br />
| [[#GPUREG_0243|GPUREG_0243]]<br />
| <br />
|<br />
|-<br />
| 0244<br />
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]<br />
|?<br />
|PICA_REG_VS_COM_MODE<br />
|-<br />
| 0245<br />
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC0<br />
|-<br />
| 0246<br />
| [[#GPUREG_0246|GPUREG_0246]]<br />
| <br />
|<br />
|-<br />
| 0247<br />
| [[#GPUREG_0247|GPUREG_0247]]<br />
| <br />
|<br />
|-<br />
| 0248<br />
| [[#GPUREG_0248|GPUREG_0248]]<br />
| <br />
|<br />
|-<br />
| 0249<br />
| [[#GPUREG_0249|GPUREG_0249]]<br />
| <br />
|<br />
|-<br />
| 024A<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM1<br />
|-<br />
| 024B<br />
| [[#GPUREG_024B|GPUREG_024B]]<br />
|<br />
|<br />
|-<br />
| 024C<br />
| [[#GPUREG_024C|GPUREG_024C]]<br />
| <br />
|<br />
|-<br />
| 024D<br />
| [[#GPUREG_024D|GPUREG_024D]]<br />
| <br />
|<br />
|-<br />
| 024E<br />
| [[#GPUREG_024E|GPUREG_024E]]<br />
| <br />
|<br />
|-<br />
| 024F<br />
| [[#GPUREG_024F|GPUREG_024F]]<br />
| <br />
|<br />
|-<br />
| 0250<br />
| [[#GPUREG_0250|GPUREG_0250]]<br />
| <br />
|<br />
|-<br />
| 0251<br />
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]<br />
|?<br />
|PICA_REG_VS_OUT_REG_NUM2<br />
|-<br />
| 0252<br />
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]<br />
|?<br />
|PICA_REG_GS_MISC_REG0<br />
|-<br />
| 0253<br />
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]<br />
|?<br />
|PICA_REG_DRAW_MODE1<br />
|-<br />
| 0254<br />
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]<br />
|?<br />
|PICA_REG_GS_MISC_REG1<br />
|-<br />
| 0255<br />
| [[#GPUREG_0255|GPUREG_0255]]<br />
| <br />
|<br />
|-<br />
| 0256<br />
| [[#GPUREG_0256|GPUREG_0256]]<br />
| <br />
|<br />
|-<br />
| 0257<br />
| [[#GPUREG_0257|GPUREG_0257]]<br />
| <br />
|<br />
|-<br />
| 0258<br />
| [[#GPUREG_0258|GPUREG_0258]]<br />
| <br />
|<br />
|-<br />
| 0259<br />
| [[#GPUREG_0259|GPUREG_0259]]<br />
| <br />
|<br />
|-<br />
| 025A<br />
| [[#GPUREG_025A|GPUREG_025A]]<br />
| <br />
|<br />
|-<br />
| 025B<br />
| [[#GPUREG_025B|GPUREG_025B]]<br />
| <br />
|<br />
|-<br />
| 025C<br />
| [[#GPUREG_025C|GPUREG_025C]]<br />
| <br />
|<br />
|-<br />
| 025D<br />
| [[#GPUREG_025D|GPUREG_025D]]<br />
| <br />
|<br />
|-<br />
| 025E<br />
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]<br />
| ?<br />
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3<br />
|-<br />
| 025F<br />
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]<br />
|?<br />
|PICA_REG_START_DRAW_FUNC1<br />
|-<br />
| 0260<br />
| [[#GPUREG_0260|GPUREG_0260]]<br />
| <br />
|<br />
|-<br />
| 0261<br />
| [[#GPUREG_0261|GPUREG_0261]]<br />
| <br />
|<br />
|-<br />
| 0262<br />
| [[#GPUREG_0262|GPUREG_0262]]<br />
| <br />
|<br />
|-<br />
| 0263<br />
| [[#GPUREG_0263|GPUREG_0263]]<br />
| <br />
|<br />
|-<br />
| 0264<br />
| [[#GPUREG_0264|GPUREG_0264]]<br />
| <br />
|<br />
|-<br />
| 0265<br />
| [[#GPUREG_0265|GPUREG_0265]]<br />
| <br />
|<br />
|-<br />
| 0266<br />
| [[#GPUREG_0266|GPUREG_0266]]<br />
| <br />
|<br />
|-<br />
| 0267<br />
| [[#GPUREG_0267|GPUREG_0267]]<br />
| <br />
|<br />
|-<br />
| 0268<br />
| [[#GPUREG_0268|GPUREG_0268]]<br />
| <br />
|<br />
|-<br />
| 0269<br />
| [[#GPUREG_0269|GPUREG_0269]]<br />
| <br />
|<br />
|-<br />
| 026A<br />
| [[#GPUREG_026A|GPUREG_026A]]<br />
| <br />
|<br />
|-<br />
| 026B<br />
| [[#GPUREG_026B|GPUREG_026B]]<br />
| <br />
|<br />
|-<br />
| 026C<br />
| [[#GPUREG_026C|GPUREG_026C]]<br />
| <br />
|<br />
|-<br />
| 026D<br />
| [[#GPUREG_026D|GPUREG_026D]]<br />
| <br />
|<br />
|-<br />
| 026E<br />
| [[#GPUREG_026E|GPUREG_026E]]<br />
| <br />
|<br />
|-<br />
| 026F<br />
| [[#GPUREG_026F|GPUREG_026F]]<br />
| <br />
|<br />
|-<br />
| 0270<br />
| [[#GPUREG_0270|GPUREG_0270]]<br />
| <br />
|<br />
|-<br />
| 0271<br />
| [[#GPUREG_0271|GPUREG_0271]]<br />
| <br />
|<br />
|-<br />
| 0272<br />
| [[#GPUREG_0272|GPUREG_0272]]<br />
| <br />
|<br />
|-<br />
| 0273<br />
| [[#GPUREG_0273|GPUREG_0273]]<br />
| <br />
|<br />
|-<br />
| 0274<br />
| [[#GPUREG_0274|GPUREG_0274]]<br />
| <br />
|<br />
|-<br />
| 0275<br />
| [[#GPUREG_0275|GPUREG_0275]]<br />
| <br />
|<br />
|-<br />
| 0276<br />
| [[#GPUREG_0276|GPUREG_0276]]<br />
| <br />
|<br />
|-<br />
| 0277<br />
| [[#GPUREG_0277|GPUREG_0277]]<br />
| <br />
|<br />
|-<br />
| 0278<br />
| [[#GPUREG_0278|GPUREG_0278]]<br />
| <br />
|<br />
|-<br />
| 0279<br />
| [[#GPUREG_0279|GPUREG_0279]]<br />
| <br />
|<br />
|-<br />
| 027A<br />
| [[#GPUREG_027A|GPUREG_027A]]<br />
| <br />
|<br />
|-<br />
| 027B<br />
| [[#GPUREG_027B|GPUREG_027B]]<br />
| <br />
|<br />
|-<br />
| 027C<br />
| [[#GPUREG_027C|GPUREG_027C]]<br />
| <br />
|<br />
|-<br />
| 027D<br />
| [[#GPUREG_027D|GPUREG_027D]]<br />
| <br />
|<br />
|-<br />
| 027E<br />
| [[#GPUREG_027E|GPUREG_027E]]<br />
| <br />
|<br />
|-<br />
| 027F<br />
| [[#GPUREG_027F|GPUREG_027F]]<br />
| <br />
|<br />
|}<br />
<br />
=== Shader registers (0x280-0x2DF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
! colspan=4 | Geometry shader<br />
|-<br />
| 0280<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_GS_BOOL<br />
|-<br />
| 0281<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_GS_INT0<br />
|-<br />
| 0282<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_GS_INT1<br />
|-<br />
| 0283<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_GS_INT2<br />
|-<br />
| 0284<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_GS_INT3<br />
|-<br />
| 0285<br />
| [[#GPUREG_0285|GPUREG_0285]]<br />
| <br />
|<br />
|-<br />
| 0286<br />
| [[#GPUREG_0286|GPUREG_0286]]<br />
| <br />
|<br />
|-<br />
| 0287<br />
| [[#GPUREG_0287|GPUREG_0287]]<br />
| <br />
|<br />
|-<br />
| 0288<br />
| [[#GPUREG_0288|GPUREG_0288]]<br />
| <br />
|<br />
|-<br />
| 0289<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_GS_ATTR_NUM<br />
|-<br />
| 028A<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_GS_START_ADDR<br />
|-<br />
| 028B<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP0<br />
|-<br />
| 028C<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_GS_ATTR_IN_REG_MAP1<br />
|-<br />
| 028D<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_GS_OUT_REG_MASK<br />
|-<br />
| 028E<br />
| [[#GPUREG_028E|GPUREG_028E]]<br />
| <br />
|<br />
|-<br />
| 028F<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_GS_PROG_RENEWAL_END<br />
|-<br />
| 0290<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_GS_FLOAT_ADDR<br />
|-<br />
| 0291<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA0<br />
|-<br />
| 0292<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA1<br />
|-<br />
| 0293<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA2<br />
|-<br />
| 0294<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA3<br />
|-<br />
| 0295<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA4<br />
|-<br />
| 0296<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA5<br />
|-<br />
| 0297<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA6<br />
|-<br />
| 0298<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_GS_FLOAT_DATA7<br />
|-<br />
| 0299<br />
| [[#GPUREG_0299|GPUREG_0299]]<br />
| <br />
|<br />
|-<br />
| 029A<br />
| [[#GPUREG_029A|GPUREG_029A]]<br />
| <br />
|<br />
|-<br />
| 029B<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_GS_PROG_ADDR<br />
|-<br />
| 029C<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_DATA0<br />
|-<br />
| 029D<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_DATA1<br />
|-<br />
| 029E<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_DATA2<br />
|-<br />
| 029F<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_DATA3<br />
|-<br />
| 02A0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_DATA4<br />
|-<br />
| 02A1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_DATA5<br />
|-<br />
| 02A2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_DATA6<br />
|-<br />
| 02A3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_DATA7<br />
|-<br />
| 02A4<br />
| [[#GPUREG_02A4|GPUREG_02A4]]<br />
| <br />
|<br />
|-<br />
| 02A5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02A6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02A7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02A8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02A9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02AA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02AB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02AC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02AD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_GS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02AE<br />
| [[#GPUREG_02AE|GPUREG_02AE]]<br />
| <br />
|<br />
|-<br />
| 02AF<br />
| [[#GPUREG_02AF|GPUREG_02AF]]<br />
| <br />
|<br />
|-<br />
! colspan=4 | Vertex shader<br />
|-<br />
| 02B0<br />
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]<br />
| <br />
|PICA_REG_VS_BOOL<br />
|-<br />
| 02B1<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]<br />
| <br />
|PICA_REG_VS_INT0<br />
|-<br />
| 02B2<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]<br />
| <br />
|PICA_REG_VS_INT1<br />
|-<br />
| 02B3<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]<br />
| <br />
|PICA_REG_VS_INT2<br />
|-<br />
| 02B4<br />
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]<br />
| <br />
|PICA_REG_VS_INT3<br />
|-<br />
| 02B5<br />
| [[#GPUREG_02B5|GPUREG_02B5]]<br />
| <br />
|<br />
|-<br />
| 02B6<br />
| [[#GPUREG_02B6|GPUREG_02B6]]<br />
| <br />
|<br />
|-<br />
| 02B7<br />
| [[#GPUREG_02B7|GPUREG_02B7]]<br />
| <br />
|<br />
|-<br />
| 02B8<br />
| [[#GPUREG_02B8|GPUREG_02B8]]<br />
| <br />
|<br />
|-<br />
| 02B9<br />
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]<br />
| <br />
|PICA_REG_VS_ATTR_NUM0<br />
|-<br />
| 02BA<br />
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]<br />
| <br />
|PICA_REG_VS_START_ADDR<br />
|-<br />
| 02BB<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP0<br />
|-<br />
| 02BC<br />
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]<br />
| <br />
|PICA_REG_VS_ATTR_IN_REG_MAP1<br />
|-<br />
| 02BD<br />
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]<br />
| <br />
|PICA_REG_VS_OUT_REG_MASK<br />
|-<br />
| 02BE<br />
| [[#GPUREG_02BE|GPUREG_02BE]]<br />
| <br />
|<br />
|-<br />
| 02BF<br />
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]<br />
| <br />
|PICA_REG_VS_PROG_RENEWAL_END<br />
|-<br />
| 02C0<br />
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]<br />
| <br />
|PICA_REG_VS_FLOAT_ADDR<br />
|-<br />
| 02C1<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA0<br />
|-<br />
| 02C2<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA1<br />
|-<br />
| 02C3<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA2<br />
|-<br />
| 02C4<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA3<br />
|-<br />
| 02C5<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA4<br />
|-<br />
| 02C6<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA5<br />
|-<br />
| 02C7<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA6<br />
|-<br />
| 02C8<br />
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]<br />
| <br />
|PICA_REG_VS_FLOAT_DATA7<br />
|-<br />
| 02C9<br />
| [[#GPUREG_02C9|GPUREG_02C9]]<br />
| <br />
|<br />
|-<br />
| 02CA<br />
| [[#GPUREG_02CA|GPUREG_02CA]]<br />
| <br />
|<br />
|-<br />
| 02CB<br />
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_ADDR<br />
|-<br />
| 02CC<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_DATA0<br />
|-<br />
| 02CD<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_DATA1<br />
|-<br />
| 02CE<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_DATA2<br />
|-<br />
| 02CF<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_DATA3<br />
|-<br />
| 02D0<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_DATA4<br />
|-<br />
| 02D1<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_DATA5<br />
|-<br />
| 02D2<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_DATA6<br />
|-<br />
| 02D3<br />
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_DATA7<br />
|-<br />
| 02D4<br />
| [[#GPUREG_02D4|GPUREG_02D4]]<br />
| <br />
|<br />
|-<br />
| 02D5<br />
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]<br />
| ?<br />
|PICA_REG_VS_PROG_SWIZZLE_ADDR<br />
|-<br />
| 02D6<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA0<br />
|-<br />
| 02D7<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA1<br />
|-<br />
| 02D8<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA2<br />
|-<br />
| 02D9<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA3<br />
|-<br />
| 02DA<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA4<br />
|-<br />
| 02DB<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA5<br />
|-<br />
| 02DC<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA6<br />
|-<br />
| 02DD<br />
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]<br />
| <br />
|PICA_REG_VS_PROG_SWIZZLE_DATA7<br />
|-<br />
| 02DE<br />
| [[#GPUREG_02DE|GPUREG_02DE]]<br />
| <br />
|<br />
|-<br />
| 02DF<br />
| [[#GPUREG_02DF|GPUREG_02DF]]<br />
| <br />
|<br />
|}<br />
<br />
=== Unknown registers (0x2E0-0x2FF) ===<br />
<br />
{| class="wikitable" border="1"<br />
! Register ID<br />
! Register name<br />
! Notes<br />
! Official Name<br />
|-<br />
| 02E0<br />
| [[#GPUREG_02E0|GPUREG_02E0]]<br />
| <br />
|<br />
|-<br />
| 02E1<br />
| [[#GPUREG_02E1|GPUREG_02E1]]<br />
| <br />
|<br />
|-<br />
| 02E2<br />
| [[#GPUREG_02E2|GPUREG_02E2]]<br />
| <br />
|<br />
|-<br />
| 02E3<br />
| [[#GPUREG_02E3|GPUREG_02E3]]<br />
| <br />
|<br />
|-<br />
| 02E4<br />
| [[#GPUREG_02E4|GPUREG_02E4]]<br />
| <br />
|<br />
|-<br />
| 02E5<br />
| [[#GPUREG_02E5|GPUREG_02E5]]<br />
| <br />
|<br />
|-<br />
| 02E6<br />
| [[#GPUREG_02E6|GPUREG_02E6]]<br />
| <br />
|<br />
|-<br />
| 02E7<br />
| [[#GPUREG_02E7|GPUREG_02E7]]<br />
| <br />
|<br />
|-<br />
| 02E8<br />
| [[#GPUREG_02E8|GPUREG_02E8]]<br />
| <br />
|<br />
|-<br />
| 02E9<br />
| [[#GPUREG_02E9|GPUREG_02E9]]<br />
| <br />
|<br />
|-<br />
| 02EA<br />
| [[#GPUREG_02EA|GPUREG_02EA]]<br />
| <br />
|<br />
|-<br />
| 02EB<br />
| [[#GPUREG_02EB|GPUREG_02EB]]<br />
| <br />
|<br />
|-<br />
| 02EC<br />
| [[#GPUREG_02EC|GPUREG_02EC]]<br />
| <br />
|<br />
|-<br />
| 02ED<br />
| [[#GPUREG_02ED|GPUREG_02ED]]<br />
| <br />
|<br />
|-<br />
| 02EE<br />
| [[#GPUREG_02EE|GPUREG_02EE]]<br />
| <br />
|<br />
|-<br />
| 02EF<br />
| [[#GPUREG_02EF|GPUREG_02EF]]<br />
| <br />
|<br />
|-<br />
| 02F0<br />
| [[#GPUREG_02F0|GPUREG_02F0]]<br />
| <br />
|<br />
|-<br />
| 02F1<br />
| [[#GPUREG_02F1|GPUREG_02F1]]<br />
| <br />
|<br />
|-<br />
| 02F2<br />
| [[#GPUREG_02F2|GPUREG_02F2]]<br />
| <br />
|<br />
|-<br />
| 02F3<br />
| [[#GPUREG_02F3|GPUREG_02F3]]<br />
| <br />
|<br />
|-<br />
| 02F4<br />
| [[#GPUREG_02F4|GPUREG_02F4]]<br />
| <br />
|<br />
|-<br />
| 02F5<br />
| [[#GPUREG_02F5|GPUREG_02F5]]<br />
| <br />
|<br />
|-<br />
| 02F6<br />
| [[#GPUREG_02F6|GPUREG_02F6]]<br />
| <br />
|<br />
|-<br />
| 02F7<br />
| [[#GPUREG_02F7|GPUREG_02F7]]<br />
| <br />
|<br />
|-<br />
| 02F8<br />
| [[#GPUREG_02F8|GPUREG_02F8]]<br />
| <br />
|<br />
|-<br />
| 02F9<br />
| [[#GPUREG_02F9|GPUREG_02F9]]<br />
| <br />
|<br />
|-<br />
| 02FA<br />
| [[#GPUREG_02FA|GPUREG_02FA]]<br />
| <br />
|<br />
|-<br />
| 02FB<br />
| [[#GPUREG_02FB|GPUREG_02FB]]<br />
| <br />
|<br />
|-<br />
| 02FC<br />
| [[#GPUREG_02FC|GPUREG_02FC]]<br />
| <br />
|<br />
|-<br />
| 02FD<br />
| [[#GPUREG_02FD|GPUREG_02FD]]<br />
| <br />
|<br />
|-<br />
| 02FE<br />
| [[#GPUREG_02FE|GPUREG_02FE]]<br />
| <br />
|<br />
|-<br />
| 02FF<br />
| [[#GPUREG_02FF|GPUREG_02FF]]<br />
| <br />
|<br />
|}<br />
<br />
== Miscellaneous registers ==<br />
<br />
=== GPUREG_FINALIZE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)<br />
|}<br />
<br />
Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.<br />
Failure to write to this register in any command buffer will result in the GPU hanging.<br />
<br />
== Rasterizer registers ==<br />
<br />
=== GPUREG_FACECULLING_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Culling mode<br />
|}<br />
<br />
This register is used to configure the face culling mode.<br />
<br />
Culling mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Front Face (Counter Clockwise)<br />
|-<br />
| 2<br />
| Back Face (Counter Clockwise)<br />
|}<br />
<br />
=== GPUREG_VIEWPORT_WIDTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, width / 2<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.<br />
<br />
=== GPUREG_VIEWPORT_INVW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / width<br />
|}<br />
<br />
This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.<br />
<br />
=== GPUREG_VIEWPORT_HEIGHT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, height / 2<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.<br />
<br />
=== GPUREG_VIEWPORT_INVH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-31<br />
| float1.7.23, 2 / height<br />
|}<br />
<br />
This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.<br />
<br />
=== GPUREG_FRAGOP_CLIP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable clipping planes.<br />
<br />
=== GPUREG_FRAGOP_CLIP_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Clipping plane coefficient ''i''<br />
|}<br />
<br />
This register is used to configure clipping plane coefficients.<br />
<br />
=== GPUREG_DEPTHMAP_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near - Far<br />
|}<br />
<br />
This register is used to configure the depth range scale.<br />
<br />
=== GPUREG_DEPTHMAP_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| float1.7.16, Near + Polygon Offset<br />
|}<br />
<br />
This register is used to configure the depth range bias.<br />
<br />
=== GPUREG_SH_OUTMAP_TOTAL ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of following attributes<br />
|}<br />
<br />
This register is used to configure the total shader output map attributes.<br />
<br />
=== GPUREG_SH_OUTMAP_O''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Semantic for the x component of the register.<br />
|-<br />
| 8-12<br />
| unsigned, Semantic for the y component of the register.<br />
|-<br />
| 16-20<br />
| unsigned, Semantic for the z component of the register.<br />
|-<br />
| 24-28<br />
| unsigned, Semantic for the w component of the register.<br />
|}<br />
<br />
These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.<br />
<br />
Semantic values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Semantic<br />
! Description<br />
|-<br />
| 0x00<br />
| position.x<br />
| rowspan="4" | Vertex Position<br />
|-<br />
| 0x01<br />
| position.y<br />
|-<br />
| 0x02<br />
| position.z<br />
|-<br />
| 0x03<br />
| position.w<br />
|-<br />
| 0x04<br />
| normquat.x<br />
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)<br />
|-<br />
| 0x05<br />
| normquat.y<br />
|-<br />
| 0x06<br />
| normquat.z<br />
|-<br />
| 0x07<br />
| normquat.w<br />
|-<br />
| 0x08<br />
| color.r<br />
| rowspan="4" | Vertex color<br />
|-<br />
| 0x09<br />
| color.g<br />
|-<br />
| 0x0A<br />
| color.b<br />
|-<br />
| 0x0B<br />
| color.a<br />
|-<br />
| 0x0C<br />
| texcoord0.u<br />
| rowspan="2" | Texture coordinates for texture 0<br />
|-<br />
| 0x0D<br />
| texcoord0.v<br />
|-<br />
| 0x0E<br />
| texcoord1.u<br />
| rowspan="2" | Texture coordinates for texture 1<br />
|-<br />
| 0x0F<br />
| texcoord1.v<br />
|-<br />
| 0x10<br />
| texcoord0.w<br />
|<br />
<br />
|-<br />
| 0x12<br />
| view.x<br />
| rowspan="3" | View vector (for fragment lighting)<br />
|-<br />
| 0x13<br />
| view.y<br />
|-<br />
| 0x14<br />
| view.z<br />
<br />
|-<br />
| 0x16<br />
| texcoord2.u<br />
| rowspan="2" | Texture coordinates for texture 2<br />
|-<br />
| 0x17<br />
| texcoord2.v<br />
<br />
|-<br />
| 0x1F<br />
| Unused component<br />
| Should be set for unused components of the output register<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Early depth function<br />
|}<br />
<br />
This register configures the early depth test function.<br />
<br />
Early depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| >=<br />
|-<br />
| 1<br />
| ><br />
|-<br />
| 2<br />
| <=<br />
|-<br />
| 3<br />
| <<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether the early depth test is enabled.<br />
<br />
=== GPUREG_EARLYDEPTH_CLEAR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = clear)<br />
|}<br />
<br />
This register triggers clearing the early depth data.<br />
<br />
=== GPUREG_SH_OUTATTR_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Use texture coordinates (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register is used to configure the shader output attribute mode.<br />
<br />
=== GPUREG_SCISSORTEST_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Enabled (0 = disabled, 3 = enabled)<br />
|}<br />
<br />
This register is used to enable scissor testing.<br />
<br />
=== GPUREG_SCISSORTEST_POS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X1<br />
|-<br />
| 16-25<br />
| unsigned, Y1<br />
|}<br />
<br />
This register is used to configure the scissor test start position.<br />
<br />
=== GPUREG_SCISSORTEST_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| unsigned, X2<br />
|-<br />
| 16-25<br />
| unsigned, Y2<br />
|}<br />
<br />
This register is used to configure the scissor test end position.<br />
<br />
=== GPUREG_VIEWPORT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-9<br />
| signed, X<br />
|-<br />
| 16-25<br />
| signed, Y<br />
|}<br />
<br />
This register is used to configure the viewport position.<br />
<br />
=== GPUREG_EARLYDEPTH_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| unsigned, Clear value<br />
|}<br />
<br />
This register is used to configure the early depth clear value.<br />
<br />
=== GPUREG_DEPTHMAP_ENABLE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable depth range.<br />
<br />
=== GPUREG_RENDERBUF_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register is used to configure the output framebuffer dimensions.<br />
<br />
=== GPUREG_SH_OUTATTR_CLOCK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, 'position.z' present (0 = absent, 1 = present)<br />
|-<br />
| 1<br />
| unsigned, 'color' component present (0 = absent, 1 = present)<br />
|-<br />
| 8<br />
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)<br />
|-<br />
| 9<br />
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)<br />
|-<br />
| 10<br />
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)<br />
|-<br />
| 16<br />
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)<br />
|-<br />
| 24<br />
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)<br />
|}<br />
<br />
This register controls the clock supply to parts relating to certain attributes.<br />
<br />
== Texturing registers ==<br />
<br />
=== GPUREG_TEXUNIT_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| 0x0<br />
|-<br />
| 8-9<br />
| unsigned, Texture 3 coordinates<br />
|-<br />
| 10<br />
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| 0x1<br />
|-<br />
| 13<br />
| unsigned, Texture 2 coordinates<br />
|-<br />
| 16<br />
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)<br />
|-<br />
| 17-31<br />
| 0x0<br />
|}<br />
<br />
This register is used to enable texture units.<br />
<br />
Texture 3 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 0<br />
|-<br />
| 1<br />
| Texture 1<br />
|-<br />
| 2<br />
| Texture 2<br />
|}<br />
<br />
Texture 2 coordinates values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Texture 2<br />
|-<br />
| 1<br />
| Texture 1<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to set a texture unit's border color.<br />
<br />
=== GPUREG_TEXUNIT''i''_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Height<br />
|-<br />
| 16-26<br />
| unsigned, Width<br />
|}<br />
<br />
This register is used to set a texture unit's dimensions.<br />
<br />
=== GPUREG_TEXUNIT''i''_PARAM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, Magnification filter<br />
|-<br />
| 2<br />
| unsigned, Minification filter<br />
|-<br />
| 4-5<br />
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4<br />
|-<br />
| 8-10<br />
| unsigned, Wrap T<br />
|-<br />
| 12-14<br />
| unsigned, Wrap S<br />
|-<br />
| 16-17<br />
| 0x0<br />
|-<br />
| 20<br />
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)<br />
|-<br />
| 24<br />
| unsigned, Mipmap filter<br />
|-<br />
| 28-30<br />
| unsigned, Type (Texture 0 only)<br />
|}<br />
<br />
This register is used to set a texture unit's extra parameters.<br />
<br />
Filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|}<br />
<br />
Wrap values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to edge<br />
|-<br />
| 1<br />
| Clamp to border<br />
|-<br />
| 2<br />
| Repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|}<br />
<br />
Type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 2D<br />
|-<br />
| 1<br />
| Cube map<br />
|-<br />
| 2<br />
| Shadow 2D<br />
|-<br />
| 3<br />
| Projection<br />
|-<br />
| 4<br />
| Shadow cube<br />
|-<br />
| 5<br />
| Disabled<br />
|}<br />
<br />
=== GPUREG_TEXUNIT''i''_LOD ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.4.8, Bias<br />
|-<br />
| 16-19<br />
| unsigned, Max Level<br />
|-<br />
| 24-27<br />
| unsigned, Min Level<br />
|}<br />
<br />
This register is used to configure a texture unit's level of detail.<br />
<br />
=== GPUREG_TEXUNIT''i''_ADDR''i'' ===<br />
<br />
First ADDR register:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Texture physical address >> 3<br />
|}<br />
<br />
Subsequent ADDR registers:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-21<br />
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)<br />
|}<br />
<br />
This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.<br />
<br />
If the texture is a cube:<br />
<br />
{| class="wikitable" border="1"<br />
! Register<br />
! Description<br />
|-<br />
| ADDR1<br />
| Positive X<br />
|-<br />
| ADDR2<br />
| Negative X<br />
|-<br />
| ADDR3<br />
| Positive Y<br />
|-<br />
| ADDR4<br />
| Negative Y<br />
|-<br />
| ADDR5<br />
| Positive Z<br />
|-<br />
| ADDR6<br />
| Negative Z<br />
|}<br />
<br />
Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.<br />
<br />
=== GPUREG_TEXUNIT''i''_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Perspective (0 = perspective, 1 = not perspective)<br />
|-<br />
| 1-23<br />
| fixed0.0.24, Z bias (upper 23 bits)<br />
|}<br />
<br />
This register is used to set a texture unit's shadow texture properties.<br />
<br />
=== GPUREG_TEXUNIT''i''_TYPE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Format<br />
|}<br />
<br />
This register is used to set a texture unit's data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! GL Format<br />
! GL Data Type<br />
|-<br />
| 0x0<br />
| RGBA8888<br />
| GL_RGBA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x1<br />
| RGB888<br />
| GL_RGB<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x2<br />
| RGBA5551<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_5_5_5_1<br />
|-<br />
| 0x3<br />
| RGB565<br />
| GL_RGB<br />
| GL_UNSIGNED_SHORT_5_6_5<br />
|-<br />
| 0x4<br />
| RGBA4444<br />
| GL_RGBA<br />
| GL_UNSIGNED_SHORT_4_4_4_4<br />
|-<br />
| 0x5<br />
| IA8<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x6<br />
| HILO8<br />
| <br />
| <br />
|-<br />
| 0x7<br />
| I8<br />
| GL_LUMINANCE<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x8<br />
| A8<br />
| GL_ALPHA<br />
| GL_UNSIGNED_BYTE<br />
|-<br />
| 0x9<br />
| IA44<br />
| GL_LUMINANCE_ALPHA<br />
| GL_UNSIGNED_BYTE_4_4_EXT<br />
|-<br />
| 0xA<br />
| I4<br />
| <br />
|<br />
|-<br />
| 0xB<br />
| A4<br />
| GL_ALPHA<br />
| GL_UNSIGNED_NIBBLE_EXT<br />
|-<br />
| 0xC<br />
| ETC1<br />
| GL_ETC1_RGB8_OES<br />
| <br />
|-<br />
| 0xD<br />
| ETC1A4<br />
|<br />
| <br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to enable lighting.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, U-direction clamp<br />
|-<br />
| 3-5<br />
| unsigned, V-direction clamp<br />
|-<br />
| 6-9<br />
| unsigned, RGB mapping function<br />
|-<br />
| 10-13<br />
| unsigned, Alpha mapping function<br />
|-<br />
| 14<br />
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)<br />
|-<br />
| 15<br />
| unsigned, Noise enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 16-17<br />
| unsigned, U-direction shift<br />
|-<br />
| 18-19<br />
| unsigned, V-direction shift<br />
|-<br />
| 20-27<br />
| float1.5.10, Texture bias (lower 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Clamp values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clamp to zero<br />
|-<br />
| 1<br />
| Clamp to edge<br />
|-<br />
| 2<br />
| Symmetrical repeat<br />
|-<br />
| 3<br />
| Mirrored repeat<br />
|-<br />
| 4<br />
| Pulse<br />
|}<br />
<br />
Mapping function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| U<br />
|-<br />
| 1<br />
| U²<br />
|-<br />
| 2<br />
| V<br />
|-<br />
| 3<br />
| V²<br />
|-<br />
| 4<br />
| (U + V) / 2<br />
|-<br />
| 5<br />
| (U² + V²) / 2<br />
|-<br />
| 6<br />
| sqrt(U² + V²)<br />
|-<br />
| 7<br />
| Minimum<br />
|-<br />
| 8<br />
| Maximum<br />
|-<br />
| 9<br />
| Rmax<br />
|}<br />
<br />
Shift values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Odd<br />
|-<br />
| 2<br />
| Even<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, U-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, U-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| fixed1.3.12, V-direction noise amplitude<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise phase<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX3 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, U-direction noise frequency<br />
|-<br />
| 16-31<br />
| float1.5.10, V-direction noise frequency<br />
|}<br />
<br />
This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX4 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Minification filter<br />
|-<br />
| 3-10<br />
| 0x60<br />
|-<br />
| 11-18<br />
| unsigned, Texture width<br />
|-<br />
| 19-26<br />
| float1.5.10, Texture bias (upper 8 bits)<br />
|}<br />
<br />
This register is used to configure the procedural texture unit.<br />
<br />
Minification filter values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Nearest<br />
|-<br />
| 1<br />
| Linear<br />
|-<br />
| 2<br />
| Nearest, Mipmap Nearest<br />
|-<br />
| 3<br />
| Linear, Mipmap Nearest<br />
|-<br />
| 4<br />
| Nearest, Mipmap Linear<br />
|-<br />
| 5<br />
| Linear, Mipmap Linear<br />
|}<br />
<br />
=== GPUREG_TEXUNIT3_PROCTEX5 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Texture offset<br />
|-<br />
| 8-31<br />
| 0xE0C080<br />
|}<br />
<br />
This register is used to set the procedural texture unit's offset.<br />
<br />
=== GPUREG_PROCTEX_LUT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Index<br />
|-<br />
| 8-11<br />
| unsigned, Reference table<br />
|}<br />
<br />
This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.<br />
<br />
Reference table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Noise table<br />
|-<br />
| 2<br />
| RGB mapping function table<br />
|-<br />
| 3<br />
| Alpha mapping function table<br />
|-<br />
| 4<br />
| Color table<br />
|-<br />
| 5<br />
| Color difference table<br />
|}<br />
<br />
=== GPUREG_PROCTEX_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.<br />
<br />
==== Noise Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== RGB Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Alpha Mapping Function Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Difference from next element<br />
|}<br />
<br />
==== Color Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
==== Color Difference Table ====<br />
<br />
256 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| fixed1.0.7, Red difference between current and next color table elements<br />
|-<br />
| 8-15<br />
| fixed1.0.7, Green difference between current and next color table elements<br />
|-<br />
| 16-23<br />
| fixed1.0.7, Blue difference between current and next color table elements<br />
|-<br />
| 24-31<br />
| fixed1.0.7, Alpha difference between current and next color table elements<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_SOURCE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB source 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB source 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB source 2<br />
|-<br />
| 16-19<br />
| unsigned, Alpha source 0<br />
|-<br />
| 20-23<br />
| unsigned, Alpha source 1<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source 2<br />
|}<br />
<br />
This register configures a texture combiner's sources.<br />
<br />
Source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Primary color<br />
|-<br />
| 1<br />
| Fragment primary color<br />
|-<br />
| 2<br />
| Fragment secondary color<br />
|-<br />
| 3<br />
| Texture 0<br />
|-<br />
| 4<br />
| Texture 1<br />
|-<br />
| 5<br />
| Texture 2<br />
|-<br />
| 6<br />
| Texture 3<br />
|-<br />
| 13<br />
| Previous buffer<br />
|-<br />
| 14<br />
| Constant (from GPUREG_TEXENV''i''_COLOR)<br />
|-<br />
| 15<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_OPERAND ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB operand 0<br />
|-<br />
| 4-7<br />
| unsigned, RGB operand 1<br />
|-<br />
| 8-11<br />
| unsigned, RGB operand 2<br />
|-<br />
| 12-14<br />
| unsigned, Alpha operand 0<br />
|-<br />
| 16-18<br />
| unsigned, Alpha operand 1<br />
|-<br />
| 20-22<br />
| unsigned, Alpha operand 2<br />
|}<br />
<br />
This register configures a texture combiner's operands.<br />
<br />
RGB operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source color<br />
|-<br />
| 1<br />
| One minus source color<br />
|-<br />
| 2<br />
| Source alpha<br />
|-<br />
| 3<br />
| One minus source alpha<br />
|-<br />
| 4<br />
| Source red<br />
|-<br />
| 5<br />
| One minus source red<br />
|-<br />
| 8<br />
| Source green<br />
|-<br />
| 9<br />
| One minus source green<br />
|-<br />
| 12<br />
| Source blue<br />
|-<br />
| 13<br />
| One minus source blue<br />
|}<br />
<br />
Alpha operand values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Source alpha<br />
|-<br />
| 1<br />
| One minus source alpha<br />
|-<br />
| 2<br />
| Source red<br />
|-<br />
| 3<br />
| One minus source red<br />
|-<br />
| 4<br />
| Source green<br />
|-<br />
| 5<br />
| One minus source green<br />
|-<br />
| 6<br />
| Source blue<br />
|-<br />
| 7<br />
| One minus source blue<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COMBINER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, RGB combine<br />
|-<br />
| 16-19<br />
| unsigned, Alpha combine<br />
|}<br />
<br />
This register configures a texture combiner's combine mode.<br />
<br />
Combine values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Replace<br />
|-<br />
| 1<br />
| Modulate<br />
|-<br />
| 2<br />
| Add<br />
|-<br />
| 3<br />
| Add signed<br />
|-<br />
| 4<br />
| Interpolate<br />
|-<br />
| 5<br />
| Subtract<br />
|-<br />
| 6<br />
| Dot3 RGB<br />
|-<br />
| 7<br />
| Dot3 RGBA<br />
|-<br />
| 8<br />
| Multiply then add<br />
|-<br />
| 9<br />
| Add then multiply<br />
|}<br />
<br />
=== GPUREG_TEXENV''i''_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register configures a texture combiner's constant color.<br />
<br />
=== GPUREG_TEXENV''i''_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, RGB scale<br />
|-<br />
| 16-17<br />
| unsigned, Alpha scale<br />
|}<br />
<br />
This register configures a texture combiner's scale value.<br />
<br />
Scale values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|}<br />
<br />
=== GPUREG_TEXENV_UPDATE_BUFFER ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fog mode<br />
|-<br />
| 3<br />
| unsigned, Shading density source<br />
|-<br />
| 8<br />
| unsigned, TexEnv 1 RGB buffer input<br />
|-<br />
| 9<br />
| unsigned, TexEnv 2 RGB buffer input<br />
|-<br />
| 10<br />
| unsigned, TexEnv 3 RGB buffer input<br />
|-<br />
| 11<br />
| unsigned, TexEnv 4 RGB buffer input<br />
|-<br />
| 12<br />
| unsigned, TexEnv 1 alpha buffer input<br />
|-<br />
| 13<br />
| unsigned, TexEnv 2 alpha buffer input<br />
|-<br />
| 14<br />
| unsigned, TexEnv 3 alpha buffer input<br />
|-<br />
| 15<br />
| unsigned, TexEnv 4 alpha buffer input<br />
|-<br />
| 16<br />
| unsigned, Z flip (0 = don't flip, 1 = flip)<br />
|-<br />
| 24-25<br />
| 0x0<br />
|}<br />
<br />
This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.<br />
<br />
Fog mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Disabled<br />
|-<br />
| 5<br />
| Fog<br />
|-<br />
| 7<br />
| Gas<br />
|}<br />
<br />
Shading density source values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Plain density<br />
|-<br />
| 1<br />
| Depth density<br />
|}<br />
<br />
Buffer input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Previous buffer<br />
|-<br />
| 1<br />
| Previous<br />
|}<br />
<br />
=== GPUREG_FOG_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
This register is used to configure the color of fog.<br />
<br />
=== GPUREG_GAS_ATTENUATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas density attenuation<br />
|}<br />
<br />
This register is used to configure the gas density attenuation.<br />
<br />
=== GPUREG_GAS_ACCMAX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Gas maximum density accumulation<br />
|}<br />
<br />
This register is used to configure the gas maximum density accumulation.<br />
<br />
=== GPUREG_FOG_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.<br />
<br />
=== GPUREG_FOG_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.<br />
<br />
==== Fog Look-Up Table ====<br />
<br />
128 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Difference from next element <br />
|-<br />
| 13-23<br />
| fixed0.0.11, Value<br />
|}<br />
<br />
=== GPUREG_TEXENV_BUFFER_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the texture combiner buffer color.<br />
<br />
== Framebuffer registers ==<br />
<br />
=== GPUREG_COLOR_OPERATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Fragment operation mode<br />
|-<br />
| 8<br />
| unsigned, Blend mode<br />
|-<br />
| 16-25<br />
| 0x0E4<br />
|}<br />
<br />
This register is used to configure the fragment operation mode and whether to use logic ops or blending.<br />
<br />
Fragment operation mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Default<br />
|-<br />
| 1<br />
| Gas<br />
|-<br />
| 3<br />
| Shadow<br />
|}<br />
<br />
Blend mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Logic op<br />
|-<br />
| 1<br />
| Blend<br />
|}<br />
<br />
=== GPUREG_BLEND_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, RGB equation<br />
|-<br />
| 8-10<br />
| unsigned, Alpha equation<br />
|-<br />
| 16-19<br />
| unsigned, RGB source function<br />
|-<br />
| 20-23<br />
| unsigned, RGB destination function<br />
|-<br />
| 24-27<br />
| unsigned, Alpha source function<br />
|-<br />
| 28-31<br />
| unsigned, Alpha destination function<br />
|}<br />
<br />
This register is used to configure the blending function.<br />
<br />
Equation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Add<br />
|-<br />
| 1<br />
| Subtract<br />
|-<br />
| 2<br />
| Reverse subtract<br />
|-<br />
| 3<br />
| Minimum<br />
|-<br />
| 4<br />
| Maximum<br />
|}<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Zero<br />
|-<br />
| 1<br />
| One<br />
|-<br />
| 2<br />
| Source color<br />
|-<br />
| 3<br />
| One minus source color<br />
|-<br />
| 4<br />
| Destination color<br />
|-<br />
| 5<br />
| One minus destination color<br />
|-<br />
| 6<br />
| Source alpha<br />
|-<br />
| 7<br />
| One minus source alpha<br />
|-<br />
| 8<br />
| Destination alpha<br />
|-<br />
| 9<br />
| One minus destination alpha<br />
|-<br />
| 10<br />
| Constant color<br />
|-<br />
| 11<br />
| One minus constant color<br />
|-<br />
| 12<br />
| Constant alpha<br />
|-<br />
| 13<br />
| One minus constant alpha<br />
|-<br />
| 14<br />
| Source alpha saturate<br />
|}<br />
<br />
=== GPUREG_LOGIC_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Logic op<br />
|}<br />
<br />
This register is used to configure the logic op.<br />
<br />
Logic op values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Clear<br />
|-<br />
| 1<br />
| AND<br />
|-<br />
| 2<br />
| Reverse AND<br />
|-<br />
| 3<br />
| Copy<br />
|-<br />
| 4<br />
| Set<br />
|-<br />
| 5<br />
| Inverted copy<br />
|-<br />
| 6<br />
| Noop<br />
|-<br />
| 7<br />
| Invert<br />
|-<br />
| 8<br />
| NAND<br />
|-<br />
| 9<br />
| OR<br />
|-<br />
| 10<br />
| NOR<br />
|-<br />
| 11<br />
| XOR<br />
|-<br />
| 12<br />
| Equivalent<br />
|-<br />
| 13<br />
| Inverted AND<br />
|-<br />
| 14<br />
| Reverse OR<br />
|-<br />
| 15<br />
| Inverted OR<br />
|}<br />
<br />
=== GPUREG_BLEND_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|-<br />
| 24-31<br />
| unsigned, Alpha<br />
|}<br />
<br />
This register is used to configure the blending color.<br />
<br />
=== GPUREG_FRAGOP_ALPHA_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Reference value<br />
|}<br />
<br />
This register is used to configure alpha testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_TEST ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Function<br />
|-<br />
| 8-15<br />
| unsigned, Buffer mask<br />
|-<br />
| 16-23<br />
| signed, Reference value<br />
|-<br />
| 24-31<br />
| unsigned, Mask<br />
|}<br />
<br />
This register is used to configure stencil testing.<br />
<br />
Function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_STENCIL_OP ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Fail operation<br />
|-<br />
| 4-6<br />
| unsigned, Z-fail operation<br />
|-<br />
| 8-10<br />
| unsigned, Z-pass operation<br />
|}<br />
<br />
This register is used to configure stencil result operations.<br />
<br />
Operation values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Keep<br />
|-<br />
| 1<br />
| Zero<br />
|-<br />
| 2<br />
| Replace<br />
|-<br />
| 3<br />
| Increment<br />
|-<br />
| 4<br />
| Decrement<br />
|-<br />
| 5<br />
| Invert<br />
|-<br />
| 6<br />
| Increment and wrap<br />
|-<br />
| 7<br />
| Decrement and wrap<br />
|}<br />
<br />
=== GPUREG_DEPTH_COLOR_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4-6<br />
| unsigned, Depth function<br />
|-<br />
| 8<br />
| unsigned, Red write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 9<br />
| unsigned, Green write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 10<br />
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 11<br />
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 12<br />
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register is used to depth testing and framebuffer write masking.<br />
<br />
Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.<br />
<br />
Depth function values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Never<br />
|-<br />
| 1<br />
| Always<br />
|-<br />
| 2<br />
| Equal<br />
|-<br />
| 3<br />
| Not equal<br />
|-<br />
| 4<br />
| Less than<br />
|-<br />
| 5<br />
| Less than or equal<br />
|-<br />
| 6<br />
| Greater than<br />
|-<br />
| 7<br />
| Greater than or equal<br />
|}<br />
<br />
=== GPUREG_FRAMEBUFFER_INVALIDATE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = invalidate)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.<br />
<br />
=== GPUREG_FRAMEBUFFER_FLUSH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = flush)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.<br />
<br />
=== GPUREG_COLORBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow read (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures read access from the color buffer.<br />
<br />
=== GPUREG_COLORBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Allow write (0 = disable, 0xF = enable)<br />
|}<br />
<br />
This register configures write access to the color buffer.<br />
<br />
=== GPUREG_DEPTHBUFFER_READ ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil read (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth read (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures read access from the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_WRITE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Allow stencil write (0 = disable, 1 = enable)<br />
|-<br />
| 1<br />
| unsigned, Allow depth write (0 = disable, 1 = enable)<br />
|}<br />
<br />
This register configures write access to the depth and stencil buffers.<br />
<br />
=== GPUREG_DEPTHBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the depth buffer data format.<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit depth<br />
|-<br />
| 2<br />
| 24-bit depth<br />
|-<br />
| 3<br />
| 24-bit depth + 8-bit stencil<br />
|}<br />
<br />
=== GPUREG_COLORBUFFER_FORMAT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Pixel size<br />
|-<br />
| 16-18<br />
| unsigned, Format<br />
|}<br />
<br />
This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.<br />
<br />
Pixel size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 16-bit color<br />
|-<br />
| 2<br />
| 32-bit color<br />
|}<br />
<br />
Format values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| RGBA8/Gas<br />
|-<br />
| 2<br />
| RGB5A1<br />
|-<br />
| 3<br />
| RGB565<br />
|-<br />
| 4<br />
| RGBA4<br />
|}<br />
<br />
=== GPUREG_EARLYDEPTH_TEST2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register enables the early depth test.<br />
<br />
=== GPUREG_FRAMEBUFFER_BLOCK32 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Render block mode<br />
|}<br />
<br />
This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.<br />
<br />
Render block mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8x8 blocks<br />
|-<br />
| 1<br />
| 32x32 blocks<br />
|}<br />
<br />
=== GPUREG_DEPTHBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Depth buffer physical address >> 3<br />
|}<br />
<br />
This register configures the depth buffer physical address.<br />
<br />
=== GPUREG_COLORBUFFER_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Color buffer physical address >> 3<br />
|}<br />
<br />
This register configures the color buffer physical address.<br />
<br />
=== GPUREG_FRAMEBUFFER_DIM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-10<br />
| unsigned, Width<br />
|-<br />
| 12-21<br />
| unsigned, Height - 1<br />
|-<br />
| 24<br />
| 0x1<br />
|}<br />
<br />
This register configures the framebuffer dimensions.<br />
<br />
=== GPUREG_GAS_LIGHT_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Planar shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, Planar shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, Planar shading density attenuation<br />
|}<br />
<br />
This register configures gas light planar shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading minimum intensity<br />
|-<br />
| 8-15<br />
| unsigned, View shading maximum intensity<br />
|-<br />
| 16-23<br />
| unsigned, View shading density attenuation<br />
|}<br />
<br />
This register configures gas light view shading.<br />
<br />
=== GPUREG_GAS_LIGHT_Z_COLOR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, View shading effect in line-of-sight direction<br />
|-<br />
| 8<br />
| Gas color LUT input<br />
|}<br />
<br />
This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.<br />
<br />
Color LUT input values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Gas density<br />
|-<br />
| 1<br />
| Light factor<br />
|}<br />
<br />
=== GPUREG_GAS_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Index<br />
|}<br />
<br />
This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.<br />
<br />
=== GPUREG_GAS_LUT_DATA ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| LUT data<br />
|}<br />
<br />
These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.<br />
<br />
==== Gas Look-Up Table ====<br />
<br />
16 elements:<br />
<br />
First 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| signed, Red<br />
|-<br />
| 8-15<br />
| signed, Green<br />
|-<br />
| 16-23<br />
| signed, Blue<br />
|}<br />
<br />
Last 8 elements:<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Red<br />
|-<br />
| 8-15<br />
| unsigned, Green<br />
|-<br />
| 16-23<br />
| unsigned, Blue<br />
|}<br />
<br />
=== GPUREG_GAS_DELTAZ_DEPTH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| fixed0.16.8, Depth direction attenuation proportion<br />
|}<br />
<br />
This register is used to configure the gas depth direction attenuation proportion.<br />
<br />
=== GPUREG_FRAGOP_SHADOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Sum of penumbra scale and penumbra bias<br />
|-<br />
| 16-31<br />
| float1.5.10, Penumbra scale with reversed sign<br />
|}<br />
<br />
This register is used to configure shadow properties.<br />
<br />
== Fragment lighting registers ==<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.<br />
<br />
=== GPUREG_LIGHT''i''_SPECULAR1 ===<br />
<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.<br />
<br />
=== GPUREG_LIGHT''i''_DIFFUSE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.<br />
<br />
=== GPUREG_LIGHT''i''_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.<br />
<br />
=== GPUREG_LIGHT''i''_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, X coordinate<br />
|-<br />
| 16-31<br />
| float1.5.10, Y coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| float1.5.10, Z coordinate<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_XY ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, X coordinate (negated)<br />
|-<br />
| 16-28<br />
| fixed1.1.11, Y coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_SPOTDIR_Z ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-12<br />
| fixed1.1.11, Z coordinate (negated)<br />
|}<br />
<br />
These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.<br />
<br />
=== GPUREG_LIGHT''i''_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Light type (0 = positional light, 1 = directional light)<br />
|-<br />
| 1<br />
| unsigned, Two side diffuse (0 = one side, 1 = both sides)<br />
|-<br />
| 2<br />
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)<br />
|-<br />
| 3<br />
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures a light's properties.<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation bias<br />
|}<br />
<br />
These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-19<br />
| float1.7.12, Distance attenuation scale<br />
|}<br />
<br />
These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).<br />
<br />
=== GPUREG_LIGHTING_AMBIENT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Blue<br />
|-<br />
| 10-17<br />
| unsigned, Green<br />
|-<br />
| 20-27<br />
| unsigned, Red<br />
|}<br />
<br />
This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.<br />
<br />
=== GPUREG_LIGHTING_NUM_LIGHTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Number of active lights - 1<br />
|}<br />
<br />
This register configures the number of active lights.<br />
<br />
=== GPUREG_LIGHTING_CONFIG0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)<br />
|-<br />
| 2-3<br />
| unsigned, Fresnel selector<br />
|-<br />
| 4-7<br />
| unsigned, Light environment configuration<br />
|-<br />
| 8-11<br />
| 0x4<br />
|-<br />
| 16<br />
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 17<br />
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)<br />
|-<br />
| 18<br />
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)<br />
|-<br />
| 19<br />
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)<br />
|-<br />
| 22-23<br />
| unsigned, Bump map texture unit<br />
|-<br />
| 24-25<br />
| unsigned, Shadow map texture unit<br />
|-<br />
| 27<br />
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)<br />
|-<br />
| 28-29<br />
| unsigned, Bump mode<br />
|-<br />
| 30<br />
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)<br />
|-<br />
| 31<br />
| 0x1<br />
|}<br />
<br />
This register configures the light environment.<br />
<br />
Fresnel selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| None<br />
|-<br />
| 1<br />
| Primary alpha<br />
|-<br />
| 2<br />
| Secondary alpha<br />
|-<br />
| 3<br />
| Primary and secondary alpha<br />
|}<br />
<br />
The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.<br />
<br />
Light environment configuration values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
! Available LUTs<br />
|-<br />
| 0<br />
| Configuration 0<br />
| D0, RR, SP, DA<br />
|-<br />
| 1<br />
| Configuration 1<br />
| FR, RR, SP, DA<br />
|-<br />
| 2<br />
| Configuration 2<br />
| D0, D1, RR, DA<br />
|-<br />
| 3<br />
| Configuration 3<br />
| D0, D1, FR, DA<br />
|-<br />
| 4<br />
| Configuration 4<br />
| All except for FR<br />
|-<br />
| 5<br />
| Configuration 5<br />
| All except for D1<br />
|-<br />
| 6<br />
| Configuration 6<br />
| All except for RB and RG<br />
|-<br />
| 8<br />
| Configuration 7<br />
| All<br />
|}<br />
<br />
Bump mode values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Not used<br />
|-<br />
| 1<br />
| Use as bump map<br />
|-<br />
| 2<br />
| Use as tangent map<br />
|}<br />
<br />
=== GPUREG_LIGHTING_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 1<br />
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 2<br />
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 3<br />
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 4<br />
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 6<br />
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 7<br />
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 8<br />
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 10<br />
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 11<br />
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 12<br />
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 14<br />
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 15<br />
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 16<br />
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 18<br />
| 0x1<br />
|-<br />
| 19<br />
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 20-22<br />
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 21<br />
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 22<br />
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 7 = disabled)<br />
|-<br />
| 24<br />
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 26<br />
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 27<br />
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 28<br />
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 29<br />
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 30<br />
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|-<br />
| 31<br />
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is used to disable various aspects of the light environment.<br />
<br />
=== GPUREG_LIGHTING_LUT_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Starting index<br />
|-<br />
| 8-12<br />
| unsigned, Look-up table<br />
|}<br />
<br />
This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.<br />
<br />
Lookup table values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| D0<br />
|-<br />
| 1<br />
| D1<br />
|-<br />
| 3<br />
| FR<br />
|-<br />
| 4<br />
| RB<br />
|-<br />
| 5<br />
| RG<br />
|-<br />
| 6<br />
| RR<br />
|-<br />
| 8-15<br />
| SP0-7<br />
|-<br />
| 16-23<br />
| DA0-7<br />
|}<br />
<br />
=== GPUREG_LIGHTING_ENABLE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Disabled (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.<br />
<br />
=== GPUREG_LIGHTING_LUT_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-23<br />
| LUT data<br />
|}<br />
<br />
Lighting LUT data is written here.<br />
<br />
A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.<br />
<br />
DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.<br />
<br />
Format of an entry:<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| fixed0.0.12, Entry value<br />
|-<br />
| 12-23<br />
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_ABS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1<br />
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)<br />
|-<br />
| 5<br />
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)<br />
|-<br />
| 9<br />
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)<br />
|-<br />
| 13<br />
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)<br />
|-<br />
| 17<br />
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)<br />
|-<br />
| 21<br />
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)<br />
|-<br />
| 25<br />
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)<br />
|}<br />
<br />
This register controls whether the absolute value of the input is taken before using a LUT.<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SELECT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Input selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Input selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Input selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Input selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Input selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Input selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Input selector for RR<br />
|}<br />
<br />
This register selects the input from LUTs.<br />
<br />
Input selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| N·H<br />
|-<br />
| 1<br />
| V·H<br />
|-<br />
| 2<br />
| N·V<br />
|-<br />
| 3<br />
| L·N<br />
|-<br />
| 4<br />
| -L·P (aka Spotlight aka SP)<br />
|-<br />
| 5<br />
| cos φ (aka CP)<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LUTINPUT_SCALE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, Scaler selector for D0<br />
|-<br />
| 4-6<br />
| unsigned, Scaler selector for D1<br />
|-<br />
| 8-10<br />
| unsigned, Scaler selector for SP<br />
|-<br />
| 12-14<br />
| unsigned, Scaler selector for FR<br />
|-<br />
| 16-18<br />
| unsigned, Scaler selector for RB<br />
|-<br />
| 20-22<br />
| unsigned, Scaler selector for RG<br />
|-<br />
| 24-26<br />
| unsigned, Scaler selector for RR<br />
|}<br />
<br />
This register controls the scaling that is applied to the output of a LUT.<br />
<br />
Scaler selector values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 1x<br />
|-<br />
| 1<br />
| 2x<br />
|-<br />
| 2<br />
| 4x<br />
|-<br />
| 3<br />
| 8x<br />
|-<br />
| 6<br />
| 0.25x<br />
|-<br />
| 7<br />
| 0.5x<br />
|}<br />
<br />
=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-2<br />
| unsigned, ID of the 1st enabled light<br />
|-<br />
| 4-6<br />
| unsigned, ID of the 2nd enabled light<br />
|-<br />
| 8-10<br />
| unsigned, ID of the 3rd enabled light<br />
|-<br />
| 12-14<br />
| unsigned, ID of the 4th enabled light<br />
|-<br />
| 16-18<br />
| unsigned, ID of the 5th enabled light<br />
|-<br />
| 20-22<br />
| unsigned, ID of the 6th enabled light<br />
|-<br />
| 24-26<br />
| unsigned, ID of the 7th enabled light<br />
|-<br />
| 28-30<br />
| unsigned, ID of the 8th enabled light<br />
|}<br />
<br />
This register sets the IDs of enabled light sources.<br />
<br />
== Geometry pipeline registers ==<br />
<br />
=== GPUREG_ATTRIBBUFFERS_LOC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 1-28<br />
| unsigned, Vertex arrays base address<br />
|}<br />
<br />
This register sets the base address of all vertex arrays.<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 0 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 0 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 1 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 1 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 2 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 2 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 3 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 3 size<br />
|-<br />
| 16-17<br />
| unsigned, Vertex attribute 4 type<br />
|-<br />
| 18-19<br />
| unsigned, Vertex attribute 4 size<br />
|-<br />
| 20-21<br />
| unsigned, Vertex attribute 5 type<br />
|-<br />
| 22-23<br />
| unsigned, Vertex attribute 5 size<br />
|-<br />
| 24-25<br />
| unsigned, Vertex attribute 6 type<br />
|-<br />
| 26-27<br />
| unsigned, Vertex attribute 6 size<br />
|-<br />
| 28-29<br />
| unsigned, Vertex attribute 7 type<br />
|-<br />
| 30-31<br />
| unsigned, Vertex attribute 7 size<br />
|}<br />
<br />
This register configures the types and sizes of the first 8 vertex attributes.<br />
<br />
Vertex attribute type values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Byte<br />
|-<br />
| 1<br />
| Unsigned byte<br />
|-<br />
| 2<br />
| Short<br />
|-<br />
| 3<br />
| Float<br />
|}<br />
<br />
Vertex attribute size values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| 8 bits<br />
|-<br />
| 1<br />
| 16 bits<br />
|-<br />
| 2<br />
| 24 bits<br />
|-<br />
| 3<br />
| 32 bits<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Vertex attribute 8 type<br />
|-<br />
| 2-3<br />
| unsigned, Vertex attribute 8 size<br />
|-<br />
| 4-5<br />
| unsigned, Vertex attribute 9 type<br />
|-<br />
| 6-7<br />
| unsigned, Vertex attribute 9 size<br />
|-<br />
| 8-9<br />
| unsigned, Vertex attribute 10 type<br />
|-<br />
| 10-11<br />
| unsigned, Vertex attribute 10 size<br />
|-<br />
| 12-13<br />
| unsigned, Vertex attribute 11 type<br />
|-<br />
| 14-15<br />
| unsigned, Vertex attribute 11 size<br />
|-<br />
| 16-27<br />
| unsigned, Fixed vertex attribute mask<br />
|-<br />
| 28-31<br />
| unsigned, Total vertex attribute count - 1<br />
|}<br />
<br />
This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.<br />
<br />
See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|}<br />
<br />
This register configures the offset of a vertex array from the base vertex arrays address.<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 1<br />
|-<br />
| 4-7<br />
| unsigned, Component 2<br />
|-<br />
| 8-11<br />
| unsigned, Component 3<br />
|-<br />
| 12-15<br />
| unsigned, Component 4<br />
|-<br />
| 16-19<br />
| unsigned, Component 5<br />
|-<br />
| 20-23<br />
| unsigned, Component 6<br />
|-<br />
| 24-27<br />
| unsigned, Component 7<br />
|-<br />
| 28-31<br />
| unsigned, Component 8<br />
|}<br />
<br />
This register configures the first 8 component types of a vertex array.<br />
<br />
Component values:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Vertex attribute 0<br />
|-<br />
| 1<br />
| Vertex attribute 1<br />
|-<br />
| 2<br />
| Vertex attribute 2<br />
|-<br />
| 3<br />
| Vertex attribute 3<br />
|-<br />
| 4<br />
| Vertex attribute 4<br />
|-<br />
| 5<br />
| Vertex attribute 5<br />
|-<br />
| 6<br />
| Vertex attribute 6<br />
|-<br />
| 7<br />
| Vertex attribute 7<br />
|-<br />
| 8<br />
| Vertex attribute 8<br />
|-<br />
| 9<br />
| Vertex attribute 9<br />
|-<br />
| 10<br />
| Vertex attribute 10<br />
|-<br />
| 11<br />
| Vertex attribute 11<br />
|-<br />
| 12<br />
| 4-byte padding<br />
|-<br />
| 13<br />
| 8-byte padding<br />
|-<br />
| 14<br />
| 12-byte padding<br />
|-<br />
| 15<br />
| 16-byte padding<br />
|}<br />
<br />
=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Component 9<br />
|-<br />
| 4-7<br />
| unsigned, Component 10<br />
|-<br />
| 8-11<br />
| unsigned, Component 11<br />
|-<br />
| 12-15<br />
| unsigned, Component 12<br />
|-<br />
| 16-23<br />
| unsigned, Bytes per vertex<br />
|-<br />
| 28-31<br />
| unsigned, Total number of components<br />
|}<br />
<br />
This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.<br />
<br />
See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.<br />
<br />
=== GPUREG_INDEXBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-27<br />
| unsigned, Offset from base vertex arrays address<br />
|-<br />
| 31<br />
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)<br />
|}<br />
<br />
This register configures the index array used when drawing elements.<br />
<br />
=== GPUREG_NUMVERTICES ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Number of vertices to render<br />
|}<br />
<br />
This register sets the number of vertices to render.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|-<br />
| 9<br />
| 0x0<br />
|-<br />
| 31<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_VERTEX_OFFSET ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Starting vertex offset<br />
|}<br />
<br />
This register sets the offset of the first vertex in an array to render.<br />
<br />
=== GPUREG_POST_VERTEX_CACHE_NUM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)<br />
|}<br />
<br />
This register configures the post-vertex cache.<br />
<br />
=== GPUREG_DRAWARRAYS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw arrays)<br />
|}<br />
<br />
This register triggers drawing vertex arrays.<br />
<br />
=== GPUREG_DRAWELEMENTS ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = draw elements)<br />
|}<br />
<br />
This register triggers drawing vertex array elements.<br />
<br />
=== GPUREG_VTX_FUNC ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)<br />
|}<br />
<br />
This register triggers clearing the post-vertex cache.<br />
<br />
=== GPUREG_FIXEDATTRIB_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)<br />
|}<br />
<br />
This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.<br />
<br />
=== GPUREG_FIXEDATTRIB_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| colspan="2" | '''DATA0:'''<br />
|-<br />
| 0-7<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)<br />
|-<br />
| 8-31<br />
| float1.7.16, Vertex attribute element 4 (W)<br />
|-<br />
| colspan="2" | '''DATA1:'''<br />
|-<br />
| 0-15<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)<br />
|-<br />
| 16-31<br />
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)<br />
|-<br />
| colspan="2" | '''DATA2:'''<br />
|-<br />
| 0-23<br />
| float1.7.16, Vertex attribute element 1 (X)<br />
|-<br />
| 24-31<br />
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)<br />
|}<br />
<br />
Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.<br />
<br />
=== GPUREG_CMDBUF_SIZE0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the size of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_SIZE1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-20<br />
| unsigned, Size of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the size of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 0 >> 3<br />
|}<br />
<br />
This register sets the physical address of the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_ADDR1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-28<br />
| unsigned, Physical address of command buffer 1 >> 3<br />
|}<br />
<br />
This register sets the physical address of the second command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)<br />
|}<br />
<br />
This register triggers a jump to the first command buffer.<br />
<br />
=== GPUREG_CMDBUF_JUMP1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)<br />
|}<br />
<br />
This register triggers a jump to the second command buffer.<br />
<br />
=== GPUREG_VSH_NUM_ATTR ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader input attributes - 1<br />
|}<br />
<br />
This register sets the number of vertex shader input attributes.<br />
<br />
=== GPUREG_VSH_COM_MODE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)<br />
|}<br />
<br />
This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.<br />
<br />
=== GPUREG_START_DRAW_FUNC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Mode (0 = drawing, 1 = configuration)<br />
|-<br />
| 1-7<br />
| 0x0<br />
|}<br />
<br />
This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_VSH_OUTMAP_TOTAL2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|}<br />
<br />
This register sets the number of vertex shader output map registers.<br />
<br />
=== GPUREG_GSH_MISC0 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)<br />
|}<br />
<br />
This register configures miscellaneous geometry shader properties.<br />
<br />
=== GPUREG_GEOSTAGE_CONFIG2 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)<br />
|-<br />
| 8<br />
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)<br />
|}<br />
<br />
This register configures the geometry stage of the GPU pipeline.<br />
<br />
When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.<br />
<br />
When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.<br />
<br />
=== GPUREG_GSH_MISC1 ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-4<br />
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)<br />
|}<br />
<br />
This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.<br />
<br />
=== GPUREG_PRIMITIVE_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Number of vertex shader output map registers - 1<br />
|-<br />
| 8-9<br />
| unsigned, Primitive mode<br />
|}<br />
<br />
This register configures primitive drawing.<br />
<br />
Primitive mode value:<br />
<br />
{| class="wikitable" border="1"<br />
! Value<br />
! Description<br />
|-<br />
| 0<br />
| Triangles<br />
|-<br />
| 1<br />
| Triangle strip<br />
|-<br />
| 2<br />
| Triangle fan<br />
|-<br />
| 3<br />
| Geometry primitive<br />
|}<br />
<br />
=== GPUREG_RESTART_PRIMITIVE ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Trigger (0 = idle, 1 = reset primitive)<br />
|-<br />
| 1-31<br />
| 0x0<br />
|}<br />
<br />
This register triggers resetting primitive drawing.<br />
<br />
== Shader registers ==<br />
<br />
=== GPUREG_''SH''_BOOLUNIFORM ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Boolean register b0 value (0 = false, 1 = true)<br />
|-<br />
| 1<br />
| unsigned, Boolean register b1 value (0 = false, 1 = true)<br />
|-<br />
| 2<br />
| unsigned, Boolean register b2 value (0 = false, 1 = true)<br />
|-<br />
| 3<br />
| unsigned, Boolean register b3 value (0 = false, 1 = true)<br />
|-<br />
| 4<br />
| unsigned, Boolean register b4 value (0 = false, 1 = true)<br />
|-<br />
| 5<br />
| unsigned, Boolean register b5 value (0 = false, 1 = true)<br />
|-<br />
| 6<br />
| unsigned, Boolean register b6 value (0 = false, 1 = true)<br />
|-<br />
| 7<br />
| unsigned, Boolean register b7 value (0 = false, 1 = true)<br />
|-<br />
| 8<br />
| unsigned, Boolean register b8 value (0 = false, 1 = true)<br />
|-<br />
| 9<br />
| unsigned, Boolean register b9 value (0 = false, 1 = true)<br />
|-<br />
| 10<br />
| unsigned, Boolean register b10 value (0 = false, 1 = true)<br />
|-<br />
| 11<br />
| unsigned, Boolean register b11 value (0 = false, 1 = true)<br />
|-<br />
| 12<br />
| unsigned, Boolean register b12 value (0 = false, 1 = true)<br />
|-<br />
| 13<br />
| unsigned, Boolean register b13 value (0 = false, 1 = true)<br />
|-<br />
| 14<br />
| unsigned, Boolean register b14 value (0 = false, 1 = true)<br />
|-<br />
| 15<br />
| unsigned, Boolean register b15 value (0 = false, 1 = true)<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register is used to set a shader unit's boolean registers.<br />
<br />
=== GPUREG_''SH''_INTUNIFORM_I''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Integer register i''i'' X value<br />
|-<br />
| 8-15<br />
| unsigned, Integer register i''i'' Y value<br />
|-<br />
| 16-23<br />
| unsigned, Integer register i''i'' Z value<br />
|-<br />
| 24-31<br />
| unsigned, Integer register i''i'' W value<br />
|}<br />
<br />
These registers are used to set a shader unit's integer registers.<br />
<br />
=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Input vertex attributes - 1<br />
|-<br />
| 8-15<br />
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)<br />
|-<br />
| 16-23<br />
| 0x0<br />
|-<br />
| 24-31<br />
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)<br />
|}<br />
<br />
This register is used to configure a shader unit's input buffer.<br />
<br />
=== GPUREG_''SH''_ENTRYPOINT ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-15<br />
| unsigned, Code entry point offset, in 32-bit words<br />
|-<br />
| 16-31<br />
| 0x7FFF<br />
|}<br />
<br />
This register sets a shader unit's code entry point.<br />
<br />
For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.<br />
<br />
For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them. <br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 0 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 1 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 2 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 3 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 4 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 5 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 6 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 7 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.<br />
<br />
=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-3<br />
| unsigned, Vertex attribute 8 input register index<br />
|-<br />
| 4-7<br />
| unsigned, Vertex attribute 9 input register index<br />
|-<br />
| 8-11<br />
| unsigned, Vertex attribute 10 input register index<br />
|-<br />
| 12-15<br />
| unsigned, Vertex attribute 11 input register index<br />
|-<br />
| 16-19<br />
| unsigned, Vertex attribute 12 input register index<br />
|-<br />
| 20-23<br />
| unsigned, Vertex attribute 13 input register index<br />
|-<br />
| 24-27<br />
| unsigned, Vertex attribute 14 input register index<br />
|-<br />
| 28-31<br />
| unsigned, Vertex attribute 15 input register index<br />
|}<br />
<br />
This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.<br />
<br />
=== GPUREG_''SH''_OUTMAP_MASK ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 1<br />
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 2<br />
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 3<br />
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 4<br />
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 5<br />
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 6<br />
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)<br />
|-<br />
| 7<br />
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 8<br />
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 9<br />
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 10<br />
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 11<br />
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 12<br />
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 13<br />
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 14<br />
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 15<br />
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)<br />
|-<br />
| 16-31<br />
| 0x0<br />
|}<br />
<br />
This register toggles a shader unit's output registers.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_END ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Signal transfer end (0 = idle, non-zero = signal)<br />
|}<br />
<br />
This register's value should be set to 1 in order to finalize the transfer of shader code.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-7<br />
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)<br />
|-<br />
| 31<br />
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)<br />
|}<br />
<br />
This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.<br />
<br />
=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| Floating-point register component data<br />
|}<br />
<br />
This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].<br />
<br />
* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:<br />
** first word : ZZWWWWWW<br />
** second word : YYYYZZZZ<br />
** third word : XXXXXXYY<br />
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader code offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader instruction data<br />
|}<br />
<br />
This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.<br />
<br />
=== GPUREG_''SH''_OPDESCS_INDEX ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-11<br />
| unsigned, Target shader operand descriptor offset<br />
|}<br />
<br />
This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.<br />
<br />
=== GPUREG_''SH''_OPDESCS_DATA''i'' ===<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-31<br />
| unsigned, Shader operand descriptor data<br />
|}<br />
<br />
This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19589
Pinouts
2017-02-11T22:24:35Z
<p>Plutooo: </p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | 0? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | 1? || style="background: #cc9900" | 2? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | 3? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #73e600" | ? || style="background: #476b6b" | 3? || style="background: #476b6b" | 4? || style="background: #476b6b" | 5? || || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #73e600" | ? || style="background: #8efab4" | SDA || style="background: #476b6b" | 1? || style="background: #476b6b" | 2? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #8efab4" | SCL || style="background: #476b6b" | 0? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC0 (unknown)<br />
|-<br />
| style="background: #476b6b" | CODEC1 (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | + || style="background: #d9ffb3" | + || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTHM || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || PWRBTN || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}<br />
<br />
== CODEC ==<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:36%;"<br />
| || style="background: #476b6b" | 4? || style="background: #d9ffb3" | 3v3 || || style="background: #cc9900" | 3? || style="background: #cc9900" | 0? || style="background: #336600" | ? || style="background: #336600" | ? || || style="background: #bbbbbb" | G ||<br />
|-<br />
| || style="background: #476b6b" | 3? || style="background: #476b6b" | 5? || style="background: #bbbbbb" | G || || style="background: #cc9900" | 1? || style="background: #336600" | CSx || style="background: #336600" | ? || || style="background: #bbbbbb" | G ||<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #476b6b" | 2? || style="background: #476b6b" | 0? || style="background: #bbbbbb" | G || || style="background: #cc9900" | 2? || style="background: #336600" | CSy || || || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || style="background: #476b6b" | 1? || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || ||<br />
|-<br />
| CPAD || CPAD || || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || ||<br />
|-<br />
| || || || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || || SPEAKER2<br />
|-<br />
| MIC || || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || || SPEAKER2<br />
|-<br />
| JACK_R || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || || style="background: #bbbbbb" | G || || || || || || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #d9ffb3" | 3v3 || || || || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || || ||<br />
|-<br />
| || || style="background: #bbbbbb" | G || || || || JACK_L || || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G ||<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Mysteries&diff=19566
Mysteries
2017-02-09T23:43:54Z
<p>Plutooo: </p>
<hr />
<div>The following is a list of mysteries.<br />
<br />
== General ==<br />
* What is the CTR abbreviation?<br />
: C may stand for Chiheisen ("horizon" in Japanese, the O3DS's codename being "Project Horizon").<br />
:: Not true, Horizon refers to the OS.<br />
<br />
== Hardware ==<br />
=== Why are there two CTRCARD controllers? ===<br />
'''Background:''' Also [http://problemkaputt.de/twl-core.jpg DSi SoC pinout] shows evidence of dual NTRCARD controllers on the final DSi SoC. (This was a [http://i.imgur.com/0kJlbEw.png planned feature] of the DSi before being axed later in development)<br />
<br />
=== Why are there two EMMC controllers? ===<br />
'''Theory:''' At some point during 3DS hardware development there was an idea to split up CTR and TWL nand into two different chips.<br />
=== Is there a JTAG? ===<br />
=== Is there more than one revision of the bootrom? ===<br />
'''Background:''' Bootrom visible portion has been dumped on 3DS, 3DSXL, 2DS, New3DS. All matching exactly.<br />
=== What is the EMMC controller @ 0x10100000 doing? ===<br />
'''Background:''' There's dead code in NWM referencing it.<br />
=== Why did they put NTRCARD accessible from ARM11? ===<br />
'''Theory:''' At some point during 3DS hardware development there was a concept where ARM11 ran a menu with DS(i) icons while ARM9 was in TWL mode.<br />
<br />
=== Is there a secret message embedded in the 3DS keyscrambler constant? ===<br />
'''Background:''' TWL key scrambler constant was "Nintendo Co., Ltd" in Japanese ("任天堂株式会社"), UTF-16LE encoded, with byte order mark. The 3DS key scrambler constant, by comparison, is random-looking.<br />
<br />
=== What is the PDN abbreviation? ===<br />
: Power distribution network<br />
<br />
=== How does Nintendo reflash bricked systems? ===<br />
'''Background:''' The boot ROM will boot from SPI flash if the FIRM partitions are both corrupt. But if, say, Home Menu gets deleted, the system is dead, and boot ROM would still see the NAND as valid. How does Nintendo's refurbishing center reflash such systems?<br />
<br />
== Software ==<br />
=== What was the problem in "initial program loader" that was mentioned in an FCC filing by Nintendo for 2DS? ===<br />
'''Background:''' http://www.neogaf.com/forum/showthread.php?t=814624&page=1<br />
=== What did SVC 0x74 in the ARM11 kernel do before it got stubbed? ===<br />
=== What is the PTM abbreviation? ===<br />
=== Why is the DTCM not used anywhere except bootrom? ===<br />
'''Background:''' Bootrom is known to use part of DTCM as state, memsetting it to 0 when it's done. After that, it is never used again.<br />
=== How is CTRAging launched during factory setup? ===<br />
'''Background:''' No TestMenu version is capable of launching CTRAging directly: O3DS factory TestMenu can only launch DevMenu installed on NAND, the inserted cartridge and the TWL/AGB test apps; N3DS factory TestMenu can only launch DevMenu installed on NAND, the inserted cartridge and System Settings.<br />
=== Why are there 4 stubbed syscalls named SendSyncRequest1-4? ===</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG11_Registers&diff=19551
CONFIG11 Registers
2017-02-08T21:28:22Z
<p>Plutooo: </p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7><br />
| 0x10140000<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7><br />
| 0x10140008<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140100<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140102<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_FIQ_CNT|CFG11_FIQ_CNT]]<br />
| 0x10140104<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140105<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x10140108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x1014010C<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPUPROT|CFG11_GPUPROT]]<br />
| 0x10140140<br />
| 4<br />
| Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_WIFICNT|CFG11_WIFICNT]]<br />
| 0x10140180<br />
| 1<br />
| TwlBg, [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]<br />
| 0x101401C0<br />
| 4<br />
| [[SPI Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140200<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140400<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140410<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]<br />
| 0x10140420<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]<br />
| 0x10140424<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| ?<br />
| 0x10140428<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]<br />
| 0x10140FFC<br />
| 2<br />
| Boot11, Kernel11<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| CFG11_GPU_STATUS?<br />
| 0x10141000<br />
| 4<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_0<br />
| 0x10141008<br />
| 4<br />
| [[PTM Services]], [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_1<br />
| 0x1014100C<br />
| 4<br />
| [[PTM Services]], TwlBg, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_0|CFG11_TWLMODE_0]]<br />
| 0x10141100<br />
| 2<br />
| TwlProcess9, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_1|CFG11_TWLMODE_1]]<br />
| 0x10141104<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_2|CFG11_TWLMODE_2]]<br />
| 0x10141108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_HID|CFG11_TWLMODE_HID]]<br />
| 0x1014110A<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_WIFIUNK|CFG11_WIFIUNK]]<br />
| 0x1014110C<br />
| 1<br />
| [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141110<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141112<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_0]]<br />
| 0x10141114<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_1]]<br />
| 0x10141116<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141118<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141119<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141120<br />
| 1<br />
| TwlBg<br />
|-<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT|CFG11_GPU_CNT]]<br />
| 0x10141200<br />
| 4<br />
| Boot11, Kernel11, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT2|CFG11_GPU_CNT2]]<br />
| 0x10141204<br />
| 4<br />
| Boot11, Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_GPU_CNT3<br />
| 0x10141210<br />
| 2<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC_CNT|CFG11_CODEC_CNT]]<br />
| 0x10141220<br />
| 1<br />
| Boot11, TwlBg, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]]<br />
| 0x10141224<br />
| 1<br />
| [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_DSP_CNT<br />
| 0x10141230<br />
| 1<br />
| Process9, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CLKCNT|CFG11_MPCORE_CLKCNT]]<br />
| 0x10141300<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CNT|CFG11_MPCORE_CNT]]<br />
| 0x10141304<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_BOOTCNT<0-3>|CFG11_MPCORE_BOOTCNT]]<0-3><br />
| 0x10141310<br />
| 1*4<br />
| NewKernel11<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_DATA ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_CODE ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_FIQ_CNT ==<br />
Writing bit1 to this register disables FIQ interrupts.<br />
<br />
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.<br />
It is cleared when binding that software interrupt to an event and just before that event is signaled.<br />
<br />
== CFG11_SPI_CNT ==<br />
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Enable [[SPI Registers]] 0x10160000.<br />
|-<br />
| 1<br />
| Enable [[SPI Registers]] 0x10142000.<br />
|-<br />
| 2<br />
| Enable [[SPI Registers]] 0x10143000.<br />
|}<br />
<br />
== CFG11_BOOTROM_OVERLAY_CNT ==<br />
Bit0: Enable bootrom overlay functionality.<br />
<br />
== CFG11_BOOTROM_OVERLAY_VAL ==<br />
The 32-bit value to overlay data-reads to bootrom with. See [[#CFG11_MPCORE_BOOTCNT|CFG11_MPCORE_BOOTCNT]].<br />
<br />
== CFG11_SOCINFO ==<br />
Read-only register.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| 1 on both Old3DS and New3DS.<br />
| Boot11<br />
|-<br />
| 1<br />
| 1 on New3DS.<br />
| Kernel11<br />
|-<br />
| 2<br />
| Clock modifier: if set, use a 3x multiplier, otherwise 2x<br />
| Kernel11<br />
|}<br />
<br />
== CFG11_MPCORE_CLKCNT ==<br />
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.<br />
|-<br />
| 1-2<br />
| Clock multiplier (0=1x, 1=2x, 2=3x, 3=hang)<br />
|-<br />
| 15<br />
| Busy<br />
|}<br />
<br />
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG:<br />
{| class="wikitable" border="1"<br />
! Register value<br />
! Higher-clockrate bit set in svcKernelSetState Param0<br />
! CFG11_MPCORE_CFG bit2 set<br />
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state<br />
! Clock-rate multiplier<br />
! Description<br />
|-<br />
| 0x01<br />
| No<br />
| Yes<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x02<br />
| No<br />
| No<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x05<br />
| Yes<br />
| Yes<br />
| 0x03<br />
| 3x<br />
| 804MHz<br />
|-<br />
| 0x03<br />
| Yes<br />
| No<br />
| 0x02<br />
| 2x<br />
| 536MHz (tested on New3DS)<br />
|}<br />
<br />
Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).<br />
<br />
The following register value(s) were tested on New3DS by patching the kernel:<br />
* 0x00: Entire system hangs.<br />
* 0x02: Entire system hangs.<br />
* 0x03: ARM11 runs at 536MHz.<br />
* 0x04: Entire system hangs.<br />
* 0x06: Entire system hangs.<br />
* 0x07: Same result as 0x05.<br />
* 0x08: Entire system hangs.<br />
* 0x09: Entire system hangs.<br />
* 0x0A: Entire system hangs.<br />
* 0x0B: Same result as 0x03.<br />
* 0x0C: Entire system hangs.<br />
* 0x0D: Same result as 0x05.<br />
* 0x0E: Entire system hangs.<br />
* 0x0F: Same result as 0x05.<br />
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.<br />
<br />
== CFG11_MPCORE_CNT ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Power on 3rd ARM11 MPCore maybe?<br />
|-<br />
| 8<br />
| Power on 4th ARM11 MPCore maybe?<br />
|}<br />
<br />
== CFG11_MPCORE_BOOTCNT<0-3> ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable bootrom instruction overlay, maybe? This bit is only writable for core2 and core3.<br />
|-<br />
| 1<br />
| Enable bootrom data overlay. This bit is only writable for core2 and core3.<br />
|-<br />
| 4<br />
| Has core booted maybe?<br />
|-<br />
| 5<br />
| Always 1?<br />
|}<br />
<br />
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.<br />
<br />
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].<br />
<br />
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:<br />
ldr pc, [pc]<br />
<br />
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.<br />
<br />
==CFG11_GPUPROT==<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Bits<br />
! Description<br />
|-<br />
| style="background: green" | Yes<br />
| 3-0<br />
| Old FCRAM DMA cutoff size, 0 = no protection.<br />
|-<br />
| style="background: red" | No<br />
| 7-4<br />
| New FCRAM DMA cutoff size, 0 = no protection.<br />
|-<br />
| style="background: green" | Yes<br />
| 8<br />
| AXIWRAM protection, 0 = accessible.<br />
|-<br />
| style="background: red" | No<br />
| 10-9<br />
| QTM DMA cutoff size<br />
|-<br />
| style="background: green" | Yes<br />
| 31-11<br />
| Zeroes<br />
|}<br />
<br />
For the old FCRAM DMA cutoff, it protects starting from 0x28000000-(0x800000*x) until end of FCRAM. There is no way to protect the first 0x800000-bytes.<br />
<br />
For the new FCRAM DMA cutoff, it protects starting from 0x30000000-(0x800000*x) until end of FCRAM. When the old FCRAM cutoff is set to non-zero, the first 0x800000-bytes bytes of new FCRAM are protected.<br />
<br />
On New3DS the old+new FCRAM cutoff can be used at the same time, however this isn't done officially.<br />
<br />
For the QTM DMA cutoff, it protects starting from 0x1F400000-(0x100000*x) until end of QTM mem.<br />
<br />
On cold boot this reg is set to 0.<br />
<br />
When this register is set to value 0, the GPU can access the entire FCRAM, AXIWRAM, and on New3DS all QTM-mem.<br />
<br />
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with [[11.3.0-36|v11.3]].<br />
<br />
==CFG11_WIFICNT==<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Bits<br />
! Description<br />
|-<br />
| style="background: green" | Yes<br />
| 0<br />
| Enable wifi subsystem<br />
|}<br />
<br />
==CFG11_TWLMODE_0==<br />
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.<br />
<br />
This address is poked from ARM7 to signal that it has booted and begun executing code. The ARM7-mode address for this register is 0x4700000.<br />
<br />
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.<br />
<br />
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.<br />
<br />
==CFG11_TWLMODE_1==<br />
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.<br />
<br />
==CFG11_TWLMODE_2==<br />
Bitfield.<br />
<br />
==CFG11_TWLMODE_HID==<br />
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.<br />
<br />
==CFG11_WIFIUNK==<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Bits<br />
! Description<br />
|-<br />
| style="background: green" | Yes<br />
| 4<br />
| Wifi-related? Set to 1 very early in NWM-module.<br />
|}<br />
<br />
==CFG11_GPU_CNT==<br />
This one seems to control the LCD/GPU/Backlight.<br />
<br />
Bit0: Enable GPU registers at 0x10400000+.<br />
Bit16: Turn on LCD backlight.<br />
<br />
==CFG11_GPU_CNT2==<br />
Bit0: Power on GPU?<br />
<br />
==CFG11_GPU_CNT3==<br />
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.<br />
<br />
==CFG11_CODEC==<br />
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.<br />
<br />
==CFG11_CODEC_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] CODEC service.<br />
<br />
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.<br />
<br />
==CFG11_CAMERA_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] camera service.<br />
<br />
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG11_Registers&diff=19550
CONFIG11 Registers
2017-02-08T19:23:01Z
<p>Plutooo: </p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7><br />
| 0x10140000<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7><br />
| 0x10140008<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140100<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140102<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_FIQ_CNT|CFG11_FIQ_CNT]]<br />
| 0x10140104<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140105<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x10140108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x1014010C<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPUPROT|CFG11_GPUPROT]]<br />
| 0x10140140<br />
| 4<br />
| Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_WIFICNT|CFG11_WIFICNT]]<br />
| 0x10140180<br />
| 1<br />
| TwlBg, [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]<br />
| 0x101401C0<br />
| 4<br />
| [[SPI Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140200<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140400<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140410<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]<br />
| 0x10140420<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]<br />
| 0x10140424<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| ?<br />
| 0x10140428<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]<br />
| 0x10140FFC<br />
| 2<br />
| Boot11, Kernel11<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| CFG11_GPU_STATUS?<br />
| 0x10141000<br />
| 4<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_0<br />
| 0x10141008<br />
| 4<br />
| [[PTM Services]], [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_1<br />
| 0x1014100C<br />
| 4<br />
| [[PTM Services]], TwlBg, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_0|CFG11_TWLMODE_0]]<br />
| 0x10141100<br />
| 2<br />
| TwlProcess9, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_1|CFG11_TWLMODE_1]]<br />
| 0x10141104<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_2|CFG11_TWLMODE_2]]<br />
| 0x10141108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_HID|CFG11_TWLMODE_HID]]<br />
| 0x1014110A<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_WIFI?<br />
| 0x1014110C<br />
| 1<br />
| [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141110<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141112<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_0]]<br />
| 0x10141114<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_1]]<br />
| 0x10141116<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141118<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141119<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141120<br />
| 1<br />
| TwlBg<br />
|-<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT|CFG11_GPU_CNT]]<br />
| 0x10141200<br />
| 4<br />
| Boot11, Kernel11, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT2|CFG11_GPU_CNT2]]<br />
| 0x10141204<br />
| 4<br />
| Boot11, Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_GPU_CNT3<br />
| 0x10141210<br />
| 2<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC_CNT|CFG11_CODEC_CNT]]<br />
| 0x10141220<br />
| 1<br />
| Boot11, TwlBg, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]]<br />
| 0x10141224<br />
| 1<br />
| [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_DSP_CNT<br />
| 0x10141230<br />
| 1<br />
| Process9, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CLKCNT|CFG11_MPCORE_CLKCNT]]<br />
| 0x10141300<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CNT|CFG11_MPCORE_CNT]]<br />
| 0x10141304<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_BOOTCNT<0-3>|CFG11_MPCORE_BOOTCNT]]<0-3><br />
| 0x10141310<br />
| 1*4<br />
| NewKernel11<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_DATA ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_CODE ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_FIQ_CNT ==<br />
Writing bit1 to this register disables FIQ interrupts.<br />
<br />
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.<br />
It is cleared when binding that software interrupt to an event and just before that event is signaled.<br />
<br />
== CFG11_SPI_CNT ==<br />
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Enable [[SPI Registers]] 0x10160000.<br />
|-<br />
| 1<br />
| Enable [[SPI Registers]] 0x10142000.<br />
|-<br />
| 2<br />
| Enable [[SPI Registers]] 0x10143000.<br />
|}<br />
<br />
== CFG11_BOOTROM_OVERLAY_CNT ==<br />
Bit0: Enable bootrom overlay functionality.<br />
<br />
== CFG11_BOOTROM_OVERLAY_VAL ==<br />
The 32-bit value to overlay data-reads to bootrom with. See [[#CFG11_MPCORE_BOOTCNT|CFG11_MPCORE_BOOTCNT]].<br />
<br />
== CFG11_SOCINFO ==<br />
Read-only register.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| 1 on both Old3DS and New3DS.<br />
| Boot11<br />
|-<br />
| 1<br />
| 1 on New3DS.<br />
| Kernel11<br />
|-<br />
| 2<br />
| Clock modifier: if set, use a 3x multiplier, otherwise 2x<br />
| Kernel11<br />
|}<br />
<br />
== CFG11_MPCORE_CLKCNT ==<br />
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.<br />
|-<br />
| 1-2<br />
| Clock multiplier (0=1x, 1=2x, 2=3x, 3=hang)<br />
|-<br />
| 15<br />
| Busy<br />
|}<br />
<br />
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG:<br />
{| class="wikitable" border="1"<br />
! Register value<br />
! Higher-clockrate bit set in svcKernelSetState Param0<br />
! CFG11_MPCORE_CFG bit2 set<br />
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state<br />
! Clock-rate multiplier<br />
! Description<br />
|-<br />
| 0x01<br />
| No<br />
| Yes<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x02<br />
| No<br />
| No<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x05<br />
| Yes<br />
| Yes<br />
| 0x03<br />
| 3x<br />
| 804MHz<br />
|-<br />
| 0x03<br />
| Yes<br />
| No<br />
| 0x02<br />
| 2x<br />
| 536MHz (tested on New3DS)<br />
|}<br />
<br />
Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).<br />
<br />
The following register value(s) were tested on New3DS by patching the kernel:<br />
* 0x00: Entire system hangs.<br />
* 0x02: Entire system hangs.<br />
* 0x03: ARM11 runs at 536MHz.<br />
* 0x04: Entire system hangs.<br />
* 0x06: Entire system hangs.<br />
* 0x07: Same result as 0x05.<br />
* 0x08: Entire system hangs.<br />
* 0x09: Entire system hangs.<br />
* 0x0A: Entire system hangs.<br />
* 0x0B: Same result as 0x03.<br />
* 0x0C: Entire system hangs.<br />
* 0x0D: Same result as 0x05.<br />
* 0x0E: Entire system hangs.<br />
* 0x0F: Same result as 0x05.<br />
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.<br />
<br />
== CFG11_MPCORE_CNT ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Power on 3rd ARM11 MPCore maybe?<br />
|-<br />
| 8<br />
| Power on 4th ARM11 MPCore maybe?<br />
|}<br />
<br />
== CFG11_MPCORE_BOOTCNT<0-3> ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable bootrom instruction overlay, maybe? This bit is only writable for core2 and core3.<br />
|-<br />
| 1<br />
| Enable bootrom data overlay. This bit is only writable for core2 and core3.<br />
|-<br />
| 4<br />
| Has core booted maybe?<br />
|-<br />
| 5<br />
| Always 1?<br />
|}<br />
<br />
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.<br />
<br />
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].<br />
<br />
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:<br />
ldr pc, [pc]<br />
<br />
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.<br />
<br />
==CFG11_GPUPROT==<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Bits<br />
! Description<br />
|-<br />
| style="background: green" | Yes<br />
| 3-0<br />
| Old FCRAM DMA cutoff size, 0 = no protection.<br />
|-<br />
| style="background: red" | No<br />
| 7-4<br />
| New FCRAM DMA cutoff size, 0 = no protection.<br />
|-<br />
| style="background: green" | Yes<br />
| 8<br />
| AXIWRAM protection, 0 = accessible.<br />
|-<br />
| style="background: red" | No<br />
| 10-9<br />
| QTM DMA cutoff size<br />
|-<br />
| style="background: green" | Yes<br />
| 31-11<br />
| Zeroes<br />
|}<br />
<br />
For the old FCRAM DMA cutoff, it protects starting from 0x28000000-(0x800000*x) until end of FCRAM. There is no way to protect the first 0x800000-bytes.<br />
<br />
For the new FCRAM DMA cutoff, it protects starting from 0x30000000-(0x800000*x) until end of FCRAM. When the old FCRAM cutoff is set to non-zero, the first 0x800000-bytes bytes of new FCRAM are protected.<br />
<br />
On New3DS the old+new FCRAM cutoff can be used at the same time, however this isn't done officially.<br />
<br />
For the QTM DMA cutoff, it protects starting from 0x1F400000-(0x100000*x) until end of QTM mem.<br />
<br />
On cold boot this reg is set to 0.<br />
<br />
When this register is set to value 0, the GPU can access the entire FCRAM, AXIWRAM, and on New3DS all QTM-mem.<br />
<br />
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with [[11.3.0-36|v11.3]].<br />
<br />
==CFG11_WIFICNT==<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Bits<br />
! Description<br />
|-<br />
| style="background: green" | Yes<br />
| 0<br />
| Enable wifi subsystem<br />
|}<br />
<br />
==CFG11_TWLMODE_0==<br />
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.<br />
<br />
This address is poked from ARM7 to signal that it has booted and begun executing code. The ARM7-mode address for this register is 0x4700000.<br />
<br />
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.<br />
<br />
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.<br />
<br />
==CFG11_TWLMODE_1==<br />
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.<br />
<br />
==CFG11_TWLMODE_2==<br />
Bitfield.<br />
<br />
==CFG11_TWLMODE_HID==<br />
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.<br />
<br />
==CFG11_WIFI?==<br />
Bit4=unknown enabled by NWM on launch. Potentially powers on wifi card.<br />
<br />
==CFG11_GPU_CNT==<br />
This one seems to control the LCD/GPU/Backlight.<br />
<br />
Bit0: Enable GPU registers at 0x10400000+.<br />
Bit16: Turn on LCD backlight.<br />
<br />
==CFG11_GPU_CNT2==<br />
Bit0: Power on GPU?<br />
<br />
==CFG11_GPU_CNT3==<br />
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.<br />
<br />
==CFG11_CODEC==<br />
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.<br />
<br />
==CFG11_CODEC_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] CODEC service.<br />
<br />
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.<br />
<br />
==CFG11_CAMERA_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] camera service.<br />
<br />
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=GPIO_Services&diff=19549
GPIO Services
2017-02-08T19:19:46Z
<p>Plutooo: /* GPIO Bits */</p>
<hr />
<div>[[Category:Services]]<br />
= GPIO Service Names =<br />
{| class="wikitable" border="1"<br />
|-<br />
! Service name<br />
! Permitted GPIO bitmasks<br />
|-<br />
| gpio:CDC<br />
| 0x48<br />
|-<br />
| gpio:MCU<br />
| 0x48020<br />
|-<br />
| gpio:HID<br />
| 0x4301<br />
|-<br />
| gpio:NWM<br />
| 0x40020<br />
|-<br />
| gpio:IR<br />
| 0xEC0<br />
|-<br />
| gpio:NFC<br />
| 0x13000<br />
|-<br />
| gpio:QTM<br />
| 0x20000<br />
|}<br />
<br />
For the mapping between GPIO bitmasks and IRQs see: [[GPIO:BindInterrupt#Supported_values]].<br />
<br />
The commands for these services are identical.<br />
<br />
The input bitmask for each command is masked with the above permission bitmask, if the result is non-zero an error is occurred.<br />
<br />
= GPIO Services =<br />
{| class="wikitable" border="1"<br />
|-<br />
! Command Header<br />
! Description<br />
! Uses [[GPIO_Registers|GPIO Regs]]<br />
|-<br />
| 0x0001....<br />
| ?(u32 unk1,u32* ret)<br />
| 0x10147010, 0x10147020<br />
|-<br />
| 0x00020080<br />
| ?(u32 unk1,u32 unk2)<br />
| 0x10147010, 0x10147020<br />
|-<br />
| 0x0003....<br />
| ?(u32 unk1,u32* ret)<br />
| 0x10147010, 0x10147024<br />
|-<br />
| 0x00040080<br />
| ?(u32 unk1,u32 unk2)<br />
| 0x10147010, 0x10147024<br />
|-<br />
| 0x0005....<br />
| ?(u32 unk1,u32* ret)<br />
| 0x10147010, 0x10147024<br />
|-<br />
| 0x00060080<br />
| ?(u32 unk1,u32 unk2)<br />
| 0x10147010, 0x10147024<br />
|-<br />
| 0x00070040<br />
| [[GPIO:GetGPIOData|GetGPIOData]]<br />
| 0x10147000, 0x10147010, 0x10147014, 0x10147020, 0x10147028<br />
|-<br />
| 0x00080080<br />
| [[GPIO:SetGPIOData|SetGPIOData]]<br />
| 0x10147010, 0x10147014, 0x10147020, 0x10147028<br />
|-<br />
| 0x00090082<br />
| [[GPIO:BindInterrupt|BindInterrupt]]<br />
| None<br />
|-<br />
| 0x000A0042<br />
| [[GPIO:UnbindInterrupt|UnbindInterrupt]]<br />
| None<br />
|}<br />
<br />
=GPIO Bitmask=<br />
The bitmask used by the service commands determines which bits in the GPIO registers to access. The output value from [[GPIO:GetGPIOData|GetGPIOData]] uses the same format as the bitmask: the values of bits in the output field are set to the value of GPIO data when those bits are set in the input bitmask.<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Bits in the bitmask<br />
! Register<br />
! Bits from register<br />
! Handled with [[GPIO:SetGPIOData]]<br />
|-<br />
| 0-2 (0x7)<br />
| 0x10147000<br />
| 0-2<br />
| No<br />
|-<br />
| 3-4 (0x18)<br />
| 0x10147010<br />
| 0-1<br />
| Yes<br />
|-<br />
| 5 (0x20)<br />
| 0x10147014<br />
| 0<br />
| Yes<br />
|-<br />
| 6-17 (0x3FFC0)<br />
| 0x10147020<br />
| 0-11<br />
| Yes<br />
|-<br />
| 18 (0x40000)<br />
| 0x10147028<br />
| 0<br />
| Yes<br />
|}<br />
<br />
==GPIO Bits==<br />
{| class="wikitable" border="1"<br />
|-<br />
! Bit<br />
! Bitmask<br />
! Accessible via GPIO service<br />
! Used by<br />
! Description<br />
|-<br />
| 0<br />
| 0x1<br />
| gpio:HID<br />
| HID-sysmodule<br />
| Used with [[HID_Shared_Memory|HID]] PAD state.<br />
|-<br />
| 1<br />
| 0x2<br />
| None<br />
| <br />
| Not known to be used by ''anything'', with the latest system-version at least.<br />
|-<br />
| 2<br />
| 0x4<br />
| None<br />
| <br />
| Not known to be used by ''anything'', with the latest system-version at least.<br />
|-<br />
| 3<br />
| 0x8<br />
| gpio:CDC<br />
| ?<br />
| ?<br />
|-<br />
| 4<br />
| 0x10<br />
| None<br />
| <br />
| Not known to be used by ''anything'', with the latest system-version at least.<br />
|-<br />
| 5<br />
| 0x20<br />
| gpio:MCU, gpio:NWM<br />
| ?<br />
| ?<br />
|-<br />
| 6<br />
| 0x40<br />
| gpio:CDC, gpio:IR<br />
| ?<br />
| ?<br />
|-<br />
| 7<br />
| 0x80<br />
| gpio:IR<br />
| ?<br />
| ?<br />
|-<br />
| 8<br />
| 0x100<br />
| gpio:HID<br />
| ?<br />
| ?<br />
|-<br />
| 9<br />
| 0x200<br />
| gpio:HID, gpio:IR<br />
| HID-sysmodule and IR-sysmodule<br />
| Unknown, used with ir:rst.<br />
|-<br />
| 10<br />
| 0x400<br />
| gpio:IR<br />
| IR-sysmodule<br />
| IR [[IRU:SetIRLEDState|send]]. 1 = IR LED enable, 0 = IR LED disable.<br />
|-<br />
| 11<br />
| 0x800<br />
| gpio:IR<br />
| IR-sysmodule<br />
| IR [[IRU:GetIRLEDRecvState|receive]]<br />
|-<br />
| 12<br />
| 0x1000<br />
| gpio:NFC<br />
| ?<br />
| ?<br />
|-<br />
| 13<br />
| 0x2000<br />
| gpio:NFC<br />
| ?<br />
| ?<br />
|-<br />
| 14<br />
| 0x4000<br />
| gpio:HID<br />
| HID-sysmodule<br />
| Used with [[HID_Shared_Memory|HID]] PAD state.<br />
|-<br />
| 15<br />
| 0x8000<br />
| gpio:MCU<br />
| ?<br />
| ?<br />
|-<br />
| 16<br />
| 0x10000<br />
| gpio:NFC<br />
| ?<br />
| ?<br />
|-<br />
| 17<br />
| 0x20000<br />
| gpio:QTM<br />
| ?<br />
| ?<br />
|-<br />
| 18<br />
| 0x40000<br />
| gpio:MCU, gpio:NWM<br />
| NWM-sysmodule<br />
| Wifi enable. 1=Enabled, 0=Disabled.<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=MCU_Services&diff=19548
MCU Services
2017-02-08T19:17:47Z
<p>Plutooo: /* MCU wifi service "mcu::NWM" */</p>
<hr />
<div>Only one session can be open per service at a time. If a session is already open for a service, MCU module will wait for the thread handling the session to terminate(triggered by the session being closed by the user process), then it accepts the new session. The commands for each service are handled by separate threads.<br />
<br />
=MCU camera service "mcu::CAM"=<br />
{| class="wikitable" border="1"<br />
|-<br />
! Command Header<br />
! Description<br />
|-<br />
| 0x0001....<br />
| ?<br />
|-<br />
| 0x0002....<br />
| ?<br />
|}<br />
<br />
=MCU GPU service "mcu::GPU"=<br />
{| class="wikitable" border="1"<br />
|-<br />
! Command Header<br />
! Description<br />
|-<br />
| 0x00010000<br />
| GetLcdPowerState. This writes the value of I2C-MCU register 0xf bit6 to u8 cmdreply[2], and the value of bit5 from that register to u8 cmdreply[3].<br />
|-<br />
| 0x00020080<br />
| SetLcdPowerState. This writes the upper LCD bits of MCU register 0x22.<br />
|-<br />
| 0x00030000<br />
| GetGpuLcdInterfaceState. This writes the value of I2C-MCU register 0xf bit7 to u8 cmdreply[2].<br />
|-<br />
| 0x00040040<br />
| SetGpuLcdInterfaceState. This writes the lower two bits of MCU register 0x22.<br />
|-<br />
| 0x0005....<br />
| ?<br />
|-<br />
| 0x0006....<br />
| ?<br />
|-<br />
| 0x0007....<br />
| ?<br />
|-<br />
| 0x0008....<br />
| ?<br />
|-<br />
| 0x00090000<br />
| GetMcuFwVerHigh. Called by GSP module<br />
|-<br />
| 0x000A0000<br />
| GetMcuFwVerLow. Called by GSP module<br />
|-<br />
| 0x000B0040<br />
| Set3dLedState<br />
|-<br />
| 0x000C....<br />
| Get3dLedState<br />
|-<br />
| 0x000D0000<br />
| GetMcuGpuEventHandle. Event handle written to TLS+0x8c. MCU notifications 24 to 29 signal this.<br />
|-<br />
| 0x000E0000<br />
| GetMcuGpuEventReason. Writes some value to TLS+0x88. Called by GSP module<br />
|}<br />
<br />
=MCU HID service "mcu::HID"=<br />
{| class="wikitable" border="1"<br />
|-<br />
! Command Header<br />
! Description<br />
|-<br />
| 0x00010040<br />
| ?<br />
|-<br />
| 0x0002....<br />
| ?<br />
|-<br />
| 0x0003....<br />
| ?<br />
|-<br />
| 0x0004....<br />
| ?<br />
|-<br />
| 0x0005....<br />
| ?<br />
|-<br />
| 0x0006....<br />
| ?<br />
|-<br />
| 0x00070000<br />
| Get3dSliderState<br />
|-<br />
| 0x0008....<br />
| ?<br />
|-<br />
| 0x00090000<br />
| ?<br />
|-<br />
| 0x000A0000<br />
| ?<br />
|-<br />
| 0x000B....<br />
| ?<br />
|-<br />
| 0x000C0000<br />
| GetMcuHidEventHandle. MCU notifications 11 and 12 signal this.<br />
|-<br />
| 0x000D0000<br />
| GetMcuHidEventReason<br />
|-<br />
| 0x000E0000<br />
| [[MCUHID:GetSoundVolume|GetSoundVolume]]<br />
|-<br />
| 0x000F0040<br />
| SetAccelerometerState(int enable). 1 = enable, 0 = disable accelerometer<br />
|}<br />
<br />
=MCU service "mcu::RTC"=<br />
{| class="wikitable" border="1"<br />
|-<br />
! Command Header<br />
! Description<br />
|-<br />
| 0x0001....<br />
| SetSystemClock (RTC)<br />
|-<br />
| 0x0002....<br />
| GetSystemClock (RTC)<br />
|-<br />
| 0x0003....<br />
| ?<br />
|-<br />
| 0x0004....<br />
| ?<br />
|-<br />
| 0x0005....<br />
| ?<br />
|-<br />
| 0x0006....<br />
| ?<br />
|-<br />
| 0x0007....<br />
| ?<br />
|-<br />
| 0x0008....<br />
| ?<br />
|-<br />
| 0x0009....<br />
| ?<br />
|-<br />
| 0x000A....<br />
| ?<br />
|-<br />
| 0x000B....<br />
| ?<br />
|-<br />
| 0x000C....<br />
| ?<br />
|-<br />
| 0x000D....<br />
| ?<br />
|-<br />
| 0x000E....<br />
| ?<br />
|-<br />
| 0x000F....<br />
| ?<br />
|-<br />
| 0x0010....<br />
| ?<br />
|-<br />
| 0x0011....<br />
| ?<br />
|-<br />
| 0x0012....<br />
| ?<br />
|-<br />
| 0x0013....<br />
| ?<br />
|-<br />
| 0x0014....<br />
| ?<br />
|-<br />
| 0x0015....<br />
| ?<br />
|-<br />
| 0x0016....<br />
| ?<br />
|-<br />
| 0x0017....<br />
| ?<br />
|-<br />
| 0x0018....<br />
| ?<br />
|-<br />
| 0x0019....<br />
| ?<br />
|-<br />
| 0x001A....<br />
| ?<br />
|-<br />
| 0x001B....<br />
| ?<br />
|-<br />
| 0x001C....<br />
| ?<br />
|-<br />
| 0x001D....<br />
| ?<br />
|-<br />
| 0x001E....<br />
| ?<br />
|-<br />
| 0x001F0040<br />
| SetPedometerRecordingMode<br />
|-<br />
| 0x00200000<br />
| GetPedometerState<br />
|-<br />
| 0x0021....<br />
| ?<br />
|-<br />
| 0x0022....<br />
| ?<br />
|-<br />
| 0x0023....<br />
| ?<br />
|-<br />
| 0x0024....<br />
| GetMcuRtcEventHandle. MCU notifications 1, 8, 9, 10, 13, 14 and 15 signal this.<br />
|-<br />
| 0x0025....<br />
| GetMcuRtcEventReason<br />
|-<br />
| 0x0026....<br />
| ?<br />
|-<br />
| 0x0027....<br />
| ?<br />
|-<br />
| 0x0028....<br />
| ?<br />
|-<br />
| 0x0029....<br />
| ?<br />
|-<br />
| 0x002A0000<br />
| GetShellState. This writes the value of I2C-MCU register 0xf bit1 to u8 cmdreply[2].<br />
|-<br />
| 0x002B0000<br />
| GetAdapterState. This writes the value of I2C-MCU register 0xf bit3 to u8 cmdreply[2].<br />
|-<br />
| 0x002C0000<br />
| GetBatteryChargeState. This writes the value of I2C-MCU register 0xf bit4 to u8 cmdreply[2].<br />
|-<br />
| 0x002D0000<br />
| [[MCURTC:GetBatteryLevel|GetBatteryLevel]]<br />
|-<br />
| 0x002E....<br />
| ?<br />
|-<br />
| 0x002F....<br />
| ?<br />
|-<br />
| 0x0030....<br />
| ?<br />
|-<br />
| 0x0031....<br />
| ?<br />
|-<br />
| 0x0032....<br />
| [[MCURTC:PowerOff|PowerOff]] (writes 0x1 to i2c MCU device, reg 0x20)<br />
|-<br />
| 0x0033....<br />
| [[MCURTC:HardwareReboot|HardwareReboot]] (writes 0x4 to i2c MCU device, reg 0x20)<br />
|-<br />
| 0x0034....<br />
| ?<br />
|-<br />
| 0x0035....<br />
| Writes 0x10 to i2c MCU device, reg 0x20<br />
|-<br />
| 0x0036....<br />
| SetWatchdogTimer<br />
|-<br />
| 0x0037....<br />
| GetWatchdogTimer<br />
|-<br />
| 0x0038....<br />
| ?<br />
|-<br />
| 0x0039....<br />
| ?<br />
|-<br />
| 0x003A....<br />
| ?<br />
|-<br />
| 0x003B0640<br />
| [[MCURTC:SetInfoLEDPattern|SetInfoLEDPattern]]<br />
|-<br />
| 0x003C0040<br />
| [[MCURTC:SetInfoLEDPatternHeader|SetInfoLEDPatternHeader]]<br />
|-<br />
| 0x003D0000<br />
| [[MCURTC:GetInfoLEDStatus|GetInfoLEDStatus]]<br />
|-<br />
| 0x003E....<br />
| ?<br />
|-<br />
| 0x003F....<br />
| ?<br />
|-<br />
| 0x0040....<br />
| ?<br />
|-<br />
| 0x0041....<br />
| ?<br />
|-<br />
| 0x00420040<br />
| [[MCURTC:SetBatteryEmptyLEDPattern|SetBatteryEmptyLEDPattern]]<br />
|-<br />
| 0x0043....<br />
| ?<br />
|-<br />
| 0x0044....<br />
| ?<br />
|-<br />
| 0x0045....<br />
| ?<br />
|-<br />
| 0x0046....<br />
| ?<br />
|-<br />
| 0x0047....<br />
| ?<br />
|-<br />
| 0x0048....<br />
| ?<br />
|-<br />
| 0x0049....<br />
| ?<br />
|-<br />
| 0x004A....<br />
| ?<br />
|-<br />
| 0x004B....<br />
| ?<br />
|-<br />
| 0x004C....<br />
| ?<br />
|-<br />
| 0x004D....<br />
| [[MCURTC:ReadHidFlagRegister|ReadHidFlagRegister]] (reads i2c MCU device, reg 0x10)<br />
|-<br />
| 0x004E0040<br />
| [[MCURTC:PublishNotifications|PublishNotifications]]<br />
|-<br />
| 0x004F....<br />
| Sets some flag (otherwise set when uploading MCU firmware)<br />
|-<br />
| 0x0050....<br />
| Returns the above flag<br />
|-<br />
| 0x00510040<br />
| [[MCURTC:SetSoftwareClosedFlag|SetSoftwareClosedFlag]]<br />
|-<br />
| 0x00520000<br />
| [[MCURTC:GetSoftwareClosedFlag|GetSoftwareClosedFlag]]<br />
|-<br />
| 0x0053....<br />
| ?<br />
|-<br />
| 0x0054....<br />
| ?<br />
|-<br />
| 0x0055....<br />
| ?<br />
|-<br />
| 0x0056....<br />
| ?<br />
|-<br />
| 0x0057....<br />
| ?<br />
|-<br />
| 0x0058....<br />
| ?<br />
|-<br />
| 0x00590040<br />
| [[MCURTC:SetLegacyJumpProhibitedFlag|SetLegacyJumpProhibitedFlag]]<br />
|-<br />
| 0x005A0000<br />
| [[MCURTC:GetLegacyJumpProhibitedFlag|GetLegacyJumpProhibitedFlag]]<br />
|}<br />
<br />
Note that using invalid input with these InfoLED/SetBatteryEmptyLEDPattern commands(especially SetInfoLEDPattern) can cause the system to be bricked(however the boot failure may not begin immediately after using the invalid parameters).<br />
<br />
=MCU sound service "mcu::SND"=<br />
{| class="wikitable" border="1"<br />
|-<br />
! Command Header<br />
! Description<br />
|-<br />
| 0x0001....<br />
| GetSoundVolume<br />
|-<br />
| 0x0002....<br />
| ?<br />
|-<br />
| 0x0003....<br />
| ?<br />
|}<br />
<br />
=MCU wifi service "mcu::NWM"=<br />
{| class="wikitable" border="1"<br />
|-<br />
! Command Header<br />
! Description<br />
|-<br />
| 0x0001....<br />
| SetWirelessLedState<br />
|-<br />
| 0x0002....<br />
| GetWirelessLedState<br />
|-<br />
| 0x0003....<br />
| Sets GPIO 0x20 high/low?<br />
|-<br />
| 0x0004....<br />
| Gets GPIO 0x20 high/low?<br />
|-<br />
| 0x0005....<br />
| SetEnableWifiGpio<br />
|-<br />
| 0x0006....<br />
| GetEnableWifiGpio<br />
|-<br />
| 0x0007....<br />
| [[MCUNWM:SetWirelessDisabledFlag|SetWirelessDisabledFlag]]<br />
|-<br />
| 0x0008....<br />
| [[MCUNWM:GetWirelessDisabledFlag|GetWirelessDisabledFlag]]<br />
|}<br />
<br />
=MCU service "mcu::HWC"=<br />
{| class="wikitable" border="1"<br />
|-<br />
! Command Header<br />
! Description<br />
|-<br />
| 0x00010082<br />
| [[MCUHWC:ReadRegister|ReadRegister]]<br />
|-<br />
| 0x00020082<br />
| [[MCUHWC:WriteRegister|WriteRegister]]<br />
|-<br />
| 0x00030042<br />
| [[MCUHWC:GetInfoRegisters|GetInfoRegisters]]<br />
|-<br />
| 0x00040000<br />
| [[MCUHWC:GetBatteryVoltage|GetBatteryVoltage]]<br />
|-<br />
| 0x00050000<br />
| [[MCUHWC:GetBatteryLevel|GetBatteryLevel]]<br />
|-<br />
| 0x00060040<br />
| [[MCUHWC:SetPowerLEDPattern|SetPowerLEDPattern]]<br />
|-<br />
| 0x00070040<br />
| [[MCUHWC:SetWifiLEDState|SetWifiLEDState]]<br />
|-<br />
| 0x00080040<br />
| [[MCUHWC:SetCameraLEDPattern|SetCameraLEDPattern]]<br />
|-<br />
| 0x00090040<br />
| [[MCUHWC:Set3DLEDState|Set3DLEDState]]<br />
|-<br />
| 0x000A0640<br />
| This is the same as [[MCURTC:SetInfoLEDPattern]].<br />
|-<br />
| 0x000B0000<br />
| [[MCUHWC:GetSoundVolume|GetSoundVolume]]<br />
|-<br />
| 0x000C....<br />
| ?<br />
|-<br />
| 0x000D....<br />
| ?<br />
|-<br />
| 0x000E....<br />
| ?<br />
|-<br />
| 0x000F....<br />
| GetRtcTime<br />
|-<br />
| 0x00100000<br />
| GetMcuFwVerHigh<br />
|-<br />
| 0x00110000<br />
| GetMcuFwVerLow<br />
|}<br />
<br />
=MCU service "mcu::PLS"=<br />
<br />
RTC-related? Each of these seems to retrieve a second counter from a different RTC register.<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Command Header<br />
! Description<br />
|-<br />
| 0x0001....<br />
| ?<br />
|-<br />
| 0x0002....<br />
| ?<br />
|-<br />
| 0x0003....<br />
| ?<br />
|-<br />
| 0x0004....<br />
| ?<br />
|-<br />
| 0x0005....<br />
| ?<br />
|-<br />
| 0x0006....<br />
| ?<br />
|-<br />
| 0x0007....<br />
| ?<br />
|-<br />
| 0x0008....<br />
| ?<br />
|-<br />
| 0x0009....<br />
| ?<br />
|}<br />
<br />
=MCU codec service "mcu::CDC"=<br />
{| class="wikitable" border="1"<br />
|-<br />
! Command Header<br />
! Description<br />
|-<br />
| 0x00010000<br />
| ?<br />
|}<br />
<br />
=New3DS=<br />
The Old3DS/New3DS MCU sysmodules are identical except that the MCU firmware binary written via I2C is different. The size of that binary is the same. The only different words in .text are for the version of that MCU fw binary.<br />
<br />
=MCU firmware versions=<br />
<br />
These reside in mcu-module .rodata, are uploaded to MCU register 0x05 and are usually size 0x4003 bytes. (0x4000 bytes with 3 byte magic "jhl"?)<br />
<br />
There exists an alternate code path where uploading is done using register 0x3B (decided by making some nonsense conclusions about registers 0x0F and 0x10). This may be a "hack" around early versions of MCU? Register 0x3B is RTC-related on recent versions of MCU, and the "nonsense" condition is not met even on factory MCU firmware.<br />
<br />
On dev-units, the user-facing representation of this firmware version is displayed by first subtracting 0x10 from the major field (raw register 0x00). It is these user-facing versions that are displayed in the table below. It is unknown what bit4 (0x10) actually represents, but it is seemingly always set.<br />
<br />
{| class="wikitable" border="1"<br />
|-<br />
! Title version<br />
! Firmware<br />
|-<br />
| New3DS v8192/safe v9217 (latest)<br />
| 3.56<br />
|-<br />
| Old3DS v6145 to v8192 (latest)<br />
| 2.37<br />
|-<br />
| Old3DS v5122<br />
| 2.35<br />
|-<br />
| Old3DS v4102<br />
| 2.30<br />
|-<br />
| Old3DS v3072<br />
| 2.16<br />
|-<br />
| Old3DS v2048<br />
| 1.52<br />
|-<br />
| Old3DS v1026<br />
| 1.51<br />
|-<br />
| Old3DS v0/safe v0<br />
| 1.20<br />
|-<br />
| Old3DS factory<br />
| 1.07<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG11_Registers&diff=19543
CONFIG11 Registers
2017-02-07T23:10:19Z
<p>Plutooo: /* CFG11_GPUPROT */</p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7><br />
| 0x10140000<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7><br />
| 0x10140008<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140100<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140102<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_FIQ_CNT|CFG11_FIQ_CNT]]<br />
| 0x10140104<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140105<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x10140108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x1014010C<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPUPROT|CFG11_GPUPROT]]<br />
| 0x10140140<br />
| 4<br />
| Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_WIFI_CNT|CFG11_WIFI_CNT]]<br />
| 0x10140180<br />
| 1<br />
| TwlBg, [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]<br />
| 0x101401C0<br />
| 4<br />
| [[SPI Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140200<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140400<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140410<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]<br />
| 0x10140420<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]<br />
| 0x10140424<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| ?<br />
| 0x10140428<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]<br />
| 0x10140FFC<br />
| 2<br />
| Boot11, Kernel11<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| CFG11_GPU_STATUS?<br />
| 0x10141000<br />
| 4<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_0<br />
| 0x10141008<br />
| 4<br />
| [[PTM Services]], [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_1<br />
| 0x1014100C<br />
| 4<br />
| [[PTM Services]], TwlBg, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_0|CFG11_TWLMODE_0]]<br />
| 0x10141100<br />
| 2<br />
| TwlProcess9, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_1|CFG11_TWLMODE_1]]<br />
| 0x10141104<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_2|CFG11_TWLMODE_2]]<br />
| 0x10141108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_HID|CFG11_TWLMODE_HID]]<br />
| 0x1014110A<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_WIFI?<br />
| 0x1014110C<br />
| 1<br />
| [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141110<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141112<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_0]]<br />
| 0x10141114<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_1]]<br />
| 0x10141116<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141118<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141119<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141120<br />
| 1<br />
| TwlBg<br />
|-<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT|CFG11_GPU_CNT]]<br />
| 0x10141200<br />
| 4<br />
| Boot11, Kernel11, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT2|CFG11_GPU_CNT2]]<br />
| 0x10141204<br />
| 4<br />
| Boot11, Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_GPU_CNT3<br />
| 0x10141210<br />
| 2<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC_CNT|CFG11_CODEC_CNT]]<br />
| 0x10141220<br />
| 1<br />
| Boot11, TwlBg, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]]<br />
| 0x10141224<br />
| 1<br />
| [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_DSP_CNT<br />
| 0x10141230<br />
| 1<br />
| Process9, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CLKCNT|CFG11_MPCORE_CLKCNT]]<br />
| 0x10141300<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CNT|CFG11_MPCORE_CNT]]<br />
| 0x10141304<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_BOOTCNT<0-3>|CFG11_MPCORE_BOOTCNT]]<0-3><br />
| 0x10141310<br />
| 1*4<br />
| NewKernel11<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_DATA ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_CODE ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_FIQ_CNT ==<br />
Writing bit1 to this register disables FIQ interrupts.<br />
<br />
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.<br />
It is cleared when binding that software interrupt to an event and just before that event is signaled.<br />
<br />
== CFG11_SPI_CNT ==<br />
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Enable [[SPI Registers]] 0x10160000.<br />
|-<br />
| 1<br />
| Enable [[SPI Registers]] 0x10142000.<br />
|-<br />
| 2<br />
| Enable [[SPI Registers]] 0x10143000.<br />
|}<br />
<br />
== CFG11_BOOTROM_OVERLAY_CNT ==<br />
Bit0: Enable bootrom overlay functionality.<br />
<br />
== CFG11_BOOTROM_OVERLAY_VAL ==<br />
The 32-bit value to overlay data-reads to bootrom with. See [[#CFG11_MPCORE_BOOTCNT|CFG11_MPCORE_BOOTCNT]].<br />
<br />
== CFG11_SOCINFO ==<br />
Read-only register.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| 1 on both Old3DS and New3DS.<br />
| Boot11<br />
|-<br />
| 1<br />
| 1 on New3DS.<br />
| Kernel11<br />
|-<br />
| 2<br />
| Clock modifier: if set, use a 3x multiplier, otherwise 2x<br />
| Kernel11<br />
|}<br />
<br />
== CFG11_MPCORE_CLKCNT ==<br />
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.<br />
|-<br />
| 1-2<br />
| Clock multiplier (0=1x, 1=2x, 2=3x, 3=hang)<br />
|-<br />
| 15<br />
| Busy<br />
|}<br />
<br />
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG:<br />
{| class="wikitable" border="1"<br />
! Register value<br />
! Higher-clockrate bit set in svcKernelSetState Param0<br />
! CFG11_MPCORE_CFG bit2 set<br />
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state<br />
! Clock-rate multiplier<br />
! Description<br />
|-<br />
| 0x01<br />
| No<br />
| Yes<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x02<br />
| No<br />
| No<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x05<br />
| Yes<br />
| Yes<br />
| 0x03<br />
| 3x<br />
| 804MHz<br />
|-<br />
| 0x03<br />
| Yes<br />
| No<br />
| 0x02<br />
| 2x<br />
| 536MHz (tested on New3DS)<br />
|}<br />
<br />
Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).<br />
<br />
The following register value(s) were tested on New3DS by patching the kernel:<br />
* 0x00: Entire system hangs.<br />
* 0x02: Entire system hangs.<br />
* 0x03: ARM11 runs at 536MHz.<br />
* 0x04: Entire system hangs.<br />
* 0x06: Entire system hangs.<br />
* 0x07: Same result as 0x05.<br />
* 0x08: Entire system hangs.<br />
* 0x09: Entire system hangs.<br />
* 0x0A: Entire system hangs.<br />
* 0x0B: Same result as 0x03.<br />
* 0x0C: Entire system hangs.<br />
* 0x0D: Same result as 0x05.<br />
* 0x0E: Entire system hangs.<br />
* 0x0F: Same result as 0x05.<br />
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.<br />
<br />
== CFG11_MPCORE_CNT ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Power on 3rd ARM11 MPCore maybe?<br />
|-<br />
| 8<br />
| Power on 4th ARM11 MPCore maybe?<br />
|}<br />
<br />
== CFG11_MPCORE_BOOTCNT<0-3> ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable bootrom instruction overlay, maybe? This bit is only writable for core2 and core3.<br />
|-<br />
| 1<br />
| Enable bootrom data overlay. This bit is only writable for core2 and core3.<br />
|-<br />
| 4<br />
| Has core booted maybe?<br />
|-<br />
| 5<br />
| Always 1?<br />
|}<br />
<br />
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.<br />
<br />
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].<br />
<br />
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:<br />
ldr pc, [pc]<br />
<br />
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.<br />
<br />
==CFG11_GPUPROT==<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Bits<br />
! Description<br />
|-<br />
| style="background: green" | Yes<br />
| 3-0<br />
| Old FCRAM DMA cutoff size, 0 = no protection.<br />
|-<br />
| style="background: red" | No<br />
| 7-4<br />
| New FCRAM DMA cutoff size, 0 = no protection.<br />
|-<br />
| style="background: green" | Yes<br />
| 8<br />
| AXIWRAM protection, 0 = accessible.<br />
|-<br />
| style="background: red" | No<br />
| 10-9<br />
| QTM DMA cutoff size<br />
|-<br />
| style="background: green" | Yes<br />
| 31-11<br />
| Zeroes<br />
|}<br />
<br />
For the old FCRAM DMA cutoff, it protects starting from 0x28000000-(0x800000*x) until end of FCRAM. There is no way to protect the first 0x800000-bytes.<br />
<br />
For the new FCRAM DMA cutoff, it protects starting from 0x30000000-(0x800000*x) until end of FCRAM. When the old FCRAM cutoff is set to non-zero, the first 0x800000-bytes bytes of new FCRAM are protected.<br />
<br />
On New3DS the old+new FCRAM cutoff can be used at the same time, however this isn't done officially.<br />
<br />
For the QTM DMA cutoff, it protects starting from 0x1F400000-(0x100000*x) until end of QTM mem.<br />
<br />
On cold boot this reg is set to 0.<br />
<br />
When this register is set to value 0, the GPU can access the entire FCRAM, AXIWRAM, and on New3DS all QTM-mem.<br />
<br />
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with [[11.3.0-36|v11.3]].<br />
<br />
==CFG11_WIFI_CNT==<br />
Bit0: Enable wifi.<br />
<br />
==CFG11_TWLMODE_0==<br />
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.<br />
<br />
This address is poked from ARM7 to signal that it has booted and begun executing code. The ARM7-mode address for this register is 0x4700000.<br />
<br />
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.<br />
<br />
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.<br />
<br />
==CFG11_TWLMODE_1==<br />
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.<br />
<br />
==CFG11_TWLMODE_2==<br />
Bitfield.<br />
<br />
==CFG11_TWLMODE_HID==<br />
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.<br />
<br />
==CFG11_WIFI?==<br />
Bit4=unknown enabled by NWM on launch. Potentially powers on wifi card.<br />
<br />
==CFG11_GPU_CNT==<br />
This one seems to control the LCD/GPU/Backlight.<br />
<br />
Bit0: Enable GPU registers at 0x10400000+.<br />
Bit16: Turn on LCD backlight.<br />
<br />
==CFG11_GPU_CNT2==<br />
Bit0: Power on GPU?<br />
<br />
==CFG11_GPU_CNT3==<br />
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.<br />
<br />
==CFG11_CODEC==<br />
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.<br />
<br />
==CFG11_CODEC_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] CODEC service.<br />
<br />
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.<br />
<br />
==CFG11_CAMERA_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] camera service.<br />
<br />
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG11_Registers&diff=19531
CONFIG11 Registers
2017-02-07T18:28:10Z
<p>Plutooo: /* CFG11_GPUPROT */</p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7><br />
| 0x10140000<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7><br />
| 0x10140008<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140100<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140102<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_FIQ_CNT|CFG11_FIQ_CNT]]<br />
| 0x10140104<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140105<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x10140108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x1014010C<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPUPROT|CFG11_GPUPROT]]<br />
| 0x10140140<br />
| 4<br />
| Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_WIFI_CNT|CFG11_WIFI_CNT]]<br />
| 0x10140180<br />
| 1<br />
| TwlBg, [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]<br />
| 0x101401C0<br />
| 4<br />
| [[SPI Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140200<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140400<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140410<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]<br />
| 0x10140420<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]<br />
| 0x10140424<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| ?<br />
| 0x10140428<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]<br />
| 0x10140FFC<br />
| 2<br />
| Boot11, Kernel11<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| CFG11_GPU_STATUS?<br />
| 0x10141000<br />
| 4<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_0<br />
| 0x10141008<br />
| 4<br />
| [[PTM Services]], [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_1<br />
| 0x1014100C<br />
| 4<br />
| [[PTM Services]], TwlBg, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_0|CFG11_TWLMODE_0]]<br />
| 0x10141100<br />
| 2<br />
| TwlProcess9, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_1|CFG11_TWLMODE_1]]<br />
| 0x10141104<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_2|CFG11_TWLMODE_2]]<br />
| 0x10141108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_HID|CFG11_TWLMODE_HID]]<br />
| 0x1014110A<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_WIFI?<br />
| 0x1014110C<br />
| 1<br />
| [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141110<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141112<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_0]]<br />
| 0x10141114<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_1]]<br />
| 0x10141116<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141118<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141119<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141120<br />
| 1<br />
| TwlBg<br />
|-<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT|CFG11_GPU_CNT]]<br />
| 0x10141200<br />
| 4<br />
| Boot11, Kernel11, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT2|CFG11_GPU_CNT2]]<br />
| 0x10141204<br />
| 4<br />
| Boot11, Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_GPU_CNT3<br />
| 0x10141210<br />
| 2<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC_CNT|CFG11_CODEC_CNT]]<br />
| 0x10141220<br />
| 1<br />
| Boot11, TwlBg, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]]<br />
| 0x10141224<br />
| 1<br />
| [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_DSP_CNT<br />
| 0x10141230<br />
| 1<br />
| Process9, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CLKCNT|CFG11_MPCORE_CLKCNT]]<br />
| 0x10141300<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CNT|CFG11_MPCORE_CNT]]<br />
| 0x10141304<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_BOOTCNT<0-3>|CFG11_MPCORE_BOOTCNT]]<0-3><br />
| 0x10141310<br />
| 1*4<br />
| NewKernel11<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_DATA ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_CODE ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_FIQ_CNT ==<br />
Writing bit1 to this register disables FIQ interrupts.<br />
<br />
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.<br />
It is cleared when binding that software interrupt to an event and just before that event is signaled.<br />
<br />
== CFG11_SPI_CNT ==<br />
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Enable [[SPI Registers]] 0x10160000.<br />
|-<br />
| 1<br />
| Enable [[SPI Registers]] 0x10142000.<br />
|-<br />
| 2<br />
| Enable [[SPI Registers]] 0x10143000.<br />
|}<br />
<br />
== CFG11_BOOTROM_OVERLAY_CNT ==<br />
Bit0: Enable bootrom overlay functionality.<br />
<br />
== CFG11_BOOTROM_OVERLAY_VAL ==<br />
The 32-bit value to overlay data-reads to bootrom with. See [[#CFG11_MPCORE_BOOTCNT|CFG11_MPCORE_BOOTCNT]].<br />
<br />
== CFG11_SOCINFO ==<br />
Read-only register.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| 1 on both Old3DS and New3DS.<br />
| Boot11<br />
|-<br />
| 1<br />
| 1 on New3DS.<br />
| Kernel11<br />
|-<br />
| 2<br />
| Clock modifier: if set, use a 3x multiplier, otherwise 2x<br />
| Kernel11<br />
|}<br />
<br />
== CFG11_MPCORE_CLKCNT ==<br />
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.<br />
|-<br />
| 1-2<br />
| Clock multiplier (0=1x, 1=2x, 2=3x, 3=hang)<br />
|-<br />
| 15<br />
| Busy<br />
|}<br />
<br />
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG:<br />
{| class="wikitable" border="1"<br />
! Register value<br />
! Higher-clockrate bit set in svcKernelSetState Param0<br />
! CFG11_MPCORE_CFG bit2 set<br />
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state<br />
! Clock-rate multiplier<br />
! Description<br />
|-<br />
| 0x01<br />
| No<br />
| Yes<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x02<br />
| No<br />
| No<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x05<br />
| Yes<br />
| Yes<br />
| 0x03<br />
| 3x<br />
| 804MHz<br />
|-<br />
| 0x03<br />
| Yes<br />
| No<br />
| 0x02<br />
| 2x<br />
| 536MHz (tested on New3DS)<br />
|}<br />
<br />
Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).<br />
<br />
The following register value(s) were tested on New3DS by patching the kernel:<br />
* 0x00: Entire system hangs.<br />
* 0x02: Entire system hangs.<br />
* 0x03: ARM11 runs at 536MHz.<br />
* 0x04: Entire system hangs.<br />
* 0x06: Entire system hangs.<br />
* 0x07: Same result as 0x05.<br />
* 0x08: Entire system hangs.<br />
* 0x09: Entire system hangs.<br />
* 0x0A: Entire system hangs.<br />
* 0x0B: Same result as 0x03.<br />
* 0x0C: Entire system hangs.<br />
* 0x0D: Same result as 0x05.<br />
* 0x0E: Entire system hangs.<br />
* 0x0F: Same result as 0x05.<br />
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.<br />
<br />
== CFG11_MPCORE_CNT ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Power on 3rd ARM11 MPCore maybe?<br />
|-<br />
| 8<br />
| Power on 4th ARM11 MPCore maybe?<br />
|}<br />
<br />
== CFG11_MPCORE_BOOTCNT<0-3> ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable bootrom instruction overlay, maybe? This bit is only writable for core2 and core3.<br />
|-<br />
| 1<br />
| Enable bootrom data overlay. This bit is only writable for core2 and core3.<br />
|-<br />
| 4<br />
| Has core booted maybe?<br />
|-<br />
| 5<br />
| Always 1?<br />
|}<br />
<br />
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.<br />
<br />
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].<br />
<br />
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:<br />
ldr pc, [pc]<br />
<br />
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.<br />
<br />
==CFG11_GPUPROT==<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Bits<br />
! Description<br />
|-<br />
| style="background: green" | Yes<br />
| 3-0<br />
| Old FCRAM DMA cutoff size<br />
|-<br />
| style="background: red" | No<br />
| 7-4<br />
| New FCRAM DMA cutoff size<br />
|-<br />
| style="background: green" | Yes<br />
| 8<br />
| AXIWRAM protection, 0 = accessible.<br />
|-<br />
| style="background: red" | No<br />
| 10-9<br />
| QTM DMA cutoff size<br />
|-<br />
| style="background: green" | Yes<br />
| 31-11<br />
| Zeroes<br />
|}<br />
<br />
For the old FCRAM DMA cutoff, it appears to start at 0x28000000-(0x800000*x) length 0x800000*x.<br />
<br />
For the new FCRAM DMA cutoff, it appears to start at 0x30000000-(0x800000*x) length 0x800000*x.<br />
<br />
For the QTM DMA cutoff, it appears to start at 0x1F400000-(0x100000*x) length 0x100000*x<br />
<br />
On cold boot this reg is set to 0.<br />
<br />
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with [[11.3.0-36|v11.3]].<br />
<br />
==CFG11_WIFI_CNT==<br />
Bit0: Enable wifi.<br />
<br />
==CFG11_TWLMODE_0==<br />
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.<br />
<br />
This address is poked from ARM7 to signal that it has booted and begun executing code. The ARM7-mode address for this register is 0x4700000.<br />
<br />
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.<br />
<br />
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.<br />
<br />
==CFG11_TWLMODE_1==<br />
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.<br />
<br />
==CFG11_TWLMODE_2==<br />
Bitfield.<br />
<br />
==CFG11_TWLMODE_HID==<br />
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.<br />
<br />
==CFG11_WIFI?==<br />
Bit4=unknown enabled by NWM on launch. Potentially powers on wifi card.<br />
<br />
==CFG11_GPU_CNT==<br />
This one seems to control the LCD/GPU/Backlight.<br />
<br />
Bit0: Enable GPU registers at 0x10400000+.<br />
Bit16: Turn on LCD backlight.<br />
<br />
==CFG11_GPU_CNT2==<br />
Bit0: Power on GPU?<br />
<br />
==CFG11_GPU_CNT3==<br />
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.<br />
<br />
==CFG11_CODEC==<br />
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.<br />
<br />
==CFG11_CODEC_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] CODEC service.<br />
<br />
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.<br />
<br />
==CFG11_CAMERA_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] camera service.<br />
<br />
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG11_Registers&diff=19528
CONFIG11 Registers
2017-02-07T18:08:12Z
<p>Plutooo: </p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7><br />
| 0x10140000<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7><br />
| 0x10140008<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140100<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140102<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_FIQ_CNT|CFG11_FIQ_CNT]]<br />
| 0x10140104<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140105<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x10140108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x1014010C<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPUPROT|CFG11_GPUPROT]]<br />
| 0x10140140<br />
| 4<br />
| Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_WIFI_CNT|CFG11_WIFI_CNT]]<br />
| 0x10140180<br />
| 1<br />
| TwlBg, [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]<br />
| 0x101401C0<br />
| 4<br />
| [[SPI Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140200<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140400<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140410<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]<br />
| 0x10140420<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]<br />
| 0x10140424<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| ?<br />
| 0x10140428<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]<br />
| 0x10140FFC<br />
| 2<br />
| Boot11, Kernel11<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| CFG11_GPU_STATUS?<br />
| 0x10141000<br />
| 4<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_0<br />
| 0x10141008<br />
| 4<br />
| [[PTM Services]], [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_1<br />
| 0x1014100C<br />
| 4<br />
| [[PTM Services]], TwlBg, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_0|CFG11_TWLMODE_0]]<br />
| 0x10141100<br />
| 2<br />
| TwlProcess9, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_1|CFG11_TWLMODE_1]]<br />
| 0x10141104<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_2|CFG11_TWLMODE_2]]<br />
| 0x10141108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_HID|CFG11_TWLMODE_HID]]<br />
| 0x1014110A<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_WIFI?<br />
| 0x1014110C<br />
| 1<br />
| [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141110<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141112<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_0]]<br />
| 0x10141114<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_1]]<br />
| 0x10141116<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141118<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141119<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141120<br />
| 1<br />
| TwlBg<br />
|-<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT|CFG11_GPU_CNT]]<br />
| 0x10141200<br />
| 4<br />
| Boot11, Kernel11, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT2|CFG11_GPU_CNT2]]<br />
| 0x10141204<br />
| 4<br />
| Boot11, Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_GPU_CNT3<br />
| 0x10141210<br />
| 2<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC_CNT|CFG11_CODEC_CNT]]<br />
| 0x10141220<br />
| 1<br />
| Boot11, TwlBg, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]]<br />
| 0x10141224<br />
| 1<br />
| [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_DSP_CNT<br />
| 0x10141230<br />
| 1<br />
| Process9, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CLKCNT|CFG11_MPCORE_CLKCNT]]<br />
| 0x10141300<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CNT|CFG11_MPCORE_CNT]]<br />
| 0x10141304<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_BOOTCNT<0-3>|CFG11_MPCORE_BOOTCNT]]<0-3><br />
| 0x10141310<br />
| 1*4<br />
| NewKernel11<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_DATA ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_CODE ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_FIQ_CNT ==<br />
Writing bit1 to this register disables FIQ interrupts.<br />
<br />
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.<br />
It is cleared when binding that software interrupt to an event and just before that event is signaled.<br />
<br />
== CFG11_SPI_CNT ==<br />
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Enable [[SPI Registers]] 0x10160000.<br />
|-<br />
| 1<br />
| Enable [[SPI Registers]] 0x10142000.<br />
|-<br />
| 2<br />
| Enable [[SPI Registers]] 0x10143000.<br />
|}<br />
<br />
== CFG11_BOOTROM_OVERLAY_CNT ==<br />
Bit0: Enable bootrom overlay functionality.<br />
<br />
== CFG11_BOOTROM_OVERLAY_VAL ==<br />
The 32-bit value to overlay data-reads to bootrom with. See [[#CFG11_MPCORE_BOOTCNT|CFG11_MPCORE_BOOTCNT]].<br />
<br />
== CFG11_SOCINFO ==<br />
Read-only register.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| 1 on both Old3DS and New3DS.<br />
| Boot11<br />
|-<br />
| 1<br />
| 1 on New3DS.<br />
| Kernel11<br />
|-<br />
| 2<br />
| Clock modifier: if set, use a 3x multiplier, otherwise 2x<br />
| Kernel11<br />
|}<br />
<br />
== CFG11_MPCORE_CLKCNT ==<br />
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.<br />
|-<br />
| 1-2<br />
| Clock multiplier (0=1x, 1=2x, 2=3x, 3=hang)<br />
|-<br />
| 15<br />
| Busy<br />
|}<br />
<br />
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG:<br />
{| class="wikitable" border="1"<br />
! Register value<br />
! Higher-clockrate bit set in svcKernelSetState Param0<br />
! CFG11_MPCORE_CFG bit2 set<br />
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state<br />
! Clock-rate multiplier<br />
! Description<br />
|-<br />
| 0x01<br />
| No<br />
| Yes<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x02<br />
| No<br />
| No<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x05<br />
| Yes<br />
| Yes<br />
| 0x03<br />
| 3x<br />
| 804MHz<br />
|-<br />
| 0x03<br />
| Yes<br />
| No<br />
| 0x02<br />
| 2x<br />
| 536MHz (tested on New3DS)<br />
|}<br />
<br />
Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).<br />
<br />
The following register value(s) were tested on New3DS by patching the kernel:<br />
* 0x00: Entire system hangs.<br />
* 0x02: Entire system hangs.<br />
* 0x03: ARM11 runs at 536MHz.<br />
* 0x04: Entire system hangs.<br />
* 0x06: Entire system hangs.<br />
* 0x07: Same result as 0x05.<br />
* 0x08: Entire system hangs.<br />
* 0x09: Entire system hangs.<br />
* 0x0A: Entire system hangs.<br />
* 0x0B: Same result as 0x03.<br />
* 0x0C: Entire system hangs.<br />
* 0x0D: Same result as 0x05.<br />
* 0x0E: Entire system hangs.<br />
* 0x0F: Same result as 0x05.<br />
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.<br />
<br />
== CFG11_MPCORE_CNT ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Power on 3rd ARM11 MPCore maybe?<br />
|-<br />
| 8<br />
| Power on 4th ARM11 MPCore maybe?<br />
|}<br />
<br />
== CFG11_MPCORE_BOOTCNT<0-3> ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable bootrom instruction overlay, maybe? This bit is only writable for core2 and core3.<br />
|-<br />
| 1<br />
| Enable bootrom data overlay. This bit is only writable for core2 and core3.<br />
|-<br />
| 4<br />
| Has core booted maybe?<br />
|-<br />
| 5<br />
| Always 1?<br />
|}<br />
<br />
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.<br />
<br />
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].<br />
<br />
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:<br />
ldr pc, [pc]<br />
<br />
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.<br />
<br />
==CFG11_GPUPROT==<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Bits<br />
! Description<br />
|-<br />
| style="background: green" | Yes<br />
| 3-0<br />
| Old FCRAM DMA cutoff size<br />
|-<br />
| style="background: red" | No<br />
| 7-4<br />
| New FCRAM DMA cutoff size<br />
|-<br />
| style="background: green" | Yes<br />
| 8<br />
| ?!?!?!<br />
|-<br />
| style="background: red" | No<br />
| 10-9<br />
| QTM DMA cutoff size<br />
|-<br />
| style="background: green" | Yes<br />
| 31-11<br />
| Zeroes<br />
|}<br />
<br />
For the old FCRAM DMA cutoff, it appears to start at 0x28000000-(0x800000*x) length 0x800000*x.<br />
<br />
For the new FCRAM DMA cutoff, it appears to start at 0x30000000-(0x800000*x) length 0x800000*x.<br />
<br />
For the QTM DMA cutoff, it appears to start at 0x1F400000-(0x100000*x) length 0x100000*x<br />
<br />
On cold boot this reg is set to 0.<br />
<br />
Seems to control what memory GPU can access for DMA, this needs verified.<br />
<br />
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with v11.3.<br />
<br />
==CFG11_WIFI_CNT==<br />
Bit0: Enable wifi.<br />
<br />
==CFG11_TWLMODE_0==<br />
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.<br />
<br />
This address is poked from ARM7 to signal that it has booted and begun executing code. The ARM7-mode address for this register is 0x4700000.<br />
<br />
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.<br />
<br />
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.<br />
<br />
==CFG11_TWLMODE_1==<br />
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.<br />
<br />
==CFG11_TWLMODE_2==<br />
Bitfield.<br />
<br />
==CFG11_TWLMODE_HID==<br />
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.<br />
<br />
==CFG11_WIFI?==<br />
Bit4=unknown enabled by NWM on launch. Potentially powers on wifi card.<br />
<br />
==CFG11_GPU_CNT==<br />
This one seems to control the LCD/GPU/Backlight.<br />
<br />
Bit0: Enable GPU registers at 0x10400000+.<br />
Bit16: Turn on LCD backlight.<br />
<br />
==CFG11_GPU_CNT2==<br />
Bit0: Power on GPU?<br />
<br />
==CFG11_GPU_CNT3==<br />
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.<br />
<br />
==CFG11_CODEC==<br />
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.<br />
<br />
==CFG11_CODEC_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] CODEC service.<br />
<br />
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.<br />
<br />
==CFG11_CAMERA_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] camera service.<br />
<br />
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG11_Registers&diff=19526
CONFIG11 Registers
2017-02-07T17:56:26Z
<p>Plutooo: yellows8</p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7><br />
| 0x10140000<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7><br />
| 0x10140008<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140100<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140102<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_FIQ_CNT|CFG11_FIQ_CNT]]<br />
| 0x10140104<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140105<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x10140108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x1014010C<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPUPROT|CFG11_GPUPROT]]<br />
| 0x10140140<br />
| 4<br />
| Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_WIFI_CNT|CFG11_WIFI_CNT]]<br />
| 0x10140180<br />
| 1<br />
| TwlBg, [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]<br />
| 0x101401C0<br />
| 4<br />
| [[SPI Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140200<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140400<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140410<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]<br />
| 0x10140420<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]<br />
| 0x10140424<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| ?<br />
| 0x10140428<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]<br />
| 0x10140FFC<br />
| 2<br />
| Boot11, Kernel11<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| CFG11_GPU_STATUS?<br />
| 0x10141000<br />
| 4<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_0<br />
| 0x10141008<br />
| 4<br />
| [[PTM Services]], [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_1<br />
| 0x1014100C<br />
| 4<br />
| [[PTM Services]], TwlBg, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_0|CFG11_TWLMODE_0]]<br />
| 0x10141100<br />
| 2<br />
| TwlProcess9, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_1|CFG11_TWLMODE_1]]<br />
| 0x10141104<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_2|CFG11_TWLMODE_2]]<br />
| 0x10141108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_HID|CFG11_TWLMODE_HID]]<br />
| 0x1014110A<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_WIFI?<br />
| 0x1014110C<br />
| 1<br />
| [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141110<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141112<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_0]]<br />
| 0x10141114<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_1]]<br />
| 0x10141116<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141118<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141119<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141120<br />
| 1<br />
| TwlBg<br />
|-<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT|CFG11_GPU_CNT]]<br />
| 0x10141200<br />
| 4<br />
| Boot11, Kernel11, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT2|CFG11_GPU_CNT2]]<br />
| 0x10141204<br />
| 4<br />
| Boot11, Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_GPU_CNT3<br />
| 0x10141210<br />
| 2<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC_CNT|CFG11_CODEC_CNT]]<br />
| 0x10141220<br />
| 1<br />
| Boot11, TwlBg, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]]<br />
| 0x10141224<br />
| 1<br />
| [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_DSP_CNT<br />
| 0x10141230<br />
| 1<br />
| Process9, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CLKCNT|CFG11_MPCORE_CLKCNT]]<br />
| 0x10141300<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CNT|CFG11_MPCORE_CNT]]<br />
| 0x10141304<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_BOOTCNT<0-3>|CFG11_MPCORE_BOOTCNT]]<0-3><br />
| 0x10141310<br />
| 1*4<br />
| NewKernel11<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_DATA ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_CODE ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_FIQ_CNT ==<br />
Writing bit1 to this register disables FIQ interrupts.<br />
<br />
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.<br />
It is cleared when binding that software interrupt to an event and just before that event is signaled.<br />
<br />
== CFG11_SPI_CNT ==<br />
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Enable [[SPI Registers]] 0x10160000.<br />
|-<br />
| 1<br />
| Enable [[SPI Registers]] 0x10142000.<br />
|-<br />
| 2<br />
| Enable [[SPI Registers]] 0x10143000.<br />
|}<br />
<br />
== CFG11_BOOTROM_OVERLAY_CNT ==<br />
Bit0: Enable bootrom overlay functionality.<br />
<br />
== CFG11_BOOTROM_OVERLAY_VAL ==<br />
The 32-bit value to overlay data-reads to bootrom with. See [[#CFG11_MPCORE_BOOTCNT|CFG11_MPCORE_BOOTCNT]].<br />
<br />
== CFG11_SOCINFO ==<br />
Read-only register.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| 1 on both Old3DS and New3DS.<br />
| Boot11<br />
|-<br />
| 1<br />
| 1 on New3DS.<br />
| Kernel11<br />
|-<br />
| 2<br />
| Clock modifier: if set, use a 3x multiplier, otherwise 2x<br />
| Kernel11<br />
|}<br />
<br />
== CFG11_MPCORE_CLKCNT ==<br />
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.<br />
|-<br />
| 1-2<br />
| Clock multiplier (0=1x, 1=2x, 2=3x, 3=hang)<br />
|-<br />
| 15<br />
| Busy<br />
|}<br />
<br />
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG:<br />
{| class="wikitable" border="1"<br />
! Register value<br />
! Higher-clockrate bit set in svcKernelSetState Param0<br />
! CFG11_MPCORE_CFG bit2 set<br />
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state<br />
! Clock-rate multiplier<br />
! Description<br />
|-<br />
| 0x01<br />
| No<br />
| Yes<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x02<br />
| No<br />
| No<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x05<br />
| Yes<br />
| Yes<br />
| 0x03<br />
| 3x<br />
| 804MHz<br />
|-<br />
| 0x03<br />
| Yes<br />
| No<br />
| 0x02<br />
| 2x<br />
| 536MHz (tested on New3DS)<br />
|}<br />
<br />
Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).<br />
<br />
The following register value(s) were tested on New3DS by patching the kernel:<br />
* 0x00: Entire system hangs.<br />
* 0x02: Entire system hangs.<br />
* 0x03: ARM11 runs at 536MHz.<br />
* 0x04: Entire system hangs.<br />
* 0x06: Entire system hangs.<br />
* 0x07: Same result as 0x05.<br />
* 0x08: Entire system hangs.<br />
* 0x09: Entire system hangs.<br />
* 0x0A: Entire system hangs.<br />
* 0x0B: Same result as 0x03.<br />
* 0x0C: Entire system hangs.<br />
* 0x0D: Same result as 0x05.<br />
* 0x0E: Entire system hangs.<br />
* 0x0F: Same result as 0x05.<br />
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.<br />
<br />
== CFG11_MPCORE_CNT ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Power on 3rd ARM11 MPCore maybe?<br />
|-<br />
| 8<br />
| Power on 4th ARM11 MPCore maybe?<br />
|}<br />
<br />
== CFG11_MPCORE_BOOTCNT<0-3> ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable bootrom instruction overlay, maybe? This bit is only writable for core2 and core3.<br />
|-<br />
| 1<br />
| Enable bootrom data overlay. This bit is only writable for core2 and core3.<br />
|-<br />
| 4<br />
| Has core booted maybe?<br />
|-<br />
| 5<br />
| Always 1?<br />
|}<br />
<br />
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.<br />
<br />
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].<br />
<br />
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:<br />
ldr pc, [pc]<br />
<br />
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.<br />
<br />
==CFG11_GPUPROT==<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Bits<br />
! Description<br />
|-<br />
| style="background: green" | Yes<br />
| 3-0<br />
| Old GPU DMA cutoff size<br />
|-<br />
| style="background: red" | No<br />
| 7-4<br />
| New GPU DMA cutoff size<br />
|-<br />
| style="background: green" | Yes<br />
| 8<br />
| ?!?!?!<br />
|-<br />
| style="background: red" | No<br />
| 9<br />
| ?!?!?!<br />
|-<br />
| style="background: red" | No<br />
| 10<br />
| Protect upper QTM mem<br />
|-<br />
| style="background: green" | Yes<br />
| 31-11<br />
| Zeroes<br />
|}<br />
<br />
For the old GPU DMA cutoff, it appears to start at 0x28000000-(0x800000*x) length 0x800000*x.<br />
<br />
For the new GPU DMA cutoff, it appears to start at 0x30000000-(0x800000*x) length 0x800000*x.<br />
<br />
On cold boot this reg is set to 0.<br />
<br />
Seems to control what memory GPU can access for DMA, this needs verified.<br />
<br />
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with v11.3.<br />
<br />
==CFG11_WIFI_CNT==<br />
Bit0: Enable wifi.<br />
<br />
==CFG11_TWLMODE_0==<br />
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.<br />
<br />
This address is poked from ARM7 to signal that it has booted and begun executing code. The ARM7-mode address for this register is 0x4700000.<br />
<br />
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.<br />
<br />
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.<br />
<br />
==CFG11_TWLMODE_1==<br />
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.<br />
<br />
==CFG11_TWLMODE_2==<br />
Bitfield.<br />
<br />
==CFG11_TWLMODE_HID==<br />
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.<br />
<br />
==CFG11_WIFI?==<br />
Bit4=unknown enabled by NWM on launch. Potentially powers on wifi card.<br />
<br />
==CFG11_GPU_CNT==<br />
This one seems to control the LCD/GPU/Backlight.<br />
<br />
Bit0: Enable GPU registers at 0x10400000+.<br />
Bit16: Turn on LCD backlight.<br />
<br />
==CFG11_GPU_CNT2==<br />
Bit0: Power on GPU?<br />
<br />
==CFG11_GPU_CNT3==<br />
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.<br />
<br />
==CFG11_CODEC==<br />
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.<br />
<br />
==CFG11_CODEC_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] CODEC service.<br />
<br />
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.<br />
<br />
==CFG11_CAMERA_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] camera service.<br />
<br />
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG11_Registers&diff=19525
CONFIG11 Registers
2017-02-07T17:23:14Z
<p>Plutooo: /* CFG11_GPUPROT */</p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7><br />
| 0x10140000<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7><br />
| 0x10140008<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140100<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140102<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_FIQ_CNT|CFG11_FIQ_CNT]]<br />
| 0x10140104<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140105<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x10140108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x1014010C<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPUPROT|CFG11_GPUPROT]]<br />
| 0x10140140<br />
| 4<br />
| Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_WIFI_CNT|CFG11_WIFI_CNT]]<br />
| 0x10140180<br />
| 1<br />
| TwlBg, [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]<br />
| 0x101401C0<br />
| 4<br />
| [[SPI Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140200<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140400<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140410<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]<br />
| 0x10140420<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]<br />
| 0x10140424<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| ?<br />
| 0x10140428<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]<br />
| 0x10140FFC<br />
| 2<br />
| Boot11, Kernel11<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| CFG11_GPU_STATUS?<br />
| 0x10141000<br />
| 4<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_0<br />
| 0x10141008<br />
| 4<br />
| [[PTM Services]], [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_1<br />
| 0x1014100C<br />
| 4<br />
| [[PTM Services]], TwlBg, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_0|CFG11_TWLMODE_0]]<br />
| 0x10141100<br />
| 2<br />
| TwlProcess9, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_1|CFG11_TWLMODE_1]]<br />
| 0x10141104<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_2|CFG11_TWLMODE_2]]<br />
| 0x10141108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_HID|CFG11_TWLMODE_HID]]<br />
| 0x1014110A<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_WIFI?<br />
| 0x1014110C<br />
| 1<br />
| [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141110<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141112<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_0]]<br />
| 0x10141114<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_1]]<br />
| 0x10141116<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141118<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141119<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141120<br />
| 1<br />
| TwlBg<br />
|-<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT|CFG11_GPU_CNT]]<br />
| 0x10141200<br />
| 4<br />
| Boot11, Kernel11, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT2|CFG11_GPU_CNT2]]<br />
| 0x10141204<br />
| 4<br />
| Boot11, Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_GPU_CNT3<br />
| 0x10141210<br />
| 2<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC_CNT|CFG11_CODEC_CNT]]<br />
| 0x10141220<br />
| 1<br />
| Boot11, TwlBg, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]]<br />
| 0x10141224<br />
| 1<br />
| [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_DSP_CNT<br />
| 0x10141230<br />
| 1<br />
| Process9, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CLKCNT|CFG11_MPCORE_CLKCNT]]<br />
| 0x10141300<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CNT|CFG11_MPCORE_CNT]]<br />
| 0x10141304<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_BOOTCNT<0-3>|CFG11_MPCORE_BOOTCNT]]<0-3><br />
| 0x10141310<br />
| 1*4<br />
| NewKernel11<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_DATA ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_CODE ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_FIQ_CNT ==<br />
Writing bit1 to this register disables FIQ interrupts.<br />
<br />
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.<br />
It is cleared when binding that software interrupt to an event and just before that event is signaled.<br />
<br />
== CFG11_SPI_CNT ==<br />
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Enable [[SPI Registers]] 0x10160000.<br />
|-<br />
| 1<br />
| Enable [[SPI Registers]] 0x10142000.<br />
|-<br />
| 2<br />
| Enable [[SPI Registers]] 0x10143000.<br />
|}<br />
<br />
== CFG11_BOOTROM_OVERLAY_CNT ==<br />
Bit0: Enable bootrom overlay functionality.<br />
<br />
== CFG11_BOOTROM_OVERLAY_VAL ==<br />
The 32-bit value to overlay data-reads to bootrom with. See [[#CFG11_MPCORE_BOOTCNT|CFG11_MPCORE_BOOTCNT]].<br />
<br />
== CFG11_SOCINFO ==<br />
Read-only register.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| 1 on both Old3DS and New3DS.<br />
| Boot11<br />
|-<br />
| 1<br />
| 1 on New3DS.<br />
| Kernel11<br />
|-<br />
| 2<br />
| Clock modifier: if set, use a 3x multiplier, otherwise 2x<br />
| Kernel11<br />
|}<br />
<br />
== CFG11_MPCORE_CLKCNT ==<br />
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.<br />
|-<br />
| 1-2<br />
| Clock multiplier (0=1x, 1=2x, 2=3x, 3=hang)<br />
|-<br />
| 15<br />
| Busy<br />
|}<br />
<br />
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG:<br />
{| class="wikitable" border="1"<br />
! Register value<br />
! Higher-clockrate bit set in svcKernelSetState Param0<br />
! CFG11_MPCORE_CFG bit2 set<br />
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state<br />
! Clock-rate multiplier<br />
! Description<br />
|-<br />
| 0x01<br />
| No<br />
| Yes<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x02<br />
| No<br />
| No<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x05<br />
| Yes<br />
| Yes<br />
| 0x03<br />
| 3x<br />
| 804MHz<br />
|-<br />
| 0x03<br />
| Yes<br />
| No<br />
| 0x02<br />
| 2x<br />
| 536MHz (tested on New3DS)<br />
|}<br />
<br />
Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).<br />
<br />
The following register value(s) were tested on New3DS by patching the kernel:<br />
* 0x00: Entire system hangs.<br />
* 0x02: Entire system hangs.<br />
* 0x03: ARM11 runs at 536MHz.<br />
* 0x04: Entire system hangs.<br />
* 0x06: Entire system hangs.<br />
* 0x07: Same result as 0x05.<br />
* 0x08: Entire system hangs.<br />
* 0x09: Entire system hangs.<br />
* 0x0A: Entire system hangs.<br />
* 0x0B: Same result as 0x03.<br />
* 0x0C: Entire system hangs.<br />
* 0x0D: Same result as 0x05.<br />
* 0x0E: Entire system hangs.<br />
* 0x0F: Same result as 0x05.<br />
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.<br />
<br />
== CFG11_MPCORE_CNT ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Power on 3rd ARM11 MPCore maybe?<br />
|-<br />
| 8<br />
| Power on 4th ARM11 MPCore maybe?<br />
|}<br />
<br />
== CFG11_MPCORE_BOOTCNT<0-3> ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable bootrom instruction overlay, maybe? This bit is only writable for core2 and core3.<br />
|-<br />
| 1<br />
| Enable bootrom data overlay. This bit is only writable for core2 and core3.<br />
|-<br />
| 4<br />
| Has core booted maybe?<br />
|-<br />
| 5<br />
| Always 1?<br />
|}<br />
<br />
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.<br />
<br />
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].<br />
<br />
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:<br />
ldr pc, [pc]<br />
<br />
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.<br />
<br />
==CFG11_GPUPROT==<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Bits<br />
! Description<br />
|-<br />
| style="background: green" | Yes<br />
| 3-0<br />
| Old GPU DMA cutoff size<br />
|-<br />
| style="background: red" | No<br />
| 7-4<br />
| New GPU DMA cutoff size<br />
|-<br />
| style="background: green" | Yes<br />
| 8<br />
| Enable old GPU DMA cutoff<br />
|-<br />
| style="background: red" | No<br />
| 9<br />
| ?!?!?!<br />
|-<br />
| style="background: red" | No<br />
| 10<br />
| Enable new GPU DMA cutoff<br />
|-<br />
| style="background: green" | Yes<br />
| 31-11<br />
| Zeroes<br />
|}<br />
<br />
For the old GPU DMA cutoff, it appears to start at 0x28000000-(0x800000*x) length 0x800000*x.<br />
<br />
For the new GPU DMA cutoff, it appears to start at 0x30000000-(0x800000*x) length 0x800000*x.<br />
<br />
On cold boot this reg is set to 0.<br />
<br />
Seems to control what memory GPU can access for DMA, this needs verified.<br />
<br />
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with v11.3.<br />
<br />
==CFG11_WIFI_CNT==<br />
Bit0: Enable wifi.<br />
<br />
==CFG11_TWLMODE_0==<br />
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.<br />
<br />
This address is poked from ARM7 to signal that it has booted and begun executing code. The ARM7-mode address for this register is 0x4700000.<br />
<br />
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.<br />
<br />
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.<br />
<br />
==CFG11_TWLMODE_1==<br />
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.<br />
<br />
==CFG11_TWLMODE_2==<br />
Bitfield.<br />
<br />
==CFG11_TWLMODE_HID==<br />
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.<br />
<br />
==CFG11_WIFI?==<br />
Bit4=unknown enabled by NWM on launch. Potentially powers on wifi card.<br />
<br />
==CFG11_GPU_CNT==<br />
This one seems to control the LCD/GPU/Backlight.<br />
<br />
Bit0: Enable GPU registers at 0x10400000+.<br />
Bit16: Turn on LCD backlight.<br />
<br />
==CFG11_GPU_CNT2==<br />
Bit0: Power on GPU?<br />
<br />
==CFG11_GPU_CNT3==<br />
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.<br />
<br />
==CFG11_CODEC==<br />
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.<br />
<br />
==CFG11_CODEC_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] CODEC service.<br />
<br />
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.<br />
<br />
==CFG11_CAMERA_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] camera service.<br />
<br />
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG11_Registers&diff=19524
CONFIG11 Registers
2017-02-07T17:22:43Z
<p>Plutooo: </p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7><br />
| 0x10140000<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7><br />
| 0x10140008<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140100<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140102<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_FIQ_CNT|CFG11_FIQ_CNT]]<br />
| 0x10140104<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140105<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x10140108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x1014010C<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPUPROT|CFG11_GPUPROT]]<br />
| 0x10140140<br />
| 4<br />
| Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_WIFI_CNT|CFG11_WIFI_CNT]]<br />
| 0x10140180<br />
| 1<br />
| TwlBg, [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]<br />
| 0x101401C0<br />
| 4<br />
| [[SPI Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140200<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140400<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140410<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]<br />
| 0x10140420<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]<br />
| 0x10140424<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| ?<br />
| 0x10140428<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]<br />
| 0x10140FFC<br />
| 2<br />
| Boot11, Kernel11<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| CFG11_GPU_STATUS?<br />
| 0x10141000<br />
| 4<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_0<br />
| 0x10141008<br />
| 4<br />
| [[PTM Services]], [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_1<br />
| 0x1014100C<br />
| 4<br />
| [[PTM Services]], TwlBg, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_0|CFG11_TWLMODE_0]]<br />
| 0x10141100<br />
| 2<br />
| TwlProcess9, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_1|CFG11_TWLMODE_1]]<br />
| 0x10141104<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_2|CFG11_TWLMODE_2]]<br />
| 0x10141108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_HID|CFG11_TWLMODE_HID]]<br />
| 0x1014110A<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_WIFI?<br />
| 0x1014110C<br />
| 1<br />
| [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141110<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141112<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_0]]<br />
| 0x10141114<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_1]]<br />
| 0x10141116<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141118<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141119<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141120<br />
| 1<br />
| TwlBg<br />
|-<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT|CFG11_GPU_CNT]]<br />
| 0x10141200<br />
| 4<br />
| Boot11, Kernel11, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT2|CFG11_GPU_CNT2]]<br />
| 0x10141204<br />
| 4<br />
| Boot11, Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_GPU_CNT3<br />
| 0x10141210<br />
| 2<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC_CNT|CFG11_CODEC_CNT]]<br />
| 0x10141220<br />
| 1<br />
| Boot11, TwlBg, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]]<br />
| 0x10141224<br />
| 1<br />
| [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_DSP_CNT<br />
| 0x10141230<br />
| 1<br />
| Process9, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CLKCNT|CFG11_MPCORE_CLKCNT]]<br />
| 0x10141300<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CNT|CFG11_MPCORE_CNT]]<br />
| 0x10141304<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_BOOTCNT<0-3>|CFG11_MPCORE_BOOTCNT]]<0-3><br />
| 0x10141310<br />
| 1*4<br />
| NewKernel11<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_DATA ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_CODE ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_FIQ_CNT ==<br />
Writing bit1 to this register disables FIQ interrupts.<br />
<br />
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.<br />
It is cleared when binding that software interrupt to an event and just before that event is signaled.<br />
<br />
== CFG11_SPI_CNT ==<br />
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Enable [[SPI Registers]] 0x10160000.<br />
|-<br />
| 1<br />
| Enable [[SPI Registers]] 0x10142000.<br />
|-<br />
| 2<br />
| Enable [[SPI Registers]] 0x10143000.<br />
|}<br />
<br />
== CFG11_BOOTROM_OVERLAY_CNT ==<br />
Bit0: Enable bootrom overlay functionality.<br />
<br />
== CFG11_BOOTROM_OVERLAY_VAL ==<br />
The 32-bit value to overlay data-reads to bootrom with. See [[#CFG11_MPCORE_BOOTCNT|CFG11_MPCORE_BOOTCNT]].<br />
<br />
== CFG11_SOCINFO ==<br />
Read-only register.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| 1 on both Old3DS and New3DS.<br />
| Boot11<br />
|-<br />
| 1<br />
| 1 on New3DS.<br />
| Kernel11<br />
|-<br />
| 2<br />
| Clock modifier: if set, use a 3x multiplier, otherwise 2x<br />
| Kernel11<br />
|}<br />
<br />
== CFG11_MPCORE_CLKCNT ==<br />
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.<br />
|-<br />
| 1-2<br />
| Clock multiplier (0=1x, 1=2x, 2=3x, 3=hang)<br />
|-<br />
| 15<br />
| Busy<br />
|}<br />
<br />
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG:<br />
{| class="wikitable" border="1"<br />
! Register value<br />
! Higher-clockrate bit set in svcKernelSetState Param0<br />
! CFG11_MPCORE_CFG bit2 set<br />
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state<br />
! Clock-rate multiplier<br />
! Description<br />
|-<br />
| 0x01<br />
| No<br />
| Yes<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x02<br />
| No<br />
| No<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x05<br />
| Yes<br />
| Yes<br />
| 0x03<br />
| 3x<br />
| 804MHz<br />
|-<br />
| 0x03<br />
| Yes<br />
| No<br />
| 0x02<br />
| 2x<br />
| 536MHz (tested on New3DS)<br />
|}<br />
<br />
Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).<br />
<br />
The following register value(s) were tested on New3DS by patching the kernel:<br />
* 0x00: Entire system hangs.<br />
* 0x02: Entire system hangs.<br />
* 0x03: ARM11 runs at 536MHz.<br />
* 0x04: Entire system hangs.<br />
* 0x06: Entire system hangs.<br />
* 0x07: Same result as 0x05.<br />
* 0x08: Entire system hangs.<br />
* 0x09: Entire system hangs.<br />
* 0x0A: Entire system hangs.<br />
* 0x0B: Same result as 0x03.<br />
* 0x0C: Entire system hangs.<br />
* 0x0D: Same result as 0x05.<br />
* 0x0E: Entire system hangs.<br />
* 0x0F: Same result as 0x05.<br />
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.<br />
<br />
== CFG11_MPCORE_CNT ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Power on 3rd ARM11 MPCore maybe?<br />
|-<br />
| 8<br />
| Power on 4th ARM11 MPCore maybe?<br />
|}<br />
<br />
== CFG11_MPCORE_BOOTCNT<0-3> ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable bootrom instruction overlay, maybe? This bit is only writable for core2 and core3.<br />
|-<br />
| 1<br />
| Enable bootrom data overlay. This bit is only writable for core2 and core3.<br />
|-<br />
| 4<br />
| Has core booted maybe?<br />
|-<br />
| 5<br />
| Always 1?<br />
|}<br />
<br />
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.<br />
<br />
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].<br />
<br />
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:<br />
ldr pc, [pc]<br />
<br />
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.<br />
<br />
==CFG11_GPUPROT==<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Bits<br />
! Description<br />
|-<br />
| style="background: green" | Yes<br />
| 3-0<br />
| Old GPU DMA cutoff size<br />
|-<br />
| style="background: red" | No<br />
| 7-4<br />
| New GPU DMA cutoff size<br />
|-<br />
| style="background: green" | Yes<br />
| 8<br />
| Enable old GPU DMA cutoff<br />
|-<br />
| style="background: red" | No<br />
| 9<br />
| ?!?!?!<br />
|-<br />
| style="background: red" | No<br />
| 10<br />
| Enable new GPU DMA cutoff<br />
|}<br />
<br />
For the old GPU DMA cutoff, it appears to start at 0x28000000-(0x800000*x) length 0x800000*x.<br />
<br />
For the new GPU DMA cutoff, it appears to start at 0x30000000-(0x800000*x) length 0x800000*x.<br />
<br />
On cold boot this reg is set to 0.<br />
<br />
Seems to control what memory GPU can access for DMA, this needs verified.<br />
<br />
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with v11.3.<br />
<br />
==CFG11_WIFI_CNT==<br />
Bit0: Enable wifi.<br />
<br />
==CFG11_TWLMODE_0==<br />
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.<br />
<br />
This address is poked from ARM7 to signal that it has booted and begun executing code. The ARM7-mode address for this register is 0x4700000.<br />
<br />
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.<br />
<br />
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.<br />
<br />
==CFG11_TWLMODE_1==<br />
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.<br />
<br />
==CFG11_TWLMODE_2==<br />
Bitfield.<br />
<br />
==CFG11_TWLMODE_HID==<br />
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.<br />
<br />
==CFG11_WIFI?==<br />
Bit4=unknown enabled by NWM on launch. Potentially powers on wifi card.<br />
<br />
==CFG11_GPU_CNT==<br />
This one seems to control the LCD/GPU/Backlight.<br />
<br />
Bit0: Enable GPU registers at 0x10400000+.<br />
Bit16: Turn on LCD backlight.<br />
<br />
==CFG11_GPU_CNT2==<br />
Bit0: Power on GPU?<br />
<br />
==CFG11_GPU_CNT3==<br />
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.<br />
<br />
==CFG11_CODEC==<br />
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.<br />
<br />
==CFG11_CODEC_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] CODEC service.<br />
<br />
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.<br />
<br />
==CFG11_CAMERA_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] camera service.<br />
<br />
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG11_Registers&diff=19523
CONFIG11 Registers
2017-02-07T16:59:28Z
<p>Plutooo: Thanks profi</p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7><br />
| 0x10140000<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7><br />
| 0x10140008<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140100<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140102<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_FIQ_CNT|CFG11_FIQ_CNT]]<br />
| 0x10140104<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140105<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x10140108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x1014010C<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPUPROT|CFG11_GPUPROT]]<br />
| 0x10140140<br />
| 4<br />
| Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_WIFI_CNT|CFG11_WIFI_CNT]]<br />
| 0x10140180<br />
| 1<br />
| TwlBg, [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]<br />
| 0x101401C0<br />
| 4<br />
| [[SPI Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140200<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140400<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140410<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]<br />
| 0x10140420<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]<br />
| 0x10140424<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| ?<br />
| 0x10140428<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]<br />
| 0x10140FFC<br />
| 2<br />
| Boot11, Kernel11<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| CFG11_GPU_STATUS?<br />
| 0x10141000<br />
| 4<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_0<br />
| 0x10141008<br />
| 4<br />
| [[PTM Services]], [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_1<br />
| 0x1014100C<br />
| 4<br />
| [[PTM Services]], TwlBg, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_0|CFG11_TWLMODE_0]]<br />
| 0x10141100<br />
| 2<br />
| TwlProcess9, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_1|CFG11_TWLMODE_1]]<br />
| 0x10141104<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_2|CFG11_TWLMODE_2]]<br />
| 0x10141108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_HID|CFG11_TWLMODE_HID]]<br />
| 0x1014110A<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_WIFI?<br />
| 0x1014110C<br />
| 1<br />
| [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141110<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141112<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_0]]<br />
| 0x10141114<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_1]]<br />
| 0x10141116<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141118<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141119<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141120<br />
| 1<br />
| TwlBg<br />
|-<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT|CFG11_GPU_CNT]]<br />
| 0x10141200<br />
| 4<br />
| Boot11, Kernel11, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT2|CFG11_GPU_CNT2]]<br />
| 0x10141204<br />
| 4<br />
| Boot11, Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_GPU_CNT3<br />
| 0x10141210<br />
| 2<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC_CNT|CFG11_CODEC_CNT]]<br />
| 0x10141220<br />
| 1<br />
| Boot11, TwlBg, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]]<br />
| 0x10141224<br />
| 1<br />
| [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_DSP_CNT<br />
| 0x10141230<br />
| 1<br />
| Process9, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CLKCNT|CFG11_MPCORE_CLKCNT]]<br />
| 0x10141300<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CNT|CFG11_MPCORE_CNT]]<br />
| 0x10141304<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_BOOTCNT<0-3>|CFG11_MPCORE_BOOTCNT]]<0-3><br />
| 0x10141310<br />
| 1*4<br />
| NewKernel11<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_DATA ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_CODE ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_FIQ_CNT ==<br />
Writing bit1 to this register disables FIQ interrupts.<br />
<br />
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.<br />
It is cleared when binding that software interrupt to an event and just before that event is signaled.<br />
<br />
== CFG11_SPI_CNT ==<br />
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Enable [[SPI Registers]] 0x10160000.<br />
|-<br />
| 1<br />
| Enable [[SPI Registers]] 0x10142000.<br />
|-<br />
| 2<br />
| Enable [[SPI Registers]] 0x10143000.<br />
|}<br />
<br />
== CFG11_BOOTROM_OVERLAY_CNT ==<br />
Bit0: Enable bootrom overlay functionality.<br />
<br />
== CFG11_BOOTROM_OVERLAY_VAL ==<br />
The 32-bit value to overlay data-reads to bootrom with. See [[#CFG11_MPCORE_BOOTCNT|CFG11_MPCORE_BOOTCNT]].<br />
<br />
== CFG11_SOCINFO ==<br />
Read-only register.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| 1 on both Old3DS and New3DS.<br />
| Boot11<br />
|-<br />
| 1<br />
| 1 on New3DS.<br />
| Kernel11<br />
|-<br />
| 2<br />
| Clock modifier: if set, use a 3x multiplier, otherwise 2x<br />
| Kernel11<br />
|}<br />
<br />
== CFG11_MPCORE_CLKCNT ==<br />
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.<br />
|-<br />
| 1-2<br />
| Clock multiplier (0=1x, 1=2x, 2=3x, 3=hang)<br />
|-<br />
| 15<br />
| Busy<br />
|}<br />
<br />
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG:<br />
{| class="wikitable" border="1"<br />
! Register value<br />
! Higher-clockrate bit set in svcKernelSetState Param0<br />
! CFG11_MPCORE_CFG bit2 set<br />
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state<br />
! Clock-rate multiplier<br />
! Description<br />
|-<br />
| 0x01<br />
| No<br />
| Yes<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x02<br />
| No<br />
| No<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x05<br />
| Yes<br />
| Yes<br />
| 0x03<br />
| 3x<br />
| 804MHz<br />
|-<br />
| 0x03<br />
| Yes<br />
| No<br />
| 0x02<br />
| 2x<br />
| 536MHz (tested on New3DS)<br />
|}<br />
<br />
Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).<br />
<br />
The following register value(s) were tested on New3DS by patching the kernel:<br />
* 0x00: Entire system hangs.<br />
* 0x02: Entire system hangs.<br />
* 0x03: ARM11 runs at 536MHz.<br />
* 0x04: Entire system hangs.<br />
* 0x06: Entire system hangs.<br />
* 0x07: Same result as 0x05.<br />
* 0x08: Entire system hangs.<br />
* 0x09: Entire system hangs.<br />
* 0x0A: Entire system hangs.<br />
* 0x0B: Same result as 0x03.<br />
* 0x0C: Entire system hangs.<br />
* 0x0D: Same result as 0x05.<br />
* 0x0E: Entire system hangs.<br />
* 0x0F: Same result as 0x05.<br />
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.<br />
<br />
== CFG11_MPCORE_CNT ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Power on 3rd ARM11 MPCore maybe?<br />
|-<br />
| 8<br />
| Power on 4th ARM11 MPCore maybe?<br />
|}<br />
<br />
== CFG11_MPCORE_BOOTCNT<0-3> ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable bootrom instruction overlay, maybe? This bit is only writable for core2 and core3.<br />
|-<br />
| 1<br />
| Enable bootrom data overlay. This bit is only writable for core2 and core3.<br />
|-<br />
| 4<br />
| Has core booted maybe?<br />
|-<br />
| 5<br />
| Always 1?<br />
|}<br />
<br />
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.<br />
<br />
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].<br />
<br />
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:<br />
ldr pc, [pc]<br />
<br />
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.<br />
<br />
==CFG11_GPUPROT==<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Bits<br />
! Description<br />
|-<br />
| style="background: green" | Yes<br />
| 3-0<br />
| Old GPU DMA cutoff size<br />
|-<br />
| style="background: red" | No<br />
| 7-4<br />
| New GPU DMA cutoff size<br />
|-<br />
| style="background: green" | Yes<br />
| 8<br />
| Enable old GPU DMA cutoff<br />
|-<br />
| style="background: red" | No<br />
| 10<br />
| Enable new GPU DMA cutoff<br />
|}<br />
<br />
For the old GPU DMA cutoff, it appears to start at 0x28000000-(0x800000*x) length 0x800000*x.<br />
<br />
For the new GPU DMA cutoff, it appears to start at 0x30000000-(0x800000*x) length 0x800000*x.<br />
<br />
On cold boot this reg is set to 0.<br />
<br />
Seems to control what memory GPU can access for DMA, this needs verified.<br />
<br />
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with v11.3.<br />
<br />
==CFG11_WIFI_CNT==<br />
Bit0: Enable wifi.<br />
<br />
==CFG11_TWLMODE_0==<br />
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.<br />
<br />
This address is poked from ARM7 to signal that it has booted and begun executing code. The ARM7-mode address for this register is 0x4700000.<br />
<br />
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.<br />
<br />
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.<br />
<br />
==CFG11_TWLMODE_1==<br />
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.<br />
<br />
==CFG11_TWLMODE_2==<br />
Bitfield.<br />
<br />
==CFG11_TWLMODE_HID==<br />
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.<br />
<br />
==CFG11_WIFI?==<br />
Bit4=unknown enabled by NWM on launch. Potentially powers on wifi card.<br />
<br />
==CFG11_GPU_CNT==<br />
This one seems to control the LCD/GPU/Backlight.<br />
<br />
Bit0: Enable GPU registers at 0x10400000+.<br />
Bit16: Turn on LCD backlight.<br />
<br />
==CFG11_GPU_CNT2==<br />
Bit0: Power on GPU?<br />
<br />
==CFG11_GPU_CNT3==<br />
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.<br />
<br />
==CFG11_CODEC==<br />
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.<br />
<br />
==CFG11_CODEC_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] CODEC service.<br />
<br />
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.<br />
<br />
==CFG11_CAMERA_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] camera service.<br />
<br />
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG11_Registers&diff=19522
CONFIG11 Registers
2017-02-07T16:49:43Z
<p>Plutooo: /* CFG11_GPUPROT */</p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7><br />
| 0x10140000<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7><br />
| 0x10140008<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140100<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140102<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_FIQ_CNT|CFG11_FIQ_CNT]]<br />
| 0x10140104<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140105<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x10140108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x1014010C<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPUPROT|CFG11_GPUPROT]]<br />
| 0x10140140<br />
| 4<br />
| Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_WIFI_CNT|CFG11_WIFI_CNT]]<br />
| 0x10140180<br />
| 1<br />
| TwlBg, [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]<br />
| 0x101401C0<br />
| 4<br />
| [[SPI Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140200<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140400<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140410<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]<br />
| 0x10140420<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]<br />
| 0x10140424<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| ?<br />
| 0x10140428<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]<br />
| 0x10140FFC<br />
| 2<br />
| Boot11, Kernel11<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| CFG11_GPU_STATUS?<br />
| 0x10141000<br />
| 4<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_0<br />
| 0x10141008<br />
| 4<br />
| [[PTM Services]], [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_1<br />
| 0x1014100C<br />
| 4<br />
| [[PTM Services]], TwlBg, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_0|CFG11_TWLMODE_0]]<br />
| 0x10141100<br />
| 2<br />
| TwlProcess9, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_1|CFG11_TWLMODE_1]]<br />
| 0x10141104<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_2|CFG11_TWLMODE_2]]<br />
| 0x10141108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_HID|CFG11_TWLMODE_HID]]<br />
| 0x1014110A<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_WIFI?<br />
| 0x1014110C<br />
| 1<br />
| [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141110<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141112<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_0]]<br />
| 0x10141114<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_1]]<br />
| 0x10141116<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141118<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141119<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141120<br />
| 1<br />
| TwlBg<br />
|-<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT|CFG11_GPU_CNT]]<br />
| 0x10141200<br />
| 4<br />
| Boot11, Kernel11, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT2|CFG11_GPU_CNT2]]<br />
| 0x10141204<br />
| 4<br />
| Boot11, Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_GPU_CNT3<br />
| 0x10141210<br />
| 2<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC_CNT|CFG11_CODEC_CNT]]<br />
| 0x10141220<br />
| 1<br />
| Boot11, TwlBg, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]]<br />
| 0x10141224<br />
| 1<br />
| [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_DSP_CNT<br />
| 0x10141230<br />
| 1<br />
| Process9, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CLKCNT|CFG11_MPCORE_CLKCNT]]<br />
| 0x10141300<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CNT|CFG11_MPCORE_CNT]]<br />
| 0x10141304<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_BOOTCNT<0-3>|CFG11_MPCORE_BOOTCNT]]<0-3><br />
| 0x10141310<br />
| 1*4<br />
| NewKernel11<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_DATA ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_CODE ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_FIQ_CNT ==<br />
Writing bit1 to this register disables FIQ interrupts.<br />
<br />
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.<br />
It is cleared when binding that software interrupt to an event and just before that event is signaled.<br />
<br />
== CFG11_SPI_CNT ==<br />
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Enable [[SPI Registers]] 0x10160000.<br />
|-<br />
| 1<br />
| Enable [[SPI Registers]] 0x10142000.<br />
|-<br />
| 2<br />
| Enable [[SPI Registers]] 0x10143000.<br />
|}<br />
<br />
== CFG11_BOOTROM_OVERLAY_CNT ==<br />
Bit0: Enable bootrom overlay functionality.<br />
<br />
== CFG11_BOOTROM_OVERLAY_VAL ==<br />
The 32-bit value to overlay data-reads to bootrom with. See [[#CFG11_MPCORE_BOOTCNT|CFG11_MPCORE_BOOTCNT]].<br />
<br />
== CFG11_SOCINFO ==<br />
Read-only register.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| 1 on both Old3DS and New3DS.<br />
| Boot11<br />
|-<br />
| 1<br />
| 1 on New3DS.<br />
| Kernel11<br />
|-<br />
| 2<br />
| Clock modifier: if set, use a 3x multiplier, otherwise 2x<br />
| Kernel11<br />
|}<br />
<br />
== CFG11_MPCORE_CLKCNT ==<br />
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.<br />
|-<br />
| 1-2<br />
| Clock multiplier (0=1x, 1=2x, 2=3x, 3=hang)<br />
|-<br />
| 15<br />
| Busy<br />
|}<br />
<br />
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG:<br />
{| class="wikitable" border="1"<br />
! Register value<br />
! Higher-clockrate bit set in svcKernelSetState Param0<br />
! CFG11_MPCORE_CFG bit2 set<br />
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state<br />
! Clock-rate multiplier<br />
! Description<br />
|-<br />
| 0x01<br />
| No<br />
| Yes<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x02<br />
| No<br />
| No<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x05<br />
| Yes<br />
| Yes<br />
| 0x03<br />
| 3x<br />
| 804MHz<br />
|-<br />
| 0x03<br />
| Yes<br />
| No<br />
| 0x02<br />
| 2x<br />
| 536MHz (tested on New3DS)<br />
|}<br />
<br />
Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).<br />
<br />
The following register value(s) were tested on New3DS by patching the kernel:<br />
* 0x00: Entire system hangs.<br />
* 0x02: Entire system hangs.<br />
* 0x03: ARM11 runs at 536MHz.<br />
* 0x04: Entire system hangs.<br />
* 0x06: Entire system hangs.<br />
* 0x07: Same result as 0x05.<br />
* 0x08: Entire system hangs.<br />
* 0x09: Entire system hangs.<br />
* 0x0A: Entire system hangs.<br />
* 0x0B: Same result as 0x03.<br />
* 0x0C: Entire system hangs.<br />
* 0x0D: Same result as 0x05.<br />
* 0x0E: Entire system hangs.<br />
* 0x0F: Same result as 0x05.<br />
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.<br />
<br />
== CFG11_MPCORE_CNT ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Power on 3rd ARM11 MPCore maybe?<br />
|-<br />
| 8<br />
| Power on 4th ARM11 MPCore maybe?<br />
|}<br />
<br />
== CFG11_MPCORE_BOOTCNT<0-3> ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable bootrom instruction overlay, maybe? This bit is only writable for core2 and core3.<br />
|-<br />
| 1<br />
| Enable bootrom data overlay. This bit is only writable for core2 and core3.<br />
|-<br />
| 4<br />
| Has core booted maybe?<br />
|-<br />
| 5<br />
| Always 1?<br />
|}<br />
<br />
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.<br />
<br />
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].<br />
<br />
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:<br />
ldr pc, [pc]<br />
<br />
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.<br />
<br />
==CFG11_GPUPROT==<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Bits<br />
! Description<br />
|-<br />
| style="background: green" | Yes<br />
| 3-0<br />
| Old GPU DMA cutoff size<br />
|-<br />
| style="background: red" | No<br />
| 7-4<br />
| New GPU DMA cutoff size<br />
|-<br />
| style="background: green" | Yes<br />
| 8<br />
| Enable old GPU DMA cutoff<br />
|-<br />
| style="background: red" | No<br />
| 10<br />
| Enable new GPU DMA cutoff<br />
|}<br />
<br />
For the old GPU DMA cutoff, it appears to start at 0x28000000-(0x800000*x) length 0x800000*x.<br />
For the new GPU DMA cutoff, it appears to start at 0x30000000-(0x800000*x) length 0x800000*x.<br />
<br />
Seems to control what memory GPU can access for DMA, this needs verified.<br />
<br />
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with v11.3.<br />
<br />
==CFG11_WIFI_CNT==<br />
Bit0: Enable wifi.<br />
<br />
==CFG11_TWLMODE_0==<br />
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.<br />
<br />
This address is poked from ARM7 to signal that it has booted and begun executing code. The ARM7-mode address for this register is 0x4700000.<br />
<br />
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.<br />
<br />
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.<br />
<br />
==CFG11_TWLMODE_1==<br />
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.<br />
<br />
==CFG11_TWLMODE_2==<br />
Bitfield.<br />
<br />
==CFG11_TWLMODE_HID==<br />
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.<br />
<br />
==CFG11_WIFI?==<br />
Bit4=unknown enabled by NWM on launch. Potentially powers on wifi card.<br />
<br />
==CFG11_GPU_CNT==<br />
This one seems to control the LCD/GPU/Backlight.<br />
<br />
Bit0: Enable GPU registers at 0x10400000+.<br />
Bit16: Turn on LCD backlight.<br />
<br />
==CFG11_GPU_CNT2==<br />
Bit0: Power on GPU?<br />
<br />
==CFG11_GPU_CNT3==<br />
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.<br />
<br />
==CFG11_CODEC==<br />
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.<br />
<br />
==CFG11_CODEC_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] CODEC service.<br />
<br />
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.<br />
<br />
==CFG11_CAMERA_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] camera service.<br />
<br />
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG11_Registers&diff=19521
CONFIG11 Registers
2017-02-07T16:45:45Z
<p>Plutooo: </p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7><br />
| 0x10140000<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7><br />
| 0x10140008<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140100<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140102<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_FIQ_CNT|CFG11_FIQ_CNT]]<br />
| 0x10140104<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140105<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x10140108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x1014010C<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPUPROT|CFG11_GPUPROT]]<br />
| 0x10140140<br />
| 4<br />
| Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_WIFI_CNT|CFG11_WIFI_CNT]]<br />
| 0x10140180<br />
| 1<br />
| TwlBg, [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]<br />
| 0x101401C0<br />
| 4<br />
| [[SPI Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140200<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140400<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140410<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]<br />
| 0x10140420<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]<br />
| 0x10140424<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| ?<br />
| 0x10140428<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]<br />
| 0x10140FFC<br />
| 2<br />
| Boot11, Kernel11<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| CFG11_GPU_STATUS?<br />
| 0x10141000<br />
| 4<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_0<br />
| 0x10141008<br />
| 4<br />
| [[PTM Services]], [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_1<br />
| 0x1014100C<br />
| 4<br />
| [[PTM Services]], TwlBg, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_0|CFG11_TWLMODE_0]]<br />
| 0x10141100<br />
| 2<br />
| TwlProcess9, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_1|CFG11_TWLMODE_1]]<br />
| 0x10141104<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_2|CFG11_TWLMODE_2]]<br />
| 0x10141108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_HID|CFG11_TWLMODE_HID]]<br />
| 0x1014110A<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_WIFI?<br />
| 0x1014110C<br />
| 1<br />
| [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141110<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141112<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_0]]<br />
| 0x10141114<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_1]]<br />
| 0x10141116<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141118<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141119<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141120<br />
| 1<br />
| TwlBg<br />
|-<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT|CFG11_GPU_CNT]]<br />
| 0x10141200<br />
| 4<br />
| Boot11, Kernel11, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT2|CFG11_GPU_CNT2]]<br />
| 0x10141204<br />
| 4<br />
| Boot11, Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_GPU_CNT3<br />
| 0x10141210<br />
| 2<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC_CNT|CFG11_CODEC_CNT]]<br />
| 0x10141220<br />
| 1<br />
| Boot11, TwlBg, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]]<br />
| 0x10141224<br />
| 1<br />
| [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_DSP_CNT<br />
| 0x10141230<br />
| 1<br />
| Process9, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CLKCNT|CFG11_MPCORE_CLKCNT]]<br />
| 0x10141300<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CNT|CFG11_MPCORE_CNT]]<br />
| 0x10141304<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_BOOTCNT<0-3>|CFG11_MPCORE_BOOTCNT]]<0-3><br />
| 0x10141310<br />
| 1*4<br />
| NewKernel11<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_DATA ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_CODE ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_FIQ_CNT ==<br />
Writing bit1 to this register disables FIQ interrupts.<br />
<br />
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.<br />
It is cleared when binding that software interrupt to an event and just before that event is signaled.<br />
<br />
== CFG11_SPI_CNT ==<br />
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Enable [[SPI Registers]] 0x10160000.<br />
|-<br />
| 1<br />
| Enable [[SPI Registers]] 0x10142000.<br />
|-<br />
| 2<br />
| Enable [[SPI Registers]] 0x10143000.<br />
|}<br />
<br />
== CFG11_BOOTROM_OVERLAY_CNT ==<br />
Bit0: Enable bootrom overlay functionality.<br />
<br />
== CFG11_BOOTROM_OVERLAY_VAL ==<br />
The 32-bit value to overlay data-reads to bootrom with. See [[#CFG11_MPCORE_BOOTCNT|CFG11_MPCORE_BOOTCNT]].<br />
<br />
== CFG11_SOCINFO ==<br />
Read-only register.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| 1 on both Old3DS and New3DS.<br />
| Boot11<br />
|-<br />
| 1<br />
| 1 on New3DS.<br />
| Kernel11<br />
|-<br />
| 2<br />
| Clock modifier: if set, use a 3x multiplier, otherwise 2x<br />
| Kernel11<br />
|}<br />
<br />
== CFG11_MPCORE_CLKCNT ==<br />
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.<br />
|-<br />
| 1-2<br />
| Clock multiplier (0=1x, 1=2x, 2=3x, 3=hang)<br />
|-<br />
| 15<br />
| Busy<br />
|}<br />
<br />
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG:<br />
{| class="wikitable" border="1"<br />
! Register value<br />
! Higher-clockrate bit set in svcKernelSetState Param0<br />
! CFG11_MPCORE_CFG bit2 set<br />
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state<br />
! Clock-rate multiplier<br />
! Description<br />
|-<br />
| 0x01<br />
| No<br />
| Yes<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x02<br />
| No<br />
| No<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x05<br />
| Yes<br />
| Yes<br />
| 0x03<br />
| 3x<br />
| 804MHz<br />
|-<br />
| 0x03<br />
| Yes<br />
| No<br />
| 0x02<br />
| 2x<br />
| 536MHz (tested on New3DS)<br />
|}<br />
<br />
Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).<br />
<br />
The following register value(s) were tested on New3DS by patching the kernel:<br />
* 0x00: Entire system hangs.<br />
* 0x02: Entire system hangs.<br />
* 0x03: ARM11 runs at 536MHz.<br />
* 0x04: Entire system hangs.<br />
* 0x06: Entire system hangs.<br />
* 0x07: Same result as 0x05.<br />
* 0x08: Entire system hangs.<br />
* 0x09: Entire system hangs.<br />
* 0x0A: Entire system hangs.<br />
* 0x0B: Same result as 0x03.<br />
* 0x0C: Entire system hangs.<br />
* 0x0D: Same result as 0x05.<br />
* 0x0E: Entire system hangs.<br />
* 0x0F: Same result as 0x05.<br />
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.<br />
<br />
== CFG11_MPCORE_CNT ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Power on 3rd ARM11 MPCore maybe?<br />
|-<br />
| 8<br />
| Power on 4th ARM11 MPCore maybe?<br />
|}<br />
<br />
== CFG11_MPCORE_BOOTCNT<0-3> ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable bootrom instruction overlay, maybe? This bit is only writable for core2 and core3.<br />
|-<br />
| 1<br />
| Enable bootrom data overlay. This bit is only writable for core2 and core3.<br />
|-<br />
| 4<br />
| Has core booted maybe?<br />
|-<br />
| 5<br />
| Always 1?<br />
|}<br />
<br />
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.<br />
<br />
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].<br />
<br />
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:<br />
ldr pc, [pc]<br />
<br />
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.<br />
<br />
==CFG11_GPUPROT==<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Bits<br />
! Description<br />
|-<br />
| style="background: green" | Yes<br />
| 0-2<br />
| Old GPU DMA cutoff size<br />
|-<br />
| style="background: green" | Yes<br />
| 3<br />
| ?<br />
|-<br />
| style="background: red" | No<br />
| 4-7<br />
| New GPU DMA cutoff<br />
|-<br />
| style="background: green" | Yes<br />
| 8<br />
| Enable old GPU DMA cutoff<br />
|-<br />
| style="background: red" | No<br />
| 10<br />
| Enable new GPU DMA cutoff<br />
|}<br />
<br />
For the old GPU DMA cutoff, it appears to start at 0x28000000-(0x800000*x) length 0x800000*x.<br />
For the new GPU DMA cutoff, it appears to start at 0x30000000-(0x800000*x) length 0x800000*x.<br />
<br />
Seems to control what memory GPU can access for DMA, this needs verified.<br />
<br />
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with v11.3.<br />
<br />
==CFG11_WIFI_CNT==<br />
Bit0: Enable wifi.<br />
<br />
==CFG11_TWLMODE_0==<br />
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.<br />
<br />
This address is poked from ARM7 to signal that it has booted and begun executing code. The ARM7-mode address for this register is 0x4700000.<br />
<br />
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.<br />
<br />
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.<br />
<br />
==CFG11_TWLMODE_1==<br />
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.<br />
<br />
==CFG11_TWLMODE_2==<br />
Bitfield.<br />
<br />
==CFG11_TWLMODE_HID==<br />
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.<br />
<br />
==CFG11_WIFI?==<br />
Bit4=unknown enabled by NWM on launch. Potentially powers on wifi card.<br />
<br />
==CFG11_GPU_CNT==<br />
This one seems to control the LCD/GPU/Backlight.<br />
<br />
Bit0: Enable GPU registers at 0x10400000+.<br />
Bit16: Turn on LCD backlight.<br />
<br />
==CFG11_GPU_CNT2==<br />
Bit0: Power on GPU?<br />
<br />
==CFG11_GPU_CNT3==<br />
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.<br />
<br />
==CFG11_CODEC==<br />
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.<br />
<br />
==CFG11_CODEC_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] CODEC service.<br />
<br />
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.<br />
<br />
==CFG11_CAMERA_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] camera service.<br />
<br />
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG11_Registers&diff=19513
CONFIG11 Registers
2017-02-07T16:01:57Z
<p>Plutooo: </p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_DATA|CFG11_SHAREDWRAM_32K_DATA]]<0-7><br />
| 0x10140000<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SHAREDWRAM_32K_CODE|CFG11_SHAREDWRAM_32K_CODE]]<0-7><br />
| 0x10140008<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140100<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140102<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_FIQ_CNT|CFG11_FIQ_CNT]]<br />
| 0x10140104<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140105<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x10140108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x1014010C<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140140<br />
| 4<br />
| Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_WIFI_CNT|CFG11_WIFI_CNT]]<br />
| 0x10140180<br />
| 1<br />
| TwlBg, [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_SPI_CNT|CFG11_SPI_CNT]]<br />
| 0x101401C0<br />
| 4<br />
| [[SPI Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140200<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140400<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140410<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_CNT|CFG11_BOOTROM_OVERLAY_CNT]]<br />
| 0x10140420<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]<br />
| 0x10140424<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| ?<br />
| 0x10140428<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_SOCINFO|CFG11_SOCINFO]]<br />
| 0x10140FFC<br />
| 2<br />
| Boot11, Kernel11<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| CFG11_GPU_STATUS?<br />
| 0x10141000<br />
| 4<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_0<br />
| 0x10141008<br />
| 4<br />
| [[PTM Services]], [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_PTM_1<br />
| 0x1014100C<br />
| 4<br />
| [[PTM Services]], TwlBg, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_0|CFG11_TWLMODE_0]]<br />
| 0x10141100<br />
| 2<br />
| TwlProcess9, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_1|CFG11_TWLMODE_1]]<br />
| 0x10141104<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_2|CFG11_TWLMODE_2]]<br />
| 0x10141108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_TWLMODE_HID|CFG11_TWLMODE_HID]]<br />
| 0x1014110A<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_WIFI?<br />
| 0x1014110C<br />
| 1<br />
| [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141110<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141112<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_0]]<br />
| 0x10141114<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC|CFG11_CODEC_1]]<br />
| 0x10141116<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141118<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141119<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141120<br />
| 1<br />
| TwlBg<br />
|-<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT|CFG11_GPU_CNT]]<br />
| 0x10141200<br />
| 4<br />
| Boot11, Kernel11, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_GPU_CNT2|CFG11_GPU_CNT2]]<br />
| 0x10141204<br />
| 4<br />
| Boot11, Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_GPU_CNT3<br />
| 0x10141210<br />
| 2<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CODEC_CNT|CFG11_CODEC_CNT]]<br />
| 0x10141220<br />
| 1<br />
| Boot11, TwlBg, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG11_CAMERA_CNT|CFG11_CAMERA_CNT]]<br />
| 0x10141224<br />
| 1<br />
| [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| CFG11_DSP_CNT<br />
| 0x10141230<br />
| 1<br />
| Process9, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CLKCNT|CFG11_MPCORE_CLKCNT]]<br />
| 0x10141300<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_CNT|CFG11_MPCORE_CNT]]<br />
| 0x10141304<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG11_MPCORE_BOOTCNT<0-3>|CFG11_MPCORE_BOOTCNT]]<0-3><br />
| 0x10141310<br />
| 1*4<br />
| NewKernel11<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_DATA ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_SHAREDWRAM_32K_CODE ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== CFG11_FIQ_CNT ==<br />
Writing bit1 to this register disables FIQ interrupts.<br />
<br />
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.<br />
It is cleared when binding that software interrupt to an event and just before that event is signaled.<br />
<br />
== CFG11_SPI_CNT ==<br />
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Enable [[SPI Registers]] 0x10160000.<br />
|-<br />
| 1<br />
| Enable [[SPI Registers]] 0x10142000.<br />
|-<br />
| 2<br />
| Enable [[SPI Registers]] 0x10143000.<br />
|}<br />
<br />
== CFG11_BOOTROM_OVERLAY_CNT ==<br />
Bit0: Enable bootrom overlay functionality.<br />
<br />
== CFG11_BOOTROM_OVERLAY_VAL ==<br />
The 32-bit value to overlay data-reads to bootrom with. See [[#CFG11_MPCORE_BOOTCNT|CFG11_MPCORE_BOOTCNT]].<br />
<br />
== CFG11_SOCINFO ==<br />
Read-only register.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| 1 on both Old3DS and New3DS.<br />
| Boot11<br />
|-<br />
| 1<br />
| 1 on New3DS.<br />
| Kernel11<br />
|-<br />
| 2<br />
| Clock modifier: if set, use a 3x multiplier, otherwise 2x<br />
| Kernel11<br />
|}<br />
<br />
== CFG11_MPCORE_CLKCNT ==<br />
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.<br />
|-<br />
| 1-2<br />
| Clock multiplier (0=1x, 1=2x, 2=3x, 3=hang)<br />
|-<br />
| 15<br />
| Busy<br />
|}<br />
<br />
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of CFG11_MPCORE_CFG:<br />
{| class="wikitable" border="1"<br />
! Register value<br />
! Higher-clockrate bit set in svcKernelSetState Param0<br />
! CFG11_MPCORE_CFG bit2 set<br />
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state<br />
! Clock-rate multiplier<br />
! Description<br />
|-<br />
| 0x01<br />
| No<br />
| Yes<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x02<br />
| No<br />
| No<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x05<br />
| Yes<br />
| Yes<br />
| 0x03<br />
| 3x<br />
| 804MHz<br />
|-<br />
| 0x03<br />
| Yes<br />
| No<br />
| 0x02<br />
| 2x<br />
| 536MHz (tested on New3DS)<br />
|}<br />
<br />
Note that the above CFG11_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).<br />
<br />
The following register value(s) were tested on New3DS by patching the kernel:<br />
* 0x00: Entire system hangs.<br />
* 0x02: Entire system hangs.<br />
* 0x03: ARM11 runs at 536MHz.<br />
* 0x04: Entire system hangs.<br />
* 0x06: Entire system hangs.<br />
* 0x07: Same result as 0x05.<br />
* 0x08: Entire system hangs.<br />
* 0x09: Entire system hangs.<br />
* 0x0A: Entire system hangs.<br />
* 0x0B: Same result as 0x03.<br />
* 0x0C: Entire system hangs.<br />
* 0x0D: Same result as 0x05.<br />
* 0x0E: Entire system hangs.<br />
* 0x0F: Same result as 0x05.<br />
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.<br />
<br />
== CFG11_MPCORE_CNT ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Power on 3rd ARM11 MPCore maybe?<br />
|-<br />
| 8<br />
| Power on 4th ARM11 MPCore maybe?<br />
|}<br />
<br />
== CFG11_MPCORE_BOOTCNT<0-3> ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable bootrom instruction overlay, maybe? This bit is only writable for core2 and core3.<br />
|-<br />
| 1<br />
| Enable bootrom data overlay. This bit is only writable for core2 and core3.<br />
|-<br />
| 4<br />
| Has core booted maybe?<br />
|-<br />
| 5<br />
| Always 1?<br />
|}<br />
<br />
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.<br />
<br />
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]].<br />
<br />
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#CFG11_BOOTROM_OVERLAY_VAL|CFG11_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:<br />
ldr pc, [pc]<br />
<br />
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.<br />
<br />
==0x10140140==<br />
Seems to control what memory GPU can access for DMA, this needs verified.<br />
<br />
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with v11.3.<br />
<br />
==CFG11_WIFI_CNT==<br />
Bit0: Enable wifi.<br />
<br />
==CFG11_TWLMODE_0==<br />
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.<br />
<br />
This address is poked from ARM7 to signal that it has booted and begun executing code. The ARM7-mode address for this register is 0x4700000.<br />
<br />
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.<br />
<br />
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.<br />
<br />
==CFG11_TWLMODE_1==<br />
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.<br />
<br />
==CFG11_TWLMODE_2==<br />
Bitfield.<br />
<br />
==CFG11_TWLMODE_HID==<br />
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.<br />
<br />
==CFG11_WIFI?==<br />
Bit4=unknown enabled by NWM on launch. Potentially powers on wifi card.<br />
<br />
==CFG11_GPU_CNT==<br />
This one seems to control the LCD/GPU/Backlight.<br />
<br />
Bit0: Enable GPU registers at 0x10400000+.<br />
Bit16: Turn on LCD backlight.<br />
<br />
==CFG11_GPU_CNT2==<br />
Bit0: Power on GPU?<br />
<br />
==CFG11_GPU_CNT3==<br />
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.<br />
<br />
==CFG11_CODEC==<br />
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.<br />
<br />
==CFG11_CODEC_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] CODEC service.<br />
<br />
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.<br />
<br />
==CFG11_CAMERA_CNT==<br />
This is the power register used for the [[CFG11_Services|PDN]] camera service.<br />
<br />
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG9_Registers&diff=19512
CONFIG9 Registers
2017-02-07T15:58:19Z
<p>Plutooo: </p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG9_SYSPROT9|CFG9_SYSPROT9]]<br />
| 0x10000000<br />
| 1<br />
| Boot9<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG9_SYSPROT11|CFG9_SYSPROT11]]<br />
| 0x10000001<br />
| 1<br />
| Boot9<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG9_RST11|CFG9_RST11]]<br />
| 0x10000002<br />
| 1<br />
| Boot9<br />
|-<br />
| style="background: green" | Yes<br />
| CFG9_DEBUGCTL<br />
| 0x10000004<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10000008<br />
| 1<br />
| Boot9, Process9, TwlProcess9<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG9_CARDCTL|CFG9_CARDCTL]]<br />
| 0x1000000C<br />
| 2<br />
| Process9<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG9_CARDSTATUS|CFG9_CARDSTATUS]]<br />
| 0x10000010<br />
| 1<br />
| Process9<br />
|-<br />
| style="background: green" | Yes<br />
| CFG9_CARDCYCLES0<br />
| 0x10000012<br />
| 2<br />
| Boot9, Process9<br />
|-<br />
| style="background: green" | Yes<br />
| CFG9_CARDCYCLES1<br />
| 0x10000014<br />
| 2<br />
| Boot9, Process9<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10000020<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10000100<br />
| 2<br />
|<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG9_EXTMEMCNT9|CFG9_EXTMEMCNT9]]<br />
| 0x10000200<br />
| 1<br />
| NewKernel9<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG9_MPCORECFG|CFG9_MPCORECFG]]<br />
| 0x10000FFC<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG9_BOOTENV|CFG9_BOOTENV]]<br />
| 0x10010000<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG9_UNITINFO|CFG9_UNITINFO]]<br />
| 0x10010010<br />
| 1<br />
| Process9<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG9_TWLUNITINFO|CFG9_TWLUNITINFO]]<br />
| 0x10010014<br />
| 1<br />
| Process9<br />
|}<br />
<br />
== CFG9_SYSPROT9 ==<br />
CFG9_SYSPROT9 is used to permanently disable certain security-sensitive ARM9 memory areas until the next hard reset.<br />
<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| Disables ARM9 [[Memory_layout|bootrom]](+0x8000) when set to 1. Cannot be cleared to 0 once set to 1.<br />
| Boot9<br />
|-<br />
| 1<br />
| Disables [[OTP_Registers|OTP area]] when set to 1. Cannot be cleared to 0 once set to 1.<br />
| NewKernel9Loader, Process9<br />
|-<br />
| 31-2<br />
| Not used<br />
|<br />
|}<br />
<br />
On Old 3DS, NATIVE_FIRM reads CFG9_SYSPROT9 to know whether it has previously initialized the TWL console-unique keys using the OTP data. After setting the TWL console-unique keys, NATIVE_FIRM sets CFG9_SYSPROT9 bit 1 to disable the OTP area. In subsequent FIRM launches prior to the next reset, NATIVE_FIRM will see that the OTP area is disabled, and skip this step.<br />
<br />
On New 3DS, the above is instead done by the [[FIRM#New_3DS_FIRM|Kernel9 loader]]. In addition to using the OTP data for initializing the TWL console-unique keys, the Kernel9 loader will generate the decryption key for NATIVE_FIRM. The final keyslot for NATIVE_FIRM is preserved, so that at a non-reset FIRM launch, the keyslot can be reused, since the OTP would then be inaccessible.<br />
<br />
== CFG9_SYSPROT11 ==<br />
<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| Disables ARM11 [[Memory_layout|bootrom]](+0x8000) when set to 1. Cannot be cleared to 0 once set to 1.<br />
| Boot9<br />
|-<br />
| 31-1<br />
| Not used<br />
|<br />
|}<br />
<br />
== CFG9_RST11 ==<br />
<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| Presumably takes ARM11 out of reset. Cannot be set to 1 once it has been cleared.<br />
| Boot9<br />
|-<br />
| 31-1<br />
| Not used<br />
|<br />
|}<br />
<br />
== 0x10000008 ==<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
! Used by<br />
|-<br />
| 1-0<br />
| ?<br />
|<br />
|-<br />
| 3-2<br />
| AES related? Value 3 written after write to AES_CTL.<br />
| Boot9, Process9, TwlProcess9<br />
|-<br />
| 31-4<br />
| Reserved<br />
|<br />
|}<br />
<br />
== CFG9_CARDCTL ==<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
! Used by<br />
|-<br />
| 1-0<br />
| Gamecard active controller select (0=NTRCARD, 1=?, 2=CTRCARD0, 3=CTRCARD1)<br />
| Process9<br />
|-<br />
| 8<br />
| Enable gamecard eject IRQ, maybe?<br />
| Process9<br />
|}<br />
<br />
Depending on the gamecard controller that has been selected, one of the following gamecard registers will become active:<br />
* Selecting NTRCARD will activate the register space at [[NTRCARD|0x10164000]].<br />
* Selecting CTRCARD0 will activate the register space at [[CTRCARD|0x10004000]].<br />
* Selecting CTRCARD1 will activate the register space at [[CTRCARD|0x10005000]].<br />
<br />
== CFG9_CARDSTATUS ==<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| Cartridge-slot empty (0=inserted, 1=empty)<br />
| Process9<br />
|-<br />
| 3-2<br />
| ?<br />
| Process9<br />
|}<br />
<br />
== CFG9_EXTMEMCNT9 ==<br />
This register is New3DS-only.<br />
<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| Hide extended ARM9 memory (0=hidden, 1=shown)<br />
| Kernel9 (New3DS)<br />
|-<br />
| 31-1<br />
| Reserved<br />
|<br />
|}<br />
<br />
== CFG9_MPCORECFG ==<br />
Identical to [[PDN#PDN_MPCORE_CFG|PDN_MPCORE_CFG]].<br />
<br />
== CFG9_BOOTENV ==<br />
This register is used to determine what the previous running FIRM was. Its value is kept following an MCU reboot. Its initial value (on a cold boot) is 0. NATIVE_FIRM [[Development_Services_PXI|sets it to 1]] on shutdown/FIRM launch. [[Legacy_FIRM_PXI|LGY FIRM]] writes value 3 here when launching a TWL title, and writes value 7 when launching an AGB title.<br />
<br />
NATIVE_FIRM will only launch titles if this is not value 0, and will only save the [[Flash_Filesystem|AGB_FIRM savegame]] to SD if this is value 7.<br />
<br />
== CFG9_UNITINFO ==<br />
This 8-bit register is value zero for retail, non-zero for dev/debug units.<br />
<br />
== CFG9_TWLUNITINFO ==<br />
In the console-unique TWL key-init/etc function the ARM9 copies the u8 value from REG_UNITINFO to this register.<br />
<br />
This is also used by TWL_FIRM Process9.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=PDN_Registers&diff=19510
PDN Registers
2017-02-07T15:54:19Z
<p>Plutooo: Plutooo moved page PDN Registers to CONFIG11 Registers</p>
<hr />
<div>#REDIRECT [[CONFIG11 Registers]]</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG11_Registers&diff=19509
CONFIG11 Registers
2017-02-07T15:54:18Z
<p>Plutooo: Plutooo moved page PDN Registers to CONFIG11 Registers</p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#PDN_SHAREDWRAM_32K_DATA|PDN_SHAREDWRAM_32K_DATA]]<0-7><br />
| 0x10140000<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#PDN_SHAREDWRAM_32K_CODE|PDN_SHAREDWRAM_32K_CODE]]<0-7><br />
| 0x10140008<br />
| 1*8<br />
| Boot11, Process9, [[DSP Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140100<br />
| 2<br />
| <br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140102<br />
| 2<br />
| <br />
|-<br />
| style="background: green" | Yes<br />
| [[#PDN_FIQ_CNT|PDN_FIQ_CNT]]<br />
| 0x10140104<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140105<br />
| 1<br />
| Kernel11.<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x10140108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| Related to [[HID_Registers|HID_?]]<br />
| 0x1014010C<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140140<br />
| 4<br />
| Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| [[#PDN_WIFI_CNT|PDN_WIFI_CNT]]<br />
| 0x10140180<br />
| 1<br />
| TwlBg, [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#PDN_SPI_CNT|PDN_SPI_CNT]]<br />
| 0x101401C0<br />
| 4<br />
| [[SPI Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10140200<br />
| 4<br />
| <br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140400<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| Clock related?<br />
| 0x10140410<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#PDN_BOOTROM_OVERLAY_CNT|PDN_BOOTROM_OVERLAY_CNT]]<br />
| 0x10140420<br />
| 1<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#PDN_BOOTROM_OVERLAY_VAL|PDN_BOOTROM_OVERLAY_VAL]]<br />
| 0x10140424<br />
| 4<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| ?<br />
| 0x10140428<br />
| 4<br />
| <br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#PDN_SOCINFO|PDN_SOCINFO]]<br />
| 0x10140FFC<br />
| 2<br />
| Boot11, Kernel11<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| PDN_GPU_STATUS?<br />
| 0x10141000<br />
| 4<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| PDN_PTM_0<br />
| 0x10141008<br />
| 4<br />
| [[PTM Services]], [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| PDN_PTM_1<br />
| 0x1014100C<br />
| 4<br />
| [[PTM Services]], TwlBg, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#PDN_TWLMODE_0|PDN_TWLMODE_0]]<br />
| 0x10141100<br />
| 2<br />
| TwlProcess9, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#PDN_TWLMODE_1|PDN_TWLMODE_1]]<br />
| 0x10141104<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#PDN_TWLMODE_2|PDN_TWLMODE_2]]<br />
| 0x10141108<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#PDN_TWLMODE_HID|PDN_TWLMODE_HID]]<br />
| 0x1014110A<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| PDN_WIFI?<br />
| 0x1014110C<br />
| 1<br />
| [[NWM Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141110<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141112<br />
| 2<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#PDN_CODEC|PDN_CODEC_0]]<br />
| 0x10141114<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#PDN_CODEC|PDN_CODEC_1]]<br />
| 0x10141116<br />
| 2<br />
| [[CODEC Services]], TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141118<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141119<br />
| 1<br />
| TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10141120<br />
| 1<br />
| TwlBg<br />
|-<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#PDN_GPU_CNT|PDN_GPU_CNT]]<br />
| 0x10141200<br />
| 4<br />
| Boot11, Kernel11, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#PDN_GPU_CNT2|PDN_GPU_CNT2]]<br />
| 0x10141204<br />
| 4<br />
| Boot11, Kernel11<br />
|-<br />
| style="background: green" | Yes<br />
| PDN_GPU_CNT3<br />
| 0x10141210<br />
| 2<br />
| Kernel11, TwlBg<br />
|-<br />
| style="background: green" | Yes<br />
| [[#PDN_CODEC_CNT|PDN_CODEC_CNT]]<br />
| 0x10141220<br />
| 1<br />
| Boot11, TwlBg, [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| [[#PDN_CAMERA_CNT|PDN_CAMERA_CNT]]<br />
| 0x10141224<br />
| 1<br />
| [[PDN Services]]<br />
|-<br />
| style="background: green" | Yes<br />
| PDN_DSP_CNT<br />
| 0x10141230<br />
| 1<br />
| Process9, [[PDN Services]]<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| [[#PDN_MPCORE_CLKCNT|PDN_MPCORE_CLKCNT]]<br />
| 0x10141300<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#PDN_MPCORE_CNT|PDN_MPCORE_CNT]]<br />
| 0x10141304<br />
| 2<br />
| NewKernel11<br />
|-<br />
| style="background: red" | No<br />
| [[#PDN_MPCORE_BOOTCNT<0-3>|PDN_MPCORE_BOOTCNT]]<0-3><br />
| 0x10141310<br />
| 1*4<br />
| NewKernel11<br />
|}<br />
<br />
== PDN_SHAREDWRAM_32K_DATA ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/data)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== PDN_SHAREDWRAM_32K_CODE ==<br />
Used for mapping 32K chunks of shared WRAM for DSP data.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0-1<br />
| Master (0=ARM9?, 1=ARM11?, 2 or 3=DSP/code)<br />
|-<br />
| 2-4<br />
| Offset (0..7) (slot 0..7) (LSB of address in 32Kbyte units)<br />
|-<br />
| 5-6<br />
| Not used (0)<br />
|-<br />
| 7<br />
| Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== PDN_FIQ_CNT ==<br />
Writing bit1 to this register disables FIQ interrupts. <br />
<br />
This bit is set upon receipt of a FIQ interrupt and when [[SVC|svcUnbindInterrupt]] is called on the FIQ-abstraction [[ARM11_Interrupts#Private_Interrupts|software interrupt]] for the current core.<br />
It is cleared when binding that software interrupt to an event and just before that event is signaled.<br />
<br />
== PDN_SPI_CNT ==<br />
When the corresponding bit is 0, the bus has to be accessed using the DS SPI registers. Otherwise it has to be accessed using the 3DS SPI registers.<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
|-<br />
| 0<br />
| Enable [[SPI Registers]] 0x10160000.<br />
|-<br />
| 1<br />
| Enable [[SPI Registers]] 0x10142000.<br />
|-<br />
| 2<br />
| Enable [[SPI Registers]] 0x10143000.<br />
|}<br />
<br />
== PDN_BOOTROM_OVERLAY_CNT ==<br />
Bit0: Enable bootrom overlay functionality.<br />
<br />
== PDN_BOOTROM_OVERLAY_VAL ==<br />
The 32-bit value to overlay data-reads to bootrom with. See [[#PDN_MPCORE_BOOTCNT|PDN_MPCORE_BOOTCNT]].<br />
<br />
== PDN_SOCINFO ==<br />
Read-only register.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| 1 on both Old3DS and New3DS.<br />
| Boot11<br />
|-<br />
| 1<br />
| 1 on New3DS.<br />
| Kernel11<br />
|-<br />
| 2<br />
| Clock modifier: if set, use a 3x multiplier, otherwise 2x<br />
| Kernel11<br />
|}<br />
<br />
== PDN_MPCORE_CLKCNT ==<br />
This is used for configuring the New3DS ARM11 CPU clock-rate. This register is New3DS-only: reading from here on Old3DS always returns all-zeros even when one tried writing data here prior to the read.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable clock multiplier? This must be set to 1 before writing a non-zero value to bit1-2, otherwise freeze.<br />
|-<br />
| 1-2<br />
| Clock multiplier (0=1x, 1=2x, 2=3x, 3=hang)<br />
|-<br />
| 15<br />
| Busy<br />
|}<br />
<br />
[[SVC#KernelSetState|svcKernelSetState]] type10, only implemented on New3DS, uses this register. That code writes the following values to this register, depending on the input Param0 bit0 state, and the state of PDN_MPCORE_CFG:<br />
{| class="wikitable" border="1"<br />
! Register value<br />
! Higher-clockrate bit set in svcKernelSetState Param0<br />
! PDN_MPCORE_CFG bit2 set<br />
! MPCore timer/watchdog prescaler value, prior to subtracting it by 0x1 when writing it into hw/state<br />
! Clock-rate multiplier<br />
! Description<br />
|-<br />
| 0x01<br />
| No<br />
| Yes<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x02<br />
| No<br />
| No<br />
| 0x01<br />
| 1x<br />
| 268MHz<br />
|-<br />
| 0x05<br />
| Yes<br />
| Yes<br />
| 0x03<br />
| 3x<br />
| 804MHz<br />
|-<br />
| 0x03<br />
| Yes<br />
| No<br />
| 0x02<br />
| 2x<br />
| 536MHz (tested on New3DS)<br />
|}<br />
<br />
Note that the above PDN_MPCORE_CFG bit is 1 on New3DS, and 0 on Old3DS. Since this SVC is only available with the New3DS ARM11-kernel, the only additional available clock-rate is 804MHz when running on New3DS(with official kernel code).<br />
<br />
The following register value(s) were tested on New3DS by patching the kernel:<br />
* 0x00: Entire system hangs.<br />
* 0x02: Entire system hangs.<br />
* 0x03: ARM11 runs at 536MHz.<br />
* 0x04: Entire system hangs.<br />
* 0x06: Entire system hangs.<br />
* 0x07: Same result as 0x05.<br />
* 0x08: Entire system hangs.<br />
* 0x09: Entire system hangs.<br />
* 0x0A: Entire system hangs.<br />
* 0x0B: Same result as 0x03.<br />
* 0x0C: Entire system hangs.<br />
* 0x0D: Same result as 0x05.<br />
* 0x0E: Entire system hangs.<br />
* 0x0F: Same result as 0x05.<br />
* 0x1F, 0x2F, 0x4F, 0x8F, 0xFF: Same result as 0x05.<br />
<br />
== PDN_MPCORE_CNT ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Power on 3rd ARM11 MPCore maybe?<br />
|-<br />
| 8<br />
| Power on 4th ARM11 MPCore maybe?<br />
|}<br />
<br />
== PDN_MPCORE_BOOTCNT<0-3> ==<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Description<br />
|-<br />
| 0<br />
| Enable bootrom instruction overlay, maybe? This bit is only writable for core2 and core3.<br />
|-<br />
| 1<br />
| Enable bootrom data overlay. This bit is only writable for core2 and core3.<br />
|-<br />
| 4<br />
| Has core booted maybe?<br />
|-<br />
| 5<br />
| Always 1?<br />
|}<br />
<br />
The normal ARM11 bootrom checks cpuid and hangs if cpuid >= 2. This is a problem when booting the 2 additional New3DS ARM11 MPCores. NewKernel11 solves this by using a hardware feature to overlay the bootrom with a configurable branch to a kernel function. This overlay feature was added with the New3DS.<br />
<br />
Bit1 in register above enables a bootrom data-override for physical addresses 0xFFFF0000-0xFFFF1000 and 0x10000-0x11000. All _data reads_ made to those regions now read the 32-bit value provided in [[#PDN_BOOTROM_OVERLAY_VAL|PDN_BOOTROM_OVERLAY_VAL]].<br />
<br />
Bit0 enables a bootrom instruction-overlay which means that _instruction reads_ made to the bootrom region are overridden. We have not been able to dump what instructions are actually placed at bootrom by this switch (because reading the area only yields data-reads). Jumping randomly into the 0xFFFF0000-0xFFFF1000 region works fine and jumps to the value provided by the data overlay [[#PDN_BOOTROM_OVERLAY_VAL|PDN_BOOTROM_OVERLAY_VAL]]. Thus we may predict that the entire bootrom region is filled by:<br />
ldr pc, [pc]<br />
<br />
Or equivalent. However, jumping to some high addresses such as 0xFFFF0FF0+ will crash the core. This may be explained by prefetching in the ARM pipeline, and might help us identify what instructions are placed by the instruction-overlay.<br />
<br />
==0x10140140==<br />
Seems to control what memory GPU can access for DMA, this needs verified.<br />
<br />
[[SVC|Initialized]] during kernel boot, and used with [[SVC]] 0x59 which was implemented with v11.3.<br />
<br />
==PDN_WIFI_CNT==<br />
Bit0: Enable wifi.<br />
<br />
==PDN_TWLMODE_0==<br />
Observed 0x8001 when running under TWL_ and AGB_FIRM, 0 NATIVE_FIRM.<br />
<br />
This address is poked from ARM7 to signal that it has booted and begun executing code. The ARM7-mode address for this register is 0x4700000.<br />
<br />
The very last 3DS-mode register poke the [[FIRM|TWL_FIRM]] Process9 does before it gets switched into TWL-mode, is writing 0x8000 to this register. Before writing this register, TWL Process9 waits for ARM7 to change the value of this register. The Process9 code for this runs from ITCM, since switching into TWL-mode includes remapping all ARM9 physical memory.<br />
<br />
Writing 0x8000 to here from the ARM9 with NATIVE_FIRM running doesn't seem to do anything, other reg-pokes likely need done first.<br />
<br />
==PDN_TWLMODE_1==<br />
Observed 0x8000 when running under TWL_FIRM, 0 NATIVE_FIRM.<br />
<br />
==PDN_TWLMODE_2==<br />
Bitfield.<br />
<br />
==PDN_TWLMODE_HID==<br />
The value of this register is copied to [[HID_Registers|HID_?]] under certain conditions.<br />
<br />
==PDN_WIFI?==<br />
Bit4=unknown enabled by NWM on launch. Potentially powers on wifi card.<br />
<br />
==PDN_GPU_CNT==<br />
This one seems to control the LCD/GPU/Backlight.<br />
<br />
Bit0: Enable GPU registers at 0x10400000+.<br />
Bit16: Turn on LCD backlight.<br />
<br />
==PDN_GPU_CNT2==<br />
Bit0: Power on GPU?<br />
<br />
==PDN_GPU_CNT3==<br />
Bit1: FCRAM access from ARM11? Clearing this bit in 3DS-mode causes the ARM11 and ARM9 to hang/crash.<br />
<br />
==PDN_CODEC==<br />
The following is the only time the ARM11 CODEC module uses any 0x1EC41XXX registers. In one case CODEC module clears bit1 in register 0x1EC41114, in the other case CODEC module sets bit1 in registers 0x1EC41114 and 0x1EC41116.<br />
<br />
==PDN_CODEC_CNT==<br />
This is the power register used for the [[PDN_Services|PDN]] CODEC service.<br />
<br />
bit0 = unknown, bit1 = turn on/off DSP, rest = always 0.<br />
<br />
==PDN_CAMERA_CNT==<br />
This is the power register used for the [[PDN_Services|PDN]] camera service.<br />
<br />
bit0 = unknown, bit1 = turn on/off cameras, rest = always 0.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG_Registers&diff=19508
CONFIG Registers
2017-02-07T15:54:00Z
<p>Plutooo: Plutooo moved page CONFIG Registers to CONFIG9 Registers</p>
<hr />
<div>#REDIRECT [[CONFIG9 Registers]]</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=CONFIG9_Registers&diff=19507
CONFIG9 Registers
2017-02-07T15:54:00Z
<p>Plutooo: Plutooo moved page CONFIG Registers to CONFIG9 Registers</p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG_SYSPROT9|CFG_SYSPROT9]]<br />
| 0x10000000<br />
| 1<br />
| Boot9<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG_SYSPROT11|CFG_SYSPROT11]]<br />
| 0x10000001<br />
| 1<br />
| Boot9<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG_RST11|CFG_RST11]]<br />
| 0x10000002<br />
| 1<br />
| Boot9<br />
|-<br />
| style="background: green" | Yes<br />
| CFG_DEBUGCTL<br />
| 0x10000004<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10000008<br />
| 1<br />
| Boot9, Process9, TwlProcess9<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG_CARDCTL|CFG_CARDCTL]]<br />
| 0x1000000C<br />
| 2<br />
| Process9<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG_CARDSTATUS|CFG_CARDSTATUS]]<br />
| 0x10000010<br />
| 1<br />
| Process9<br />
|-<br />
| style="background: green" | Yes<br />
| CFG_CARDCYCLES0<br />
| 0x10000012<br />
| 2<br />
| Boot9, Process9<br />
|-<br />
| style="background: green" | Yes<br />
| CFG_CARDCYCLES1<br />
| 0x10000014<br />
| 2<br />
| Boot9, Process9<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10000020<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| ?<br />
| 0x10000100<br />
| 2<br />
|<br />
|-<br />
| style="background: red" | No<br />
| [[#CFG_EXTMEMCNT9|CFG_EXTMEMCNT9]]<br />
| 0x10000200<br />
| 1<br />
| NewKernel9<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG_MPCORECFG|CFG_MPCORECFG]]<br />
| 0x10000FFC<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG_BOOTENV|CFG_BOOTENV]]<br />
| 0x10010000<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG_UNITINFO|CFG_UNITINFO]]<br />
| 0x10010010<br />
| 1<br />
| Process9<br />
|-<br />
| style="background: green" | Yes<br />
| [[#CFG_TWLUNITINFO|CFG_TWLUNITINFO]]<br />
| 0x10010014<br />
| 1<br />
| Process9<br />
|}<br />
<br />
== CFG_SYSPROT9 == <br />
CFG_SYSPROT9 is used to permanently disable certain security-sensitive ARM9 memory areas until the next hard reset.<br />
<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| Disables ARM9 [[Memory_layout|bootrom]](+0x8000) when set to 1. Cannot be cleared to 0 once set to 1.<br />
| Boot9<br />
|-<br />
| 1<br />
| Disables [[OTP_Registers|OTP area]] when set to 1. Cannot be cleared to 0 once set to 1.<br />
| NewKernel9Loader, Process9<br />
|-<br />
| 31-2<br />
| Not used<br />
|<br />
|}<br />
<br />
On Old 3DS, NATIVE_FIRM reads CFG_SYSPROT9 to know whether it has previously initialized the TWL console-unique keys using the OTP data. After setting the TWL console-unique keys, NATIVE_FIRM sets CFG_SYSPROT9 bit 1 to disable the OTP area. In subsequent FIRM launches prior to the next reset, NATIVE_FIRM will see that the OTP area is disabled, and skip this step.<br />
<br />
On New 3DS, the above is instead done by the [[FIRM#New_3DS_FIRM|Kernel9 loader]]. In addition to using the OTP data for initializing the TWL console-unique keys, the Kernel9 loader will generate the decryption key for NATIVE_FIRM. The final keyslot for NATIVE_FIRM is preserved, so that at a non-reset FIRM launch, the keyslot can be reused, since the OTP would then be inaccessible.<br />
<br />
== CFG_SYSPROT11 == <br />
<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| Disables ARM11 [[Memory_layout|bootrom]](+0x8000) when set to 1. Cannot be cleared to 0 once set to 1.<br />
| Boot9<br />
|-<br />
| 31-1<br />
| Not used<br />
|<br />
|}<br />
<br />
== CFG_RST11 == <br />
<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| Presumably takes ARM11 out of reset. Cannot be set to 1 once it has been cleared.<br />
| Boot9<br />
|-<br />
| 31-1<br />
| Not used<br />
|<br />
|}<br />
<br />
== 0x10000008 ==<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
! Used by<br />
|-<br />
| 1-0<br />
| ?<br />
|<br />
|-<br />
| 3-2<br />
| AES related? Value 3 written after write to AES_CTL.<br />
| Boot9, Process9, TwlProcess9<br />
|-<br />
| 31-4<br />
| Reserved<br />
|<br />
|}<br />
<br />
== CFG_CARDCTL ==<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
! Used by<br />
|-<br />
| 1-0<br />
| Gamecard active controller select (0=NTRCARD, 1=?, 2=CTRCARD0, 3=CTRCARD1)<br />
| Process9<br />
|-<br />
| 8<br />
| Enable gamecard eject IRQ, maybe?<br />
| Process9<br />
|}<br />
<br />
Depending on the gamecard controller that has been selected, one of the following gamecard registers will become active:<br />
* Selecting NTRCARD will activate the register space at [[NTRCARD|0x10164000]].<br />
* Selecting CTRCARD0 will activate the register space at [[CTRCARD|0x10004000]].<br />
* Selecting CTRCARD1 will activate the register space at [[CTRCARD|0x10005000]].<br />
<br />
== CFG_CARDSTATUS ==<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| Cartridge-slot empty (0=inserted, 1=empty)<br />
| Process9<br />
|-<br />
| 3-2<br />
| ?<br />
| Process9<br />
|}<br />
<br />
== CFG_EXTMEMCNT9 ==<br />
This register is New3DS-only.<br />
<br />
{| class="wikitable" border="1"<br />
! Bit<br />
! Description<br />
! Used by<br />
|-<br />
| 0<br />
| Hide extended ARM9 memory (0=hidden, 1=shown)<br />
| Kernel9 (New3DS)<br />
|-<br />
| 31-1<br />
| Reserved<br />
|<br />
|}<br />
<br />
== CFG_MPCORECFG ==<br />
Identical to [[PDN#PDN_MPCORE_CFG|PDN_MPCORE_CFG]].<br />
<br />
== CFG_BOOTENV ==<br />
This register is used to determine what the previous running FIRM was. Its value is kept following an MCU reboot. Its initial value (on a cold boot) is 0. NATIVE_FIRM [[Development_Services_PXI|sets it to 1]] on shutdown/FIRM launch. [[Legacy_FIRM_PXI|LGY FIRM]] writes value 3 here when launching a TWL title, and writes value 7 when launching an AGB title.<br />
<br />
NATIVE_FIRM will only launch titles if this is not value 0, and will only save the [[Flash_Filesystem|AGB_FIRM savegame]] to SD if this is value 7.<br />
<br />
== CFG_UNITINFO ==<br />
This 8-bit register is value zero for retail, non-zero for dev/debug units.<br />
<br />
== CFG_TWLUNITINFO ==<br />
In the console-unique TWL key-init/etc function the ARM9 copies the u8 value from REG_UNITINFO to this register.<br />
<br />
This is also used by TWL_FIRM Process9.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=IO_Registers&diff=19506
IO Registers
2017-02-07T15:53:35Z
<p>Plutooo: </p>
<hr />
<div>= Overview =<br />
<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! A9/A11<br />
! Category<br />
! Physaddr<br />
! Used by<br />
! Comments<br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| [[CONFIG9 Registers]]<br />
| 0x10000000<br />
| Boot9, Process9<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| [[IRQ Registers]]<br />
| 0x10001000<br />
| Boot9, Process9, Kernel9<br />
| ARM9 Interrupt Masking<br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| [[NDMA Registers]]<br />
| 0x10002000<br />
| Boot9, Process9<br />
| DMA Engine<br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| [[TIMER Registers]]<br />
| 0x10003000<br />
| Boot9, Process9<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| [[CTRCARD Registers]]<br />
| 0x10004000 / 0x10005000<br />
| Process9<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| [[EMMC Registers]]<br />
| 0x10006000 / 0x10007000<br />
| Boot9, Process9, NewKernel9Loader<br />
| 0x10007000 is normally not enabled on retail, all-zeros when read.<br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| [[PXI Registers]]<br />
| 0x10008000<br />
| Boot9, Process9<br />
| <br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| [[AES Registers]]<br />
| 0x10009000<br />
| Boot9, Process9, NewKernel9Loader<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| [[SHA Registers]]<br />
| 0x1000A000<br />
| Boot9, Process9, NewKernel9Loader<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| [[RSA Registers]]<br />
| 0x1000B000<br />
| Boot9, Process9<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| [[Corelink DMA Engines|XDMA Registers]]<br />
| 0x1000C000<br />
| Boot9, Kernel9<br />
| [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424d/index.html CoreLink™ DMA-330] (single-channel).<br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| [[SPICARD Registers]]<br />
| 0x1000D800<br />
| Process9<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| A9<br />
| [[CONFIG Registers]]<br />
| 0x10010000<br />
| Process9<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| PRNG Registers<br />
| 0x10011000<br />
| Boot9, Process9<br />
| Used as entropy-source for seeding random number generators.<br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| [[OTP Registers]]<br />
| 0x10012000<br />
| Boot9, Kernel9, NewKernel9Loader<br />
| Top secret.<br />
|-<br />
| style="background: green" | Yes<br />
| A9<br />
| [[ARM7|ARM7 Registers]]<br />
| 0x10018000<br />
| TwlProcess9<br />
| Used to setup the ARM7 core for AGB/TWL<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| Debug WIFI SDIO Registers?<br />
| 0x10100000<br />
| <br />
| An SDIO controller is mapped here, NWM references this controller but doesn't have access to it.<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[HASH Registers]]<br />
| 0x10101000<br />
| [[Filesystem services]]<br />
| <br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[Y2R Registers]]<br />
| 0x10102000<br />
| [[Camera Services]]<br />
| y2r<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[CSND Registers]] / [[DSP Registers]]<br />
| 0x10103000<br />
| TwlBg, [[Codec Services]], [[CSND Services]], [[DSP Services]]<br />
| Sound hardware. For DSP regs, see the "DSi XpertTeak" section in [http://problemkaputt.de/gba.htm no$gba] help.<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| LGYFB0<br />
| 0x10110000<br />
| TwlBg<br />
| IO registers used to access legacy output framebuffer, as well as configure the upscaling filter.<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| LGYFB1<br />
| 0x10111000<br />
| TwlBg<br />
| IO registers used to access legacy output framebuffer, as well as configure the upscaling filter.<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[Camera Registers]] <br />
| 0x10120000<br />
| [[Camera Services]]<br />
| <br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[Camera Registers]]<br />
| 0x10121000<br />
| [[Camera Services]]<br />
| Mirror of 0x10120000?<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[WIFI Registers]]<br />
| 0x10122000<br />
| [[NWM Services]]<br />
| WIFI SDIO bus registers<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| ?<br />
| 0x10123000<br />
| [[NWM Services]]<br />
| WIFI?<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| A11/A9<br />
| [[MVD Registers]]<br />
| 0x10130000<br />
| [[MVD Services]]<br />
| <br />
|-<br />
| style="background: red" | No<br />
| A11/A9<br />
| [[MVD Registers]]<br />
| 0x10131000<br />
| [[MVD Services]]<br />
| <br />
|-<br />
| style="background: red" | No<br />
| A11/A9<br />
| [[MVD Registers]]<br />
| 0x10132000<br />
| [[MVD Services]]<br />
| <br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[CONFIG11 Registers]]<br />
| 0x10140000<br />
| Process9, Boot11, Kernel11, TwlBg, [[DSP Services]], [[NWM Services]], [[SPI Services]]<br />
| Power management. <br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[CONFIG11 Registers]]<br />
| 0x10141000<br />
| Process9, Boot11, Kernel11, TwlBg, [[Codec Services]], [[NWM Services]], [[SPI Services]], [[PDN Services]]<br />
| Power management<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[SPI Registers]]<br />
| 0x10142000<br />
| TwlBg, [[SPI Services]]<br />
| <br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[SPI Registers]]<br />
| 0x10143000<br />
| TwlBg, dmnt Module<br />
| Debugger related?<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[I2C Registers]]<br />
| 0x10144000<br />
| Boot11, Kernel11, TwlBg, [[I2C Services]]<br />
| 3DS I2C interface (MCU + Cameras + LCD)<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[CODEC Registers]]<br />
| 0x10145000<br />
| TwlBg, [[Codec Services]]<br />
| <br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[HID Registers]]<br />
| 0x10146000<br />
| Boot9, Boot11, Kernel11, TwlBg, [[HID Services]], dlp Services<br />
| See [[PAD]].<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[GPIO Registers]]<br />
| 0x10147000<br />
| Boot11, TwlBg, [[GPIO Services]], [[DSP Services]](v0)<br />
| <br />
|- <br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[I2C Registers]]<br />
| 0x10148000<br />
| TwlBg, [[I2C Services]]<br />
| 3DS I2C interface (Gyro + IR)<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[SPI Registers]]<br />
| 0x10160000<br />
| Boot9, TwlBg, [[SPI Services]]<br />
| <br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[I2C Registers]]<br />
| 0x10161000<br />
| Boot11, TwlBg, [[I2C Services]]<br />
| TWL I2C interface (MCU + Cameras)<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[MIC Registers]]<br />
| 0x10162000<br />
| [[MIC Services]]<br />
| <br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[PXI Registers]]<br />
| 0x10163000<br />
| Boot11, Kernel11, TwlBg, [[PXI Services]]<br />
| <br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[NTRCARD Registers]]<br />
| 0x10164000<br />
| Boot9, Process9<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[MP Registers]]<br />
| 0x10165000<br />
| [[MP Services]]<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[MP Registers]]<br />
| 0x10170000<br />
| [[MP Services]]<br />
| NTR WIFI Registers, see [http://problemkaputt.de/gbatek.htm#dswirelesscommunications GBATek].<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[MP Registers]]<br />
| 0x10171000<br />
| [[MP Services]]<br />
| NTR WIFI Registers (mirror)<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
|?<br />
| 0x10172000<br />
|?<br />
| NTR WIFI Unused?<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
|?<br />
| 0x10173000<br />
|?<br />
| NTR WIFI Unused?<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[MP Registers]]<br />
| 0x10174000<br />
| [[MP Services]]<br />
| NTR WIFI RAM<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[MP Registers]]<br />
| 0x10175000<br />
|?<br />
| NTR WIFI RAM<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[MP Registers]]<br />
| 0x10176000<br />
|?<br />
| NTR WIFI Registers (mirror)<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[MP Registers]]<br />
| 0x10177000<br />
|?<br />
| NTR WIFI Registers (mirror)<br />
|-<br />
| style="background: green" | Yes<br />
| A11/A9<br />
| [[MP Registers]]<br />
| 0x10178000 - 0x10180000<br />
| [[MP Services]]<br />
| NTR WIFI WS1 Region<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| A11<br />
| [[Corelink DMA Engines|CDMA]]<br />
| 0x10200000<br />
| Boot11, Kernel11<br />
| [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424d/index.html CoreLink™ DMA-330]. Only used by bootrom on New3DS.<br />
|-<br />
| style="background: green" | Yes<br />
| A11<br />
| ?<br />
| 0x10201000<br />
| TwlBg<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| A11<br />
| [[LCD Registers]]<br />
| 0x10202000<br />
| TwlBg, Kernel11, [[GSP Services]]<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| A11<br />
| [[DSP Registers]]<br />
| 0x10203000<br />
| [[DSP Services]]<br />
| <br />
|-<br />
| style="background: green" | Yes<br />
| A11<br />
| ?<br />
| 0x10204000<br />
| <br />
|<br />
|-style="border-top: double"<br />
| style="background: red" | No<br />
| A11<br />
| [[Corelink DMA Engines|CDMA]]<br />
| 0x10206000<br />
| NewKernel11<br />
| CDMA was moved (mirrored?) here on New 3DS. [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0424d/index.html CoreLink™ DMA-330].<br />
|-<br />
| style="background: red" | No<br />
| A11<br />
| [[MVD Registers]]<br />
| 0x10207000<br />
| [[MVD Services]]<br />
| New 3DS only?<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| A11<br />
| AXI<br />
| 0x1020F000<br />
| TwlBg, [[GSP Services]]<br />
| [http://infocenter.arm.com/help/topic/com.arm.doc.ddi0422a/CHDGHIID.html CoreLink™ NIC-301 r1p0].<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| A11<br />
| DMA region<br />
| 0x10300000-0x10400000<br />
|<br />
| CDMA wants these addresses. Each page in this region corresponds to the same page in the 0x10100000-0x10200000 region. It is unknown if this is just a separate bus and/or if there are any differences in the registers.<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| A11<br />
| [[GPU/External_Registers|GPU Registers]]<br />
| 0x10400000<br />
| Boot11, Kernel11, [[GSP Services]]<br />
||<br />
|}<br />
<br />
IO registers starting at physical address 0x10200000 are not accessible from the ARM9 (which includes all LCD/GPU registers). It seems IO registers below physical address 0x10100000 are not accessible from the ARM11 bus.<br />
<br />
ARM11 kernel virtual address mappings for these registers varies for different builds. For ARM11 user mode applications you have:<br />
physaddr = virtaddr - 0x1EC00000 + 0x10100000</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=SPI_Registers&diff=19449
SPI Registers
2017-01-29T09:57:22Z
<p>Plutooo: /* SPI_CNT */</p>
<hr />
<div>= Registers =<br />
{| class="wikitable" border="1"<br />
! Old3DS<br />
! Name<br />
! Address<br />
! Width<br />
! Used by<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_CNT|SPI_CNT]]0<br />
| 0x10142000<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| SPI_DATA0<br />
| 0x10142002<br />
| 1 <br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]0<br />
| 0x10142800<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_DONE|SPI_NEW_DONE]]0<br />
| 0x10142804<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]0<br />
| 0x10142808<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]0<br />
| 0x1014280C<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]0<br />
| 0x10142810<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#SPI_CNT|SPI_CNT]]1<br />
| 0x10143000<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| SPI_DATA1<br />
| 0x10143002<br />
| 1 <br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]1<br />
| 0x10143800<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_DONE|SPI_NEW_DONE]]1<br />
| 0x10143804<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]1<br />
| 0x10143808<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]1<br />
| 0x1014380C<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]1<br />
| 0x10143810<br />
| 4<br />
|<br />
|-style="border-top: double"<br />
| style="background: green" | Yes<br />
| [[#SPI_CNT|SPI_CNT]]2<br />
| 0x10160000<br />
| 2<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| SPI_DATA2<br />
| 0x10160002<br />
| 1 <br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_CNT|SPI_NEW_CNT]]2<br />
| 0x10160800<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_DONE|SPI_NEW_DONE]]2<br />
| 0x10160804<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_BLKLEN|SPI_NEW_BLKLEN]]2<br />
| 0x10160808<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_FIFO|SPI_NEW_FIFO]]2<br />
| 0x1016080C<br />
| 4<br />
|<br />
|-<br />
| style="background: green" | Yes<br />
| [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]2<br />
| 0x10160810<br />
| 4<br />
|<br />
|}<br />
<br />
== SPI_CNT ==<br />
This is the old NDS/DSi SPI interface.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Name<br />
|-<br />
| 0-1<br />
| Baudrate (0=4MHz, 1=2MHz, 2=1MHz, 3=512KHz)<br />
|-<br />
| 2-6<br />
| This was added with 3DS.<br />
|-<br />
| 7<br />
| Busy Flag (0=Ready, 1=Busy) (presumably Read-only)<br />
|- <br />
| 8-9<br />
| Device Select (0=Powerman., 1=Firmware, 2=Touchscreen)<br />
|-<br />
| 10<br />
| Transfer Size (0=8bit/Normal, 1=16bit/Bugged)<br />
|-<br />
| 11<br />
| Chipselect Hold (0=Deselect after transfer, 1=Keep selected)<br />
|-<br />
| 12-13<br />
| Not used (Zero)<br />
|-<br />
| 14<br />
| Interrupt Request (0=Disable, 1=Enable)<br />
|-<br />
| 15<br />
| SPI Bus Enable (0=Disable, 1=Enable)<br />
|}<br />
<br />
== SPI_NEW_CNT ==<br />
This is an alternative faster interface introduced with the 3DS.<br />
<br />
{| class="wikitable" border="1"<br />
! Bits<br />
! Name<br />
|-<br />
| 0-5<br />
| Baudrate?<br />
|-<br />
| 6-7<br />
| Device Select<br />
|-<br />
| 13<br />
| Transfer Direction? (0=Incoming, 1=Outgoing)<br />
|-<br />
| 15<br />
| Busy/enable<br />
|}<br />
<br />
{| class="wikitable" border="1"<br />
! Device id<br />
! Device select bits<br />
|-<br />
| 0, 3, >=6<br />
| 0<br />
|-<br />
| 1, 4<br />
| 1<br />
|-<br />
| 2, 5<br />
| 2<br />
|}<br />
<br />
{| class="wikitable" border="1"<br />
! Device id<br />
! Used baudrate<br />
|-<br />
| 3<br />
| 5<br />
|-<br />
| 0<br />
| 2<br />
|}<br />
<br />
== SPI_NEW_DONE ==<br />
When the transfer is finished, a 0 has to be written to this register.<br />
<br />
==SPI_NEW_BLKLEN==<br />
The number of bytes to be sent/read is written to this register.<br />
<br />
==SPI_NEW_FIFO==<br />
32-bit FIFO for reading/writing the SPI payload.<br />
<br />
==SPI_NEW_STATUS==<br />
Bit0: FIFO busy.</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19447
Pinouts
2017-01-28T23:29:13Z
<p>Plutooo: </p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | 0? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | 1? || style="background: #cc9900" | 2? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | 3? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #73e600" | ? || style="background: #476b6b" | 3? || style="background: #476b6b" | 4? || style="background: #476b6b" | 5? || || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #73e600" | ? || style="background: #8efab4" | SDA || style="background: #476b6b" | 1? || style="background: #476b6b" | 2? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #8efab4" | SCL || style="background: #476b6b" | 0? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC0 (unknown)<br />
|-<br />
| style="background: #476b6b" | CODEC1 (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | + || style="background: #d9ffb3" | + || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTHM || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || PWRBTN || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}<br />
<br />
== CODEC ==<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:36%;"<br />
| || style="background: #476b6b" | 4? || 3v3 || || style="background: #cc9900" | 3? || style="background: #cc9900" | 0? || style="background: #336600" | ? || style="background: #336600" | ? || || G ||<br />
|-<br />
| || style="background: #476b6b" | 3? || style="background: #476b6b" | 5? || G || || style="background: #cc9900" | 1? || style="background: #336600" | CSx || style="background: #336600" | ? || || G ||<br />
|-<br />
| G || style="background: #476b6b" | 2? || style="background: #476b6b" | 0? || G || || style="background: #cc9900" | 2? || style="background: #336600" | CSy || || || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || style="background: #476b6b" | 1? || G || G || G || G || G || G || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| CPAD || CPAD || || G || G || G || G || G || G || ||<br />
|-<br />
| || || || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| MIC || || G || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| JACK_R || G || G || || G || || || || || || G<br />
|-<br />
| 3v3 || || || || G || G || G || G || || ||<br />
|-<br />
| || || G || || || || JACK_L || || G || G ||<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19446
Pinouts
2017-01-28T23:22:32Z
<p>Plutooo: </p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | 0? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | 1? || style="background: #cc9900" | 2? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | 3? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || + || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #73e600" | ? || style="background: #476b6b" | 3? || style="background: #476b6b" | 4? || style="background: #476b6b" | 5? || || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #73e600" | ? || style="background: #8efab4" | SDA || style="background: #476b6b" | 1? || style="background: #476b6b" | 2? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #8efab4" | SCL || style="background: #476b6b" | 0? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC0 (unknown)<br />
|-<br />
| style="background: #476b6b" | CODEC1 (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | + || style="background: #d9ffb3" | + || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTHM || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || PWRBTN || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}<br />
<br />
== CODEC ==<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:36%;"<br />
| || style="background: #476b6b" | 4? || 3v3 || || style="background: #cc9900" | 3? || style="background: #cc9900" | 0? || style="background: #336600" | ? || style="background: #336600" | ? || || G ||<br />
|-<br />
| || style="background: #476b6b" | 3? || style="background: #476b6b" | 5? || G || || style="background: #cc9900" | 1? || style="background: #336600" | CSx || style="background: #336600" | ? || || G ||<br />
|-<br />
| G || style="background: #476b6b" | 2? || style="background: #476b6b" | 0? || G || || style="background: #cc9900" | 2? || style="background: #336600" | CSy || || || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || style="background: #476b6b" | 1? || G || G || G || G || G || G || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| CPAD || CPAD || || G || G || G || G || G || G || ||<br />
|-<br />
| || || || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| MIC || || G || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| JACK_R || G || G || || G || || || || || || G<br />
|-<br />
| 3v3 || || || || G || G || G || G || || ||<br />
|-<br />
| || || G || || || || JACK_L || || G || G ||<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19445
Pinouts
2017-01-28T23:13:07Z
<p>Plutooo: </p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | 0? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | 1? || style="background: #cc9900" | 2? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | 3? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || + || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #73e600" | ? || style="background: #476b6b" | 3? || style="background: #476b6b" | 4? || style="background: #476b6b" | 5? || || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #73e600" | ? || style="background: #8efab4" | SDA || style="background: #476b6b" | 1? || style="background: #476b6b" | 2? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #8efab4" | SCL || style="background: #476b6b" | 0? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC0 (unknown)<br />
|-<br />
| style="background: #476b6b" | CODEC1 (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | + || style="background: #d9ffb3" | + || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTHM || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || PWRBTN || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}<br />
<br />
== CODEC ==<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:36%;"<br />
| || style="background: #476b6b" | 4? || 3v3 || || style="background: #cc9900" | 3? || style="background: #cc9900" | 0? || || || || G ||<br />
|-<br />
| || style="background: #476b6b" | 3? || style="background: #476b6b" | 5? || G || || style="background: #cc9900" | 1? || || || || G ||<br />
|-<br />
| G || style="background: #476b6b" | 2? || style="background: #476b6b" | 0? || G || || style="background: #cc9900" | 2? || || || || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || style="background: #476b6b" | 1? || G || G || G || G || G || G || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| CPAD || CPAD || || G || G || G || G || G || G || ||<br />
|-<br />
| || || || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| MIC || || G || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| JACK_R || G || G || || G || || || || || || G<br />
|-<br />
| 3v3 || || || || G || G || G || G || || ||<br />
|-<br />
| || || G || || || || JACK_L || || G || G ||<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19444
Pinouts
2017-01-28T22:03:16Z
<p>Plutooo: if anyone is bored please color the grounds</p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | 0? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | 1? || style="background: #cc9900" | 2? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | 3? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || + || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #73e600" | ? || style="background: #476b6b" | 3? || style="background: #476b6b" | 4? || style="background: #476b6b" | 5? || || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #73e600" | ? || style="background: #8efab4" | SDA || style="background: #476b6b" | 1? || style="background: #476b6b" | 2? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #8efab4" | SCL || style="background: #476b6b" | 0? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC0 (unknown)<br />
|-<br />
| style="background: #476b6b" | CODEC1 (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | + || style="background: #d9ffb3" | + || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTHM || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || PWRBTN || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}<br />
<br />
== CODEC ==<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:36%;"<br />
| || style="background: #476b6b" | 4? || 3v3 || || style="background: #cc9900" | 3? || style="background: #cc9900" | 0? || || || || G ||<br />
|-<br />
| || style="background: #476b6b" | 3? || style="background: #476b6b" | 5? || G || || style="background: #cc9900" | 1? || || || || G ||<br />
|-<br />
| G || style="background: #476b6b" | 2? || style="background: #476b6b" | 0? || G || || style="background: #cc9900" | 2? || || || || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || style="background: #476b6b" | 1? || G || G || G || G || G || G || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| CPAD || CPAD || || G || G || G || G || G || G || ||<br />
|-<br />
| || || || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| MIC || || G || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| JACK_R || G || G || || G || || || || || || G<br />
|-<br />
| 3v3 || || || || G || G || G || G || || ||<br />
|-<br />
| || || G || || || || JACK_L || || G || G ||<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19441
Pinouts
2017-01-28T17:56:23Z
<p>Plutooo: </p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | 0? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | 1? || style="background: #cc9900" | 2? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | 3? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || + || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #73e600" | ? || style="background: #476b6b" | 3? || style="background: #476b6b" | 4? || style="background: #476b6b" | 5? || || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #73e600" | ? || style="background: #8efab4" | SDA || style="background: #476b6b" | 1? || style="background: #476b6b" | 2? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || style="background: #8efab4" | SCL || style="background: #476b6b" | 0? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC0 (unknown)<br />
|-<br />
| style="background: #476b6b" | CODEC1 (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | + || style="background: #d9ffb3" | + || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTHM || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || PWRBTN || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}<br />
<br />
== CODEC ==<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:36%;"<br />
| || style="background: #476b6b" | 4? || 3v3 || || style="background: #cc9900" | 3? || style="background: #cc9900" | 0? || || || || G ||<br />
|-<br />
| || style="background: #476b6b" | 3? || style="background: #476b6b" | 5? || G || || style="background: #cc9900" | 1? || || || || G ||<br />
|-<br />
| G || style="background: #476b6b" | 2? || style="background: #476b6b" | 0? || G || || style="background: #cc9900" | 2? || || || || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || 1? || G || G || G || G || G || G || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| CPAD || CPAD || || G || G || G || G || G || G || ||<br />
|-<br />
| || || || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| MIC || || G || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| JACK_R || G || G || || G || || || || || || G<br />
|-<br />
| 3v3 || || || || G || G || G || G || || ||<br />
|-<br />
| || || G || || || || JACK_L || || G || G ||<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19438
Pinouts
2017-01-28T13:57:11Z
<p>Plutooo: /* CODEC */</p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | 0? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | 1? || style="background: #cc9900" | 2? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | 3? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || + || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || style="background: #73e600" | ? || style="background: #476b6b" | 3? || style="background: #476b6b" | 4? || style="background: #476b6b" | 5? || || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || || || || || || || || style="background: #73e600" | ? || style="background: #8efab4" | SDA || style="background: #476b6b" | 1? || style="background: #476b6b" | 2? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || || || || || style="background: #b19cd9" | ? || style="background: #8efab4" | SCL || style="background: #476b6b" | 0? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC0 (unknown)<br />
|-<br />
| style="background: #476b6b" | CODEC1 (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | + || style="background: #d9ffb3" | + || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTHM || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || PWRBTN || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}<br />
<br />
== CODEC ==<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:36%;"<br />
| || style="background: #476b6b" | 4? || 3v3 || || style="background: #cc9900" | 3? || style="background: #cc9900" | 0? || || || || G ||<br />
|-<br />
| || style="background: #476b6b" | 3? || style="background: #476b6b" | 5? || G || || style="background: #cc9900" | 1? || || || || G ||<br />
|-<br />
| G || style="background: #476b6b" | 2? || style="background: #476b6b" | 0? || G || || style="background: #cc9900" | 2? || || || || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || 1? || G || G || G || G || G || G || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| CPAD || CPAD || || G || G || G || G || G || G || ||<br />
|-<br />
| || || || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| MIC || || G || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| JACK_R || G || G || || G || || || || || || G<br />
|-<br />
| 3v3 || || || || G || G || G || G || || ||<br />
|-<br />
| || || G || || || || JACK_L || || G || G ||<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19437
Pinouts
2017-01-28T13:46:31Z
<p>Plutooo: </p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | 0? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | 1? || style="background: #cc9900" | 2? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | 3? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || + || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || style="background: #73e600" | ? || style="background: #476b6b" | 3? || style="background: #476b6b" | 4? || style="background: #476b6b" | 5? || || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || || || || || || || || style="background: #73e600" | ? || style="background: #8efab4" | SDA || style="background: #476b6b" | 1? || style="background: #476b6b" | 2? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || || || || || style="background: #b19cd9" | ? || style="background: #8efab4" | SCL || style="background: #476b6b" | 0? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC0 (unknown)<br />
|-<br />
| style="background: #476b6b" | CODEC1 (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | + || style="background: #d9ffb3" | + || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTHM || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || PWRBTN || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}<br />
<br />
== CODEC ==<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:36%;"<br />
| || style="background: #476b6b" | 4? || || || style="background: #cc9900" | 3? || style="background: #cc9900" | 0? || || || || G ||<br />
|-<br />
| || style="background: #476b6b" | 3? || style="background: #476b6b" | 5? || G || || style="background: #cc9900" | 1? || || || || G ||<br />
|-<br />
| G || style="background: #476b6b" | 2? || style="background: #476b6b" | 0? || G || || style="background: #cc9900" | 2? || || || || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || 1? || G || G || G || G || G || G || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| CPAD || CPAD || || G || G || G || G || G || G || ||<br />
|-<br />
| || || || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| MIC || || G || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| JACK_R || G || G || || G || || || || || || G<br />
|-<br />
| JACK_DET || || || || G || G || G || G || || ||<br />
|-<br />
| || || G || || || || JACK_L || || G || G ||<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19436
Pinouts
2017-01-28T13:30:08Z
<p>Plutooo: </p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | 0? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | 1? || style="background: #cc9900" | 2? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | 3? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || + || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || style="background: #73e600" | ? || style="background: #476b6b" | 3? || style="background: #476b6b" | 4? || style="background: #476b6b" | 5? || || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || || || || || || || || style="background: #73e600" | ? || style="background: #8efab4" | SDA || style="background: #476b6b" | 1? || style="background: #476b6b" | 2? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || || || || || style="background: #b19cd9" | ? || style="background: #8efab4" | SCL || style="background: #476b6b" | 0? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC0 (unknown)<br />
|-<br />
| style="background: #476b6b" | CODEC1 (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | + || style="background: #d9ffb3" | + || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTHM || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || PWRBTN || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}<br />
<br />
== CODEC ==<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:36%;"<br />
| || style="background: #476b6b" | 4? || || || style="background: #cc9900" | 3? || style="background: #cc9900" | 0? || || || || G ||<br />
|-<br />
| || style="background: #476b6b" | 3? || style="background: #476b6b" | 5? || G || || style="background: #cc9900" | 1? || || || || G ||<br />
|-<br />
| G || style="background: #476b6b" | 2? || style="background: #476b6b" | 0? || G || || style="background: #cc9900" | 2? || || || || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || 1? || G || G || G || G || G || G || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| CPAD || CPAD || || G || G || G || G || G || G || ||<br />
|-<br />
| || || || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| || || G || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| || G || G || || G || || || || || || G<br />
|-<br />
| || || || || G || G || G || G || || ||<br />
|-<br />
| || || G || || || || || || G || G ||<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19435
Pinouts
2017-01-28T13:14:53Z
<p>Plutooo: </p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | 0? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | 1? || style="background: #cc9900" | 2? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | 3? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || + || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || style="background: #73e600" | ? || style="background: #476b6b" | ? || style="background: #476b6b" | ? || style="background: #476b6b" | ? || style="background: #476b6b" | ? || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || || || || || || || || style="background: #73e600" | ? || style="background: #8efab4" | SDA || style="background: #476b6b" | ? || style="background: #476b6b" | ? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || || || || || style="background: #b19cd9" | ? || style="background: #8efab4" | SCL || style="background: #476b6b" | ? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC0 (unknown)<br />
|-<br />
| style="background: #476b6b" | CODEC1 (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | +? || style="background: #d9ffb3" | +? || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTHM || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || PWRBTN || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}<br />
<br />
== CODEC ==<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:36%;"<br />
| || || || || style="background: #cc9900" | 3? || style="background: #cc9900" | 0? || || || || G ||<br />
|-<br />
| || || || G || || style="background: #cc9900" | 1? || || || || G ||<br />
|-<br />
| G || || || G || || style="background: #cc9900" | 2? || || || || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| CPAD || CPAD || || G || G || G || G || G || G || ||<br />
|-<br />
| || || || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| || || G || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| || G || G || || G || || || || || || G<br />
|-<br />
| || || || || G || G || G || G || || ||<br />
|-<br />
| || || G || || || || || || G || G ||<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19434
Pinouts
2017-01-28T13:07:58Z
<p>Plutooo: </p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | 0? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | 1? || style="background: #cc9900" | 2? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | 3? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || + || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || style="background: #73e600" | ? || style="background: #476b6b" | ? || style="background: #476b6b" | ? || style="background: #476b6b" | ? || style="background: #476b6b" | ? || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || || || || || || || || style="background: #73e600" | ? || style="background: #8efab4" | SDA || style="background: #476b6b" | ? || style="background: #476b6b" | ? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || || || || || style="background: #b19cd9" | ? || style="background: #8efab4" | SCL || style="background: #476b6b" | ? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC0 (unknown)<br />
|-<br />
| style="background: #476b6b" | CODEC1 (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | +? || style="background: #d9ffb3" | +? || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTHM || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || PWRBTN || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}<br />
<br />
== CODEC ==<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:36%;"<br />
| || || || || style="background: #cc9900" | 3? || style="background: #cc9900" | 0? || || || || G ||<br />
|-<br />
| || || || G || || style="background: #cc9900" | 1? || || || || G ||<br />
|-<br />
| G || || || G || || style="background: #cc9900" | 2? || || || || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| CPAD || CPAD || || G || G || G || G || G || G || ||<br />
|-<br />
| || || || G || G || G || G || G || G || ||<br />
|-<br />
| || || G || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| || G || G || || G || || || || || ||<br />
|-<br />
| || || || || G || G || G || G || || ||<br />
|-<br />
| || || G || || || || || || G || G ||<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19433
Pinouts
2017-01-28T13:05:50Z
<p>Plutooo: </p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | 0? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | 1? || style="background: #cc9900" | 2? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | 3? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || + || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || style="background: #73e600" | ? || style="background: #476b6b" | ? || style="background: #476b6b" | ? || style="background: #476b6b" | ? || style="background: #476b6b" | ? || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || || || || || || || || style="background: #73e600" | ? || style="background: #8efab4" | ? || style="background: #476b6b" | ? || style="background: #476b6b" | ? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || || || || || style="background: #b19cd9" | ? || style="background: #8efab4" | ? || style="background: #476b6b" | ? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC0 (unknown)<br />
|-<br />
| style="background: #476b6b" | CODEC1 (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | +? || style="background: #d9ffb3" | +? || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTHM || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || PWRBTN || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}<br />
<br />
== CODEC ==<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:36%;"<br />
| || || || || style="background: #cc9900" | 3? || style="background: #cc9900" | 0? || || || || G ||<br />
|-<br />
| || || || G || || style="background: #cc9900" | 1? || || || || G ||<br />
|-<br />
| G || || || G || || style="background: #cc9900" | 2? || || || || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| CPAD || CPAD || || G || G || G || G || G || G || ||<br />
|-<br />
| || || || G || G || G || G || G || G || ||<br />
|-<br />
| || || G || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| || G || G || || G || || || || || ||<br />
|-<br />
| || || || || G || G || G || G || || ||<br />
|-<br />
| || || G || || || || || || G || G ||<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19432
Pinouts
2017-01-28T12:52:18Z
<p>Plutooo: </p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | ? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | ? || style="background: #cc9900" | ? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | ? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || + || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || style="background: #73e600" | ? || style="background: #cc9900" | ? || style="background: #cc9900" | ? || style="background: #cc9900" | ? || style="background: #cc9900" | ? || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || || || || || || || || style="background: #73e600" | ? || style="background: #8efab4" | ? || style="background: #cc9900" | ? || style="background: #cc9900" | ? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || || || || || style="background: #b19cd9" | ? || style="background: #8efab4" | ? || style="background: #cc9900" | ? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | +? || style="background: #d9ffb3" | +? || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTHM || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || PWRBTN || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}<br />
<br />
== CODEC ==<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:36%;"<br />
| || || || || || || || || || G ||<br />
|-<br />
| || || || G || || || || || || G ||<br />
|-<br />
| G || || || G || || || || || || || SPEAKER1<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| TOUCH || TOUCH || || G || G || G || G || G || G || ||<br />
|-<br />
| CPAD || CPAD || || G || G || G || G || G || G || ||<br />
|-<br />
| || || || G || G || G || G || G || G || ||<br />
|-<br />
| || || G || G || G || G || G || G || G || || SPEAKER2<br />
|-<br />
| || G || G || || G || || || || || ||<br />
|-<br />
| || || || || G || G || G || G || || ||<br />
|-<br />
| || || G || || || || || || G || G ||<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19384
Pinouts
2017-01-22T22:01:44Z
<p>Plutooo: /* UC CTR */</p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | ? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | ? || style="background: #cc9900" | ? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | ? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || + || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || style="background: #73e600" | ? || style="background: #cc9900" | ? || style="background: #cc9900" | ? || style="background: #cc9900" | ? || style="background: #cc9900" | ? || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || || || || || || || || style="background: #73e600" | ? || style="background: #8efab4" | ? || style="background: #cc9900" | ? || style="background: #cc9900" | ? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || || || || || style="background: #b19cd9" | ? || style="background: #8efab4" | ? || style="background: #cc9900" | ? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | +? || style="background: #d9ffb3" | +? || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTEMP || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || PWRBTN || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}</div>
Plutooo
https://www.3dbrew.org/w/index.php?title=Pinouts&diff=19383
Pinouts
2017-01-22T21:53:00Z
<p>Plutooo: /* UC CTR */</p>
<hr />
<div>== CTR CPU B ==<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;"<br />
| style="background: #bbbbbb" | G || style="background: #cc9900" | ? || style="background: #336600" | CS1 || style="background: #336600" | ? || style="background: #336600" | ? || style="background: #a060a0" | D5 || style="background: #a060a0" | D2 || || style="background: #a060a0" | RST || style="background: #a060a0" | CLK || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #ff0000" | X || style="background: #ff0000" | X || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || style="background: #666633" | IRIRQ || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #bbbbbb" | G<br />
|-<br />
| style="background: #cc9900" | ? || style="background: #cc9900" | ? || style="background: #336600" | CSx || style="background: #336600" | CSy || style="background: #336600" | ? || style="background: #a060a0" | D6 || style="background: #a060a0" | D3 || style="background: #a060a0" | D0 || style="background: #a060a0" | IRQ || style="background: #a060a0" | CS1 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || || style="background: #bbbbbb" | G || || || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || || || || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc9900" | ? || ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CLK || style="background: #ffff00" | D0 ||style="background: #ffffff" | || + || || style="background: #a060a0" | D7 || style="background: #a060a0" | D4 || style="background: #a060a0" | D1 || style="background: #a060a0" | DET || style="background: #a060a0" | CS2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #d9ffb3" | 3v3 || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #a52a2a" | ? || style="background: #666633" | IRTX || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | D1 || style="background: #ffff00" | D2 ||style="background: #ffffff" | || style="background: #ffff00" | D3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ffff00" | CMD || style="background: #ffff00" | IRQ ||style="background: #ffffff" | || style="background: #ffff00" | WP || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | CLK || style="background: #00aaee" | D0 ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #00aaee" | D1 || style="background: #00aaee" | D2 ||style="background: #ffffff" | || style="background: #00aaee" | D3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #00aaee" | CMD ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #20b2aa" | ? || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #20b2aa" | ? ||style="background: #ffffff" | || style="background: #20b2aa" | ? || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || ||style="background: #ffffff" | || || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SCL || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 3v3 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #33ffff" | SDA || ||style="background: #ffffff" | || || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 3v3 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || <br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #cc6600" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v8 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v2 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #d9ffb3" | 1v2 ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #d9ffb3" | 1v8 || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #d9ffb3" | 1v8 || style="background: #d9ffb3" | 1v2 || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | || style="background: #cc6600" | ? || || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || style="background: #73e600" | ? || style="background: #cc9900" | ? || style="background: #cc9900" | ? || style="background: #cc9900" | ? || style="background: #cc9900" | ? || || || || style="background: #ff69b4" | B || style="background: #ff69b4" | PADR || style="background: #ff69b4" | PADD || style="background: #bbbbbb" | G || style="background: #4d4d33" | ? || style="background: #4d4d33" | ? || style="background: #bbbbbb" | G || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #ff8000" | ? || style="background: #cc6600" | ? ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | ||style="background: #ffffff" | || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || || || || || || || || style="background: #73e600" | ? || style="background: #8efab4" | ? || style="background: #cc9900" | ? || style="background: #cc9900" | ? || || || || || style="background: #ff69b4" | A || style="background: #ff69b4" | STRT || style="background: #ff69b4" | PADU || style="background: #ff69b4" | L || style="background: #ff69b4" | Y || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ?<br />
|-<br />
| style="background: #bbbbbb" | G || style="background: #b19cd9" | ? || style="background: #b19cd9" | ? || || || || || || || || style="background: #b19cd9" | ? || style="background: #8efab4" | ? || style="background: #cc9900" | ? || || || || || || || style="background: #ff69b4" | SLCT || style="background: #ff69b4" | PADL || style="background: #ff69b4" | R || style="background: #ff69b4" | X || style="background: #4d4d33" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #ff2a7f" | ? || style="background: #bbbbbb" | G<br />
|}<br />
<br />
legend:<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;table-layout:fixed;"<br />
| style="background: #ff0000" | Main<br />
|-<br />
| style="background: #a060a0" | Gamecard<br />
|-<br />
| style="background: #ffff00" | SDCARD SDIO<br />
|-<br />
| style="background: #00aaee" | NAND SDIO<br />
|-<br />
| style="background: #20b2aa" | WIFI SDIO<br />
|-<br />
| style="background: #336600" | SPI<br />
|-<br />
| style="background: #73e600" | I2C-1<br />
|-<br />
| style="background: #8efab4" | I2C-2<br />
|-<br />
| style="background: #33ffff" | I2C-3<br />
|-<br />
| style="background: #ff69b4" | Pad<br />
|-<br />
| style="background: #ff2a7f" | FCRAM<br />
|-<br />
| style="background: #b19cd9" | Camera<br />
|-<br />
| style="background: #a52a2a" | WIFI<br />
|-<br />
| style="background: #666633" | GPIO<br />
|-<br />
| style="background: #ff8000" | LCD0 (small)<br />
|-<br />
| style="background: #cc6600" | LCD1 (big)<br />
|-<br />
| style="background: #cc9900" | CODEC (unknown)<br />
|-<br />
| style="background: #4d4d33" | MCU (unknown)<br />
|-<br />
| style="background: #d9ffb3" | POWER<br />
|-<br />
| style="background: #bbbbbb" | Ground<br />
|}<br />
<br />
Orientation: Triangle bottom right on the PCB.<br />
<br />
== UC CTR ==<br />
<br />
<br />
{| class="wikitable" style="font-family:Monospace;text-align:center;width:100%;table-layout:fixed;width:26%;"<br />
| style="background: #4d4d33" | ? || style="background: #d9ffb3" | +? || style="background: #d9ffb3" | +? || CHRGLED || style="background: #bbbbbb" | G || || || style="background: #bbbbbb" | G<br />
|-<br />
| || style="background: #4d4d33" | ? || || || style="background: #bbbbbb" | G || BATTTEMP || HOMEBTN ||<br />
|-<br />
| || style="background: #4d4d33" | ? || || || || || || style="background: #8efab4" | SDA<br />
|-<br />
| TP75 || TP74 || TP76 || || || || || style="background: #8efab4" | SCL <br />
|-<br />
| || || TP77 || PWRLED1 || || || PWRLED0 ||<br />
|-<br />
| || style="background: #bbbbbb" | G || style="background: #d9ffb3" | + || TP78 || || || ||<br />
|-<br />
| style="background: #bbbbbb" | G || || || || || || ||<br />
|-<br />
| TP79 || style="background: #73e600" | ? || style="background: #73e600" | ? || style="background: #4d4d33" | ? || || || || style="background: #d9ffb3" | +<br />
|}</div>
Plutooo