Difference between revisions of "SHA Registers"
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== Registers == | == Registers == | ||
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
| − | ! | + | ! Old3DS |
| − | ! | + | ! Name |
| − | ! | + | ! Address |
| + | ! Width | ||
| + | ! Used by | ||
|- | |- | ||
| − | | | + | | style="background: green" | Yes |
| + | | [[#SHA_CNT|SHA_CNT]] | ||
| 0x1000A000 | | 0x1000A000 | ||
| 4 | | 4 | ||
| + | | | ||
|- | |- | ||
| − | | | + | | style="background: green" | Yes |
| + | | [[#SHA_INPUTSZ|SHA_INPUTSZ]] | ||
| 0x1000A004 | | 0x1000A004 | ||
| 4 | | 4 | ||
| + | | | ||
|- | |- | ||
| − | | | + | | style="background: green" | Yes |
| + | | [[#SHA_OUT|SHA_OUT]] | ||
| 0x1000A040 | | 0x1000A040 | ||
| 0x20 | | 0x20 | ||
| + | | | ||
|- | |- | ||
| − | | | + | | style="background: green" | Yes |
| + | | [[#SHA_IN|SHA_IN]] | ||
| 0x1000A080 | | 0x1000A080 | ||
| 0x40 | | 0x40 | ||
| + | | | ||
|} | |} | ||
| − | == | + | == SHA_CNT == |
{| class="wikitable" border="1" | {| class="wikitable" border="1" | ||
! Bits | ! Bits | ||
| Line 50: | Line 60: | ||
|} | |} | ||
| − | + | == SHA_INPUTSZ == | |
| − | == | ||
This reg contains the total size of the data written to REG_SHA_IN. | This reg contains the total size of the data written to REG_SHA_IN. | ||
| − | == | + | == SHA_OUT == |
This reg contains the SHA* hash after the final round. | This reg contains the SHA* hash after the final round. | ||
| − | == | + | == SHA_IN == |
The data to be hashed must be written here. The data must be padded with 0x00s to align with the register size (if needed). | The data to be hashed must be written here. The data must be padded with 0x00s to align with the register size (if needed). | ||
Revision as of 00:56, 20 March 2015
Registers
| Old3DS | Name | Address | Width | Used by |
|---|---|---|---|---|
| Yes | SHA_CNT | 0x1000A000 | 4 | |
| Yes | SHA_INPUTSZ | 0x1000A004 | 4 | |
| Yes | SHA_OUT | 0x1000A040 | 0x20 | |
| Yes | SHA_IN | 0x1000A080 | 0x40 |
SHA_CNT
| Bits | Description |
|---|---|
| 0-1 | 0=Hash ready, 1=Normal, 2=Final Round |
| 3 | Endianess (0=Little endian, 1=Big endian) |
| 4 | ? Input related. Changes the hash completely |
| 5 | Mode (0=SHA256, 1=SHA1) |
| 8 | Unknown. When set, the *entire* ARM9 hangs/crashes when attempting to read REG_SHA_IN. |
| 16 | Enable |
| 17 | 1 when FIFO expects read/write |
SHA_INPUTSZ
This reg contains the total size of the data written to REG_SHA_IN.
SHA_OUT
This reg contains the SHA* hash after the final round.
SHA_IN
The data to be hashed must be written here. The data must be padded with 0x00s to align with the register size (if needed).