Difference between revisions of "RSA Registers"
|Line 51:||Line 51:|
Revision as of 01:02, 5 September 2014
|0||Start (1=Enable/Busy, 0=Idle)|
|4-7||Keyslot (Bit6-7 don't actually affect the keyslot)|
|8||Endianness (1=Little endian, 0=Big endian)|
|9||Word order (1=Normal order, 0=Reversed order)|
|0||Key status (1=Key has been set, 0=Key has not been set yet)|
This contains the RSA size for this slot, in words. Normally this is 0x40 for RSA-2048.
The 0x100-byte private or public exponent is written to this write-only FIFO.
The RSA key modulo for the selected keyslot can be written here. When writing the RSA modulo, the modulo must align with the end of the register area.
The RSA signature can be written here, and the data read from here is the message. When writing the RSA signature, the signature must be prepended with zeroes until it is a multiple of 8 bytes, and the end of the signature must align with the end of the register area.
The PKCS message padding must be manually checked by software, as hardware will only do raw RSA operations.
|1||CXI access desc (following the exheader)|
|2-3||Initialized by the ARM9 bootrom, but not used by any of the FIRMs. It's unknown what the ARM9 bootrom uses these for, if anything.|