Difference between revisions of "ARM11 Interrupts"
m (→Hardware Interrupts: Confirmed.)
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| gsp, TwlBg
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Revision as of 14:12, 19 April 2018
Interrupt priority is 0-0xF. A priority of 0xF means that the interrupt is disabled.
Each CPU core has 32 software interrupts that are private and belong to that core. These interrupts are numbers 0-0x1F for each core. The hardware interrupts are not core-specific and start at interrupt ID 0x20.
|0-0x3||MPCore software-interrupt. Not configured.|
|0x4||Kernel||MPCore software-interrupt. Used to manage the performance counter.|
|0x5||Kernel||MPCore software-interrupt. Does apparently nothing.|
|0x6||Kernel||MPCore software-interrupt. Extensively used by KernelSetState (and contains most of the actual code of the latter).|
|0x7||Kernel||MPCore software-interrupt. See KCacheMaintenanceInterruptEvent|
|0x8||Kernel||MPCore software-interrupt. Used for scheduling.|
|0x9||Kernel||MPCore software-interrupt. Used when handling exceptions that require termination of a thread or a process, and in some cases by svcSetDebugThreadContext, to store VFP registers in the thread's register storage.|
|0xA||Kernel||TLB operations interrupt, see KTLBOperationsInterruptEvent|
|0xB-0xE||MPCore software-interrupt. Not configured.|
|0xF||dmnt/debugger||MPCore software-interrupt. Used to abstract FIQ (debug). This interrupt is never sent to core2 nor core3 on N3DS.|
|0x1E||Kernel||MPCore watchdog - set when the watchdog counter reaches 0 in timer mode, causes interrupt 30 to set as pending. Only set on core 1 as core 1's timer is used for everything.|
There are 0x60 hardware interrupts starting at 0x20 and continuing up to 0x7F. These are not private and are accessible from any core.
|0x2A||gsp, TwlBg||PDC0 (VBlank0)|
|0x2B||gsp, TwlBg||PDC1 (VBlank1)|
|0x40||nwm||WIFI SDIO Controller @ 0x10122000|
|0x42||nwm_dev?||WIFI SDIO Controller @ 0x10100000|
|0x4B||camera||Y2R Conversion Finished|
|0x52||pxi, TwlBg||Send Fifo Empty|
|0x53||pxi, TwlBg||Receive Fifo Not Empty|
|0x54||i2c, TwlBg||I2C Bus0 work done|
|0x55||i2c, TwlBg||I2C Bus1 work done|
|0x5C||i2c, TwlBg||I2C Bus2 work done|
|0x60||gpio, TwlBg||Shell opened|
|0x62||gpio, TwlBg||Shell closed|
|0x64||gpio, TwlBg||Headphone jack plugged in/out|
|0x71||gpio, TwlBg||MCU (HOME/POWER pressed/released or WiFi switch pressed)|
|0x78 to 0x7B||Kernel||Core 0-3 Performance monitor counter (any) overflow|
|0x7A to 0x82 (PDN_MPCORE_CFG bit2 set) or
0x7C to 0x84 (bit2 clear)
(interrupts from 0x80 and up can't be mapped in available builds of the kernel)
There are 2 tables in the ARM11 kernel: the first has 32 * 2(or 32 * 4) 8-byte entries. This table is for the private interrupts that belong to each core. The data for each interrupt can be found by doing table_base + (core_num * 0x100) + (intr_num * 8). The second table is for public hardware interrupts and the data for each interrupt can be retrieved by doing table_base + (intr_num * 8).
|0x0||KBaseInterruptEvent *||Pointer to the KBaseInterruptEvent object for this interrupt|
|0x4||u8||Interrupt will be disabled by the IRQ handler as soon as it is acknowledged.
Ignored for FIQ: the FIQ handler always sets bit2 of PDN_FIQ_CNT
|0x5||u8||Interrupt is disabled|
Interrupt Table (New3DS)
(0xFFF318F4 in 10.3)
|0x0||InterruptData||Data for all hardware and software interrupts|