SPI Registers - Revision history

Profi200: /* NSPI_FIFO */

2021-02-14T22:09:41Z

NSPI_FIFO

← Older revision		Revision as of 01:09, 15 February 2021
Line 320:		Line 320:
	\|}		\|}

	32-bit FIFO for reading/writing the SPI payload.		32-bit FIFO for reading/writing the SPI payload. This FIFO is one way (half-duplex).

	== NSPI_STATUS ==		== NSPI_STATUS ==

Profi200: /* Registers */

2019-06-27T21:45:18Z

Registers

← Older revision		Revision as of 01:45, 28 June 2019
Line 365:		Line 365:
	\|-		\|-
	\| 0		\| 0
	\| Transfer finished? (1 = disabled)		\| Transfer finished (1 = disabled)
	\|-		\|-
	\| 1		\| 1
Line 380:		Line 380:
	\|-		\|-
	\| 0		\| 0
	\| Transfer finished?		\| Transfer finished (also fires on each autopoll try?)
	\|-		\|-
	\| 1		\| 1
Line 389:		Line 389:
	\|}		\|}

	[[ARM11_Interrupts#Hardware_Interrupts\|Interrupt]] ID 0x56 or 0x57 (depending on the bus) is fired when any of the bits change to 1 except for interrupts masked in [[#NSPI_INT_MASK\|NSPI_INT_MASK]]. Writing 1 to a bit in this register aknowledges the interrupt.		[[ARM11_Interrupts#Hardware_Interrupts\|Interrupt]] ID 0x24, 0x56 or 0x57 (depending on the bus) is fired when any of the bits change to 1 except for interrupts masked in [[#NSPI_INT_MASK\|NSPI_INT_MASK]]. Writing 1 to a bit in this register aknowledges the interrupt.

Profi200: /* NSPI_AUTOPOLL */

2019-05-11T18:52:41Z

NSPI_AUTOPOLL

← Older revision		Revision as of 22:52, 11 May 2019
Line 345:		Line 345:
	\|-		\|-
	\| 16-19		\| 16-19
	\| Timeout (Tries = 31<<~~Baudrate~~ (from NSPI_CNT) + Timeout)		\| Timeout (Tries = 31<<Clock (from [[#NSPI_CNT\|NSPI_CNT]]) + Timeout)
	\|-		\|-
	\| 24-26		\| 24-26

Profi200: /* Registers */

2019-05-11T18:41:17Z

Registers

Show changes

Profi200: /* Registers */ Use same naming scheme as NDMA

2019-05-07T16:36:22Z

Registers: Use same naming scheme as NDMA

← Older revision		Revision as of 20:36, 7 May 2019
Line 20:		Line 20:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_CNT~~\|~~SPI_NEW_CNT~~]]0		\| [[#NSPI_CNT\|NSPI_CNT]]0
	\| 0x10142800		\| 0x10142800
	\| 4		\| 4
Line 26:		Line 26:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_DONE~~\|~~SPI_NEW_DONE~~]]0		\| [[#NSPI_DONE\|NSPI_DONE]]0
	\| 0x10142804		\| 0x10142804
	\| 4		\| 4
Line 32:		Line 32:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_BLKLEN~~\|~~SPI_NEW_BLKLEN~~]]0		\| [[#NSPI_BLKLEN\|NSPI_BLKLEN]]0
	\| 0x10142808		\| 0x10142808
	\| 4		\| 4
Line 38:		Line 38:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_FIFO~~\|~~SPI_NEW_FIFO~~]]0		\| [[#NSPI_FIFO\|NSPI_FIFO]]0
	\| 0x1014280C		\| 0x1014280C
	\| 4		\| 4
Line 44:		Line 44:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_STATUS~~\|~~SPI_NEW_STATUS~~]]0		\| [[#NSPI_STATUS\|NSPI_STATUS]]0
	\| 0x10142810		\| 0x10142810
	\| 4		\| 4
Line 80:		Line 80:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_CNT~~\|~~SPI_NEW_CNT~~]]1		\| [[#NSPI_CNT\|NSPI_CNT]]1
	\| 0x10143800		\| 0x10143800
	\| 4		\| 4
Line 86:		Line 86:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_DONE~~\|~~SPI_NEW_DONE~~]]1		\| [[#NSPI_DONE\|NSPI_DONE]]1
	\| 0x10143804		\| 0x10143804
	\| 4		\| 4
Line 92:		Line 92:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_BLKLEN~~\|~~SPI_NEW_BLKLEN~~]]1		\| [[#NSPI_BLKLEN\|NSPI_BLKLEN]]1
	\| 0x10143808		\| 0x10143808
	\| 4		\| 4
Line 98:		Line 98:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_FIFO~~\|~~SPI_NEW_FIFO~~]]1		\| [[#NSPI_FIFO\|NSPI_FIFO]]1
	\| 0x1014380C		\| 0x1014380C
	\| 4		\| 4
Line 104:		Line 104:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_STATUS~~\|~~SPI_NEW_STATUS~~]]1		\| [[#NSPI_STATUS\|NSPI_STATUS]]1
	\| 0x10143810		\| 0x10143810
	\| 4		\| 4
Line 140:		Line 140:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_CNT~~\|~~SPI_NEW_CNT~~]]2		\| [[#NSPI_CNT\|NSPI_CNT]]2
	\| 0x10160800		\| 0x10160800
	\| 4		\| 4
Line 146:		Line 146:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_DONE~~\|~~SPI_NEW_DONE~~]]2		\| [[#NSPI_DONE\|NSPI_DONE]]2
	\| 0x10160804		\| 0x10160804
	\| 4		\| 4
Line 152:		Line 152:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_BLKLEN~~\|~~SPI_NEW_BLKLEN~~]]2		\| [[#NSPI_BLKLEN\|NSPI_BLKLEN]]2
	\| 0x10160808		\| 0x10160808
	\| 4		\| 4
Line 158:		Line 158:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_FIFO~~\|~~SPI_NEW_FIFO~~]]2		\| [[#NSPI_FIFO\|NSPI_FIFO]]2
	\| 0x1016080C		\| 0x1016080C
	\| 4		\| 4
Line 164:		Line 164:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~SPI_NEW_STATUS~~\|~~SPI_NEW_STATUS~~]]2		\| [[#NSPI_STATUS\|NSPI_STATUS]]2
	\| 0x10160810		\| 0x10160810
	\| 4		\| 4
Line 227:		Line 227:
	\|}		\|}

	== ~~SPI_NEW_CNT~~ ==		== NSPI_CNT ==
	This is an alternative faster interface introduced with the 3DS.		This is an alternative faster interface introduced with the 3DS.

Line 275:		Line 275:
	\|}		\|}

	== ~~SPI_NEW_DONE~~ ==		== NSPI_DONE ==
	This register reads as 1 after starting a transfer. When the transfer is finished, a 0 has to be written to this register. This is ~~probaly~~ the Chip Select line.		This register reads as 1 after starting a transfer. When the transfer is finished, a 0 has to be written to this register. This is probably the Chip Select line.

	==~~SPI_NEW_BLKLEN~~==		==NSPI_BLKLEN==
	The number of bytes to be sent/read is written to this register.		The number of bytes to be sent/read is written to this register.

	==~~SPI_NEW_FIFO~~==		==NSPI_FIFO==
	32-bit FIFO for reading/writing the SPI payload.		32-bit FIFO for reading/writing the SPI payload.

	==~~SPI_NEW_STATUS~~==		==NSPI_STATUS==
	Bit0: FIFO busy. At transfer start and every 32 bytes the FIFO becomes busy.		Bit0: FIFO busy. At transfer start and every 32 bytes the FIFO becomes busy.

Profi200: /* SPI_NEW_CNT */

2019-05-07T16:25:48Z

SPI_NEW_CNT

← Older revision		Revision as of 20:25, 7 May 2019
Line 241:		Line 241:
	\|-		\|-
	\| 12		\| 12
	\| ?		\| Bus mode 0=1 bit, 1=4 bit
	\|-		\|-
	\| 13		\| 13

Profi200: /* Registers */

2019-05-07T15:37:45Z

Registers

@@ Line 46: / Line 46: @@
 | [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]0
 | 0x10142810
 | 4
+|
@@ Line 88: / Line 106: @@
 | [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]1
 | 0x10143810
 | 4
+|
@@ Line 130: / Line 166: @@
 | [[#SPI_NEW_STATUS|SPI_NEW_STATUS]]2
 | 0x10160810
 | 4
+|

Profi200: /* SPI_NEW_STATUS */

2019-04-20T17:54:26Z

SPI_NEW_STATUS

← Older revision		Revision as of 21:54, 20 April 2019
Line 231:		Line 231:

	==SPI_NEW_STATUS==		==SPI_NEW_STATUS==
	Bit0: FIFO busy.		Bit0: FIFO busy. At transfer start and every 32 bytes the FIFO becomes busy.

Profi200: /* SPI_NEW_DONE */

2019-04-20T17:52:00Z

SPI_NEW_DONE

← Older revision		Revision as of 21:52, 20 April 2019
Line 222:		Line 222:

	== SPI_NEW_DONE ==		== SPI_NEW_DONE ==
	When the transfer is finished, a 0 has to be written to this register.		This register reads as 1 after starting a transfer. When the transfer is finished, a 0 has to be written to this register. This is probaly the Chip Select line.

	==SPI_NEW_BLKLEN==		==SPI_NEW_BLKLEN==

Profi200: /* SPI_NEW_CNT */

2019-04-20T17:48:10Z

SPI_NEW_CNT

← Older revision		Revision as of 21:48, 20 April 2019
Line 180:		Line 180:
	! Name		! Name
	\|-		\|-
	\| 0-5		\| 0-2
	\| Baudrate?		\| Baudrate?
	\|-		\|-
	\| 6-7		\| 6-7
	\| Device Select		\| Device Select
			\|-
			\| 12
			\| ?
	\|-		\|-
	\| 13		\| 13