PXI Registers - Revision history

Plutooo at 00:56, 6 January 2017

2017-01-05T23:56:29Z

2017-01-05T23:34:38Z

2016-07-02T18:33:52Z

clear up notes on sync cc profi200

← Older revision		Revision as of 22:33, 2 July 2016
Line 66:		Line 66:
	\| 0-7		\| 0-7
	\| R		\| R
	\| Data received from remote		\| Data received from remote bits 8-15 (unrelated to SEND/RECV FIFOs)
	\|-		\|-
	\| 8-15		\| 8-15
	\| R/W		\| R/W
	\| Data sent to remote		\| Data sent to remote bits 0-7
	\|-		\|-
	\| 23		\| 23

2015-12-12T19:18:01Z

move protocol stuff to PXI Services since it is a FIRM construct

@@ Line 1: / Line 1: @@
 = Registers =
 {| class="wikitable" border="1"
@@ Line 116: / Line 85: @@
 |-
 | 31
-| R/W
+| RW
 | PXI_SYNC IRQ enable (for local processor)
 |}

2015-12-12T00:17:03Z

← Older revision		Revision as of 03:17, 12 December 2015
Line 116:		Line 116:
	\|-		\|-
	\| 31		\| 31
	\| RW		\| R/W
	\| PXI_SYNC IRQ enable (for local processor)		\| PXI_SYNC IRQ enable (for local processor)
	\|}		\|}

2015-12-12T00:15:21Z

okay, now it's right

← Older revision		Revision as of 03:15, 12 December 2015
Line 102:		Line 102:
	\| R/W		\| R/W
	\| Data sent to remote		\| Data sent to remote
	\|-
	~~\| 21~~
	~~\| ?~~
	~~\| ?~~
	\|-		\|-
	\| 23		\| 23
Line 112:		Line 108:
	\|-		\|-
	\| 29		\| 29
	\| ?		\| W?
	\| PXI_SYNC11 ~~interrupt enable?~~		\| Trigger PXI_SYNC11 IRQ (if enabled)
	\|-		\|-
	\| 30		\| 30
	\| ?		\| W?
	\| PXI_SYNC9 ~~interrupt enable?~~		\| Trigger PXI_SYNC9 IRQ (if enabled)
	\|-		\|-
	\| 31		\| 31
	\| ?		\| RW
	\|		\| PXI_SYNC IRQ enable (for local processor)
	\|}		\|}

2015-12-11T22:53:40Z

Registers

2015-12-11T21:51:09Z

shrug

← Older revision		Revision as of 00:51, 12 December 2015
Line 39:		Line 39:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~PXI_SYNC9~~\|~~PXI_SYNC9~~]]		\| [[#PXI_SYNC\|PXI_SYNC]]9
	\| 0x10008000		\| 0x10008000
	\| 4		\| 4
	\|
	\|-
	~~\| style="background: green" \| Yes~~
	~~\| PXI_????9~~
	~~\| 0x10008003~~
	~~\| 1~~
	\|		\|
	\|-		\|-
Line 69:		Line 63:
	\|-style="border-top: double"		\|-style="border-top: double"
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| ~~PXI_SYNC11~~		\| [[#PXI_SYNC\|PXI_SYNC]]11
	\| 0x10163000		\| 0x10163000
	\| 4		\| 4
Line 87:		Line 81:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| ~~PXI_RECV_11~~		\| PXI_RECV11
	\| 0x1016300C		\| 0x1016300C
	\| 4		\| 4
Line 95:		Line 89:
	The PXI registers are similar to those on DS.		The PXI registers are similar to those on DS.

	== ~~PXI_SYNC9~~ ==		== PXI_SYNC ==
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! Bit		! Bit
Line 101:		Line 95:
	! Description		! Description
	\|-		\|-
	\| 0-8		\| 0-7
	\| R		\| R
	\| Data ~~input~~ from ~~bit8-15 of PXI_SYNC11~~		\| Data received from remote
	\|-		\|-
	\| 8-15		\| 8-15
	\| R/W		\| R/W
	\| Data ~~output~~ to ~~bit0-8 of PXI_SYNC11~~		\| Data sent to remote
	\|-		\|-
	\| 23		\| 23
Line 115:		Line 109:
	\| 29		\| 29
	\| ?		\| ?
			\| PXI_SYNC11 interrupt enable?
			\|-
			\| 30
	\| ?		\| ?
			\| PXI_SYNC9 interrupt enable?
	\|-		\|-
	\| 31		\| 31
	\| ?		\| ?
	\| ?		\|
	\|}		\|}

			This can also be accessed as 4 u8 registers.

	== PXI_CNT ==		== PXI_CNT ==

2015-09-08T01:07:46Z

2015-05-14T14:54:58Z

← Older revision		Revision as of 18:54, 14 May 2015
Line 39:		Line 39:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~PXI_SYNC~~\|~~PXI_SYNC~~]]9		\| [[#PXI_SYNC9\|PXI_SYNC9]]
	\| 0x10008000		\| 0x10008000
	\| 4		\| 4
Line 57:		Line 57:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| ~~PXI_RECV_FIFO9~~		\| PXI_RECV9
	\| 0x10008008		\| 0x10008008
	\| 4		\| 4
Line 63:		Line 63:
	\|-style="border-top: double"		\|-style="border-top: double"
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| ~~[[#PXI_SYNC\|PXI_SYNC]]11~~		\| PXI_SYNC11
	\| 0x10163000		\| 0x10163000
	\| 4		\| 4
Line 89:		Line 89:
	The PXI registers are similar to those on DS.		The PXI registers are similar to those on DS.

	== ~~PXI_SYNC~~ ==		== PXI_SYNC9 ==
	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
	! Bit		! Bit
Line 95:		Line 95:
	! Description		! Description
	\|-		\|-
	\| 0-3		\| 0-8
	\| R		\| R
	\| Data input from ~~PXI_SYNC Bit8~~-11 of ~~remote CPU (00h..0Fh)~~		\| Data input from bit8-15 of PXI_SYNC11
	\|-		\|-
	\| 8-11		\| 8-15
	\| R/W		\| R/W
	\| Data output to ~~PXI_SYNC Bit0~~-3 of ~~remote CPU (00h..0Fh)~~		\| Data output to bit0-8 of PXI_SYNC11
	\|-		\|-
	\| 13		\| 23
	\| W		\| ?
	\| ~~Send IRQ to remote CPU (0=None, 1=Send IRQ)~~		\| ?
	\|-		\|-
	\| 14		\| 29
	\| ~~R/W~~		\| ?
	\| ~~Enable IRQ from remote CPU (0=Disable, 1=Enable)~~		\| ?
	\|-		\|-
	\| 23		\| 31
	\| ?		\| ?
	\| ?		\| ?