CONFIG11 Registers - Revision history

TuxSH: /* CFG11_SOCINFO */

2021-01-26T22:56:42Z

CFG11_SOCINFO

← Older revision		Revision as of 01:56, 27 January 2021
Line 234:		Line 234:

	* CTR: O3DS		* CTR: O3DS
	* LGR1: N3DS prototype, 2 ~~cores~~, no L2C		* LGR1: N3DS prototype, 4 cores (orginally 2), up to 535MHz, no L2C (see below)
	* LGR2: retail N3DS, 4 cores, has L2C		* LGR2: retail N3DS, 4 cores, up to 804MHz, has L2C

			Kernel code suggests that devices that support LGR1 but not LGR2 only had 2 cores. All cores (the number of which can be read from MPCORE SCU registers) are usable in LGR1 mode.

	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"

TuxSH: nullpage_cnt

2021-01-23T16:09:00Z

nullpage_cnt

← Older revision		Revision as of 19:09, 23 January 2021
Line 20:		Line 20:
	\|-style="border-top: double"		\|-style="border-top: double"
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| ?		\| [[#CFG11_NULLPAGE_CNT\|CFG11_NULLPAGE_CNT]]
	\| 0x10140100		\| 0x10140100
	\| 4		\| 4
	\| ?		\|
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
Line 144:		Line 144:
	\| Enable (0=Disable, 1=Enable)		\| Enable (0=Disable, 1=Enable)
	\|}		\|}

			== CFG11_NULLPAGE_CNT ==
			{\| class="wikitable" border="1"
			! Bit
			! Description
			\|-
			\| 0
			\| Trap all ''data'' accesses to physmem addresses 0x0000 to 0x1000
			\|-
			\| 16
			\| Unknown
			\|}

			The reset value of this register is 0x10000.

	== CFG11_FIQ_MASK ==		== CFG11_FIQ_MASK ==

TuxSH: /* CFG11_SOCINFO */

2021-01-23T15:28:39Z

CFG11_SOCINFO

← Older revision		Revision as of 18:28, 23 January 2021
Line 233:		Line 233:
	\|-		\|-
	\| 1		\| 1
	\| LGR1 (1 on all N3DSes, 2 cores and 2x clockrate)		\| LGR1 (1 on all N3DSes, orginally 2 cores, and 2x clockrate)
	\| Kernel11		\| Kernel11
	\|-		\|-

TuxSH: fixup

2021-01-19T17:10:51Z

fixup

← Older revision		Revision as of 20:10, 19 January 2021
Line 18:		Line 18:
	\| 1*8		\| 1*8
	\| Boot11, Process9, [[DSP Services]]		\| Boot11, Process9, [[DSP Services]]
	\|-		\|-style="border-top: double"
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| ?		\| ?
	\| 0x10140100		\| 0x10140100
	\| 2		\| 4
	\|
	\|-
	~~\| style="background: green" \| Yes~~
	\| ?		\| ?
	~~\| 0x10140102~~
	~~\| 2~~
	\|
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
Line 36:		Line 30:
	\| 1		\| 1
	\| Kernel11.		\| Kernel11.
	\| -		\|-
			\| style="background: green" \| Yes
			\| Debug related bitfield?
			Observed: 0b1100(N3DS)/0b0000(O3DS)
			\| 0x10140105
			\| 1
			\|
			\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#CFG11_CDMA_CNT\|CFG_CDMA_CNT]]		\| [[#CFG11_CDMA_CNT\|CFG_CDMA_CNT]]
Line 60:		Line 61:
	\| 2		\| 2
	\| [[SPI Services]], TwlBg		\| [[SPI Services]], TwlBg
	\|-		\|-style="border-top: double"
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| ?		\| ?
Line 146:		Line 147:
	== CFG11_FIQ_MASK ==		== CFG11_FIQ_MASK ==
	Write bit N to mask FIQ interrutps on core N? (judging from what Kernel11 does -- it only ever configures FIQ for core1)		Write bit N to mask FIQ interrutps on core N? (judging from what Kernel11 does -- it only ever configures FIQ for core1)

			Reset value: 0xF

	== CFG11_CDMA_CNT ==		== CFG11_CDMA_CNT ==

TuxSH: /* Registers */

2021-01-19T16:19:35Z

Registers

@@ Line 36: / Line 36: @@
 | 1
 | Kernel11.
-|-
+| -
 | style="background: green" | Yes
 | [[#CFG11_CDMA_CNT|CFG_CDMA_CNT]]

TuxSH: /* CFG11_BOOTROM_OVERLAY_VAL */

2021-01-19T15:43:59Z

CFG11_BOOTROM_OVERLAY_VAL

← Older revision		Revision as of 18:43, 19 January 2021
Line 223:		Line 223:

	== CFG11_BOOTROM_OVERLAY_VAL ==		== CFG11_BOOTROM_OVERLAY_VAL ==
	The 32-bit value to overlay data-reads to bootrom with. See [[PDN Registers#~~PDN_MPCORE_BOOTCNT~~\|~~PDN_MPCORE_BOOTCNT~~]].		The 32-bit value to overlay data-reads to bootrom with. See [[PDN Registers#PDN_LGR_CPU_CNT<0-3>\|PDN_LGR_CPU_CNT]]<0-3>.

	== CFG11_SOCINFO ==		== CFG11_SOCINFO ==

TuxSH: /* CFG11_SOCINFO */

2021-01-17T22:25:44Z

CFG11_SOCINFO

← Older revision		Revision as of 01:25, 18 January 2021
Line 227:		Line 227:
	== CFG11_SOCINFO ==		== CFG11_SOCINFO ==
	Read-only register. Identifies the maximum mode-switching capabilities of the SoC.		Read-only register. Identifies the maximum mode-switching capabilities of the SoC.

			* CTR: O3DS
			* LGR1: N3DS prototype, 2 cores, no L2C
			* LGR2: retail N3DS, 4 cores, has L2C

	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"

TuxSH: /* CFG11_SOCINFO */

2021-01-17T21:36:54Z

CFG11_SOCINFO

← Older revision		Revision as of 00:36, 18 January 2021
Line 226:		Line 226:

	== CFG11_SOCINFO ==		== CFG11_SOCINFO ==
	Read-only register.		Read-only register. Identifies the maximum mode-switching capabilities of the SoC.

	{\| class="wikitable" border="1"		{\| class="wikitable" border="1"
Line 234:		Line 234:
	\|-		\|-
	\| 0		\| 0
	\| 1 on ~~both Old3DS and New3DS.~~		\| CTR mode (1 on all 3DSes)
	\| Boot11		\| Boot11
	\|-		\|-
	\| 1		\| 1
	\| 1 on ~~New3DS.~~		\| LGR1 (1 on all N3DSes, 2 cores and 2x clockrate)
	\| Kernel11		\| Kernel11
	\|-		\|-
	\| 2		\| 2
	\| ~~N3DS SoC Mode: if set~~, ~~use a 3x clock multiplier and~~ 4 cores~~, otherwise 2x~~ and ~~2 cores~~		\| LGR2 (1 on all released N3DSes, 4 cores and 3x clockrate)
	\| Kernel11		\| Kernel11
	\|}		\|}

TuxSH: /* CFG11_SOCINFO */

2020-06-05T21:23:14Z

CFG11_SOCINFO

← Older revision		Revision as of 01:23, 6 June 2020
Line 242:		Line 242:
	\|-		\|-
	\| 2		\| 2
	\| ~~Clock modifier~~: if set, use a 3x multiplier, otherwise 2x		\| N3DS SoC Mode: if set, use a 3x clock multiplier and 4 cores, otherwise 2x and 2 cores
	\| Kernel11		\| Kernel11
	\|}		\|}


	==CFG11_GPUPROT==		==CFG11_GPUPROT==

TuxSH: CFG11_CDMA_CNT, etc.

2020-06-01T18:39:03Z

CFG11_CDMA_CNT, etc.

← Older revision		Revision as of 22:39, 1 June 2020
Line 32:		Line 32:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| [[#~~CFG11_FIQ_CNT~~\|~~CFG11_FIQ_CNT~~]]		\| [[#CFG11_FIQ_MASK\|CFG11_FIQ_MASK]]
	\| 0x10140104		\| 0x10140104
	\| 1		\| 1
Line 50:		Line 50:
	\|-		\|-
	\| style="background: green" \| Yes		\| style="background: green" \| Yes
	\| ~~Related to~~ [[~~HID_Registers~~\|~~HID_?~~]]		\| [[#CFG11_CDMA_CNT\|CFG_CDMA_CNT]]
	\| 0x1014010C		\| 0x1014010C
	\| 2		\| 2
Line 86:		Line 86:
	\|-		\|-
	\| style="background: red" \| No		\| style="background: red" \| No
	\| ~~Clock related?~~		\| [[#CFG11_CDMA_PERIPHERALS\|CFG11_CDMA_PERIPHERALS]]
	\| 0x10140410		\| 0x10140410
	\| 4		\| 4
Line 158:		Line 158:
	== CFG11_FIQ_MASK ==		== CFG11_FIQ_MASK ==
	Write bit N to mask FIQ interrutps on core N? (judging from what Kernel11 does -- it only ever configures FIQ for core1)		Write bit N to mask FIQ interrutps on core N? (judging from what Kernel11 does -- it only ever configures FIQ for core1)

			== CFG11_CDMA_CNT ==
			Write 1 to enable, to disable.

			{\| class="wikitable" border="1"
			! Bits
			! Description
			\|-
			\| 0
			\| Enable Microphone DMA (CDMA 0x00)
			\|-
			\| 1
			\| Enable NTRCARD DMA on Arm11 side (CDMA 0x01)
			\|-
			\| 2-4
			\| ?
			\|-
			\| 5
			\| WiFi. Enabled during kernel init since 11.4.
			\|}

	== CFG11_SPI_CNT ==		== CFG11_SPI_CNT ==
Line 187:		Line 207:
	\|}		\|}

	~~New3DS Kernel11 writes both bits very early during init.~~		== CFG11_CDMA_PERIPHERALS ==
			{\| class="wikitable" border="1"
			! Bit
			! Description
			\|-
			\| 0-17
			\| CDMA Peripheral 0x00-0x11 data request target (0=Old CDMA, 1=New CDMA)
			\|-
			\| 18-31
			\| Unused
			\|}

	== CFG11_BOOTROM_OVERLAY_CNT ==		== CFG11_BOOTROM_OVERLAY_CNT ==