3dbrew - User contributions [en]

GPU/Internal Registers

2024-10-06T11:27:25Z

Emufan4568:

[[Category:GPU]]

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).

In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.

For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).

Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.

The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.

=== Command Header ===
{| class="wikitable" border="1"
! Bit
! Description
|-
| 0-15
| Command ID
|-
| 16-19
| Parameter mask
|-
| 20-27
| Number of extra parameters (may be zero)
|-
| 28-30
| Unused
|-
| 31
| Consecutive writing mode
|}

=== Parameter masking ===

Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]

=== Data Types ===

{| class="wikitable" border="1"
! Name
! Description
|-
| signed
| Signed integer
|-
| unsigned
| Unsigned integer
|-
| floatX.Y.Z
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits
|-
| fixedX.Y.Z
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits
|}

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|PICA_REG_INTERRUPT
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]
|?
|PICA_REG_FRAGOP_CLIP
|-
| 0048
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]
|?
|PICA_REG_FRAGOP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]
|?
|PICA_REG_FRAGOP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]
|?
|PICA_REG_FRAGOP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]
|?
|PICA_REG_FRAGOP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]
|
|PICA_REG_EARLY_DEPTH_CLEAR
|-
| 0064
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]
|?
|PICA_REG_FRAGOP_WSCALE
|-
| 006E
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]
|?
|PICA_REG_TEXTURE3_PROCTEX0
|-
| 00A9
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]
|?
|PICA_REG_TEXTURE3_PROCTEX1
|-
| 00AA
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]
|?
|PICA_REG_TEXTURE3_PROCTEX2
|-
| 00AB
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]
|?
|PICA_REG_TEXTURE3_PROCTEX3
|-
| 00AC
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]
|?
|PICA_REG_TEXTURE3_PROCTEX4
|-
| 00AD
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]
|?
|PICA_REG_TEXTURE3_PROCTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]
|?
|PICA_REG_PROCTEX_LUT
|-
| 00B0
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]
| ?
|PICA_REG_PROCTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]
| ?
|PICA_REG_PROCTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]
| ?
|PICA_REG_PROCTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]
| ?
|PICA_REG_PROCTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]
| ?
|PICA_REG_PROCTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]
| ?
|PICA_REG_PROCTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]
| ?
|PICA_REG_PROCTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]
| ?
|PICA_REG_PROCTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]
|
|PICA_REG_FRAGOP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]
|?
|PICA_REG_FRAGOP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS
|-
| 019B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS
|-
| 01AB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS
|-
| 01BB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA5
|-
| 01CE
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]
|
|PICA_REG_POST_VERTEX_CACHE_NUM
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH0
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH1
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH0
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH1
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|PICA_REG_COMMAND_BUF_KICK_CH0
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|PICA_REG_COMMAND_BUF_KICK_CH1
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_GS_FLOAT_DATA0
|-
| 0292
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0293
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0294
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0295
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0296
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0297
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0298
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_VS_FLOAT_DATA0
|-
| 02C2
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C3
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C4
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C5
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C6
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C7
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C8
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)
|}

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

=== GPUREG_FACECULLING_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Culling mode
|}

This register is used to configure the face culling mode.

Culling mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Front Face (Counter Clockwise)
|-
| 2
| Back Face (Counter Clockwise)
|}

=== GPUREG_VIEWPORT_WIDTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, width / 2
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.

=== GPUREG_VIEWPORT_INVW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / width
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.

=== GPUREG_VIEWPORT_HEIGHT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, height / 2
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.

=== GPUREG_VIEWPORT_INVH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / height
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.

=== GPUREG_FRAGOP_CLIP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable clipping planes.

=== GPUREG_FRAGOP_CLIP_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Clipping plane coefficient ''i''
|}

This register is used to configure clipping plane coefficients.

=== GPUREG_DEPTHMAP_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near - Far
|}

This register is used to configure the depth range scale.

=== GPUREG_DEPTHMAP_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near + Polygon Offset
|}

This register is used to configure the depth range bias.

=== GPUREG_SH_OUTMAP_TOTAL ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of following attributes
|}

This register is used to configure the total shader output map attributes.

=== GPUREG_SH_OUTMAP_O''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Semantic for the x component of the register.
|-
| 8-12
| unsigned, Semantic for the y component of the register.
|-
| 16-20
| unsigned, Semantic for the z component of the register.
|-
| 24-28
| unsigned, Semantic for the w component of the register.
|}

These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.

Semantics that have not been mapped to a component of an output register have a value of 1

Semantic values:

{| class="wikitable" border="1"
! Value
! Semantic
! Description
|-
| 0x00
| position.x
| rowspan="4" | Vertex Position
|-
| 0x01
| position.y
|-
| 0x02
| position.z
|-
| 0x03
| position.w
|-
| 0x04
| normquat.x
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)
|-
| 0x05
| normquat.y
|-
| 0x06
| normquat.z
|-
| 0x07
| normquat.w
|-
| 0x08
| color.r
| rowspan="4" | Vertex color
|-
| 0x09
| color.g
|-
| 0x0A
| color.b
|-
| 0x0B
| color.a
|-
| 0x0C
| texcoord0.u
| rowspan="2" | Texture coordinates for texture 0
|-
| 0x0D
| texcoord0.v
|-
| 0x0E
| texcoord1.u
| rowspan="2" | Texture coordinates for texture 1
|-
| 0x0F
| texcoord1.v
|-
| 0x10
| texcoord0.w
|

|-
| 0x12
| view.x
| rowspan="3" | View vector (for fragment lighting)
|-
| 0x13
| view.y
|-
| 0x14
| view.z

|-
| 0x16
| texcoord2.u
| rowspan="2" | Texture coordinates for texture 2
|-
| 0x17
| texcoord2.v

|-
| 0x1F
| Unused component
| Should be set for unused components of the output register
|}

=== GPUREG_EARLYDEPTH_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Early depth function
|}

This register configures the early depth test function.

Early depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| >=
|-
| 1
| >
|-
| 2
| <=
|-
| 3
| <
|}

=== GPUREG_EARLYDEPTH_TEST1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register sets whether the early depth test is enabled.

=== GPUREG_EARLYDEPTH_CLEAR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = clear)
|}

This register triggers clearing the early depth data.

=== GPUREG_SH_OUTATTR_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Use texture coordinates (0 = don't use, 1 = use)
|}

This register is used to configure the shader output attribute mode.

=== GPUREG_SCISSORTEST_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Enabled (0 = disabled, 3 = enabled)
|}

This register is used to enable scissor testing.

=== GPUREG_SCISSORTEST_POS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X1
|-
| 16-25
| unsigned, Y1
|}

This register is used to configure the scissor test start position.

=== GPUREG_SCISSORTEST_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X2
|-
| 16-25
| unsigned, Y2
|}

This register is used to configure the scissor test end position.

=== GPUREG_VIEWPORT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| signed, X
|-
| 16-25
| signed, Y
|}

This register is used to configure the viewport position.

=== GPUREG_EARLYDEPTH_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| unsigned, Clear value
|}

This register is used to configure the early depth clear value.

=== GPUREG_DEPTHMAP_ENABLE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable depth range.

=== GPUREG_RENDERBUF_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register is used to configure the output framebuffer dimensions.

=== GPUREG_SH_OUTATTR_CLOCK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, 'position.z' present (0 = absent, 1 = present)
|-
| 1
| unsigned, 'color' component present (0 = absent, 1 = present)
|-
| 8
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)
|-
| 9
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)
|-
| 10
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)
|-
| 16
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)
|-
| 24
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)
|}

This register controls the clock supply to parts relating to certain attributes.

== Texturing registers ==

=== GPUREG_TEXUNIT_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| 0x0
|-
| 8-9
| unsigned, Texture 3 coordinates
|-
| 10
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)
|-
| 12
| 0x1
|-
| 13
| unsigned, Texture 2 coordinates
|-
| 16
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)
|-
| 17-31
| 0x0
|}

This register is used to enable texture units.

Texture 3 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 0
|-
| 1
| Texture 1
|-
| 2
| Texture 2
|}

Texture 2 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 2
|-
| 1
| Texture 1
|}

=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to set a texture unit's border color.

=== GPUREG_TEXUNIT''i''_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Height
|-
| 16-26
| unsigned, Width
|}

This register is used to set a texture unit's dimensions.

=== GPUREG_TEXUNIT''i''_PARAM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, Magnification filter
|-
| 2
| unsigned, Minification filter
|-
| 4-5
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4
|-
| 8-10
| unsigned, Wrap T
|-
| 12-14
| unsigned, Wrap S
|-
| 16-17
| 0x0
|-
| 20
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)
|-
| 24
| unsigned, Mipmap filter
|-
| 28-30
| unsigned, Type (Texture 0 only)
|}

This register is used to set a texture unit's extra parameters.

Filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|}

Wrap values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to edge
|-
| 1
| Clamp to border
|-
| 2
| Repeat
|-
| 3
| Mirrored repeat
|}

Type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 2D
|-
| 1
| Cube map
|-
| 2
| Shadow 2D
|-
| 3
| Projection
|-
| 4
| Shadow cube
|-
| 5
| Disabled
|}

=== GPUREG_TEXUNIT''i''_LOD ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.4.8, Bias
|-
| 16-19
| unsigned, Max Level
|-
| 24-27
| unsigned, Min Level
|}

This register is used to configure a texture unit's level of detail.

=== GPUREG_TEXUNIT''i''_ADDR''i'' ===

First ADDR register:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Texture physical address >> 3
|}

Subsequent ADDR registers:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-21
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)
|}

This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.

If the texture is a cube:

{| class="wikitable" border="1"
! Register
! Description
|-
| ADDR1
| Positive X
|-
| ADDR2
| Negative X
|-
| ADDR3
| Positive Y
|-
| ADDR4
| Negative Y
|-
| ADDR5
| Positive Z
|-
| ADDR6
| Negative Z
|}

Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.

=== GPUREG_TEXUNIT''i''_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Perspective (0 = perspective, 1 = not perspective)
|-
| 1-23
| fixed0.0.24, Z bias (upper 23 bits)
|}

This register is used to set a texture unit's shadow texture properties.

=== GPUREG_TEXUNIT''i''_TYPE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Format
|}

This register is used to set a texture unit's data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
! GL Format
! GL Data Type
|-
| 0x0
| RGBA8888
| GL_RGBA
| GL_UNSIGNED_BYTE
|-
| 0x1
| RGB888
| GL_RGB
| GL_UNSIGNED_BYTE
|-
| 0x2
| RGBA5551
| GL_RGBA
| GL_UNSIGNED_SHORT_5_5_5_1
|-
| 0x3
| RGB565
| GL_RGB
| GL_UNSIGNED_SHORT_5_6_5
|-
| 0x4
| RGBA4444
| GL_RGBA
| GL_UNSIGNED_SHORT_4_4_4_4
|-
| 0x5
| IA8
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x6
| HILO8
|
|
|-
| 0x7
| I8
| GL_LUMINANCE
| GL_UNSIGNED_BYTE
|-
| 0x8
| A8
| GL_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x9
| IA44
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE_4_4_EXT
|-
| 0xA
| I4
|
|
|-
| 0xB
| A4
| GL_ALPHA
| GL_UNSIGNED_NIBBLE_EXT
|-
| 0xC
| ETC1
| GL_ETC1_RGB8_OES
|
|-
| 0xD
| ETC1A4
|
|
|}

=== GPUREG_LIGHTING_ENABLE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable lighting.

=== GPUREG_TEXUNIT3_PROCTEX0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, U-direction clamp
|-
| 3-5
| unsigned, V-direction clamp
|-
| 6-9
| unsigned, RGB mapping function
|-
| 10-13
| unsigned, Alpha mapping function
|-
| 14
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)
|-
| 15
| unsigned, Noise enabled (0 = disabled, 1 = enabled)
|-
| 16-17
| unsigned, U-direction shift
|-
| 18-19
| unsigned, V-direction shift
|-
| 20-27
| float1.5.10, Texture bias (lower 8 bits)
|}

This register is used to configure the procedural texture unit.

Clamp values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to zero
|-
| 1
| Clamp to edge
|-
| 2
| Symmetrical repeat
|-
| 3
| Mirrored repeat
|-
| 4
| Pulse
|}

Mapping function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| U
|-
| 1
| U²
|-
| 2
| V
|-
| 3
| V²
|-
| 4
| (U + V) / 2
|-
| 5
| (U² + V²) / 2
|-
| 6
| sqrt(U² + V²)
|-
| 7
| Minimum
|-
| 8
| Maximum
|-
| 9
| Rmax
|}

Shift values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Odd
|-
| 2
| Even
|}

=== GPUREG_TEXUNIT3_PROCTEX1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, U-direction noise amplitude
|-
| 16-31
| float1.5.10, U-direction noise phase
|}

This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, V-direction noise amplitude
|-
| 16-31
| float1.5.10, V-direction noise phase
|}

This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, U-direction noise frequency
|-
| 16-31
| float1.5.10, V-direction noise frequency
|}

This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.

=== GPUREG_TEXUNIT3_PROCTEX4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Minification filter
|-
| 3-6
| Min LOD (usually 0)
|-
| 7-10
| Max LOD (usually 6)
|-
| 11-18
| unsigned, Texture width
|-
| 19-26
| float1.5.10, Texture bias (upper 8 bits)
|}

This register is used to configure the procedural texture unit.

Minification filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|-
| 2
| Nearest, Mipmap Nearest
|-
| 3
| Linear, Mipmap Nearest
|-
| 4
| Nearest, Mipmap Linear
|-
| 5
| Linear, Mipmap Linear
|}

=== GPUREG_TEXUNIT3_PROCTEX5 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Texture offset (Mipmap level 0 / base level)
|-
| 8-15
| unsigned, mipmap level 1 offset (usually 0x80)
|-
| 16-23
| unsigned, mipmap level 2 offset (usually 0xC0)
|-
| 24-31
| unsigned, mipmap level 3 offset (usually 0xE0)
|}

This register is used to set the procedural texture unit's offset. Mipmap level 4-7 seems to be hardcoded at offset 0xF0, 0xF8, 0xFC and 0xFE .

=== GPUREG_PROCTEX_LUT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Index
|-
| 8-11
| unsigned, Reference table
|}

This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.

Reference table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Noise table
|-
| 2
| RGB mapping function table
|-
| 3
| Alpha mapping function table
|-
| 4
| Color table
|-
| 5
| Color difference table
|}

=== GPUREG_PROCTEX_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.

==== Noise Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement ( [0.5,1.0) mapped to [-1.0,0) ), Difference from next element
|}

==== RGB Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement, Difference from next element
|}

==== Alpha Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement, Difference from next element
|}

==== Color Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

==== Color Difference Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Half of red difference between current and next color table elements
|-
| 8-15
| signed, Half of green difference between current and next color table elements
|-
| 16-23
| signed, Half of blue difference between current and next color table elements
|-
| 24-31
| signed, Half of alpha difference between current and next color table elements
|}

=== GPUREG_TEXENV''i''_SOURCE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB source 0
|-
| 4-7
| unsigned, RGB source 1
|-
| 8-11
| unsigned, RGB source 2
|-
| 16-19
| unsigned, Alpha source 0
|-
| 20-23
| unsigned, Alpha source 1
|-
| 24-27
| unsigned, Alpha source 2
|}

This register configures a texture combiner's sources.

Source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Primary color
|-
| 1
| Fragment primary color
|-
| 2
| Fragment secondary color
|-
| 3
| Texture 0
|-
| 4
| Texture 1
|-
| 5
| Texture 2
|-
| 6
| Texture 3
|-
| 13
| Previous buffer
|-
| 14
| Constant (from GPUREG_TEXENV''i''_COLOR)
|-
| 15
| Previous
|}

Using Previous (15) as a source in the first TEV stage returns the value of source 3. If source 3 has Previous it returns zero. Previous buffer (13) always returns zero.

=== GPUREG_TEXENV''i''_OPERAND ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB operand 0
|-
| 4-7
| unsigned, RGB operand 1
|-
| 8-11
| unsigned, RGB operand 2
|-
| 12-14
| unsigned, Alpha operand 0
|-
| 16-18
| unsigned, Alpha operand 1
|-
| 20-22
| unsigned, Alpha operand 2
|}

This register configures a texture combiner's operands.

RGB operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source color
|-
| 1
| One minus source color
|-
| 2
| Source alpha
|-
| 3
| One minus source alpha
|-
| 4
| Source red
|-
| 5
| One minus source red
|-
| 8
| Source green
|-
| 9
| One minus source green
|-
| 12
| Source blue
|-
| 13
| One minus source blue
|}

Alpha operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source alpha
|-
| 1
| One minus source alpha
|-
| 2
| Source red
|-
| 3
| One minus source red
|-
| 4
| Source green
|-
| 5
| One minus source green
|-
| 6
| Source blue
|-
| 7
| One minus source blue
|}

=== GPUREG_TEXENV''i''_COMBINER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB combine
|-
| 16-19
| unsigned, Alpha combine
|}

This register configures a texture combiner's combine mode.

Combine values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Replace
|-
| 1
| Modulate
|-
| 2
| Add
|-
| 3
| Add signed
|-
| 4
| Interpolate
|-
| 5
| Subtract
|-
| 6
| Dot3 RGB
|-
| 7
| Dot3 RGBA
|-
| 8
| Multiply then add
|-
| 9
| Add then multiply
|}

=== GPUREG_TEXENV''i''_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register configures a texture combiner's constant color.

=== GPUREG_TEXENV''i''_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, RGB scale
|-
| 16-17
| unsigned, Alpha scale
|}

This register configures a texture combiner's scale value.

Scale values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|}

=== GPUREG_TEXENV_UPDATE_BUFFER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fog mode
|-
| 3
| unsigned, Shading density source
|-
| 8
| unsigned, TexEnv 1 RGB buffer input
|-
| 9
| unsigned, TexEnv 2 RGB buffer input
|-
| 10
| unsigned, TexEnv 3 RGB buffer input
|-
| 11
| unsigned, TexEnv 4 RGB buffer input
|-
| 12
| unsigned, TexEnv 1 alpha buffer input
|-
| 13
| unsigned, TexEnv 2 alpha buffer input
|-
| 14
| unsigned, TexEnv 3 alpha buffer input
|-
| 15
| unsigned, TexEnv 4 alpha buffer input
|-
| 16
| unsigned, Z flip (0 = don't flip, 1 = flip)
|-
| 24-25
| 0x0
|}

This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.

Fog mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Disabled
|-
| 5
| Fog
|-
| 7
| Gas
|}

Shading density source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Plain density
|-
| 1
| Depth density
|}

Buffer input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Previous buffer
|-
| 1
| Previous
|}

=== GPUREG_FOG_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

This register is used to configure the color of fog.

=== GPUREG_GAS_ATTENUATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas density attenuation
|}

This register is used to configure the gas density attenuation.

=== GPUREG_GAS_ACCMAX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas maximum density accumulation
|}

This register is used to configure the gas maximum density accumulation.

=== GPUREG_FOG_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.

=== GPUREG_FOG_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.

==== Fog Look-Up Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Difference from next element
|-
| 13-23
| fixed0.0.11, Value
|}

=== GPUREG_TEXENV_BUFFER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the texture combiner buffer color.

== Framebuffer registers ==

=== GPUREG_COLOR_OPERATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Fragment operation mode
|-
| 8
| unsigned, Blend mode
|-
| 16-25
| 0x0E4
|}

This register is used to configure the fragment operation mode and whether to use logic ops or blending.

Fragment operation mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Default
|-
| 1
| Gas
|-
| 3
| Shadow
|}

Blend mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Logic op
|-
| 1
| Blend
|}

=== GPUREG_BLEND_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, RGB equation
|-
| 8-10
| unsigned, Alpha equation
|-
| 16-19
| unsigned, RGB source function
|-
| 20-23
| unsigned, RGB destination function
|-
| 24-27
| unsigned, Alpha source function
|-
| 28-31
| unsigned, Alpha destination function
|}

This register is used to configure the blending function.

'''Equation values:'''

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Add
|-
| 1
| Subtract
|-
| 2
| Reverse subtract
|-
| 3
| Minimum
|-
| 4
| Maximum
|}

Blend equations 5, 6, 7 appear to behave the same as blend equation 0 (Add)

'''Function values:'''

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Zero
|-
| 1
| One
|-
| 2
| Source color
|-
| 3
| One minus source color
|-
| 4
| Destination color
|-
| 5
| One minus destination color
|-
| 6
| Source alpha
|-
| 7
| One minus source alpha
|-
| 8
| Destination alpha
|-
| 9
| One minus destination alpha
|-
| 10
| Constant color
|-
| 11
| One minus constant color
|-
| 12
| Constant alpha
|-
| 13
| One minus constant alpha
|-
| 14
| Source alpha saturate
|}

=== GPUREG_LOGIC_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Logic op
|}

This register is used to configure the logic op.

Logic op values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clear
|-
| 1
| AND
|-
| 2
| Reverse AND
|-
| 3
| Copy
|-
| 4
| Set
|-
| 5
| Inverted copy
|-
| 6
| Noop
|-
| 7
| Invert
|-
| 8
| NAND
|-
| 9
| OR
|-
| 10
| NOR
|-
| 11
| XOR
|-
| 12
| Equivalent
|-
| 13
| Inverted AND
|-
| 14
| Reverse OR
|-
| 15
| Inverted OR
|}

=== GPUREG_BLEND_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the blending color.

=== GPUREG_FRAGOP_ALPHA_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Reference value
|}

This register is used to configure alpha testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Buffer mask
|-
| 16-23
| signed, Reference value
|-
| 24-31
| unsigned, Mask
|}

This register is used to configure stencil testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fail operation
|-
| 4-6
| unsigned, Z-fail operation
|-
| 8-10
| unsigned, Z-pass operation
|}

This register is used to configure stencil result operations.

Operation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Keep
|-
| 1
| Zero
|-
| 2
| Replace
|-
| 3
| Increment
|-
| 4
| Decrement
|-
| 5
| Invert
|-
| 6
| Increment and wrap
|-
| 7
| Decrement and wrap
|}

=== GPUREG_DEPTH_COLOR_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Depth function
|-
| 8
| unsigned, Red write enabled (0 = disabled, 1 = enabled)
|-
| 9
| unsigned, Green write enabled (0 = disabled, 1 = enabled)
|-
| 10
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)
|-
| 11
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)
|-
| 12
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
|}

This register is used to depth testing and framebuffer write masking.

Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.

Depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = invalidate)
|-
| 1-31
| 0x0
|}

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = flush)
|-
| 1-31
| 0x0
|}

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_COLORBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow read (0 = disable, 0xF = enable)
|}

This register configures read access from the color buffer.

=== GPUREG_COLORBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow write (0 = disable, 0xF = enable)
|}

This register configures write access to the color buffer.

=== GPUREG_DEPTHBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil read (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth read (0 = disable, 1 = enable)
|}

This register configures read access from the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil write (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth write (0 = disable, 1 = enable)
|}

This register configures write access to the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Format
|}

This register configures the depth buffer data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil
|}

=== GPUREG_COLORBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Pixel size
|-
| 16-18
| unsigned, Format
|}

This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.

Pixel size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit color
|-
| 2
| 32-bit color
|}

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| RGBA8/Gas
|-
| 2
| RGB5A1
|-
| 3
| RGB565
|-
| 4
| RGBA4
|}

=== GPUREG_EARLYDEPTH_TEST2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register enables the early depth test.

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Render block mode
|}

This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

Render block mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8x8 blocks
|-
| 1
| 32x32 blocks
|}

=== GPUREG_DEPTHBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Depth buffer physical address >> 3
|}

This register configures the depth buffer physical address.

=== GPUREG_COLORBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Color buffer physical address >> 3
|}

This register configures the color buffer physical address.

=== GPUREG_FRAMEBUFFER_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register configures the framebuffer dimensions.

=== GPUREG_GAS_LIGHT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Planar shading minimum intensity
|-
| 8-15
| unsigned, Planar shading maximum intensity
|-
| 16-23
| unsigned, Planar shading density attenuation
|}

This register configures gas light planar shading.

=== GPUREG_GAS_LIGHT_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading minimum intensity
|-
| 8-15
| unsigned, View shading maximum intensity
|-
| 16-23
| unsigned, View shading density attenuation
|}

This register configures gas light view shading.

=== GPUREG_GAS_LIGHT_Z_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading effect in line-of-sight direction
|-
| 8
| Gas color LUT input
|}

This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.

Color LUT input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Gas density
|-
| 1
| Light factor
|}

=== GPUREG_GAS_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.

=== GPUREG_GAS_LUT_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.

==== Gas Look-Up Table ====

16 elements:

First 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Red
|-
| 8-15
| signed, Green
|-
| 16-23
| signed, Blue
|}

Last 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

=== GPUREG_GAS_DELTAZ_DEPTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| fixed0.16.8, Depth direction attenuation proportion
|-
| 24-25
| unsigned, Depth function
|}

This register is used to configure the gas depth direction attenuation proportion, as well as the gas depth function.

Gas depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Greater than/Greater than or equal
|-
| 3
| Less than/Less than or equal/Equal/Not equal
|}

=== GPUREG_FRAGOP_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Sum of penumbra scale and penumbra bias
|-
| 16-31
| float1.5.10, Penumbra scale with reversed sign
|}

This register is used to configure shadow properties.

== Fragment lighting registers ==

=== GPUREG_LIGHT''i''_SPECULAR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.

=== GPUREG_LIGHT''i''_SPECULAR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.

=== GPUREG_LIGHT''i''_DIFFUSE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

=== GPUREG_LIGHT''i''_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.

=== GPUREG_LIGHT''i''_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, X coordinate
|-
| 16-31
| float1.5.10, Y coordinate
|}

These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Z coordinate
|}

These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, X coordinate (negated)
|-
| 16-28
| fixed1.1.11, Y coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Z coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Light type (0 = positional light, 1 = directional light)
|-
| 1
| unsigned, Two side diffuse (0 = one side, 1 = both sides)
|-
| 2
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)
|-
| 3
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)
|}

This register configures a light's properties.

=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation bias
|}

These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation scale
|}

These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHTING_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

=== GPUREG_LIGHTING_NUM_LIGHTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of active lights - 1
|}

This register configures the number of active lights.

=== GPUREG_LIGHTING_CONFIG0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)
|-
| 2-3
| unsigned, Fresnel selector
|-
| 4-7
| unsigned, Light environment configuration
|-
| 8-11
| 0x4
|-
| 16
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)
|-
| 17
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)
|-
| 18
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)
|-
| 19
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)
|-
| 22-23
| unsigned, Bump map texture unit
|-
| 24-25
| unsigned, Shadow map texture unit
|-
| 27
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)
|-
| 28-29
| unsigned, Bump mode
|-
| 30
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)
|-
| 31
| 0x1
|}

This register configures the light environment.

Fresnel selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Primary alpha
|-
| 2
| Secondary alpha
|-
| 3
| Primary and secondary alpha
|}

The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.

Light environment configuration values:

{| class="wikitable" border="1"
! Value
! Description
! Available LUTs
|-
| 0
| Configuration 0
| D0, RR, SP, DA
|-
| 1
| Configuration 1
| FR, RR, SP, DA
|-
| 2
| Configuration 2
| D0, D1, RR, DA
|-
| 3
| Configuration 3
| D0, D1, FR, DA
|-
| 4
| Configuration 4
| All except for FR
|-
| 5
| Configuration 5
| All except for D1
|-
| 6
| Configuration 6
| All except for RB and RG
|-
| 8
| Configuration 7
| All
|}

Bump mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Not used
|-
| 1
| Use as bump map
|-
| 2
| Use as tangent map
|}

=== GPUREG_LIGHTING_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)
|-
| 1
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)
|-
| 2
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)
|-
| 3
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)
|-
| 4
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)
|-
| 6
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)
|-
| 7
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)
|-
| 8
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)
|-
| 10
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)
|-
| 11
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)
|-
| 12
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)
|-
| 14
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)
|-
| 15
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)
|-
| 16
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)
|-
| 18
| 0x1
|-
| 19
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
|-
| 20
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 1 = disabled)
|-
| 22
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 1 = disabled)
|-
| 24
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 26
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 27
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 28
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 29
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 30
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 31
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)
|}

This register is used to disable various aspects of the light environment.

=== GPUREG_LIGHTING_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Starting index
|-
| 8-12
| unsigned, Look-up table
|}

This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.

Lookup table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| D0
|-
| 1
| D1
|-
| 3
| FR
|-
| 4
| RB
|-
| 5
| RG
|-
| 6
| RR
|-
| 8-15
| SP0-7
|-
| 16-23
| DA0-7
|}

=== GPUREG_LIGHTING_ENABLE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Disabled (0 = enabled, 1 = disabled)
|}

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

=== GPUREG_LIGHTING_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

Lighting LUT data is written here.

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.

Format of an entry:

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Entry value
|-
| 12-23
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation
|}

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)
|}

This register controls whether the absolute value of the input is taken before using a LUT.

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Input selector for D0
|-
| 4-6
| unsigned, Input selector for D1
|-
| 8-10
| unsigned, Input selector for SP
|-
| 12-14
| unsigned, Input selector for FR
|-
| 16-18
| unsigned, Input selector for RB
|-
| 20-22
| unsigned, Input selector for RG
|-
| 24-26
| unsigned, Input selector for RR
|}

This register selects the input from LUTs.

Input selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Scaler selector for D0
|-
| 4-6
| unsigned, Scaler selector for D1
|-
| 8-10
| unsigned, Scaler selector for SP
|-
| 12-14
| unsigned, Scaler selector for FR
|-
| 16-18
| unsigned, Scaler selector for RB
|-
| 20-22
| unsigned, Scaler selector for RG
|-
| 24-26
| unsigned, Scaler selector for RR
|}

This register controls the scaling that is applied to the output of a LUT.

Scaler selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, ID of the 1st enabled light
|-
| 4-6
| unsigned, ID of the 2nd enabled light
|-
| 8-10
| unsigned, ID of the 3rd enabled light
|-
| 12-14
| unsigned, ID of the 4th enabled light
|-
| 16-18
| unsigned, ID of the 5th enabled light
|-
| 20-22
| unsigned, ID of the 6th enabled light
|-
| 24-26
| unsigned, ID of the 7th enabled light
|-
| 28-30
| unsigned, ID of the 8th enabled light
|}

This register sets the IDs of enabled light sources.

== Geometry pipeline registers ==

=== GPUREG_ATTRIBBUFFERS_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-28
| unsigned, Vertex arrays base address
|}

This register sets the base address of all vertex arrays.

=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 0 type
|-
| 2-3
| unsigned, Vertex attribute 0 size
|-
| 4-5
| unsigned, Vertex attribute 1 type
|-
| 6-7
| unsigned, Vertex attribute 1 size
|-
| 8-9
| unsigned, Vertex attribute 2 type
|-
| 10-11
| unsigned, Vertex attribute 2 size
|-
| 12-13
| unsigned, Vertex attribute 3 type
|-
| 14-15
| unsigned, Vertex attribute 3 size
|-
| 16-17
| unsigned, Vertex attribute 4 type
|-
| 18-19
| unsigned, Vertex attribute 4 size
|-
| 20-21
| unsigned, Vertex attribute 5 type
|-
| 22-23
| unsigned, Vertex attribute 5 size
|-
| 24-25
| unsigned, Vertex attribute 6 type
|-
| 26-27
| unsigned, Vertex attribute 6 size
|-
| 28-29
| unsigned, Vertex attribute 7 type
|-
| 30-31
| unsigned, Vertex attribute 7 size
|}

This register configures the types and sizes of the first 8 vertex attributes.

Vertex attribute type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Byte
|-
| 1
| Unsigned byte
|-
| 2
| Short
|-
| 3
| Float
|}

Vertex attribute size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8 bits
|-
| 1
| 16 bits
|-
| 2
| 24 bits
|-
| 3
| 32 bits
|}

=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 8 type
|-
| 2-3
| unsigned, Vertex attribute 8 size
|-
| 4-5
| unsigned, Vertex attribute 9 type
|-
| 6-7
| unsigned, Vertex attribute 9 size
|-
| 8-9
| unsigned, Vertex attribute 10 type
|-
| 10-11
| unsigned, Vertex attribute 10 size
|-
| 12-13
| unsigned, Vertex attribute 11 type
|-
| 14-15
| unsigned, Vertex attribute 11 size
|-
| 16-27
| unsigned, Fixed vertex attribute mask
|-
| 28-31
| unsigned, Total vertex attribute count - 1
|}

This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.

See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.

=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|}

This register configures the offset of a vertex array from the base vertex arrays address.

=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 1
|-
| 4-7
| unsigned, Component 2
|-
| 8-11
| unsigned, Component 3
|-
| 12-15
| unsigned, Component 4
|-
| 16-19
| unsigned, Component 5
|-
| 20-23
| unsigned, Component 6
|-
| 24-27
| unsigned, Component 7
|-
| 28-31
| unsigned, Component 8
|}

This register configures the first 8 component types of a vertex array.

Component values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Vertex attribute 0
|-
| 1
| Vertex attribute 1
|-
| 2
| Vertex attribute 2
|-
| 3
| Vertex attribute 3
|-
| 4
| Vertex attribute 4
|-
| 5
| Vertex attribute 5
|-
| 6
| Vertex attribute 6
|-
| 7
| Vertex attribute 7
|-
| 8
| Vertex attribute 8
|-
| 9
| Vertex attribute 9
|-
| 10
| Vertex attribute 10
|-
| 11
| Vertex attribute 11
|-
| 12
| 4-byte padding
|-
| 13
| 8-byte padding
|-
| 14
| 12-byte padding
|-
| 15
| 16-byte padding
|}

=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 9
|-
| 4-7
| unsigned, Component 10
|-
| 8-11
| unsigned, Component 11
|-
| 12-15
| unsigned, Component 12
|-
| 16-23
| unsigned, Bytes per vertex
|-
| 28-31
| unsigned, Total number of components
|}

This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.

See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.

=== GPUREG_INDEXBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|-
| 31
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)
|}

This register configures the index array used when drawing elements.

=== GPUREG_NUMVERTICES ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Number of vertices to render
|}

This register sets the number of vertices to render.

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|-
| 9
| 0x0
|-
| 31
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_VERTEX_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Starting vertex offset
|}

This register sets the offset of the first vertex in an array to render.

=== GPUREG_POST_VERTEX_CACHE_NUM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)
|}

This register configures the post-vertex cache.

=== GPUREG_DRAWARRAYS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw arrays)
|}

This register triggers drawing vertex arrays.

=== GPUREG_DRAWELEMENTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw elements)
|}

This register triggers drawing vertex array elements.

=== GPUREG_VTX_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)
|}

This register triggers clearing the post-vertex cache.

=== GPUREG_FIXEDATTRIB_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)
|}

This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

=== GPUREG_FIXEDATTRIB_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| colspan="2" | '''DATA0:'''
|-
| 0-7
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)
|-
| 8-31
| float1.7.16, Vertex attribute element 4 (W)
|-
| colspan="2" | '''DATA1:'''
|-
| 0-15
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)
|-
| 16-31
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)
|-
| colspan="2" | '''DATA2:'''
|-
| 0-23
| float1.7.16, Vertex attribute element 1 (X)
|-
| 24-31
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)
|}

Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.

=== GPUREG_CMDBUF_SIZE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 0 >> 3
|}

This register sets the size of the first command buffer.

=== GPUREG_CMDBUF_SIZE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 1 >> 3
|}

This register sets the size of the second command buffer.

=== GPUREG_CMDBUF_ADDR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 0 >> 3
|}

This register sets the physical address of the first command buffer.

=== GPUREG_CMDBUF_ADDR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 1 >> 3
|}

This register sets the physical address of the second command buffer.

=== GPUREG_CMDBUF_JUMP0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)
|}

This register triggers a jump to the first command buffer.

=== GPUREG_CMDBUF_JUMP1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)
|}

This register triggers a jump to the second command buffer.

=== GPUREG_VSH_NUM_ATTR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader input attributes - 1
|}

This register sets the number of vertex shader input attributes.

=== GPUREG_VSH_COM_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)
|}

This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.
When disabled and the geometry unit is not in use, as configured by GPUREG_GEOSTAGE_CONFIG, uniforms, outmap mask, program code and swizzle data are propagated to the geometry shader unit.

=== GPUREG_START_DRAW_FUNC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Mode (0 = drawing, 1 = configuration)
|-
| 1-7
| 0x0
|}

This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.

=== GPUREG_VSH_OUTMAP_TOTAL1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_VSH_OUTMAP_TOTAL2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_GSH_MISC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)
|}

This register configures miscellaneous geometry shader properties.

=== GPUREG_GEOSTAGE_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_GSH_MISC1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)
|}

This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.

=== GPUREG_PRIMITIVE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|-
| 8-9
| unsigned, Primitive mode
|}

This register configures primitive drawing.

Primitive mode value:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Triangles
|-
| 1
| Triangle strip
|-
| 2
| Triangle fan
|-
| 3
| Geometry primitive
|}

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = reset primitive)
|-
| 1-31
| 0x0
|}

This register triggers resetting primitive drawing.

== Shader registers ==

=== GPUREG_''SH''_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Boolean register b0 value (0 = false, 1 = true)
|-
| 1
| unsigned, Boolean register b1 value (0 = false, 1 = true)
|-
| 2
| unsigned, Boolean register b2 value (0 = false, 1 = true)
|-
| 3
| unsigned, Boolean register b3 value (0 = false, 1 = true)
|-
| 4
| unsigned, Boolean register b4 value (0 = false, 1 = true)
|-
| 5
| unsigned, Boolean register b5 value (0 = false, 1 = true)
|-
| 6
| unsigned, Boolean register b6 value (0 = false, 1 = true)
|-
| 7
| unsigned, Boolean register b7 value (0 = false, 1 = true)
|-
| 8
| unsigned, Boolean register b8 value (0 = false, 1 = true)
|-
| 9
| unsigned, Boolean register b9 value (0 = false, 1 = true)
|-
| 10
| unsigned, Boolean register b10 value (0 = false, 1 = true)
|-
| 11
| unsigned, Boolean register b11 value (0 = false, 1 = true)
|-
| 12
| unsigned, Boolean register b12 value (0 = false, 1 = true)
|-
| 13
| unsigned, Boolean register b13 value (0 = false, 1 = true)
|-
| 14
| unsigned, Boolean register b14 value (0 = false, 1 = true)
|-
| 15
| unsigned, Boolean register b15 value (0 = false, 1 = true)
|-
| 16-31
| 0x7FFF
|}

This register is used to set a shader unit's boolean registers.

=== GPUREG_''SH''_INTUNIFORM_I''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Integer register i''i'' X value
|-
| 8-15
| unsigned, Integer register i''i'' Y value
|-
| 16-23
| unsigned, Integer register i''i'' Z value
|-
| 24-31
| unsigned, Integer register i''i'' W value
|}

These registers are used to set a shader unit's integer registers.

=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Input vertex attributes - 1
|-
| 8-15
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)
|-
| 16-23
| 0x0
|-
| 24-31
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)
|}

This register is used to configure a shader unit's input buffer.

=== GPUREG_''SH''_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Code entry point offset, in 32-bit words
|-
| 16-31
| 0x7FFF
|}

This register sets a shader unit's code entry point.

For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.

For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 0 input register index
|-
| 4-7
| unsigned, Vertex attribute 1 input register index
|-
| 8-11
| unsigned, Vertex attribute 2 input register index
|-
| 12-15
| unsigned, Vertex attribute 3 input register index
|-
| 16-19
| unsigned, Vertex attribute 4 input register index
|-
| 20-23
| unsigned, Vertex attribute 5 input register index
|-
| 24-27
| unsigned, Vertex attribute 6 input register index
|-
| 28-31
| unsigned, Vertex attribute 7 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 8 input register index
|-
| 4-7
| unsigned, Vertex attribute 9 input register index
|-
| 8-11
| unsigned, Vertex attribute 10 input register index
|-
| 12-15
| unsigned, Vertex attribute 11 input register index
|-
| 16-19
| unsigned, Vertex attribute 12 input register index
|-
| 20-23
| unsigned, Vertex attribute 13 input register index
|-
| 24-27
| unsigned, Vertex attribute 14 input register index
|-
| 28-31
| unsigned, Vertex attribute 15 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_''SH''_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)
|-
| 4
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)
|-
| 5
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)
|-
| 6
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)
|-
| 7
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 8
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 9
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 10
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 11
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 12
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 13
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 14
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 15
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 16-31
| 0x0
|}

This register toggles a shader unit's output registers.

=== GPUREG_''SH''_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Signal transfer end (0 = idle, non-zero = signal)
|}

This register's value should be set to 1 in order to finalize the transfer of shader code.

=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)
|}

This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.

=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Floating-point register component data
|}

This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_''SH''_CODETRANSFER_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader code offset
|}

This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.

=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader instruction data
|}

This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.

=== GPUREG_''SH''_OPDESCS_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader operand descriptor offset
|}

This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.

=== GPUREG_''SH''_OPDESCS_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader operand descriptor data
|}

This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.

Memory Management

2024-03-30T23:29:21Z

Emufan4568: Update FCRAM memory management from latest TuxSH kernel idb

= Types and structures =

== enum MemoryOperation ==

{| class="wikitable" border="1"
! Memory operation
! Id
|-
| FREE
| 1
|-
| RESERVE
| 2
|-
| COMMIT
| 3
|-
| MAP
| 4
|-
| UNMAP
| 5
|-
| PROTECT
| 6
|-
| REGION APP
| 0x100
|-
| REGION SYSTEM
| 0x200
|-
| REGION BASE
| 0x300
|-
| LINEAR
| 0x10000
|}

The LINEAR memory-operation indicates that the mapped physical address is always MappedVAddr+0x0C000000, thus this memory can be used for hardware devices' DMA(such as the [[GPU]]). Addr0+size for this must be within the 0x14000000-0x1C000000 range when Addr0 is non-zero(Addr1 must be zero), Addr0 isn't actually used by svcControlMemory for mapping memory: Addr0 is not used by the kernel after doing address-range checks. The kernel determines what physical-address to use by allocating memory from FCRAM(about the same way as other memory), which is then used to determine the virtual-address.

[[8.0.0-18]] added a new memory mapping(0x30000000-0x38000000) for LINEAR memory, this replaces the original mapping for newer titles. The kernel uses the new mapping when the process memory-region is BASE, or when the process kernel-release-version field is >=0x022c(2.44 / system-version [[8.0.0-18]]).

The input mem-region value for svcControlMemory is only used(when non-zero) when the PID is value 1, for the [[FIRM]] ARM11 "loader" module.

== enum MemoryPermission ==

{| class="wikitable" border="1"
! Memory permission
! Id
|-
| NONE
| 0
|-
| R
| 1
|-
| W (Invalid, see below)
| 2
|-
| RW
| 3
|-
| X
| 4
|-
| RX
| 5
|-
| WX
| 6
|-
| RWX
| 7
|-
| DONTCARE
| 0x10000000
|}

Specifying write-permission without read-permission is invalid, it's handled the same way as if the RW bits were not set(ARM11-MPCore doesn't support write-only memory permissions).

== enum MemoryState ==
{| class="wikitable" border="1"
! Memory state flags
! Value
|-
| FREE
| 0
|-
| RESERVED
| 1
|-
| IO
| 2
|-
| STATIC
| 3
|-
| CODE
| 4
|-
| PRIVATE
| 5
|-
| SHARED
| 6
|-
| CONTINUOUS
| 7
|-
| ALIASED
| 8
|-
| ALIAS
| 9
|-
| ALIAS CODE
| 10
|-
| LOCKED
| 11
|}

== struct MemoryInfo ==
{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Base process virtual address
|-
| u32
| Size
|-
| u32
| Permission
|-
| enum MemoryState
| State
|}

== enum PageFlags ==
{| class="wikitable" border="1"
! Page flags
! Bit
|-
| LOCKED
| 0
|-
| CHANGED
| 1
|}

== struct PageInfo ==
{| class="wikitable" border="1"
! Type
! Field
|-
| PageFlags (u32)
| Flags
|}

= Memory Mapping =
ControlMemory and MapMemoryBlock can be used to map memory pages, these two SVCs only support mapping execute-never R/W pages. The input permissions parameter for these SVCs must therefore be <=3, where value zero is used when un-mapping memory. Furthermore it appears that only regular heap pages can be mirrored (it won't work for TLS, stack, .data, .text, for example).

Bitmask 0xF00 for ControlMemory parameter MemoryType is the memory-type, when this is zero the memory-type is loaded from the kernel flags stored in the exheader ARM11 kernel descriptors, for the process using the SVC.

ControlMemory parameter MemoryType with value 0x10003 is used for mapping the GSP [[Memory_layout|heap]]. The low 8-bits are the type: 1 is for un-mapping memory, 3 for mapping memory. Type4 is used to mirror the RW memory at Addr1, to Addr0. Type4 will return an error if Addr1 is located in read-only memory. Addr1 is not used for type1 and type3.

The ARM11 kernel does not allow processes to create shared memory blocks via svcCreateMemoryBlock, when the process memorytype (from the kernel flags stored in the exheader kernel descriptor) is the application memorytype, and when addr=0. When the memorytype is not the application memorytype and addr=0, the kernel allocates new memory for the calling process and turns it into a shared memory block. When addr is non-zero, it must be located in memory which is already mapped. Furthermore, it appears that only regular heap pages (allocated using svcControlMemory op=COMMIT) are accepted as valid addrs. The addr(+size) must be >=0x00100000 and <0x14000000.

ControlProcessMemory maps memory in the specified process, this is the only SVC which allows mapping executable memory. Format of the permissions field for memory mapping SVCs: bit0=R, bit1=W, bit2=X. Type6 sets the Addr0 memory permissions to the input permissions, for already mapped memory. Type is the MemoryOperation enum, without the memory-type/memory-region. ControlProcessMemory only supports type4, type5, and type6. ControlProcessMemory does not support using the current KProcess handle alias.

Note that with the MAP MemoryOperation, the kernel will refuse to MAP memory for the specified addr1, when addr1 was already used with another MAP operation as addr1. The kernel also doesn't allow memory to be freed via the FREE MemoryOperation, when other virtual-memory is mapped to this same memory(when the MAP MemoryOperation was used with this memory with addr1). With the MAP MemoryOperation, the memory permissions for the original buffer are also set to no-access.

<code>'''MapProcessMemory'''(Handle process, u32 destAddr, u32 limit)</code> maps memory from the given process into the current process. This memory is mapped with permissions RW-, regardless of the permissions for the memory under the specified process. First <code>min(limit, 0x3F00000)</code> bytes are mapped starting from <code>0x00100000</code> in the source process to <code>destAddr</code> in the current process. Then <code>min(limit - 0x7F00000, 0x6000000)</code> bytes (if more than 0) are mapped from <code>0x08000000</code> in the source process to <code>destAddr + 0x7F00000</code> in the current process. Another way to view this is that it is overlaying the two ranges <code>[0x0010_0000; 0x0400_0000]</code> and <code>[0x0800_0000; 0x0E00_0000]</code> from the source process onto <code>[destAddr - 0x100000; destAddr + limit]</code> in the current process, truncating whatever part of the mapping that doesn't fit. This system call is used by [[RO Services]] to map the program's code and heap into ro. Memory mapped by MapProcessMemory is unmapped by UnmapProcessMemory.

= How The Kernel Allocates And Tracks Memory =

FCRAM (128MiB for O3DS, or 256MiB for N3DS) is divided into three regions: APPLICATION, SYSTEM and BASE. A program is allowed to allocate memory in one of the three region. (For example games are always in the APPLICATION region). Inside one region, there are two kinds of memory that can be allocated: (regular) heap and linear heap.

(Regular) heap is allocated starting from the end of the memory region, and growing down. They are mostly for application private use, and sometimes for software-based memory sharing (with other process using KSharedMemory, for example). They can be mapped to anywhere inside 0x08000000~0x10000000 virtual memory range upon application request. When the application requests for a block of heap, the block is not guaranteed continuous in FCRAM and the location is not specified either.

Linear heap is allocated starting from the beginning of the memory region, and growing up. They are mostly for hardware-based memory sharing (with GPU, DMA etc.), but can also be used privately as well. They can be mapped to the linear heap virtual memory region (0x14000000+ or 0x30000000+, depending on game's kernel version). When the application requests for a linear heap block, the block is always continuous in FCRAM, and the difference between physical address and virtual address is always a constant. Therefore it gives virtual to physical address convertibility, which enables communication with other hardware.

Each region in the kernel is managed by a dedicated KPageHeap object, which tracks free memory blocks. Each free block is represented with a KPageHeapBlock structure stored in FCRAM that stores the size of the free region and links to adjacent blocks. When a chunk of memory is allocated from the heap, the block is removed from the linked list and the region is cleared, erasing the header. On initialization a free block is inserted that covers the entire region.

== KPageHeapBlock ==

Size: 0xC-bytes(?) pre-v11.0, 0x18-bytes starting with v11.0.

{| class="wikitable" border="1"
|-
! Offset
! Type
! Description
|-
| 0x0
| u32
| Size in pages
|-
| 0x4
| KPageHeapBlock*
| Next
|-
| 0x8
| KPageHeapBlock*
| Prev
|-
| 0xC
| KPageHeapBlock*
| Pointer to the current memchunk. Added with v11.0?
|-
| 0x10
| u32
| Nonce, doesn't seem to be read at all except during MAC calculation. Added with v11.0. Used with the new heap [[11.0.0-33|security]] feature. A kernel state field is copied to this field before calculating the MAC. Once done, that kernel state field is subtracted by the value of the calculated MAC stored below. Since this kernel state field is initially 0x0, this field for the FCRAM APPLICATION+0 KPageHeapBlock during kernel boot is set to 0x0.
|-
| 0x14
| u32
| MAC calculated over rest of struct. Added with v11.0. Used with the new heap [[11.0.0-33|security]] feature.
|}

== KPageHeap ==

Size: 0x10-bytes pre-[[11.0.0-33|11.0.0-X]], 0x20-bytes starting with [[11.0.0-33|11.0.0-X]].

{| class="wikitable" border="1"
|-
! Offset
! Type
! Description
|-
| 0x0
| KPageHeapBlock*
| First
|-
| 0x4
| KPageHeapBlock*
| Last
|-
| 0x8
| u32
| Region start
|-
| 0xC
| u32
| Region size
|-
| 0x10
| 0x10-byte block.
| This is the "key" used with the kernel heap MAC implemented with [[11.0.0-33|11.0.0-X]].
|}

The KPageHeap objects are owned by the KMemoryManager. This object acts as a light wrapper that abstracts allocations and freeing of memory from the heaps and handles page reference tracking.

== KMemoryManager ==

Size: 0x50-bytes pre-[[11.0.0-33|11.0.0-X]], 0x80-bytes starting with [[11.0.0-33|11.0.0-X]].

X = KPageHeap_size*3.

{| class="wikitable" border="1"
|-
! Offset
! Type
! Description
|-
| 0x0
| KPageHeap
| KPageHeap for app memory
|-
| KPageHeap_size*1
| KPageHeap
| KPageHeap for sys memory
|-
| KPageHeap_size*2
| KPageHeap
| KPageHeap for base memory
|-
| X + 0x0
| KMemoryManager*
| Ptr to start of FCRAM region descriptor
|-
| X + 0x4
| u32
| FCRAM start
|-
| X + 0x8
| u32
| FCRAM size in pages
|-
| X + 0xC
| u32*
| Pointer to FCRAM memory used for page reference tracking. Each u32 represents a page.
|-
| X + 0x10
| u32
| Count of physical FCRAM used by the kernel, in bytes. (used by [[SVC|svcGetSystemInfo]])
|-
| X + 0x14
| u32
| ?
|-
| X + 0x18
| KLightMutex
| Mutex used for thread synchronization during memory (de)allocation from the heaps.
|}

== Kernel Region Descriptor ==

GPU/Internal Registers

2024-01-24T15:36:55Z

Emufan4568: Update GPUREG_VSH_COM_MODE from hardware findings

[[Category:GPU]]

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).

In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.

For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).

Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.

The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.

=== Command Header ===
{| class="wikitable" border="1"
! Bit
! Description
|-
| 0-15
| Command ID
|-
| 16-19
| Parameter mask
|-
| 20-27
| Number of extra parameters (may be zero)
|-
| 28-30
| Unused
|-
| 31
| Consecutive writing mode
|}

=== Parameter masking ===

Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]

=== Data Types ===

{| class="wikitable" border="1"
! Name
! Description
|-
| signed
| Signed integer
|-
| unsigned
| Unsigned integer
|-
| floatX.Y.Z
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits
|-
| fixedX.Y.Z
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits
|}

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|PICA_REG_INTERRUPT
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]
|?
|PICA_REG_FRAGOP_CLIP
|-
| 0048
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]
|?
|PICA_REG_FRAGOP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]
|?
|PICA_REG_FRAGOP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]
|?
|PICA_REG_FRAGOP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]
|?
|PICA_REG_FRAGOP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]
|
|PICA_REG_EARLY_DEPTH_CLEAR
|-
| 0064
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]
|?
|PICA_REG_FRAGOP_WSCALE
|-
| 006E
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]
|?
|PICA_REG_TEXTURE3_PROCTEX0
|-
| 00A9
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]
|?
|PICA_REG_TEXTURE3_PROCTEX1
|-
| 00AA
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]
|?
|PICA_REG_TEXTURE3_PROCTEX2
|-
| 00AB
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]
|?
|PICA_REG_TEXTURE3_PROCTEX3
|-
| 00AC
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]
|?
|PICA_REG_TEXTURE3_PROCTEX4
|-
| 00AD
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]
|?
|PICA_REG_TEXTURE3_PROCTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]
|?
|PICA_REG_PROCTEX_LUT
|-
| 00B0
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]
| ?
|PICA_REG_PROCTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]
| ?
|PICA_REG_PROCTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]
| ?
|PICA_REG_PROCTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]
| ?
|PICA_REG_PROCTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]
| ?
|PICA_REG_PROCTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]
| ?
|PICA_REG_PROCTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]
| ?
|PICA_REG_PROCTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]
| ?
|PICA_REG_PROCTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]
|
|PICA_REG_FRAGOP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]
|?
|PICA_REG_FRAGOP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS
|-
| 019B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS
|-
| 01AB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS
|-
| 01BB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA5
|-
| 01CE
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]
|
|PICA_REG_POST_VERTEX_CACHE_NUM
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH0
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH1
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH0
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH1
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|PICA_REG_COMMAND_BUF_KICK_CH0
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|PICA_REG_COMMAND_BUF_KICK_CH1
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_GS_FLOAT_DATA0
|-
| 0292
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0293
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0294
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0295
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0296
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0297
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0298
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_VS_FLOAT_DATA0
|-
| 02C2
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C3
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C4
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C5
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C6
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C7
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C8
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)
|}

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

=== GPUREG_FACECULLING_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Culling mode
|}

This register is used to configure the face culling mode.

Culling mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Front Face (Counter Clockwise)
|-
| 2
| Back Face (Counter Clockwise)
|}

=== GPUREG_VIEWPORT_WIDTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, width / 2
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.

=== GPUREG_VIEWPORT_INVW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / width
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.

=== GPUREG_VIEWPORT_HEIGHT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, height / 2
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.

=== GPUREG_VIEWPORT_INVH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / height
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.

=== GPUREG_FRAGOP_CLIP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable clipping planes.

=== GPUREG_FRAGOP_CLIP_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Clipping plane coefficient ''i''
|}

This register is used to configure clipping plane coefficients.

=== GPUREG_DEPTHMAP_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near - Far
|}

This register is used to configure the depth range scale.

=== GPUREG_DEPTHMAP_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near + Polygon Offset
|}

This register is used to configure the depth range bias.

=== GPUREG_SH_OUTMAP_TOTAL ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of following attributes
|}

This register is used to configure the total shader output map attributes.

=== GPUREG_SH_OUTMAP_O''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Semantic for the x component of the register.
|-
| 8-12
| unsigned, Semantic for the y component of the register.
|-
| 16-20
| unsigned, Semantic for the z component of the register.
|-
| 24-28
| unsigned, Semantic for the w component of the register.
|}

These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.

Semantics that have not been mapped to a component of an output register have a value of 1

Semantic values:

{| class="wikitable" border="1"
! Value
! Semantic
! Description
|-
| 0x00
| position.x
| rowspan="4" | Vertex Position
|-
| 0x01
| position.y
|-
| 0x02
| position.z
|-
| 0x03
| position.w
|-
| 0x04
| normquat.x
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)
|-
| 0x05
| normquat.y
|-
| 0x06
| normquat.z
|-
| 0x07
| normquat.w
|-
| 0x08
| color.r
| rowspan="4" | Vertex color
|-
| 0x09
| color.g
|-
| 0x0A
| color.b
|-
| 0x0B
| color.a
|-
| 0x0C
| texcoord0.u
| rowspan="2" | Texture coordinates for texture 0
|-
| 0x0D
| texcoord0.v
|-
| 0x0E
| texcoord1.u
| rowspan="2" | Texture coordinates for texture 1
|-
| 0x0F
| texcoord1.v
|-
| 0x10
| texcoord0.w
|

|-
| 0x12
| view.x
| rowspan="3" | View vector (for fragment lighting)
|-
| 0x13
| view.y
|-
| 0x14
| view.z

|-
| 0x16
| texcoord2.u
| rowspan="2" | Texture coordinates for texture 2
|-
| 0x17
| texcoord2.v

|-
| 0x1F
| Unused component
| Should be set for unused components of the output register
|}

=== GPUREG_EARLYDEPTH_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Early depth function
|}

This register configures the early depth test function.

Early depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| >=
|-
| 1
| >
|-
| 2
| <=
|-
| 3
| <
|}

=== GPUREG_EARLYDEPTH_TEST1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register sets whether the early depth test is enabled.

=== GPUREG_EARLYDEPTH_CLEAR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = clear)
|}

This register triggers clearing the early depth data.

=== GPUREG_SH_OUTATTR_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Use texture coordinates (0 = don't use, 1 = use)
|}

This register is used to configure the shader output attribute mode.

=== GPUREG_SCISSORTEST_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Enabled (0 = disabled, 3 = enabled)
|}

This register is used to enable scissor testing.

=== GPUREG_SCISSORTEST_POS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X1
|-
| 16-25
| unsigned, Y1
|}

This register is used to configure the scissor test start position.

=== GPUREG_SCISSORTEST_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X2
|-
| 16-25
| unsigned, Y2
|}

This register is used to configure the scissor test end position.

=== GPUREG_VIEWPORT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| signed, X
|-
| 16-25
| signed, Y
|}

This register is used to configure the viewport position.

=== GPUREG_EARLYDEPTH_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| unsigned, Clear value
|}

This register is used to configure the early depth clear value.

=== GPUREG_DEPTHMAP_ENABLE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable depth range.

=== GPUREG_RENDERBUF_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register is used to configure the output framebuffer dimensions.

=== GPUREG_SH_OUTATTR_CLOCK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, 'position.z' present (0 = absent, 1 = present)
|-
| 1
| unsigned, 'color' component present (0 = absent, 1 = present)
|-
| 8
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)
|-
| 9
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)
|-
| 10
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)
|-
| 16
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)
|-
| 24
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)
|}

This register controls the clock supply to parts relating to certain attributes.

== Texturing registers ==

=== GPUREG_TEXUNIT_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| 0x0
|-
| 8-9
| unsigned, Texture 3 coordinates
|-
| 10
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)
|-
| 12
| 0x1
|-
| 13
| unsigned, Texture 2 coordinates
|-
| 16
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)
|-
| 17-31
| 0x0
|}

This register is used to enable texture units.

Texture 3 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 0
|-
| 1
| Texture 1
|-
| 2
| Texture 2
|}

Texture 2 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 2
|-
| 1
| Texture 1
|}

=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to set a texture unit's border color.

=== GPUREG_TEXUNIT''i''_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Height
|-
| 16-26
| unsigned, Width
|}

This register is used to set a texture unit's dimensions.

=== GPUREG_TEXUNIT''i''_PARAM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, Magnification filter
|-
| 2
| unsigned, Minification filter
|-
| 4-5
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4
|-
| 8-10
| unsigned, Wrap T
|-
| 12-14
| unsigned, Wrap S
|-
| 16-17
| 0x0
|-
| 20
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)
|-
| 24
| unsigned, Mipmap filter
|-
| 28-30
| unsigned, Type (Texture 0 only)
|}

This register is used to set a texture unit's extra parameters.

Filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|}

Wrap values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to edge
|-
| 1
| Clamp to border
|-
| 2
| Repeat
|-
| 3
| Mirrored repeat
|}

Type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 2D
|-
| 1
| Cube map
|-
| 2
| Shadow 2D
|-
| 3
| Projection
|-
| 4
| Shadow cube
|-
| 5
| Disabled
|}

=== GPUREG_TEXUNIT''i''_LOD ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.4.8, Bias
|-
| 16-19
| unsigned, Max Level
|-
| 24-27
| unsigned, Min Level
|}

This register is used to configure a texture unit's level of detail.

=== GPUREG_TEXUNIT''i''_ADDR''i'' ===

First ADDR register:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Texture physical address >> 3
|}

Subsequent ADDR registers:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-21
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)
|}

This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.

If the texture is a cube:

{| class="wikitable" border="1"
! Register
! Description
|-
| ADDR1
| Positive X
|-
| ADDR2
| Negative X
|-
| ADDR3
| Positive Y
|-
| ADDR4
| Negative Y
|-
| ADDR5
| Positive Z
|-
| ADDR6
| Negative Z
|}

Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.

=== GPUREG_TEXUNIT''i''_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Perspective (0 = perspective, 1 = not perspective)
|-
| 1-23
| fixed0.0.24, Z bias (upper 23 bits)
|}

This register is used to set a texture unit's shadow texture properties.

=== GPUREG_TEXUNIT''i''_TYPE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Format
|}

This register is used to set a texture unit's data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
! GL Format
! GL Data Type
|-
| 0x0
| RGBA8888
| GL_RGBA
| GL_UNSIGNED_BYTE
|-
| 0x1
| RGB888
| GL_RGB
| GL_UNSIGNED_BYTE
|-
| 0x2
| RGBA5551
| GL_RGBA
| GL_UNSIGNED_SHORT_5_5_5_1
|-
| 0x3
| RGB565
| GL_RGB
| GL_UNSIGNED_SHORT_5_6_5
|-
| 0x4
| RGBA4444
| GL_RGBA
| GL_UNSIGNED_SHORT_4_4_4_4
|-
| 0x5
| IA8
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x6
| HILO8
|
|
|-
| 0x7
| I8
| GL_LUMINANCE
| GL_UNSIGNED_BYTE
|-
| 0x8
| A8
| GL_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x9
| IA44
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE_4_4_EXT
|-
| 0xA
| I4
|
|
|-
| 0xB
| A4
| GL_ALPHA
| GL_UNSIGNED_NIBBLE_EXT
|-
| 0xC
| ETC1
| GL_ETC1_RGB8_OES
|
|-
| 0xD
| ETC1A4
|
|
|}

=== GPUREG_LIGHTING_ENABLE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable lighting.

=== GPUREG_TEXUNIT3_PROCTEX0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, U-direction clamp
|-
| 3-5
| unsigned, V-direction clamp
|-
| 6-9
| unsigned, RGB mapping function
|-
| 10-13
| unsigned, Alpha mapping function
|-
| 14
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)
|-
| 15
| unsigned, Noise enabled (0 = disabled, 1 = enabled)
|-
| 16-17
| unsigned, U-direction shift
|-
| 18-19
| unsigned, V-direction shift
|-
| 20-27
| float1.5.10, Texture bias (lower 8 bits)
|}

This register is used to configure the procedural texture unit.

Clamp values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to zero
|-
| 1
| Clamp to edge
|-
| 2
| Symmetrical repeat
|-
| 3
| Mirrored repeat
|-
| 4
| Pulse
|}

Mapping function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| U
|-
| 1
| U²
|-
| 2
| V
|-
| 3
| V²
|-
| 4
| (U + V) / 2
|-
| 5
| (U² + V²) / 2
|-
| 6
| sqrt(U² + V²)
|-
| 7
| Minimum
|-
| 8
| Maximum
|-
| 9
| Rmax
|}

Shift values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Odd
|-
| 2
| Even
|}

=== GPUREG_TEXUNIT3_PROCTEX1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, U-direction noise amplitude
|-
| 16-31
| float1.5.10, U-direction noise phase
|}

This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, V-direction noise amplitude
|-
| 16-31
| float1.5.10, V-direction noise phase
|}

This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, U-direction noise frequency
|-
| 16-31
| float1.5.10, V-direction noise frequency
|}

This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.

=== GPUREG_TEXUNIT3_PROCTEX4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Minification filter
|-
| 3-6
| Min LOD (usually 0)
|-
| 7-10
| Max LOD (usually 6)
|-
| 11-18
| unsigned, Texture width
|-
| 19-26
| float1.5.10, Texture bias (upper 8 bits)
|}

This register is used to configure the procedural texture unit.

Minification filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|-
| 2
| Nearest, Mipmap Nearest
|-
| 3
| Linear, Mipmap Nearest
|-
| 4
| Nearest, Mipmap Linear
|-
| 5
| Linear, Mipmap Linear
|}

=== GPUREG_TEXUNIT3_PROCTEX5 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Texture offset (Mipmap level 0 / base level)
|-
| 8-15
| unsigned, mipmap level 1 offset (usually 0x80)
|-
| 16-23
| unsigned, mipmap level 2 offset (usually 0xC0)
|-
| 24-31
| unsigned, mipmap level 3 offset (usually 0xE0)
|}

This register is used to set the procedural texture unit's offset. Mipmap level 4-7 seems to be hardcoded at offset 0xF0, 0xF8, 0xFC and 0xFE .

=== GPUREG_PROCTEX_LUT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Index
|-
| 8-11
| unsigned, Reference table
|}

This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.

Reference table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Noise table
|-
| 2
| RGB mapping function table
|-
| 3
| Alpha mapping function table
|-
| 4
| Color table
|-
| 5
| Color difference table
|}

=== GPUREG_PROCTEX_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.

==== Noise Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement ( [0.5,1.0) mapped to [-1.0,0) ), Difference from next element
|}

==== RGB Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement, Difference from next element
|}

==== Alpha Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement, Difference from next element
|}

==== Color Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

==== Color Difference Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Half of red difference between current and next color table elements
|-
| 8-15
| signed, Half of green difference between current and next color table elements
|-
| 16-23
| signed, Half of blue difference between current and next color table elements
|-
| 24-31
| signed, Half of alpha difference between current and next color table elements
|}

=== GPUREG_TEXENV''i''_SOURCE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB source 0
|-
| 4-7
| unsigned, RGB source 1
|-
| 8-11
| unsigned, RGB source 2
|-
| 16-19
| unsigned, Alpha source 0
|-
| 20-23
| unsigned, Alpha source 1
|-
| 24-27
| unsigned, Alpha source 2
|}

This register configures a texture combiner's sources.

Source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Primary color
|-
| 1
| Fragment primary color
|-
| 2
| Fragment secondary color
|-
| 3
| Texture 0
|-
| 4
| Texture 1
|-
| 5
| Texture 2
|-
| 6
| Texture 3
|-
| 13
| Previous buffer
|-
| 14
| Constant (from GPUREG_TEXENV''i''_COLOR)
|-
| 15
| Previous
|}

Using previous source in the first TEV stage returns the primary color, while previous buffer returns zero.

=== GPUREG_TEXENV''i''_OPERAND ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB operand 0
|-
| 4-7
| unsigned, RGB operand 1
|-
| 8-11
| unsigned, RGB operand 2
|-
| 12-14
| unsigned, Alpha operand 0
|-
| 16-18
| unsigned, Alpha operand 1
|-
| 20-22
| unsigned, Alpha operand 2
|}

This register configures a texture combiner's operands.

RGB operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source color
|-
| 1
| One minus source color
|-
| 2
| Source alpha
|-
| 3
| One minus source alpha
|-
| 4
| Source red
|-
| 5
| One minus source red
|-
| 8
| Source green
|-
| 9
| One minus source green
|-
| 12
| Source blue
|-
| 13
| One minus source blue
|}

Alpha operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source alpha
|-
| 1
| One minus source alpha
|-
| 2
| Source red
|-
| 3
| One minus source red
|-
| 4
| Source green
|-
| 5
| One minus source green
|-
| 6
| Source blue
|-
| 7
| One minus source blue
|}

=== GPUREG_TEXENV''i''_COMBINER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB combine
|-
| 16-19
| unsigned, Alpha combine
|}

This register configures a texture combiner's combine mode.

Combine values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Replace
|-
| 1
| Modulate
|-
| 2
| Add
|-
| 3
| Add signed
|-
| 4
| Interpolate
|-
| 5
| Subtract
|-
| 6
| Dot3 RGB
|-
| 7
| Dot3 RGBA
|-
| 8
| Multiply then add
|-
| 9
| Add then multiply
|}

=== GPUREG_TEXENV''i''_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register configures a texture combiner's constant color.

=== GPUREG_TEXENV''i''_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, RGB scale
|-
| 16-17
| unsigned, Alpha scale
|}

This register configures a texture combiner's scale value.

Scale values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|}

=== GPUREG_TEXENV_UPDATE_BUFFER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fog mode
|-
| 3
| unsigned, Shading density source
|-
| 8
| unsigned, TexEnv 1 RGB buffer input
|-
| 9
| unsigned, TexEnv 2 RGB buffer input
|-
| 10
| unsigned, TexEnv 3 RGB buffer input
|-
| 11
| unsigned, TexEnv 4 RGB buffer input
|-
| 12
| unsigned, TexEnv 1 alpha buffer input
|-
| 13
| unsigned, TexEnv 2 alpha buffer input
|-
| 14
| unsigned, TexEnv 3 alpha buffer input
|-
| 15
| unsigned, TexEnv 4 alpha buffer input
|-
| 16
| unsigned, Z flip (0 = don't flip, 1 = flip)
|-
| 24-25
| 0x0
|}

This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.

Fog mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Disabled
|-
| 5
| Fog
|-
| 7
| Gas
|}

Shading density source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Plain density
|-
| 1
| Depth density
|}

Buffer input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Previous buffer
|-
| 1
| Previous
|}

=== GPUREG_FOG_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

This register is used to configure the color of fog.

=== GPUREG_GAS_ATTENUATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas density attenuation
|}

This register is used to configure the gas density attenuation.

=== GPUREG_GAS_ACCMAX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas maximum density accumulation
|}

This register is used to configure the gas maximum density accumulation.

=== GPUREG_FOG_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.

=== GPUREG_FOG_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.

==== Fog Look-Up Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Difference from next element
|-
| 13-23
| fixed0.0.11, Value
|}

=== GPUREG_TEXENV_BUFFER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the texture combiner buffer color.

== Framebuffer registers ==

=== GPUREG_COLOR_OPERATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Fragment operation mode
|-
| 8
| unsigned, Blend mode
|-
| 16-25
| 0x0E4
|}

This register is used to configure the fragment operation mode and whether to use logic ops or blending.

Fragment operation mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Default
|-
| 1
| Gas
|-
| 3
| Shadow
|}

Blend mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Logic op
|-
| 1
| Blend
|}

=== GPUREG_BLEND_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, RGB equation
|-
| 8-10
| unsigned, Alpha equation
|-
| 16-19
| unsigned, RGB source function
|-
| 20-23
| unsigned, RGB destination function
|-
| 24-27
| unsigned, Alpha source function
|-
| 28-31
| unsigned, Alpha destination function
|}

This register is used to configure the blending function.

'''Equation values:'''

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Add
|-
| 1
| Subtract
|-
| 2
| Reverse subtract
|-
| 3
| Minimum
|-
| 4
| Maximum
|}

Blend equations 5, 6, 7 appear to behave the same as blend equation 0 (Add)

'''Function values:'''

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Zero
|-
| 1
| One
|-
| 2
| Source color
|-
| 3
| One minus source color
|-
| 4
| Destination color
|-
| 5
| One minus destination color
|-
| 6
| Source alpha
|-
| 7
| One minus source alpha
|-
| 8
| Destination alpha
|-
| 9
| One minus destination alpha
|-
| 10
| Constant color
|-
| 11
| One minus constant color
|-
| 12
| Constant alpha
|-
| 13
| One minus constant alpha
|-
| 14
| Source alpha saturate
|}

=== GPUREG_LOGIC_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Logic op
|}

This register is used to configure the logic op.

Logic op values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clear
|-
| 1
| AND
|-
| 2
| Reverse AND
|-
| 3
| Copy
|-
| 4
| Set
|-
| 5
| Inverted copy
|-
| 6
| Noop
|-
| 7
| Invert
|-
| 8
| NAND
|-
| 9
| OR
|-
| 10
| NOR
|-
| 11
| XOR
|-
| 12
| Equivalent
|-
| 13
| Inverted AND
|-
| 14
| Reverse OR
|-
| 15
| Inverted OR
|}

=== GPUREG_BLEND_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the blending color.

=== GPUREG_FRAGOP_ALPHA_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Reference value
|}

This register is used to configure alpha testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Buffer mask
|-
| 16-23
| signed, Reference value
|-
| 24-31
| unsigned, Mask
|}

This register is used to configure stencil testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fail operation
|-
| 4-6
| unsigned, Z-fail operation
|-
| 8-10
| unsigned, Z-pass operation
|}

This register is used to configure stencil result operations.

Operation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Keep
|-
| 1
| Zero
|-
| 2
| Replace
|-
| 3
| Increment
|-
| 4
| Decrement
|-
| 5
| Invert
|-
| 6
| Increment and wrap
|-
| 7
| Decrement and wrap
|}

=== GPUREG_DEPTH_COLOR_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Depth function
|-
| 8
| unsigned, Red write enabled (0 = disabled, 1 = enabled)
|-
| 9
| unsigned, Green write enabled (0 = disabled, 1 = enabled)
|-
| 10
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)
|-
| 11
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)
|-
| 12
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
|}

This register is used to depth testing and framebuffer write masking.

Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.

Depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = invalidate)
|-
| 1-31
| 0x0
|}

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = flush)
|-
| 1-31
| 0x0
|}

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_COLORBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow read (0 = disable, 0xF = enable)
|}

This register configures read access from the color buffer.

=== GPUREG_COLORBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow write (0 = disable, 0xF = enable)
|}

This register configures write access to the color buffer.

=== GPUREG_DEPTHBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil read (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth read (0 = disable, 1 = enable)
|}

This register configures read access from the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil write (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth write (0 = disable, 1 = enable)
|}

This register configures write access to the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Format
|}

This register configures the depth buffer data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil
|}

=== GPUREG_COLORBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Pixel size
|-
| 16-18
| unsigned, Format
|}

This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.

Pixel size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit color
|-
| 2
| 32-bit color
|}

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| RGBA8/Gas
|-
| 2
| RGB5A1
|-
| 3
| RGB565
|-
| 4
| RGBA4
|}

=== GPUREG_EARLYDEPTH_TEST2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register enables the early depth test.

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Render block mode
|}

This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

Render block mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8x8 blocks
|-
| 1
| 32x32 blocks
|}

=== GPUREG_DEPTHBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Depth buffer physical address >> 3
|}

This register configures the depth buffer physical address.

=== GPUREG_COLORBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Color buffer physical address >> 3
|}

This register configures the color buffer physical address.

=== GPUREG_FRAMEBUFFER_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register configures the framebuffer dimensions.

=== GPUREG_GAS_LIGHT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Planar shading minimum intensity
|-
| 8-15
| unsigned, Planar shading maximum intensity
|-
| 16-23
| unsigned, Planar shading density attenuation
|}

This register configures gas light planar shading.

=== GPUREG_GAS_LIGHT_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading minimum intensity
|-
| 8-15
| unsigned, View shading maximum intensity
|-
| 16-23
| unsigned, View shading density attenuation
|}

This register configures gas light view shading.

=== GPUREG_GAS_LIGHT_Z_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading effect in line-of-sight direction
|-
| 8
| Gas color LUT input
|}

This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.

Color LUT input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Gas density
|-
| 1
| Light factor
|}

=== GPUREG_GAS_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.

=== GPUREG_GAS_LUT_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.

==== Gas Look-Up Table ====

16 elements:

First 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Red
|-
| 8-15
| signed, Green
|-
| 16-23
| signed, Blue
|}

Last 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

=== GPUREG_GAS_DELTAZ_DEPTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| fixed0.16.8, Depth direction attenuation proportion
|-
| 24-25
| unsigned, Depth function
|}

This register is used to configure the gas depth direction attenuation proportion, as well as the gas depth function.

Gas depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Greater than/Greater than or equal
|-
| 3
| Less than/Less than or equal/Equal/Not equal
|}

=== GPUREG_FRAGOP_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Sum of penumbra scale and penumbra bias
|-
| 16-31
| float1.5.10, Penumbra scale with reversed sign
|}

This register is used to configure shadow properties.

== Fragment lighting registers ==

=== GPUREG_LIGHT''i''_SPECULAR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.

=== GPUREG_LIGHT''i''_SPECULAR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.

=== GPUREG_LIGHT''i''_DIFFUSE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

=== GPUREG_LIGHT''i''_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.

=== GPUREG_LIGHT''i''_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, X coordinate
|-
| 16-31
| float1.5.10, Y coordinate
|}

These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Z coordinate
|}

These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, X coordinate (negated)
|-
| 16-28
| fixed1.1.11, Y coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Z coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Light type (0 = positional light, 1 = directional light)
|-
| 1
| unsigned, Two side diffuse (0 = one side, 1 = both sides)
|-
| 2
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)
|-
| 3
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)
|}

This register configures a light's properties.

=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation bias
|}

These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation scale
|}

These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHTING_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

=== GPUREG_LIGHTING_NUM_LIGHTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of active lights - 1
|}

This register configures the number of active lights.

=== GPUREG_LIGHTING_CONFIG0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)
|-
| 2-3
| unsigned, Fresnel selector
|-
| 4-7
| unsigned, Light environment configuration
|-
| 8-11
| 0x4
|-
| 16
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)
|-
| 17
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)
|-
| 18
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)
|-
| 19
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)
|-
| 22-23
| unsigned, Bump map texture unit
|-
| 24-25
| unsigned, Shadow map texture unit
|-
| 27
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)
|-
| 28-29
| unsigned, Bump mode
|-
| 30
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)
|-
| 31
| 0x1
|}

This register configures the light environment.

Fresnel selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Primary alpha
|-
| 2
| Secondary alpha
|-
| 3
| Primary and secondary alpha
|}

The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.

Light environment configuration values:

{| class="wikitable" border="1"
! Value
! Description
! Available LUTs
|-
| 0
| Configuration 0
| D0, RR, SP, DA
|-
| 1
| Configuration 1
| FR, RR, SP, DA
|-
| 2
| Configuration 2
| D0, D1, RR, DA
|-
| 3
| Configuration 3
| D0, D1, FR, DA
|-
| 4
| Configuration 4
| All except for FR
|-
| 5
| Configuration 5
| All except for D1
|-
| 6
| Configuration 6
| All except for RB and RG
|-
| 8
| Configuration 7
| All
|}

Bump mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Not used
|-
| 1
| Use as bump map
|-
| 2
| Use as tangent map
|}

=== GPUREG_LIGHTING_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)
|-
| 1
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)
|-
| 2
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)
|-
| 3
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)
|-
| 4
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)
|-
| 6
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)
|-
| 7
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)
|-
| 8
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)
|-
| 10
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)
|-
| 11
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)
|-
| 12
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)
|-
| 14
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)
|-
| 15
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)
|-
| 16
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)
|-
| 18
| 0x1
|-
| 19
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
|-
| 20
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 1 = disabled)
|-
| 22
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 1 = disabled)
|-
| 24
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 26
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 27
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 28
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 29
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 30
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 31
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)
|}

This register is used to disable various aspects of the light environment.

=== GPUREG_LIGHTING_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Starting index
|-
| 8-12
| unsigned, Look-up table
|}

This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.

Lookup table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| D0
|-
| 1
| D1
|-
| 3
| FR
|-
| 4
| RB
|-
| 5
| RG
|-
| 6
| RR
|-
| 8-15
| SP0-7
|-
| 16-23
| DA0-7
|}

=== GPUREG_LIGHTING_ENABLE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Disabled (0 = enabled, 1 = disabled)
|}

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

=== GPUREG_LIGHTING_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

Lighting LUT data is written here.

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.

Format of an entry:

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Entry value
|-
| 12-23
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation
|}

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)
|}

This register controls whether the absolute value of the input is taken before using a LUT.

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Input selector for D0
|-
| 4-6
| unsigned, Input selector for D1
|-
| 8-10
| unsigned, Input selector for SP
|-
| 12-14
| unsigned, Input selector for FR
|-
| 16-18
| unsigned, Input selector for RB
|-
| 20-22
| unsigned, Input selector for RG
|-
| 24-26
| unsigned, Input selector for RR
|}

This register selects the input from LUTs.

Input selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Scaler selector for D0
|-
| 4-6
| unsigned, Scaler selector for D1
|-
| 8-10
| unsigned, Scaler selector for SP
|-
| 12-14
| unsigned, Scaler selector for FR
|-
| 16-18
| unsigned, Scaler selector for RB
|-
| 20-22
| unsigned, Scaler selector for RG
|-
| 24-26
| unsigned, Scaler selector for RR
|}

This register controls the scaling that is applied to the output of a LUT.

Scaler selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, ID of the 1st enabled light
|-
| 4-6
| unsigned, ID of the 2nd enabled light
|-
| 8-10
| unsigned, ID of the 3rd enabled light
|-
| 12-14
| unsigned, ID of the 4th enabled light
|-
| 16-18
| unsigned, ID of the 5th enabled light
|-
| 20-22
| unsigned, ID of the 6th enabled light
|-
| 24-26
| unsigned, ID of the 7th enabled light
|-
| 28-30
| unsigned, ID of the 8th enabled light
|}

This register sets the IDs of enabled light sources.

== Geometry pipeline registers ==

=== GPUREG_ATTRIBBUFFERS_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-28
| unsigned, Vertex arrays base address
|}

This register sets the base address of all vertex arrays.

=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 0 type
|-
| 2-3
| unsigned, Vertex attribute 0 size
|-
| 4-5
| unsigned, Vertex attribute 1 type
|-
| 6-7
| unsigned, Vertex attribute 1 size
|-
| 8-9
| unsigned, Vertex attribute 2 type
|-
| 10-11
| unsigned, Vertex attribute 2 size
|-
| 12-13
| unsigned, Vertex attribute 3 type
|-
| 14-15
| unsigned, Vertex attribute 3 size
|-
| 16-17
| unsigned, Vertex attribute 4 type
|-
| 18-19
| unsigned, Vertex attribute 4 size
|-
| 20-21
| unsigned, Vertex attribute 5 type
|-
| 22-23
| unsigned, Vertex attribute 5 size
|-
| 24-25
| unsigned, Vertex attribute 6 type
|-
| 26-27
| unsigned, Vertex attribute 6 size
|-
| 28-29
| unsigned, Vertex attribute 7 type
|-
| 30-31
| unsigned, Vertex attribute 7 size
|}

This register configures the types and sizes of the first 8 vertex attributes.

Vertex attribute type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Byte
|-
| 1
| Unsigned byte
|-
| 2
| Short
|-
| 3
| Float
|}

Vertex attribute size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8 bits
|-
| 1
| 16 bits
|-
| 2
| 24 bits
|-
| 3
| 32 bits
|}

=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 8 type
|-
| 2-3
| unsigned, Vertex attribute 8 size
|-
| 4-5
| unsigned, Vertex attribute 9 type
|-
| 6-7
| unsigned, Vertex attribute 9 size
|-
| 8-9
| unsigned, Vertex attribute 10 type
|-
| 10-11
| unsigned, Vertex attribute 10 size
|-
| 12-13
| unsigned, Vertex attribute 11 type
|-
| 14-15
| unsigned, Vertex attribute 11 size
|-
| 16-27
| unsigned, Fixed vertex attribute mask
|-
| 28-31
| unsigned, Total vertex attribute count - 1
|}

This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.

See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.

=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|}

This register configures the offset of a vertex array from the base vertex arrays address.

=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 1
|-
| 4-7
| unsigned, Component 2
|-
| 8-11
| unsigned, Component 3
|-
| 12-15
| unsigned, Component 4
|-
| 16-19
| unsigned, Component 5
|-
| 20-23
| unsigned, Component 6
|-
| 24-27
| unsigned, Component 7
|-
| 28-31
| unsigned, Component 8
|}

This register configures the first 8 component types of a vertex array.

Component values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Vertex attribute 0
|-
| 1
| Vertex attribute 1
|-
| 2
| Vertex attribute 2
|-
| 3
| Vertex attribute 3
|-
| 4
| Vertex attribute 4
|-
| 5
| Vertex attribute 5
|-
| 6
| Vertex attribute 6
|-
| 7
| Vertex attribute 7
|-
| 8
| Vertex attribute 8
|-
| 9
| Vertex attribute 9
|-
| 10
| Vertex attribute 10
|-
| 11
| Vertex attribute 11
|-
| 12
| 4-byte padding
|-
| 13
| 8-byte padding
|-
| 14
| 12-byte padding
|-
| 15
| 16-byte padding
|}

=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 9
|-
| 4-7
| unsigned, Component 10
|-
| 8-11
| unsigned, Component 11
|-
| 12-15
| unsigned, Component 12
|-
| 16-23
| unsigned, Bytes per vertex
|-
| 28-31
| unsigned, Total number of components
|}

This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.

See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.

=== GPUREG_INDEXBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|-
| 31
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)
|}

This register configures the index array used when drawing elements.

=== GPUREG_NUMVERTICES ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Number of vertices to render
|}

This register sets the number of vertices to render.

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|-
| 9
| 0x0
|-
| 31
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_VERTEX_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Starting vertex offset
|}

This register sets the offset of the first vertex in an array to render.

=== GPUREG_POST_VERTEX_CACHE_NUM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)
|}

This register configures the post-vertex cache.

=== GPUREG_DRAWARRAYS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw arrays)
|}

This register triggers drawing vertex arrays.

=== GPUREG_DRAWELEMENTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw elements)
|}

This register triggers drawing vertex array elements.

=== GPUREG_VTX_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)
|}

This register triggers clearing the post-vertex cache.

=== GPUREG_FIXEDATTRIB_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)
|}

This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

=== GPUREG_FIXEDATTRIB_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| colspan="2" | '''DATA0:'''
|-
| 0-7
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)
|-
| 8-31
| float1.7.16, Vertex attribute element 4 (W)
|-
| colspan="2" | '''DATA1:'''
|-
| 0-15
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)
|-
| 16-31
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)
|-
| colspan="2" | '''DATA2:'''
|-
| 0-23
| float1.7.16, Vertex attribute element 1 (X)
|-
| 24-31
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)
|}

Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.

=== GPUREG_CMDBUF_SIZE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 0 >> 3
|}

This register sets the size of the first command buffer.

=== GPUREG_CMDBUF_SIZE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 1 >> 3
|}

This register sets the size of the second command buffer.

=== GPUREG_CMDBUF_ADDR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 0 >> 3
|}

This register sets the physical address of the first command buffer.

=== GPUREG_CMDBUF_ADDR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 1 >> 3
|}

This register sets the physical address of the second command buffer.

=== GPUREG_CMDBUF_JUMP0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)
|}

This register triggers a jump to the first command buffer.

=== GPUREG_CMDBUF_JUMP1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)
|}

This register triggers a jump to the second command buffer.

=== GPUREG_VSH_NUM_ATTR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader input attributes - 1
|}

This register sets the number of vertex shader input attributes.

=== GPUREG_VSH_COM_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)
|}

This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.
When disabled and the geometry unit is not in use, as configured by GPUREG_GEOSTAGE_CONFIG, uniforms, outmap mask, program code and swizzle data are propagated to the geometry shader unit.

=== GPUREG_START_DRAW_FUNC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Mode (0 = drawing, 1 = configuration)
|-
| 1-7
| 0x0
|}

This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.

=== GPUREG_VSH_OUTMAP_TOTAL1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_VSH_OUTMAP_TOTAL2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_GSH_MISC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)
|}

This register configures miscellaneous geometry shader properties.

=== GPUREG_GEOSTAGE_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_GSH_MISC1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)
|}

This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.

=== GPUREG_PRIMITIVE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|-
| 8-9
| unsigned, Primitive mode
|}

This register configures primitive drawing.

Primitive mode value:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Triangles
|-
| 1
| Triangle strip
|-
| 2
| Triangle fan
|-
| 3
| Geometry primitive
|}

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = reset primitive)
|-
| 1-31
| 0x0
|}

This register triggers resetting primitive drawing.

== Shader registers ==

=== GPUREG_''SH''_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Boolean register b0 value (0 = false, 1 = true)
|-
| 1
| unsigned, Boolean register b1 value (0 = false, 1 = true)
|-
| 2
| unsigned, Boolean register b2 value (0 = false, 1 = true)
|-
| 3
| unsigned, Boolean register b3 value (0 = false, 1 = true)
|-
| 4
| unsigned, Boolean register b4 value (0 = false, 1 = true)
|-
| 5
| unsigned, Boolean register b5 value (0 = false, 1 = true)
|-
| 6
| unsigned, Boolean register b6 value (0 = false, 1 = true)
|-
| 7
| unsigned, Boolean register b7 value (0 = false, 1 = true)
|-
| 8
| unsigned, Boolean register b8 value (0 = false, 1 = true)
|-
| 9
| unsigned, Boolean register b9 value (0 = false, 1 = true)
|-
| 10
| unsigned, Boolean register b10 value (0 = false, 1 = true)
|-
| 11
| unsigned, Boolean register b11 value (0 = false, 1 = true)
|-
| 12
| unsigned, Boolean register b12 value (0 = false, 1 = true)
|-
| 13
| unsigned, Boolean register b13 value (0 = false, 1 = true)
|-
| 14
| unsigned, Boolean register b14 value (0 = false, 1 = true)
|-
| 15
| unsigned, Boolean register b15 value (0 = false, 1 = true)
|-
| 16-31
| 0x7FFF
|}

This register is used to set a shader unit's boolean registers.

=== GPUREG_''SH''_INTUNIFORM_I''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Integer register i''i'' X value
|-
| 8-15
| unsigned, Integer register i''i'' Y value
|-
| 16-23
| unsigned, Integer register i''i'' Z value
|-
| 24-31
| unsigned, Integer register i''i'' W value
|}

These registers are used to set a shader unit's integer registers.

=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Input vertex attributes - 1
|-
| 8-15
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)
|-
| 16-23
| 0x0
|-
| 24-31
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)
|}

This register is used to configure a shader unit's input buffer.

=== GPUREG_''SH''_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Code entry point offset, in 32-bit words
|-
| 16-31
| 0x7FFF
|}

This register sets a shader unit's code entry point.

For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.

For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 0 input register index
|-
| 4-7
| unsigned, Vertex attribute 1 input register index
|-
| 8-11
| unsigned, Vertex attribute 2 input register index
|-
| 12-15
| unsigned, Vertex attribute 3 input register index
|-
| 16-19
| unsigned, Vertex attribute 4 input register index
|-
| 20-23
| unsigned, Vertex attribute 5 input register index
|-
| 24-27
| unsigned, Vertex attribute 6 input register index
|-
| 28-31
| unsigned, Vertex attribute 7 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 8 input register index
|-
| 4-7
| unsigned, Vertex attribute 9 input register index
|-
| 8-11
| unsigned, Vertex attribute 10 input register index
|-
| 12-15
| unsigned, Vertex attribute 11 input register index
|-
| 16-19
| unsigned, Vertex attribute 12 input register index
|-
| 20-23
| unsigned, Vertex attribute 13 input register index
|-
| 24-27
| unsigned, Vertex attribute 14 input register index
|-
| 28-31
| unsigned, Vertex attribute 15 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_''SH''_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)
|-
| 4
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)
|-
| 5
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)
|-
| 6
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)
|-
| 7
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 8
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 9
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 10
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 11
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 12
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 13
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 14
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 15
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 16-31
| 0x0
|}

This register toggles a shader unit's output registers.

=== GPUREG_''SH''_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Signal transfer end (0 = idle, non-zero = signal)
|}

This register's value should be set to 1 in order to finalize the transfer of shader code.

=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)
|}

This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.

=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Floating-point register component data
|}

This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_''SH''_CODETRANSFER_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader code offset
|}

This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.

=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader instruction data
|}

This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.

=== GPUREG_''SH''_OPDESCS_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader operand descriptor offset
|}

This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.

=== GPUREG_''SH''_OPDESCS_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader operand descriptor data
|}

This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.

DSP:GetSemaphoreEventHandle

2023-12-28T18:20:01Z

Emufan4568: DSP service always sets this to zero

=Request=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code [0x00160000]
|}

=Response=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code
|-
| 1
| Resultcode
|-
| 2
| Zero
|-
| 3
| EventHandle
|}

==Semaphore==

The ARM11 application signals this semaphore to indicate it has finished writing to the [[DSP Memory Region]] this audio frame.

GPU/Programming Guide

2023-12-15T22:20:14Z

Emufan4568: Fix lin to GPUREG_FIXEDATTRIB_DATA

This page is intended to contain more higher-level explanation of concepts and features provided by the 3DS GPU. For more detailed register-level information check [[GPU/Internal Registers]].

= Geometry Pipeline =

== Fixed Vertex Attributes ==

If a certain vertex attribute is constant for the duration of a draw call, instead of specifying a vertex array with repeated contents or changing the shader to use a uniform, ''fixed vertex attributes'' can be used. They let you specify a fixed value, which will be assumed by the attribute for all vertices of the batch.

To use a fixed attribute, set the bit corresponding to the attribute in [[GPU/Internal Registers#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]] and ensure that no vertex arrays are configured for the attribute. (Any configured arrays will override the fixed value, regardless of the bit setting.) Even if a vertex array isn't being used for the attribute it still needs to be counted in the number of active attributes specified in the same register.

To specify the actual value of the fixed attribute, write the attribute index to [[GPU/Internal Registers#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]] followed by writes with packed a float24 4-tuple to the 3 [[GPU/Internal Registers#GPUREG_FIXEDATTRIB_DATA0|GPUREG_FIXEDATTRIB_DATA]] registers. The value is always specified as a float 4-component vector, the configured type is ignored.

== Immediate-Mode Vertex Submission ==

Instead of using vertex arrays to supply vertex data, drawing can be done by directly writing vertex data to a register. This allows vertex data to be inlined directly in the command buffer. Since this is restricted to 4-component float data, it is more useful for small draws like UI elements or debug displays, to avoid using an unreasonable amount of memory and processing time appending the vertices to the command buffer.

To use this feature, configure the number of attributes per vertex in [[GPU/Internal Registers#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]. (All settings in the registers related to the vertex loader are ignored.) Then setup the GPU and shaders the same as if doing a regular draw call with GPUREG_DRAWARRAYS or GPUREG_DRAWELEMENTS, but instead of writing to either register, write the value 0xF to [[GPU/Internal Registers#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]] and then follow by repeatedly writing vertex data to [[GPU/Internal Registers#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA]].

Each set of writes to the 3 data registers specifies one attribute and all attributes (as configured in GPUREG_VSH_NUM_ATTR) need to be written, in order, to specify a vertex. Drawing happens automatically as vertices are specified. After finishing specifying vertices, follow with the same writes used after a draw arrays/elements.

When drawing using triangle strips or fans, [[GPU/Internal Registers#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]] should be used to end the previous strip before (or while) drawing.

== Drawing elements ==

The 3DS GPU is capable of drawing vertex + index arrays, triggered by [[GPU/Internal_Registers#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]. A set of commands commonly used by the standard GL implementation to accomplish this is as follows:

{| class="wikitable" border="1"
! Command Index
! Register
! Description
|-
| 0
| [[GPU/Internal_Registers#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| Set whether drawing triangle elements
|-
| 1-2
| [[GPU/Internal_Registers#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
| Set whether drawing triangle elements
|-
| 3
| [[GPU/Internal_Registers#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| Set primitive mode
|-
| 4
| [[GPU/Internal_Registers#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| Set number of output map registers
|-
| 5
| [[GPU/Internal_Registers#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
| Trigger reset
|-
| 6
| [[GPU/Internal_Registers#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
| Set function indicator to 0
|-
| 7
| [[GPU/Internal_Registers#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
| Set offset and type
|-
| 8
| [[GPU/Internal_Registers#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
| Set vertex count
|-
| 9
| [[GPU/Internal_Registers#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
| Set mode to drawing
|-
| 10
| [[GPU/Internal_Registers#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
| Trigger draw
|-
| 11
| [[GPU/Internal_Registers#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
| Set mode to configuration
|-
| 12
| [[GPU/Internal_Registers#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]
| Trigger post-vertex cache clear
|-
| 13
| [[GPU/Internal_Registers#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
| Flush framebuffer
|-
| 14
| [[GPU/Internal_Registers#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| Clear drawing triangle elements
|-
| 15
| [[GPU/Internal_Registers#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
| Clear drawing triangle elements
|-
| 16
| [[GPU/Internal_Registers#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| Clear primitive mode
|-
| 17
| [[GPU/Internal_Registers#GPUREG_VSH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
| Clear entry point
|}

[[Category:GPU]]

SVC

2023-11-29T23:35:14Z

Emufan4568: Correct svc name from switchbrew

= System calls =
'''Note: The argument-lists here apply to the official syscall wrapper-functions that are found in userland processes. The actual ordering passed to the kernel via the SVC instruction is documented in [[Kernel_ABI|Kernel ABI]].'''

{| class="wikitable" border="1"
|-
! Id
! NF ARM11
! NF ARM9
! TF ARM11
! Description
! scope="col" width="200" | Notes
|-
| 0x01
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|ControlMemory]](u32* outaddr, u32 addr0, u32 addr1, u32 size, [[Memory Management#enum_MemoryOperation|MemoryOperation]] operation, [[Memory Management#enum_MemoryPermission|MemoryPermission]] permissions)
| Outaddr is usually the same as the input addr0.
|-
| 0x02
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|QueryMemory]]([[Memory Management#struct MemoryInfo|MemoryInfo]]* info, [[Memory Management#struct PageInfo|PageInfo]]* out, u32 Addr)
|
|-
| 0x03
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| void ExitProcess(void)
|
|-
| 0x04
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetProcessAffinityMask(u8* affinitymask, Handle process, s32 processorcount)
|
|-
| 0x05
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetProcessAffinityMask(Handle process, u8* affinitymask, s32 processorcount)
|
|-
| 0x06
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetProcessIdealProcessor(s32 *idealprocessor, Handle process)
|
|-
| 0x07
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetProcessIdealProcessor(Handle process, s32 idealprocessor)
|
|-
| 0x08
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#CreateThread|CreateThread]](Handle* thread, func entrypoint, u32 arg, u32 stacktop, s32 threadpriority, s32 processorid)
|
|-
| 0x09
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| void [[Multi-threading#ExitThread|ExitThread]](void)
|
|-
| 0x0A
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| void [[Multi-threading#SleepThread|SleepThread]](s64 nanoseconds)
|
|-
| 0x0B
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#GetThreadPriority|GetThreadPriority]](s32* priority, Handle thread)
|
|-
| 0x0C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#SetThreadPriority|SetThreadPriority]](Handle thread, s32 priority)
|
|-
| 0x0D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#GetThreadAffinityMask|GetThreadAffinityMask]](u8* affinitymask, Handle thread, s32 processorcount)
|
|-
| 0x0E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#SetThreadAffinityMask|SetThreadAffinityMask]](Handle thread, u8* affinitymask, s32 processorcount)
| Replaced with a stub in ARM11 NATIVE_FIRM kernel beginning with [[8.0.0-18]].
|-
| 0x0F
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#GetThreadIdealProcessor|GetThreadIdealProcessor]](s32* processorid, Handle thread)
|
|-
| 0x10
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#SetThreadIdealProcessor|SetThreadIdealProcessor]](Handle thread, s32 processorid)
| Replaced with a stub in ARM11 NATIVE_FIRM kernel beginning with [[8.0.0-18]].
|-
| 0x11
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| s32 GetCurrentProcessorNumber(void)
|
|-
| 0x12
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#Run|Run]](Handle process, StartupInfo* info)
| This starts the main() thread. Buf+0 is main-thread priority, Buf+4 is main-thread stack-size.
|-
| 0x13
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#CreateMutex|CreateMutex]](Handle* mutex, bool initialLocked)
|
|-
| 0x14
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#ReleaseMutex|ReleaseMutex]](Handle mutex)
|
|-
| 0x15
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#CreateSemaphore|CreateSemaphore]](Handle* semaphore, s32 initialCount, s32 maxCount)
|
|-
| 0x16
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#ReleaseSemaphore|ReleaseSemaphore]](s32* count, Handle semaphore, s32 releaseCount)
|
|-
| 0x17
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#CreateEvent|CreateEvent]](Handle* event, ResetType resettype)
|
|-
| 0x18
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#SignalEvent|SignalEvent]](Handle event)
|
|-
| 0x19
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#ClearEvent|ClearEvent]](Handle event)
|
|-
| 0x1A
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result CreateTimer(Handle* timer, ResetType resettype)
|
|-
| 0x1B
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result SetTimer(Handle timer, s64 initial_nanoseconds, s64 interval)
|
|-
| 0x1C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result CancelTimer(Handle timer)
|
|-
| 0x1D
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result ClearTimer(Handle timer)
|
|-
| 0x1E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|CreateMemoryBlock]](Handle* memblock, u32 addr, u32 size, [[Memory Management#enum_MemoryPermission|MemoryPermission]] mypermission, [[Memory Management#enum_MemoryPermission|MemoryPermission]] otherpermission)
|
|-
| 0x1F
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|MapMemoryBlock]](Handle memblock, u32 addr, [[Memory Management#enum_MemoryPermission|MemoryPermission]] mypermissions, [[Memory Management#enum_MemoryPermission|MemoryPermission]] otherpermission)
|
|-
| 0x20
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management|UnmapMemoryBlock]](Handle memblock, u32 addr)
|
|-
| 0x21
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#Address_Arbiters|CreateAddressArbiter]](Handle* arbiter)
|
|-
| 0x22
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#Address_Arbiters|ArbitrateAddress]](Handle arbiter, u32 addr, ArbitrationType type, s32 value, s64 nanoseconds)
|
|-
| 0x23
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result CloseHandle(Handle handle)
|
|-
| 0x24
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result WaitSynchronization1(Handle handle, s64 timeout_nanoseconds)
|
|-
| 0x25
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result WaitSynchronizationN(s32* out, Handle* handles, s32 handlecount, bool waitAll, s64 timeout_nanoseconds)
|
|-
| 0x26
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SignalAndWait(s32* out, Handle signal, Handle* handles, s32 handleCount, bool waitAll, s64 nanoseconds)
| Stubbed
|-
| 0x27
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result DuplicateHandle(Handle* out, Handle original)
|
|-
| 0x28
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| s64 GetSystemTick(void) (This returns the total CPU ticks elapsed since the CPU was powered-on)
|
|-
| 0x29
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetHandleInfo(s64* out, Handle handle, HandleInfoType type)
|
|-
| 0x2A
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result GetSystemInfo(s64* out, SystemInfoType type, s32 param)
|
|-
| 0x2B
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result GetProcessInfo(s64* out, Handle process, ProcessInfoType type)
|
|-
| 0x2C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#GetThreadInfo|GetThreadInfo]](s64* out, Handle thread, ThreadInfoType type)
|
|-
| 0x2D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[IPC|ConnectToPort]](Handle* out, const char* portName)
|
|-
| 0x2E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SendSyncRequest1(Handle session)
| Stubbed
|
|-
| 0x2F
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SendSyncRequest2(Handle session)
| Stubbed
|
|-
| 0x30
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SendSyncRequest3(Handle session)
| Stubbed
|
|-
| 0x31
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SendSyncRequest4(Handle session)
| Stubbed
|
|-
| 0x32
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[IPC|SendSyncRequest]](Handle session)
|
|-
| 0x33
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result OpenProcess(Handle* process, u32 processId)
|
|-
| 0x34
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#OpenThread|OpenThread]](Handle* thread, Handle process, u32 threadId)
|
|-
| 0x35
| style="background: green" | Yes
| style="background: red" | No
| style="background: green" | Yes
| Result GetProcessId(u32* processId, Handle process)
|
|-
| 0x36
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#GetProcessIdOfThread|GetProcessIdOfThread]](u32* processId, Handle thread)
|
|-
| 0x37
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Multi-threading#GetThreadId|GetThreadId]](u32* threadId, Handle thread)
|
|-
| 0x38
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetResourceLimit(Handle* resourceLimit, Handle process)
|
|-
| 0x39
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetResourceLimitLimitValues(s64* values, Handle resourceLimit, LimitableResource* names, s32 nameCount)
|
|-
| 0x3A
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetResourceLimitCurrentValues(s64* values, Handle resourceLimit, LimitableResource* names, s32 nameCount)
|
|-
| 0x3B
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#GetThreadContext|GetThreadContext]](ThreadContext* context, Handle thread)
| Stubbed
|-
| 0x3C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Break(BreakReason reason)
Break(BreakReason debugReason, const void* croInfo, u32 croInfoSize)
|
|-
| 0x3D
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| OutputDebugString(void const, int)
| Does nothing on non-debug units.
|-
| 0x3E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| ControlPerformanceCounter(unsigned long long, int, unsigned int, unsigned long long)
|
|- style="border-top: double"
| 0x47
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[IPC|CreatePort]](Handle* portServer, Handle* portClient, const char* name, s16 maxSessions)
| Setting name=NULL creates a private port not accessible from svcConnectToPort.
|-
| 0x48
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[IPC|CreateSessionToPort]](Handle* session, Handle port)
|
|-
| 0x49
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[IPC|CreateSession]](Handle* sessionServer, Handle* sessionClient)
|
|-
| 0x4A
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[IPC|AcceptSession]](Handle* session, Handle port)
|
|-
| 0x4B
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReplyAndReceive1(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
| Stubbed.
|-
| 0x4C
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReplyAndReceive2(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
| Stubbed.
|-
| 0x4D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReplyAndReceive3(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
| Stubbed.
|-
| 0x4E
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReplyAndReceive4(s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
| Stubbed.
|-
| 0x4F
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[IPC#svcReplyAndReceive|ReplyAndReceive]](s32* index, Handle* handles, s32 handleCount, Handle replyTarget)
|
|-
| 0x50
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[#Interrupt Handling|BindInterrupt]](Interrupt name, Handle eventOrSemaphore, s32 priority, bool isLevelHighActive)
|
|-
| 0x51
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result UnbindInterrupt(Interrupt name, Handle eventOrSemaphore)
|
|-
| 0x52
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result InvalidateProcessDataCache(Handle process, void* addr, u32 size)
|
|-
| 0x53
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result StoreProcessDataCache(Handle process, void const* addr, u32 size)
|
|-
| 0x54
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result FlushProcessDataCache(Handle process, void const* addr, u32 size)
|
|-
| 0x55
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result [[Corelink DMA Engines|StartInterProcessDma]](Handle* dma, Handle dstProcess, void* dst, Handle srcProcess, const void* src, u32 size, const DmaConfig* config)
|
|-
| 0x56
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result StopDma(Handle dma)
|
|-
| 0x57
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Result GetDmaState(DmaState* state, Handle dma)
|
|-
| 0x58
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| RestartDma(Handle, void *, void const*, unsigned int, signed char)
|
|-
| 0x59
| style="background: green" | Yes
| style="background: red" | No?
| style="background: red" | No
| SetGpuProt(s8 input_flag). Implemented with [[11.3.0-36|11.3.0-X]], see below.
|-
| 0x5A
| style="background: green" | Yes
| style="background: red" | No?
| style="background: red" | No
| SetWifiEnabled(s0 input_flag). Implemented with [[11.4.0-37|11.4.0-X]], see below.
|- style="border-top: double"
| 0x60
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result DebugActiveProcess(Handle* debug, u32 processID)
|
|-
| 0x61
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result BreakDebugProcess(Handle debug)
|
|-
| 0x62
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result TerminateDebugProcess(Handle debug)
|
|-
| 0x63
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetProcessDebugEvent(DebugEventInfo* info, Handle debug)
|
|-
| 0x64
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ContinueDebugEvent(Handle debug, u32 flags)
|
|-
| 0x65
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetProcessList(s32* processCount, u32* processIds, s32 processIdMaxCount)
|
|-
| 0x66
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetThreadList(s32* threadCount, u32* threadIds, s32 threadIdMaxCount, Handle domain)
|
|-
| 0x67
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result GetDebugThreadContext(ThreadContext* context, Handle debug, u32 threadId, u32 controlFlags)
|
|-
| 0x68
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetDebugThreadContext(Handle debug, u32 threadId, const ThreadContext* context, u32 controlFlags)
|
|-
| 0x69
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result QueryDebugProcessMemory(MemoryInfo* blockInfo, PageInfo* pageInfo, Handle debug, u32 addr)
|
|-
| 0x6A
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ReadProcessMemory(void* buffer, Handle debug, u32 addr, u32 size)
|
|-
| 0x6B
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result WriteProcessMemory(Handle debug, void const* buffer, u32 addr, u32 size)
|
|-
| 0x6C
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetHardwareBreakPoint(s32 registerId, u32 control, u32 value)
|
|-
| 0x6D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| [[Multi-threading#GetDebugThreadParam|GetDebugThreadParam]](s64* unused, u32* out, Handle kdebug, u32 threadId, DebugThreadParameter param)
|
|- style="border-top: double"
| 0x70
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result ControlProcessMemory(Handle KProcess, unsigned int Addr0, unsigned int Addr1, unsigned int Size, unsigned int Type, unsigned int Permissions)
|
|-
| 0x71
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management#Memory_Mapping|MapProcessMemory]](Handle process, u32 startAddr, u32 size)
|
|-
| 0x72
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Memory Management#Memory_Mapping|UnmapProcessMemory]](Handle process, u32 startAddr, u32 size)
|
|-
| 0x73
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#CreateCodeSet|CreateCodeSet]](Handle* handle_out, struct CodeSetInfo, u32 code_ptr, u32 ro_ptr, u32 data_ptr)
|
|-
| 0x74
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result RandomStub()
| Stubbed
|-
| 0x75
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result [[Multi-threading#CreateProcess|CreateProcess]](Handle* handle_out, Handle codeset_handle, u32 [[NCCH/Extended_Header#ARM11_Kernel_Capabilities|arm11kernelcaps_ptr]], u32 arm11kernelcaps_num)
|
|-
| 0x76
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| TerminateProcess(Handle)
|
|-
| 0x77
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetProcessResourceLimits(Handle KProcess, Handle KResourceLimit)
|
|-
| 0x78
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result CreateResourceLimit(Handle *KResourceLimit)
|
|-
| 0x79
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result SetResourceLimitLimitValues(Handle res_limit, LimitableResource* resource_type_list, s64* resource_list, u32 count)
|
|-
| 0x7A
| style="background: green" | Yes
| style="background: red" | No
| style="background: green" | Yes
| AddCodeSegment (unsigned int Addr, unsigned int Size)
| Stubbed on NATIVE_FIRM beginning with [[2.0.0-2]]. Used during TWL_FIRM boot.
|-
| 0x7B
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: red" | No
| Backdoor(unsigned int CodeAddress)
| This is used on ARM9 NATIVE_FIRM.
No ARM11 processes have access to it without some form of kernelhax, and this was removed on [[11.0.0-33]] (for ARM11).

|-
| 0x7C
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| KernelSetState(unsigned int Type, ...)
| The type determines the args to be passed
|-
| 0x7D
| style="background: green" | Yes
| style="background: red" | No
| style="background: red" | No
| Result QueryProcessMemory(MemInfo *Info, unsigned int *Out, Handle KProcess, unsigned int Addr)
|
|- style="border-top: double"
| 0xFF
| style="background: green" | Yes
| style="background: green" | Yes
| style="background: green" | Yes
| Stop point
| The svcaccesscontrol mask doesn't apply for this SVC. This svc doesn't check the "debug mode enabled" flag either. Does nothing if there is no [[KDebug]] object associated to the current process. Stubbed on ARM9 NATIVE_FIRM.
|}
NF: NATIVE_FIRM. TF: TWL_FIRM.

Note that "stubbed" here means that the SVC only returns an error, as in the following snippet:

<pre>ROM:FFF04D98 LDR R0, =0xF8C007F4
ROM:FFF04D9C BX LR</pre>

= Types and structures =

== enum ResetType ==

{| class="wikitable" border="1"
! Reset type
! Id
|-
| ONESHOT
| 0
|-
| STICKY
| 1
|-
| PULSE
| 2
|}

Timers/Events may be waited on by a thread using svcWaitSynchronization. Once the timer runs out/the event gets signaled, threads waiting on the respective handles until the timer/event is reset. STICKY timers/events wake up threads until they are explicitly reset by some thread. ONESHOT timers/events will wake up exactly one thread and then are reset automatically. PULSE timers will be reset after waking up one thread too, but will also be started again immediately. It's unknown whether PULSE is a valid reset type for events.

== struct StartupInfo ==
{| class="wikitable" border="1"
! Type
! Field
|-
| s32
| Priority
|-
| u32
| Stack size
|-
| s32
| argc
|-
| s16*
| argv
|-
| s16*
| envp
|}

== enum BreakReason ==
{| class="wikitable" border="1"
! Break Reason
! Value
|-
| PANIC
| 0
|-
| ASSERT
| 1
|-
| USER
| 2
|}

== struct DebugEventInfo ==
Size: 0x28 bytes

When using svcGetProcessDebugEvent, the kernel fetches the first [[KEventInfo]] instance of the process's [[KDebug]]. The debug event is handled and parsed into this structure.

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Event type
|-
| u32
| Thread ID (not used in all events)
|-
| u32
| Flags. Bit0 means that svcContinueDebugEvent needs to be called for this event
|-
| u8[4]
| Remnants of the corresponding flags in [[KEventInfo]], always 0 here
|-
| u32[6]
| Event-specific data (see below)
|}

{| class="wikitable" border="1"
! Event type
! Id
|-
| ATTACH PROCESS
| 0
|-
| ATTACH THREAD
| 1
|-
| EXIT THREAD
| 2
|-
| EXIT PROCESS (1)
| 3
|-
| EXCEPTION
| 4
|-
| DLL LOAD (3)
| 5
|-
| DLL UNLOAD (3)
| 6
|-
| SCHEDULE IN (1) (2)
| 7
|-
| SCHEDULE OUT (1) (2)
| 8
|-
| SYSCALL IN (1) (2)
| 9
|-
| SYSCALL OUT (1) (2)
| 10
|-
| OUTPUT STRING
| 11
|-
| MAP (1) (2)
| 12
|}

<nowiki>(1)</nowiki> Non-blocking: all other events preempt and block all the threads of their process until they are continued.

<nowiki>(2)</nowiki> There is handling code in the kernel but nothing signal those events.

<nowiki>(3)</nowiki> Completely removed from the kernel, but referenced in DMNT. Stubbed relocation code (e.g., in Process9 and in PXI sysmodule) and even whole libraries (e.g., in PXI sysmodule's .rodata section) seem to indicate that Nintendo used dynamic libraries early in system development.

When calling svcDebugActiveProcess, an ATTACH PROCESS debug event is signaled, then ATTACH THREAD for each of its opened threads, then finally ATTACH BREAK.

ATTACH THREAD events are also emitted when a thread is created from an attached process.

=== ATTACH PROCESS event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u64
| Program ID
|-
| char[8]
| Process name
|-
| u32
| Process ID
|-
| u32
| "Other" flag. Always 0 in available kernel versions
|}

=== ATTACH THREAD event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Creator thread ID (0 if attached by svcDebugActiveProcess)
|-
| void *
| Thread local storage
|-
| u32 *
| Entrypoint = .text load address of the parent process
|}

=== EXIT THREAD/PROCESS events ===

A single u32 reason field is used.

Thread exit reasons:
{| class="wikitable" border="1"
! Reason
! Id
|-
| (None)
| 0
|-
| TERMINATE
| 1
|-
| EXIT PROCESS
| 2
|-
| TERMINATE PROCESS
| 3
|}

Process exit reasons:
{| class="wikitable" border="1"
! Reason
! Id
|-
| (None)
| 0
|-
| TERMINATE
| 1
|-
| DEBUG TERMINATE
| 2
|}

=== EXCEPTION event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Exception type
|-
| u32
| Exception address
|-
| u32[4]
| Type-specific data, see below
|}

Exception types:
{| class="wikitable" border="1"
! Exception type
! Id
|-
| UNDEFINED INSTRUCTION
| 0
|-
| PREFETCH ABORT
| 1
|-
| DATA ABORT
| 2
|-
| UNALIGNED DATA ACCESS
| 3
|-
| ATTACH BREAK
| 4
|-
| STOP POINT
| 5
|-
| USER BREAK
| 6
|-
| DEBUGGER BREAK
| 7
|-
| UNDEFINED SYSCALL
| 8
|}

==== UNDEFINED INSTRUCTION/PREFETCH ABORT/DATA ABORT/UNALIGNED DATA ACCESS/UNDEFINED SYSCALL events ====
{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Fault information: Fault Address Register (for DATA ABORT and UNALIGNED DATA ACCESS),
attempted SVC ID (for UNDEFINED SYSCALL), otherwise 0
|}

==== STOP POINT event ====
{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Stop point type that caused the event: 0 = svc 0xFF, 1 = breakpoint, 2 = watchpoint
|-
| u32
| Fault information: FAR for watchpoints, 0 otherwise
|}

==== USER BREAK event ====
{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Break reason
|-
| u32[2]
| Info for LOAD_RO and UNLOAD_RO
|}

User break types:
{| class="wikitable" border="1"
! Reason
! Id
|-
| PANIC
| 0
|-
| ASSERT
| 1
|-
| USER
| 2
|-
| LOAD_RO
| 3
|-
| UNLOAD_RO
| 4
|}

==== DEBUGGER BREAK event ====
{| class="wikitable" border="1"
! Type
! Field
|-
| s32[4]
| IDs of the attached process's threads that were running on each core at the time of the @ref svcBreakDebugProcess call, or -1 (only the first 2 values are meaningful on O3DS).
|}

=== SCHEDULE/SYSCALL IN/OUT events ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u64
| Clock tick
|-
| u32
| CPU ID (SCHEDULE events) Syscall (SYSCALL events)
|}

=== OUTPUT STRING event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| String address
|-
| u32
| String size
|}

=== MAP event ===

{| class="wikitable" border="1"
! Type
! Field
|-
| u32
| Mapped address
|-
| u32
| Mapped size
|-
| u32
| MemoryPermission
|-
| u32
| MemoryState
|}

== struct ThreadContext ==

Size: 0xCC bytes

{| class="wikitable" border="1"
|-
! Offset
! Type
! Description
|-
| 0x0
| CpuRegisters
| Saved CPU registers (r0-r12, sp, lr, pc, cpsr)
|-
| 0x44
| FpuRegisters
| Saved FPU registers (d0-d15, fpscr, fpexc)
|}

The user needs to adjust pc for exceptions that occured while in Thumb mode.

'''Flags for svcGetDebugThreadContext/svcSetDebugThreadContext''':

{| class="wikitable" border="1"
|-
! Bit
! Description
|-
| 0
| Get/set CPU GPRs (r0-r12)
|-
| 1
| Get/set CPU SPRs (sp, lr, pc, cpsr)
|-
| 2
| Get/set FPU GPRs (d0-d15 aka. f0-f31)
|-
| 3
| Get/set FPU SPRs (fpscr, fpexc)
|}

When setting CPSR, the following assignment is done: <code>ctx->cpsr = ctx->cpsr & 0x7F0FDFF | userCtx->cpuRegisters.cpsr & 0xF80F0200;</code>. This is to avoid obvious security issues.

== enum DebugThreadParameter ==

{| class="wikitable" border="1"
! Parameter
! Id
|-
| PRIORITY
| 0
|-
| SCHEDULING_MASK_LOW
| 1
|-
| CPU_IDEAL
| 2
|-
| CPU_CREATOR
| 3
|}

== typedef Handle ==

User-visible references to internal objects are represented by 32-bit integers called handles. Handles are only valid in the process they have been created in; hence, they cannot be exchanged between processes directly (the [[IPC]] functions provide a mean to copy handles to other processes, though).

There are a number of special-purpose handles, which provide easy access to information on objects in the current process:
{| class="wikitable" border="1"
! Handle
! Description
|-
| 0xFFFF8000
| Handle to the active thread
|-
| 0xFFFF8001
| Handle to the active process
|}

=svcSetHardwareBreakPoint=
This is essentially an interface for writing values to the debug-unit (B/W)RP registers. registerId range 0..5 = breakpoints(BRP0-5), 0x100..0x101 = watchpoints(WRP0-1), anything outside of these ranges will result in an error. This is used for both adding and removing/disabling breakpoints/watchpoints, hence the raw control value parameter.

Here the kernel sets bit15 in the DSCR, to enable monitor-mode debugging.

Regardless of whether this is for a BRP, when bit21 is set in the control input parameter(BRP type = contextID), the kernel will load the target process [[KProcess|contextID]] and use that internally for the value field. The target process is specified via a [[KDebug]] handle passed as the "value" parameter.

Lastly, the kernel disables the specified (B/W)RP, then writes the value parameter / loaded contextID to the (B/W)VR, then writes the input control value to the (B/W)CR.

= [[DMA]] =
The CTRSDK code for using svcStartInterProcessDma will execute svcBreak when svcStartInterProcessDma returns an error(except for certain error value(s)). Therefore on retail, triggering a svcStartInterProcessDma via a system-module which results in an error from svcStartInterProcessDma will result in the system-module terminating.

= Interrupt Handling =

svcBindInterrupt registers the given event or semaphore corresponding to the handle to the global [[ARM11_Interrupts#Interrupt_Table_.28New3DS.29|"interrupt table"]] for the given interrupt ID. Interrupts 0-14 and 16-31 can never be mapped regardless of the [[NCCH/Extended_Header#ARM11_Kernel_Capabilities|interrupt flags of the process's exheader]], and the latter are not checked when mapping interrupt 15. The "is level high active"/"is manual clear" parameter must be false when binding a semaphore handle (otherwise 0xD8E007EE "invalid combination" is returned).

If something was already registered for the given ID, svcBindInterrupt returns error 0xD8E007F0. See [[KBaseInterruptEvent]] for more information on what happens on receipt of an interrupt.

Applications hence can wait for specific interrupts to happen by calling WaitSynchronization(N) on the event or semaphore handles.

The set of existing ARM11 interrupts is listed on [[ARM11 Interrupts|this page]].

= Debugging =
DebugActiveProcess is used to attach to a process for debugging. This SVC can only be used when the target process' ARM11 descriptors stored in the exheader have the kernel flag for "Enable debug" set. Otherwise when that flag is clear, the kernel flags for the process using this SVC must have the "Force debug" flag set.

This SVC can only be used when a certain kernel state debug flag is non-zero(it's set to zero for retail).

= KernelSetState =
KernelSetState uses the 6th [[ARM11_Interrupts#Private_Interrupts|software-generated interrupt]] for any operation involving synchronization between cores.

{| class="wikitable" border="1"
|-
! Type
! Enabled for the NATIVE_FIRM ARM11 kernel
! Enabled for the TWL_FIRM ARM11 kernel
! Description
|-
| 0
| Yes
| No
| Arguments : <code>u64 firmTitleID</code> (the high 32-bits of that title ID (0 when using N3DS pm) have a special meaning on N3DS, they're otherwise ignored, see below).
This initializes the programID for launching [[FIRM]], then triggers launching [[FIRM]]. With New3DS kernel, it forces the firm title ID to be the New3DS NATIVE_FIRM, when the input firm title ID is 2. The high firm title ID is always set to 0x40138. On New3DS, the kernel disables the additional New3DS cache hw prior to calling the firmlaunch function from the <handler for the KernelSetState-types called via funcptr>.
|-
| 1
| Yes
| Yes
| Does nothing.
|-
| 2
| Yes
| Yes
| Powers down the GPU and syncs with Process9 (waits for <code>*(vu8 *)PXI_SYNC11</code> to be 1) during the process.
On New3DS, the kernel disables the additional New3DS cache hw, when it's actually enabled, prior to executing the rest of the code from the <handler for the KernelSetState-types called via funcptr>.
|-
| 3
| Yes
| No
| Arguments: <code>0, void* address</code> or <code>1</code>
This used for initializing the 0x1000-byte buffer used by the launched [[FIRM]]. When the first parameter is 1, this buffer is copied to the beginning of FCRAM at 0xE0000000. When it is 0, this kernel buffer is mapped to the process address specified by the second argument.
|-
| 4
| No
| Yes
| This unmaps(?) the following virtual memory by writing value physaddr (where physaddr base is 0x80000000) to the L1 MMU table entries: 0x00300000..0x04300000, 0x08000000..0x0FE00000, and 0x10000000..0xF8000000.
|-
| 5
| Yes
| Yes
| Power state change. Takes one u32 parameter.

0: shutdown/reboot. hangs the Arm11. Used by kernelpanic and PTM. This makes all cores enter a WFI/B infinite loop.
|-
| 6
| Yes
| No
| Arguments: <code>u32 what, u64 val</code>
UNITINFO needs to be non-zero for <code>what</code> 1 and 2.

If <code>what</code> is 0 or any invalid value, nothing is done.

If it is 1, <code>val != 0</code> is written to the global variable enabling ERR:F-format register dumps on user-mode CPU/VFP exceptions (the VFP exception handler acts as if this variable was always true and works on retail environments). The user handler, stack pointer to use for exception handling, and pointer to use for the exception info structure are contiguously located in either the thread's TLS, or if the handler is NULL, in the main thread's TLS, at offset 0x40. If the specified stack pointer is 1, sp_usr - 0x5c is used instead; if the specified exception info buffer is 1, sp_usr - 0x5c is used instead, and if it is 0, <specified stack> - 0x5c is used (0x5c is the size of the exception info structure that is being pushed). Configured by NS on startup on dev-units (default being 0 on non-debugger/jtag units) using the 0x000F0000 configuration block in the [[Config_Savegame|config savegame]].

If 2, kernelpanic will be called when svcBreak is used by a non-attached process. Configured by NS on startup on dev-units (default being 0 on non-debugger/jtag units) using the 0x000F0000 configuration block in the [[Config_Savegame|config savegame]].

If 3, this changes the scheduling/preemption mode (when no threads are being preempted, otherwise returns error 0xC8A01414), see [[KResourceLimit]] for more details.
|-
| 7
| Yes
| No
| This triggers an MCU (hard) reboot. This reboot is triggered via device address 0x4A on the second [[I2C]] bus (the MCU). Register address 0x20 is written to with value 4. This code will not return.
On New3DS, the kernel disables the additional New3DS cache hw prior to calling the reboot function from the <handler for the KernelSetState-types called via funcptr>.
|-
| 8
| Yes
| No
| Hangs the Arm9, using a code path similar to the one used on firmlaunch. Used by PTM on shutdown/reboot.
|-
| 9
| Yes, implemented at some point after system-version v4.5.
| ?
| Argumens: <code>u64 titleID</code>.
When creating a process, if the process has a non-zero TID equal to the parameter above (which is stored in a global variable), then KProcessHwInfo+0x32 ("process is the currently running app") is set to <code>true</code>.
Used by NS conditionally based on the contents of the [[NS CFA]].
|-
| 10
| Yes
| ?
| Arguments: <code>u32 config</code>
ConfigureNew3DSCPU. Only available for the [[New_3DS]] kernel. The actual code for processing this runs under the <handler for the KernelSetState-types called via funcptr>, which runs on all ARM11 cores. Only bit0-1 of the argument are used here. Bit 0 enables higher core clock, and bit 1 enables additional (L2) cache. This configures the hardware [[PDN_Registers|register]] for the flags listed [[NCCH/Extended_Header#Flag1|here]], among other code which uses the MPCore private memory region registers.
|}

= GetSystemInfo =
{| class="wikitable" border="1"
! SystemInfoType value
! s32 param
! Description
|-
| 0
| 0
| This writes the total used memory size in the following memory regions to out: APPLICATION, SYSTEM, and BASE.
|-
| 0
| 1
| This writes the total used memory size in the APPLICATION memory region to out.
|-
| 0
| 2
| This writes the total used memory size in the SYSTEM memory region to out.
|-
| 0
| 3
| This writes the total used memory size in the BASE memory region to out.
|-
| 2
| Unused
| This writes the FCRAM memory [[Memory_Allocation#FCRAM_Region_Data|used by the kernel]] to out.
|-
| 25
| Unused
| This writes the total number of threads which were directly launched by the kernel, to out. No longer exists with some kernel version?
|-
| 26
| Unused
| This writes the total number of processes which were directly launched by the kernel, to out. For the NATIVE_FIRM/SAFE_MODE_FIRM ARM11 kernel, this is normally 5, for processes sm, fs, pm, loader, and pxi.
|}

= GetProcessInfo =
Input:
R0 = unused
R1 = Handle process
R2 = ProcessInfoType type

Output:
R0 = Result
R1 = output value lower word
R2 = output value upper word

{| class="wikitable" border="1"
! ProcessInfoType value
! Available since system version
! Description
|-
| 0
|
| Returns the amount of private (code, data, regular heap) and shared memory used by the process + total supervisor-mode stack size + page-rounded size of the external handle table. This is the amount of physical memory the process is using, minus TLS, main thread stack and linear memory.
|-
| 1
|
| Returns the amount of <related unused field> + total supervisor-mode stack size + page-rounded size of the external handle table
|-
| 2
|
| Returns the amount of private (code, data, heap) memory used by the process + total supervisor-mode stack size + page-rounded size of the external handle table
|-
| 3
|
| Returns the amount of <related unused field> + total supervisor-mode stack size + page-rounded size of the external handle table
|-
| 4
|
| Returns the amount of handles in use by the process.
|-
| 5
|
| Returns the highest count of handles that have been open at once by the process
|-
| 6
|
| Returns <code>*(u32*)(KProcess+0x234)</code> which is always 0
|-
| 7
|
| Returns the number of threads of the process
|-
| 8
|
| Returns the maximum number of threads which can be opened by this process (always 0)
|-
| 9-18
| [[8.0.0-18]]
| This only returns error 0xD8E007ED.
|-
| 19
| Stub: [[8.0.0-18]]. Implementation: [[11.3.0-36|11.3.0-X]].
| Originally this only returned 0xD8E007ED. Now with v11.3 this returns the memregion for the process: out low u32 = [[KProcess]] "Kernel flags from the exheader kernel descriptors" & 0xF00 (memory region flag). High out u32 = 0.
|-
| 20
| [[8.0.0-18]]
| low u32 = (0x20000000 - <LINEAR virtual-memory base for this process>). That is, the output value is the value which can be added to LINEAR memory vaddrs for converting to physical-memory addrs.
|-
| 21
| [[8.0.0-18]]. N3DS only.
| Returns the VA -> PA conversion offset for the QTM static mem block reserved in the exheader (0x800000), otherwise 0 (+ error 0xE0E01BF4) if it doesn't exist
|-
| 22
| [[8.0.0-18]]. N3DS only.
| Returns the base VA of the QTM static mem block reserved in the exheader, otherwise 0 (+ error 0xE0E01BF4) if it doesn't exist
|-
| 23
| [[8.0.0-18]]. N3DS only.
| Returns the size of the QTM static mem block reserved in the exheader, otherwise 0 (+ error 0xE0E01BF4) if it doesn't exist
|}

= GetHandleInfo =

{| class="wikitable" border="1"
! HandleInfoType value
! Description
|-
| 0
| This returns the time in ticks the KProcess referenced by the handle was created. If a KProcess handle was not given, it will write whatever was in r5, r6 when the svc was called.
|-
| 1
| Get internal refcount for kernel object (not counting the one this SVC adds internally to operate), sign-extended to 64 bits.
|-
| 2
| Unimplemented, returns an uninitialized u64 variable (corresponding to r5-r6, which were not altered outside of userland).
|-
| 0x32107
| Returns (u64) 0.
|}

= svc7B Backdoor =
This saves SVC-mode SP+LR on the user-mode stack, then sets the SVC-mode SP to the user-mode SP. This then calls the specified code in SVC-mode. Once the called code returns, this pops the saved SP+LR off the stack for restoring the SVC-mode SP, then returns from the svc7b handler. Note that this svc7b handler does not disable IRQs, if any IRQs/context-switches occur while the SVC-mode SP is set to the user-mode one here, the ARM11-kernel will crash(which hangs the whole ARM11-side system).

= svc 0x59 =
Implemented with [[11.3.0-36|11.3.0-X]]. Used with GSP module starting with that version. This always returns 0.

When input_flag is not 0x1, it will use value 0x0 internally. When a state field already matches input_flag, this will immediately return. Otherwise, after this SVC finishes running, it will write input_flag to this state field. GSP module uses 0x0 for APPLICATION-memregionid and 0x1 for non-APPLICATION-memregionid.

This writes "<nowiki>0x100 | <val></nowiki>" to [[CONFIG11_Registers#CFG11_GPUPROT|pdnregbase+0x140]], where val depends on input_flag and a kernel state field for [[Configuration_Memory|APPMEMTYPE]].

When input_flag is 0x1 val is fixed:
* Old3DS: 0x3
* New3DS: 0x460

Otherwise, val depends on the kernel APPMEMTYPE state field:
{| class="wikitable" border="1"
|-
! FIRM
! [[Memory_layout|APPMEMTYPE]]
! val
|-
| Old3DS
| 2
| 0x3
|-
| Old3DS
| 3
| 0x5
|-
| Old3DS
| 4
| 0x6
|-
| Old3DS
| Non-value-{2/3/4}
| 0x7
|-
| New3DS
| 7
| 0x490
|-
| New3DS
| Non-value-7
| 0x4F0
|}

This same register is also initialized during kernel boot starting with [[3.0.0-5]], with the following values:
* Old3DS: 0x103
* New3DS: 0x550

= svc 0x5A =
Like what NWM did previously, this one does the following:

if (in_flag)
CFG11_WIFICNT |= 1;
else
CFG11_WIFICNT &= ~1;

= Kernel error-codes =
See [[Error codes]].

{| class="wikitable" border="1"
! Error-code value
! Description
|-
| 0x09401BFE
| Timeout occurred with svcWaitSynchronization*, when timeout is not ~0.
|-
| 0xC8601801
| No more unused/free synchronization objects left to use in a given object's linked list. (KEvent, KMutex, KTimer, KSemaphore, KAddressArbiter, KThread)
|-
| 0xC8601802
| No more unused/free KSharedMemory objects left to use in the KSharedMemory linked list - out of blocks
|-
| 0xC8601809
| No more unused/free KSessions left to use in the KSession linked list - out of sessions
|-
| 0xC860180A
| Not enough free memory available for memory allocation.
|-
| 0xC920181A
| The session was closed by the other process..
|-
| 0xD0401834
| Max connections to port have been exceeded
|-
| 0xD8609013
| Unknown, probably reslimit related?
|-
| 0xD88007FA
| Returned if no KObjectName object in the linked list of such objects matches the port name provided to the svc.
|-
| 0xD8E007ED
| This indicates that a value is outside of the enum being used.
|-
| 0xD8E007F1
| This error indicates Misaligned address.
|-
| 0xD8E007F7
| This error indicates that the input handle used with the SVC does not exist in the process handle-table, or that the handle kernel object type does not match the type used by the SVC.
|-
| 0xD9000402
| Invalid memory permissions for input/output buffers, for svcStartInterProcessDma.
|-
| 0xD9001814
| Failed unprivileged load or store - wrong permissions on memory
|-
| 0xD9001BF7
| This error is returned when the kernel retrieves a pointer to a kernel object, but the object type doesn't match the desired one.
|-
| 0xD92007EA
| This error is returned when a process attempts to use svcCreateMemoryBlock when the process memorytype is the application memorytype, and when addr=0.
|-
| 0xE0E01BF5
| This indicates an invalid address was used.
|-
| 0xF8C007F4
| Invalid type/param0-param3 input for svcKernelSetState. This is also returned for those syscalls marked as stubs.
|}

PMApp:SetAppResourceLimit

2023-11-29T19:24:54Z

Emufan4568:

=Request=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code [0x000A0140]
|-
| 1
| 0
|-
| 2
| Resource limit type (9)
|-
| 3
| Resource limit value.
|-
| 4-5
| u64, 0
|}

=Response=
{| class="wikitable" border="1"
|-
! Index Word
! Description
|-
| 0
| Header code
|-
| 1
| Result code
|}

=Description=
Interface for [[SVC|svcSetResourceLimitValues]]. Resource limit type must be set to 9, meaning "Max CPU time" (see [[KResourceLimit]]). If the parameters are not set exactly as listed, or when the input reslimit-value is higher than the maximum allowed value(from PM-module state), the command will return result code 0xD8E05BF4.

11.16.0-48

2023-11-26T09:47:09Z

Emufan4568:

The Old3DS+New3DS 11.16.0-48 system update was released on August 30, 2022 (UTC). This Old3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN. This New3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN.

Security flaws fixed: <fill this in manually later, see the updatedetails page from the ninupdates-report page(s) once available for now>.

This update does NOT break Luma3DS.

==Change-log==
[https://en-americas-support.nintendo.com/app/answers/detail/a_id/231/~/system-menu-update-history Official] USA change-log:
*
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience.
*
*

==System Titles==
The following was updated: NVer/CVer, eShop, friends-sysmodule, NATIVE_FIRM, mint, Web browser Data (title 0004001B00018002). EULA was also updated only for JPN.

The following changed in the RomFs for 0004001B00018002:
* "/js/cave.js differ" updated
* "/js/cave.min.js" updated
* "/json/": The "message_" files for localization were updated.
* "/version.txt" updated

===FIRM===
Besides the usual changes (version bumps / anti-downgrade list), the only other change was updating sm.

The changes in SM added bound checks to RegisterService and RegisterPort, thereby fixing smpwn (the only other change was removing an unused field in a structure).

==See Also==
System update report(s):
* [https://yls8.mtheall.com/ninupdates/reports.php?date=2022-08-30_00-00-33&sys=ctr]
* [https://yls8.mtheall.com/ninupdates/reports.php?date=2022-08-30_00-00-41&sys=ktr]

[[Category:Firmware Versions]]

11.8.0-41

2023-11-26T09:46:17Z

Emufan4568:

The Old3DS+New3DS 11.8.0-41 system update was released on July 30, 2018. This Old3DS+New3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN.

Security flaws fixed: <fill this in manually later, see the updatedetails page from the ninupdates-report page(s) once available for now>.

==Change-log==
[https://en-americas-support.nintendo.com/app/answers/detail/a_id/667/p/430/c/267 Official] USA change-log:
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience

==System Titles==
<fill this in (manually) later>

===NATIVE_FIRM===
==== Process9 ====
Actual code changed in Process9.

pxi:am9 command 0x6d0184 was added, see [[AMPXI:ExportTicketWrapped]]

The anti-downgrade list was updated (versions bumped and new titles were added, such as TWL_FIRM).

====Kernel11====
3 functions were updated, besides the descriptor parsing func (which had the version value updated):

* [[SVC|svcControlProcessMemory]]: At the start, this was added: <code>if (Addr0==NULL || ((Type==MEMOP_MAP || Type==MEMOP_UNMAP) && Addr1==NULL)) return 0xD8E007F6;</code>
* [[SVC|svcConnectToPort]]: The string comparison func was removed and is now inlined.
* The SlabHeap object allocator func will now panic if the ptr it would have returned is NULL.

====KIPs====
No changes.

=== AM ===
New am:net command 0x8290184 was added, see [[AMNet:ExportTicketWrapped]]. This is used by nim.

=== Friends ===
fpdver version string bumped to 0xC

=== nim ===
Added 2 new strings in the codebin: "X-Authentication-Key" and "X-Authentication-Data".

Now uses [[AMNet:ExportTicketWrapped]] during code related to downloading contents(?) (function at 0x143B9C; its caller at 0x123ABC uses amnet:Begin/ResumeImportContent)

If ExportTicketWrapped succeeded, then the new http headers are passed: "X-Authentication-Key" set to base64(wrapped_aes_key) and "X-Authentication-Data" set to base64(crypted_ticket).

==Server-side changes==
When 11.8.0-41 launched, the X-Authentication headers were not required; however, if they were indeed "voluntarily" sent, unsigned tickets would still have resulted in the download being blocked.

On 2018-8-9, at approximately the later half of 13h GMT, ticket-less downloads (of [[NCCH|contents]] as well as [[TMD]]s) started being blocked for a small number of titles, mainly 1st and 2nd party (but not their entirety: [https://gbatemp.net/threads/z.514370/page-12#post-8210076 list as of 2018-8-11])

The selection of affected titles appears to be manually maintained, and it is speculated (but not readily provable) that contractual limitations may influence Nintendo's ability to implement this change without consent of the original developers, hence the still very limited number of affected titles.

At a similiar time on 2018-8-22, this restriction started being enforced for all 3DS commercial applications (titleID 00040000-*).

==See Also==
System update report(s):
* [https://yls8.mtheall.com/ninupdates/reports.php?date=07-30-18_08-00-36&sys=ctr]
* [https://yls8.mtheall.com/ninupdates/reports.php?date=07-30-18_08-00-40&sys=ktr]

[[Category:Firmware Versions]]

11.4.0-37

2023-11-26T09:45:54Z

Emufan4568:

The Old3DS+New3DS 11.4.0-37 system update was released on April 10, 2017. This Old3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN. This New3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN.

Security flaws fixed: yes.

==Change-log==
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/667/p/430/c/267 Official] USA change-log:
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience

==System Titles==
===NATIVE_FIRM===
====Process9====
Exactly two functions were changed.

The global boolean preventing [[FIRM|SAFE_FIRM]] from being launched is now set in Process9's main() if [[CONFIG9_Registers#CFG9_BOOTENV|CFG9_BOOTENV]] has bit0 set, that is to say, if it has been launched from a firmlaunch (this register is set to 1 just before a firmlaunch). The following code has also been added in the firmlaunch function itself, immediately after the code-block where the boolean is checked: <code>if(!(CFG9_BOOTENV & 1) /* not a firmlaunch */ || (CFG9_BOOTENV & 6) /* firmlaunched from LGY_FIRM (if even possible at all) */) goto panic</code>.

This is to properly fix [[3DS_System_Flaws#Process9|safehax]].

====New3DS kernel9loader====
New3DS kernel9loader wasn't updated.

====ARM11 kernel====
There's exactly three code changes:

* [[CONFIG11_Registers#CFG11_WIFIUNK|CFG11_WIFIUNK]] is now set to 0x10 in Kernel11's crt0
* A new SVC, [[SVC|svc 0x5A]] has been introduced, to enable or disable wifi
* The code handling [[SVC|svcArbitrateAddress]] with type = SIGNAL, has been changed. It now counts the actual number of threads arbitrating on that address, and if it is non-zero, it executes the following hack: <code>if(coreId == 0 && currentThread->dynamicPriority >= 50) waitCycles(0x64E)</code>. This supposedly works around the lag issue in some games, which has been introduced on [[11.3.0-36]]

===Modules===
No FIRM ARM11 sysmodule was changed.

===[[NWM_Services|NWM-sysmodule]]===
The [[CONFIG11_Registers]] are no longer directly mapped under userland for NWM-sysmodule.
This prevents anything under NWM-module from modifying the GPUPROT register. This was used by both *hax payload(prior to v11.4 release) and [https://github.com/smealum/udsploit udsploit].

The codebin was updated.

The crt0-poke in PDN that NWM previously did:
0x1EC4010C |= 0x10

.. has been removed from NWM. This one has been moved into kernel bootup.

All accesses to 0x1EC40180 have been replaced by a new syscall, [[SVC|0x5A]].

This now includes code from old CTRSDK update(s). A new func was added for calling a func, previously that func was directly called via vtable funcptr. The only other changes was new heap code(and the code for using it basically), for fixing the NWMUDS sharedmem [[3DS_System_Flaws|vuln]]. This includes code which actually validates heap memchunkhdrs, with svcBreak being executed on failure.

A new string was added at 0x13E200: "used"(with 3 0xFF bytes afterwards), this is used by the new heap code. The wifi-fw was moved from .data to .rodata.

===[[HTTP_Services|HTTP-sysmodule]]===
There were exactly 3 changes in the HTTP-sysmodule codebin.

Two functions, the memalloc and memfree functions used with HTTP sharedmem, were updated to use the new function. The new function is for heap memchunkhdr validation. This additional code is the same new heap code as NWM-sysmodule. This fixed the vuln used by ctr-httpwn at the time of sysupdate release.

===[[Friend_Services|Friends-sysmodule]]===
Like past updates the only change in this codebin was the fpdver(0x9->0xA).

===[[NS_and_APT_Services|NS-sysmodule]]===
The only changes for NS was version values in the codebin, nothing else.

===[[Internet Browser]]===
The web-browser was updated, only for New3DS. See [[Internet Browser|here]] for details.

===[[Nintendo_3DS_Sound]]===
soundhax was fixed, it appears other vulns were fixed too.

Exactly 8 functions were changed in the codebin.

L_1d3ba8
updated, prev ver @ L_1d3ba8.
Added only the following code:
if(len<2)return;
if(len>=0xfe)len=0xfe;
*lenstorage = len;

L_1d3d10
updated, prev ver @ L_1d3cfc.
When L_1ea0b8 returns non-zero, this now clears the 4-bytes at inr1.

L_1f32c4
updated, prev ver @ L_1f329c.
This now writes u32 val0 to inr0+0x34 immediately after the nop instruction.

L_275754
updated, prev ver @ L_27572c.
This now executes the following each time L_1ea0b8 returns non-zero: sp20 = 0;

L_275ed4
updated, prev ver @ L_275e94.
Added the following code after the branch for "if(*(inr1+8)==0)":
if(len>0xfe){len=0xfe;<jump over the code which checks len0>}
Identical changes were added at 0x276054, except with len val 0x82.
Likewise at 0x276138 except with len val 0x76.

L_280000
updated, prev ver @ L_27ff90.
This was added at 0x280444: if(len>0xfe)len=0xfe;
Minor(?) other changes.

L_280c74
updated, prev ver @ L_280b60.
This now writes u32 val0 to inr0+0x34 immediately after the nop instruction.

L_281ab0
updated, prev ver @ L_281998.
Added the following: if(len>=0xfe)len=0xfe;
This was added at 0x281b94:
if(somelen>=0xfe)
{
len=0xfe;
}
else
{
len=somelen;
}
*r4 = val;
Then len is used for a string data-copy(ASCII/UTF16), unless it's UTF16 and len is <=0.

===[[Title_list|SNOTE_AP]]===
This was updated with vuln fixes similar to the sound-app.

LT_1004d6
updated, prev ver @ LT_1004d6.
Added a func call for LT_1017c8 at 0x100508.

LT_1017c8
new func.
Only called by LT_1004d6.
return LT_10250c(0x405, 5, 0x5109d503);

LT_103368
updated, prev ver @ LT_1032f8.
The first func call was removed, it's now located in LT_1017c8.

LT_11ea6c
updated, prev ver @ LT_11ea60.
Added the following: if(len>0xfe)*lenptr = 0xfe;

LT_11f210
updated, prev ver @ LT_11f1fc.
The following was added at 0x11f49c: if(len>0xfe)len=0xfe;
Before executing "return ~0x63;" this now calls LT_12f542.
minor other changes.

LT_11f84c
updated, prev ver @ LT_11f828.
This now clears inr0+0x34 after calling L_14cabc.

LT_11f9ac
updated, prev ver @ LT_11f984.
Added the following: if(len>0xfe)*lenptr=0xfe;
==New 2DS XL Version==
On June 15, 2017 a new version of 11.4.0-37E was released pre-installed with the AU/NZ debut of the New 2DS XL model of the 3ds family. There are 13 updated titles over the base NUS version included this new model, apparently to ensure compatibility with the New 2DS XL's unique 3D-less hardware configuration. A list of changed titles can be found [https://gist.github.com/ihaveamac/bffc8694ac209207c8db86a98f6c4238 here].

===[[MCU Services|MCU sysmodule]]===
Differences between v8192 and v9216 (New2DSXL):

* The SDK crt0 and functions seem to have been updated
* The MCU firmware has been moved into .rodata
* Other minor changes (?)

The MCU firmware itself was updated, see below.

====MCU firmware====
With <code>u16 *g_model = (u16 *)0x000ff908;</code>, the function that were actually changed are:

* 00000189: adds <code>if(*g_model == 2DS) *g_model == N2DSXL;</code> in the function that converts model numbers to their XL versions. However the function hardcodes N3DS even on N2DSXL.
* <code>*(u8 *)0xffe3a |= (model == N3DS || model == N3DSXL) ? 8 : 0;</code> becomes <code>*(u8 *)0xffe3a |= (model == N3DS || model == N3DSXL || model == N2DSXL) ? 8 : 0</code>
* 00002be5 (previously 00002be1):
u8 *v = (u8 *)0xffe3b;
if(g_model == N3DS || g_model == N3DSXL)
{
v[0] = 0x54;
v[1] = 0x44;
}
+else if(g_model == N2DSXL)
+{
+ v[0] = 0x4e;
+ v[1] = 0x3f;
+}
else
{
v[0] = 0x4b;
v[1] = 0x3d;
}

Reminder: The MCU is similar to the rl78-g13 model; to build a reconstruct the MCU firmware, copy 0x1000 bytes after "jhl" ''twice'', and 0x1000 bytes thereafter.

==See Also==
System update report(s):
* [https://yls8.mtheall.com/ninupdates/reports.php?date=04-10-17_08-00-38&sys=ctr]
* [https://yls8.mtheall.com/ninupdates/reports.php?date=04-10-17_08-00-47&sys=ktr]

[[Category:Firmware Versions]]

11.3.0-36

2023-11-26T09:45:04Z

Emufan4568:

The Old3DS+New3DS 11.3.0-36 system update was released on February 6, 2017. This Old3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN. This New3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN.

Security flaws fixed: yes.

==Change-log==
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/667/p/430/c/267 Official] USA change-log:
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience

==System Titles==
===NATIVE_FIRM===
====Process9====
Actual code changed in Process9 .text. Exactly 2 functions were updated, and 1 new function was added which is called by the first function(see below).

Process9 now sets a global flag via the new function when starting certain titles. The flag is set when programID-high matches 0x00040000 or 0x00040010, unless the uniqueID is [[Title_list|0xF802A]] for programID-high 0x00040000. The flag is set for programID-high 0x00040030(applets) when the uniqueID doesn't match any of the 6 Home Menu regions. The flag is not set if the programID-high isn't one of these 3. This is implemented in the PXIPM cmdhandler function in the code for [[PXIPM:RegisterProgram]], in the code prior to actually calling the [[PXIPM:RegisterProgram]] function.

The flag-write function just writes hard-coded value 0x1 to the u8 flag.

The firmlaunch function panics when attempting to launch SAFE_FIRM(New3DS programID-low bitmask is masked out) if that flag has been set, to prevent [[3DS_System_Flaws|safefirmhax]].

The anti-downgrade title-listing in Process9 was also updated.

====New3DS arm9loader====
New3DS arm9loader wasn't updated.

====ARM11 kernel====
fasthax was fixed.

Exactly 4 functions were added(includes the func for SVC 0x59 and the actual func for it). Exactly 14 functions were updated, 13 if not including the kernel-flags-parser func which verifies the exheader kernel-version etc(which only had compiler(?)-related changes minus version constant).

Code addrs listed below are from the Old3DS kernel.

* A new [[SVC]] was implemented: 0x59. See [[SVC|here]] for the kernel implementation. This is used by the updated GSP-module.
* svcGetProcessInfo type19 was [[SVC|implemented]], this is used by the updated GSP-module.
* Additional bound checks were added to timer-handling code (setting and/or incrementing a timer's value, etc.) and to the KTimerAndWDTManager second virtual function, so that a timer's value can never be set to either a negative value or the past (which is what fasthax needed to do).
* The two functions that either add a [[KTimeableInterruptEvent]] instance to the global queue of pending [[KTimeableInterruptEvent]] (see [[KTimerAndWDTManager]]), or remove one from it, now return a boolean indicating whether the interrupt event already is/was in the queue (if that is true, the function that adds the interrupt event will now update the timer registers in that case as well). This is especially used for the below fixes.
* When adding a timer to that queue, its reference count is incremented (if it wasn't already in the queue). It is only decremented when needed, after actually signaling the timer by the interrupt-handling code.
* L_fff20d28(Prev ver @ L_fff20b40): Added a call to L_fff1bb74() before calling L_fff1d514(), in two locations.
* L_fff2131c(Prev ver @ L_fff21124): Same changes as L_fff20d28.
* L_fff26348(Prev ver @ L_fff2631c): Same changes as L_fff20d28 except with four locations.
* L_fff28058(Prev ver @ L_fff27e28): Same changes as L_fff20d28 except with just one location.
* A virtual method was added to the definition of abstract class [[KTimeableInterruptEvent]]. Prior to (re)adding KTimer instances as interrupt events (and some other objects) to the queue, objects of the queue with this method returning <code>false</code> are removed from it. Its implementations are the following:
** For [[KTimer]] instances, returns <code>static_cast<KAutoObject *>(this)->referenceCount != 1</code> (L_fff2c37c)
** For instances of [[KThread]] and the dummy subclass of KTimerAndWDTManager+0x10: returns <code>true</code> (L_fff26790).

===Modules===
No FIRM ARM11 sysmodule was changed.

====NS====
Only two constants were actually changed: the minimal value required for the kernel's minor version number (now 0x35, ie. 11.3 NFIRM, it used to be 0x23, ie. 5.0 NFIRM), and the version number used for [[FS:InitializeWithSdkVersion]].

====GSP====
GSP-module was updated for Old3DS+New3DS.

Exactly 4 functions were updated (11.3 N3DS addresses):

* L_102048, prev ver @ L_102048: Now writes 0 to LCD register 0x10202014 and ORs 0x1020200C with 0x10001.
* L_104CD0, prev ver @ L_104CD8: Code was added @ 0x104E6C(prev 0x104E78) for calling L_0x106C8C() when a certain field is non-zero.
* L_10B4F4, prev ver @ L_10B4A8: This is called by [[GSPGPU:AcquireRight]]. Code executed before successfully returning was moved into L_106058, this now calls that function before returning instead.
* L_10B7DC, prev ver @ L_L_10B800: This is [[GSPGPU:TryAcquireRight]]. Exact same changes as L_10B4F4.

Exactly 1 new function was added, L_106058:
* This function is just the code mentioned above that was moved into here, with some new code:
** val=0;
** [[SVC|svcGetProcessInfo]] with type19 is used with the handle from inr2.
** if(above_svc_succeeded){if((procinfo_outu32 & 0xF00) != 0x100)val=1;}//check for memregionid!=APPLICATION
** val is passed to the new [[SVC]] 0x59 as s8 r0.
** Lastly it will execute throw_fatalerr() on error.

====[[Friend_Services|Friends]]====
Exact same change as usual: only the byte for fpdver in exefs codebin was updated(changed from 8 to 9).

===[[Home Menu]]===
Exactly 1 function was updated, this fixed [[3DS_System_Flaws|bossbannerhax]](the last exploit used by [[menuhax]]). Code was added to verify that the common and {region/language}-specific [[Extended_Banner|exbanner]] sections don't have a decompressed size >{max_size}, when that happens it jumps over the func-call for doing the actual decompression.

===eShop system-application===
In RomFS, the message/ localization files and "/cad/Download.arc.lz" were updated.
Besides strings related to new localization messages, it appears the only new string in the exefs codebin is "integrated_account". Going by nearby strings this may be used with network requests.

diff --git a/v21506/US_English_tiger.msbt.lz.decom_wstrs b/v23552/US_English_tiger.msbt.lz.decom_wstrs
index 3c3938f..2890b25 100644
--- a/v21506/US_English_tiger.msbt.lz.decom_wstrs
+++ b/v23552/US_English_tiger.msbt.lz.decom_wstrs
@@ -766,6 +766,11 @@ Continue
Press
to return to
the HOME Menu.
+A receipt will be sent to the e-mail
+address registered to your Nintendo
+Account. If a child account is being
+used, the receipt will be sent to the
+parent or guardian's e-mail address.
Do you want to continue shopping?
Please read the information
on the upper screen.
@@ -783,6 +788,9 @@ more information.
You can view the code at any time
by checking the receipt within Account
Activity in the Settings / Other menu.
+The code will also be sent to the
+e-mail address registered to your
+Nintendo Account.
Transaction complete.
Generated Code(s)
A software update is available.

===mint eShop applet===
Seems to be about the same changes as eShop-app.

In the ExeFS codebin, besides message-related strings, multiple "integrated_account" strings were added + the following two strings: "privilege_infos" and "privilege_info".

The RomFS message/ files were updated.

diff --git a/v16384/US_English_mint.msbt.lz.decom_wstrs b/v18432/US_English_mint.msbt.lz.decom_wstrs
index 78a6c56..e32142a 100644
--- a/v16384/US_English_mint.msbt.lz.decom_wstrs
+++ b/v18432/US_English_mint.msbt.lz.decom_wstrs
@@ -163,6 +163,15 @@ For details, refer to the receipt for this
transaction via Account Activity in
Nintendo eShop.
Your download will commence shortly.
+A code has been issued to you.
+The code and information about its use
+will be sent to the e-mail address
+registered to your Nintendo Account.
+If a child account is being used, the
+receipt will be sent to the parent or
+guardian's e-mail address.
+Your download will be completed
+shortly.
Get All
Downloading Software
Software Download Complete
@@ -212,6 +221,10 @@ For purchase details, please check
Account Activity on Nintendo eShop.
You can view your receipt at any time within
Account Activity in the Settings / Other menu.
+Your receipt will be sent to the email address
+registered to your Nintendo Account. If a child
+account is being used, the receipt will be sent
+to the parent or guardian's email address.
Added:
Balance:
Credit-Card Funding

==New issue==
This update, even on systems not running modded-FIRM apparently, caused a slowdown in certain cases in some game(s). For example, with Sheikah Stones in "The Legend of Zelda: Ocarina of Time 3D", there's noticeable audio issues.

This was caused by the NATIVE_FIRM ARM11-kernel changes: when running v11.2 NATIVE_FIRM with v11.3-nandimage(with the required patches to get NATIVE_FIRM to run with v11.3-nandimage), this new issue doesn't occur.

==See Also==
System update report(s):
* [https://yls8.mtheall.com/ninupdates/reports.php?date=02-06-17_07-00-38&sys=ctr]
* [https://yls8.mtheall.com/ninupdates/reports.php?date=02-06-17_07-00-47&sys=ktr]

[[Category:Firmware Versions]]

11.2.0-35

2023-11-26T09:43:46Z

Emufan4568:

The Old3DS+New3DS 11.2.0-35 system update was released on October 24, 2016. This Old3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN. This New3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN.

Security flaws fixed: yes.

==Change-log==
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/667/p/430/c/267 Official] USA change-log:
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience

==System Titles==
===NATIVE_FIRM===
====Process9====
Actual code changed in Process9 .text. 2 functions were updated, and 1 new function was added which is called by the first function(see below).

The same function that was updated on [[11.0.0-33|11.0.0-33]] (to check minimum versions when installing titles) was updated again: the versions of the titles to install are now checked ''twice''. This is an attempt to fix a race condition.

====New3DS [[FIRM|arm9loader]]====
The arm9loader wasn't changed.

====ARM11-kernel====
3 functions were updated.

The first one is the actual handler function for svcWaitSynchronizationN.

After incrementing the counter with ldrex/strex, the last two functions now load the counter with plain ldr and executes kernelpanic() when it's zero.

====Modules====
The only updated FIRM module was loader.

=====loader=====
Only one function was updated, the same function involved with codebin-physmem-randomization as the previous updates.

All added titles:
* JPN/USA/EUR/CHN/TWN Paper Mario: Sticker Star
* JPN/USA/EUR Steel Diver: Sub Wars

When handling an APPLICATION memregion process and the uniqueID doesn't match any of the hard-coded ones, this then loads the [[NCCH/Extended_Header|exheader]] kernel release version. If loaded successfully, the codebin-physmem-randomization is automatically enabled if the version is >=0x234([[FIRM]] 2.52 for 11.2.0-35). Hence, all applications built for >=11.2.0-35 and have the kernel release version field will have codebin-physmem-randomization automatically enabled.

===friends-sysmodule===
Like past updates the only change was updating fdpver(changed from 7 to 8).

===mint===
Only updated for EUR. ExeFS .code and "romfs:/message/EU_Spanish/mint.msbt.lz" were updated.

===eShop===
The eShop system-application was only updated for EUR. ExeFS .code was updated, no change for RomFS.

==See Also==
System update report(s):
* [https://yls8.mtheall.com/ninupdates/reports.php?date=10-24-16_08-00-49&sys=ctr]
* [https://yls8.mtheall.com/ninupdates/reports.php?date=10-24-16_08-01-02&sys=ktr]

[[Category:Firmware Versions]]

11.0.0-33

2023-11-26T09:42:40Z

Emufan4568:

The Old3DS+New3DS 11.0.0-33 system update was released on May 9, 2016. This Old3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN. This New3DS update was released for the following regions: USA, EUR, JPN, CHN, and KOR.

Security flaws fixed: <fill this in manually later, see the updatedetails page from the ninupdates-report page(s) once available for now>.

==Change-log==
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/667/p/430/c/267 Official] USA change-log:
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience

==System Titles==
<fill this in (manually) later>

===NATIVE_FIRM===
The ARM9 FIRM section is larger.

The only updated FIRM sysmodules are loader and pm.

svcBackdoor has been removed (on ARM11).

====loader====
Exactly one function was updated: L_140022b8 (same addr as previous version).

The codebin physical-memory randomization code introduced with [[10.4.0-29]] was updated so that it's now used for OoT3D and Cubic Ninja (checked in the same aforementioned order), for the USA+EUR+JPN titles. This means oot3dhax and ninjhax need to be updated to handle this. Using the pre-sysupdate exploit versions will result in the title randomly crashing. However, if you retry enough times, it should run fine.

====pm====
Two functions were updated for calling a new function for exheader handling.

This new function at L_101cfc immediately returns when the input programID isn't a CTR title / Cubic Ninja (USA/EUR/JPN uniqueID). This function removes all services in the exheader service-access-control which match services from a blacklist stored in pm-module. This blacklist contains two services: "http:C" and "soc:U".

This breaks QR-code ninjhax with the version available at the time of sysupdate release, since the QR-code build downloads the payload via HTTPC.

====ARM11-kernel====
57 functions were updated, 47 of these are the actual functions used for handling SVCs (see below). The lone function updated with v10.4 was updated with this version again: Checks were added to make sure all the previously allocated memchunks are actually located within the requested memory region. This was implemented with the following checks which are done for each memchunk separately - right before clearing and mapping each one to the requested vaddr.
if((region_base > memchunk_addr) || ((region_base + region_size) < (memchunk_addr + memchunk_size<<12))) { kernel_panic(); }
The actual ToCToU race has not been fixed (see [[3DS System Flaws|memchunkhax2.1]]).

3 new functions used for validation with memory management were added (kernelpanic() on failure). This is a new security feature for the kernel heaps. By adding a MAC to the kernel heap [[Memory Management#MemoryBlockHeader|memchunkhdr]] they can detect when it is modified by an outside DMA device ([[3DS System Flaws|gspwn]]).

The MAC itself is custom based on xor-rot-sub-mul, and is calculated as follows (pseudo-code):

u32* crypto_state = (u32*) r4; // Safe kernel memory. This is actually the [[Memory Management#RegionDescriptor|RegionDescriptor]].
u32* data_ptr = (u32*) lr; // Unsafe FCRAM pointer.

r0 = crypto_state[16/4] // Load "key".
r1 = crypto_state[20/4]
r2 = crypto_state[28/4]
r3 = crypto_state[24/4]

for(size_t i=0; i<2; i++) {
for(size_t j=0; j<5; j++) {
r0 -= (r1 >>> 3) - data_ptr[j]
r1 -= (r3 >>> ((r2 & 0xf) + 3)) ^ (r2 >>> ((r0 & 0xf) + 13))
r3 -= (r2 >>> r0) * r1
r2 -= (r0 >>> r1) * r3
}
}

// Verify MAC.
if(data_ptr[5] != (r0 ^ r1)) {
kernel_panic()
}

The function which initializes a memalloc heap had a major update (used for FCRAM memregions and the SlabHeap container). It generates a random MAC key based on svcGetSystemTick, like this:

crypto_state[16/4] = 0 //This is actually the [[Memory Management#RegionDescriptor|RegionDescriptor]].
crypto_state[20/4] = 0
crypto_state[24/4] = 0
crypto_state[28/4] = 0

u32* key = &crypto_state[16/4];

for(size_t i=0; i<0x40; i++) {
for(size_t j=0; j<4; j++) {
r0 = key[j] - GetSystemTick()
key[j] = r0 ^ ((r0 >>> 7) - (key[(i+j) % 4] >>> 17))
}
}

However, it's unknown how much the svcGetSystemTick() output really varies if anything(?) for each hard-boot during initialization of the heaps.

6 memory management functions were updated to use the above new functions, these func-calls replaced the validation code previously used in these functions in some cases. These were also updated for the above heap security implementation. One function had a validation func-call added where previously there wasn't any validation done in the beginning of the function for previous versions.

Another function(L_fff13b68 previously at L_fff13b68) was updated for offsets it uses, nothing else.

The function handling the arm11kernel exheader descriptors was updated, if anything changed besides the kernel-version value it seems minor.

The first 47 updated functions are used for the actual SVC handling. It seems each change just added code at the start of the function for initializing the output data. This includes SVCs which were already stubbed. All of the updated SVCs for this, in the same order as the arm11kernel code binary:
{| class="wikitable" border="1"
|-
! SVC
! Additional changes if any
|-
| svcCreatePort
| None
|-
| svcOpenThread
| None
|-
| svcCreateEvent
| None
|-
| svcCreateMutex
| None
|-
| svcCreateTimer
| None
|-
| svcGetThreadId
| None
|-
| svcRandomStub (SVC 0x74)
| None
|-
| svcOpenProcess
| None
|-
| svcQueryMemory
| None
|-
| svcCreateThread
| None
|-
| svcGetProcessId
| None
|-
| svcAcceptSession
| None
|-
| svcConnectToPort
| None
|-
| svcControlMemory
| None
|-
| svcCreateCodeSet (SVC 0x73)
| None
|-
| svcCreateProcess (SVC 0x75)
| None
|-
| svcCreateSession
| None
|-
| svcGetHandleInfo
| The code which clears the variables that get written into the output 8-byte buffer, was moved to before the code which checks the input type value (previously this was only executed for type 0x32107).
|-
| svcGetSystemInfo
| None
|-
| svcGetThreadInfo
| None
|-
| svcGetThreadList
| None
|-
| svcSignalAndWait
| None
|-
| svcGetProcessInfo
| None
|-
| svcGetProcessList
| None
|-
| svcCreateSemaphore
| None
|-
| svcDuplicateHandle
| None
|-
| svcReplyAndReceive
| None
|-
| svcGetResourceLimit
| None
|-
| svcReleaseSemaphore
| None
|-
| svcReplyAndReceive1
| None
|-
| svcReplyAndReceive2
| None
|-
| svcReplyAndReceive3
| None
|-
| svcReplyAndReceive4
| None
|-
| svcCreateMemoryBlock
| None
|-
| svcGetThreadPriority
| None
|-
| svcDebugActiveProcess
| None
|-
| svcQueryProcessMemory
| None
|-
| svcCreateResourceLimit
| None
|-
| svcCreateSessionToPort
| None
|-
| svcCreateAddressArbiter
| None
|-
| svcGetProcessIdOfThread
| None
|-
| svcWaitSynchronizationN
| None
|-
| svcGetThreadIdealProcessor
| None
|-
| svcQueryDebugProcessMemory
| None
|-
| svcGetProcessIdealProcessor
| None
|-
| svcControlPerformanceCounter
| None
|-
| svcStartInterProcessDma
| None
|}

====Process9====
Various data was moved around in the .data section (.data is 0x99C-bytes smaller than before).

The only actual change in .text was that only one function was updated. This function is only called by [[AMPXI:InstallTitlesFinish]] and [[AMPXI:InstallTitlesFinishFIRM]]. Right after the mediatype validation at the very beginning of the function, a code block was added for the functionality described below which is only executed on [[CONFIG_Registers#CFG_UNITINFO|retail]].

This AMPXI function will now check the high 6-bits of the title-version(major-version) of the title to finish-install against a hard-coded list of (titleID, minimumVersionRequired) pairs. This list is identical for Old3DS/New3DS Process9. This applies to MSET, Home Menu, spider, ErrDisp, SKATER, NATIVE_FIRM, and every retail system module. When the title-version is invalid, this returns the invalid title-version error(0xD8E08027).

This prevents downgrading on the ARM11 side via AM-service access.

====New3DS====
The arm9loader wasn't changed at all.

Nothing New3DS-only changed in Process9.

===friends-sysmodule===
Only the value used for fpdver changed in the codebin, from 5 to 6. This is not required server-side yet, last checked on May 11, 2016.

===IR-sysmodule===
Exactly two functions were updated with the same changes: L_1053b0 and L_10547c.

When the input value is zero, this now requires bitmask 0x2 to be clear in a certain state field before passing a ptr to a function, instead of 0x0.

===0004001B00010802===
The 1-byte content of "romfs:/dummy.txt" was changed from '2' to '3'.

==See Also==
System update report(s):
* [https://yls8.mtheall.com/ninupdates/reports.php?date=05-09-16_08-00-49&sys=ctr]
* [https://yls8.mtheall.com/ninupdates/reports.php?date=05-09-16_08-00-58&sys=ktr]

[[Category:Firmware Versions]]

10.4.0-29

2023-11-26T09:41:22Z

Emufan4568:

The Old3DS+New3DS 10.4.0-29 system update was released on January 18, 2016. This Old3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN. This New3DS update was released for the following regions: USA, EUR, JPN, CHN, and KOR.

Security flaws fixed: yes, see below.

Old3DS/New3DS browserhax and menuhax were not fixed(the Old3DS browser wasn't even updated).

==Change-log==
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/667/p/430/c/267 Official] USA change-log:
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience

==System Titles==

===NATIVE_FIRM===
[[3DS_System_Flaws#Kernel11|memchunkhax2]] was partially fixed by reading the [[MemoryBlockHeader]] next pointer before it is mapped to userland, but it can still be exploited using GPU. Only ''one'' function was changed in arm11kernel.

The only updated FIRM sysmodules were fs and loader, for fs only a version-field in .code was updated used with a debug NOP-instruction.

====loader====
The loader process .text was previously 0x331C-bytes, it's now 0x36F0-bytes.

All code changes:
* Some code using svcGetSystemTick was added. This is used by L_14002670.
* L_140022b8(L_14002234 in previous loader version): This is the function which calls L_140025f0. Code was added between the code which loads the memregion value from exheader, and the func call for mapping it(L_140025f0). This new code determines what to pass for the L_140025f0 insp4 flag. By default the value passed for that flag is 0.
** When the process memregion is APPLICATION, the programID is for a CTR title, and the uniqueid matches the eShop system-application(''all'' regions including CHN), the flag is set to 1.
** When the process memregion is SYSTEM, the flag is set to 1 when the reslimit_category is not LIB_APPLET.
* L_140025f0(L_140024e4 in previous loader version) now calls another function(L_14002670) instead of svcControlMemory directly, for mapping the codebin memory. The insp4 flag from the L_140025f0 input is passed to L_14002670 as sp0.
* L_14002670: New function used for mapping the codebin. When the insp0 flag is zero, this does the normal memory-mapping, otherwise a special memory-mapping codepath is used. This codepath still uses the same memregion specified in the exheader.

The special memory-mapping codepath is basically a method of mapping the codebin with svcControlMemory using up to 8 chunks, each with a random size. Each chunk is done in a random order. Since the allocation order is random, this also means the order of each .text chunk in physmem is random too. When the total size of the randomized page-count is less than the required amount, an 8th chunk is used to pad the total size to the exact required size. It appears the total combined size used with svcControlMemory is ''always'' exactly the same as what's required for the codebin.

Regarding chunk size calculation:
* s32 maxval = (codebin_totalrequiredpages - pagepos) >> 4;
* The above maxval field is set to 15 if it's >=15.
* pagecount = L_14001730(maxval);
* pagecount = (pagecount+1) << 4;
* chunksize = pagecount << 12;

This is an attempt at randomizing the layout of physmem .text, due to gspwn.

====ARM9====
There were no New3DS-only changes in Process9, the arm9loader wasn't changed either.

There were exactly 4 updated functions in Process9, all of these involve NTRCARD:
* The first two functions had code added which clears a certain state field to 0 around the beginning of the function.
* The third function now passes value 0x1000 as inr2 when calling the fourth function.
* The fourth and last function, this is the function used for reading the card header. A buffer-overflow check was added in the NTRCARD reading loop: "if(out_bufpos >= inr2)<skip over copying the word to output>".

===NS===
NS added [[APT:IsTitleAllowed|a new APT command]] used by Home Menu which now checks whether IronFall is on the latest version before launching; if it is on an exploitable version and the function is called to launch IronFall the system will refuse to launch the title(it's unknown what exactly caused a "reboot" here). This check is done again before launching the title, throwing an error if it fails.

All [[NS]] code changes:
* L_103e6c(prev ver at L_103e6c): APT cmd-handler, this was updated for the command mentioned above.
* L_1086f4: New function, this is called by the above cmd-handler. This basically just calls L_10b1cc.
* L_10b1cc: New function, this is the actual [[APT:IsTitleAllowed]] implementation. Returns 0 for blocked, 1 for allowed.
** The beginning of this function is the same as L_10d598, without the u16 check right away.
** This initializes amu, then uses [[AM:GetTitleInfo]] with the input programID(mediatype is hard-coded to SD). If the latter returns an error, this will exit with retval0.
** If u16 entry+4 is < (titleversion>>10), this then exits with retval1.
** Then the AM:GetTitleInfo + versioncheck code is repeated using the update-data title.
** This lastly exits, with retval1 if the update-data titlever is newer than the entry one.
* L_10d598: New function, only called by L_10df40. This is the internal-NS-only version of the [[APT:IsTitleAllowed]] code. Returns 0 for blocked, 1 for allowed.
** This immediately returns 1 when the mediatype isn't SD, or when the title isn't a CTR title.
** Then it loads the uniqueid from the input struct, for determining which entry to use from a table in .rodata. The uniqueid is compared with hard-coded constants in the function code itself, even though the table contains the uniqueids too. The code looks like: "if(uniqueid == constant0) {entryptr = addr0} else if ...". When no entry is found, this immediately returns 1.
** Lastly, if input_version_value is <= u16 entry+4, this returns 0, otherwise 1 is returned.
* L_10df40(prev ver at L_10ddd4): This appears to be the main function used by NS for launching titles in general(minus [[NSS:LaunchTitle]] used by the *hax payloads). Code was added for calling L_10d598() in two locations. The version value passed to L_10d598 here is the title NCCH remaster-version. When that function returns <blocked>, this code returns error 0xC8A0CC04.

See [[APT:IsTitleAllowed|here]] regarding the contents of that table.

===Home Menu===
The code changes for Home Menu appear to be just title/AM related / GUI.

Code was implemented for using [[APT:IsTitleAllowed]] mentioned above. This is only done after VersionList handling(for example when one tries to launch the app without updating), prior to doing the actual application launch. When that returns 0, Home Menu will display a message using the following text from new message-strings:
You need to update this
software before you can
launch it.

===SpotPass sysmodule===
Only one function was changed in the [[BOSS_Services|BOSS]]/SpotPass sysmodule, the changes in this function seem to be minor.

===Internet Browser===
Only the New3DS Internet Browser was updated, see [[Internet_Browser|here]] for that.

===eShop system-application===
Some ratings-related strings were added to the main codebin("ratPEGI_U_02" and "detailPEGI_D_01").

The message files were updated:
diff --git a/v19465/tiger.msbt.lz.decom.wstrs b/v20482/tiger.msbt.lz.decom.wstrs
index 2a3a24e..55358d0 100644
--- a/v19465/tiger.msbt.lz.decom.wstrs
+++ b/v20482/tiger.msbt.lz.decom.wstrs
@@ -258,6 +258,7 @@ Charts
Search Results:
Price: TBD
Offers in-game purchases
+Video
This software is currently unavailable.
Page
Go to Page

===mint===
Only the main codebin was updated, nothing changed with strings in that codebin(besides a string containing a version which gets updated for each mint update).

===0004009B00012302===
The USA 0004009B00012302 CFA(and the equivalent titleIDs for the other regions) was updated, the following message was added to 20000_msbt_LZ.bin:
An error has occurred.
Please check if there is corrupted data
in Data Management
Nintendo 3DS
in the System Settings.
If the problem persists, please
make a note of the error code
and visit support.nintendo.com.

==See Also==
System update report(s):
* [http://yls8.mtheall.com/ninupdates/reports.php?date=01-18-16_07-00-49&sys=ctr]
* [http://yls8.mtheall.com/ninupdates/reports.php?date=01-18-16_07-00-58&sys=ktr]

[[Category:Firmware Versions]]

10.2.0-28

2023-11-26T09:40:21Z

Emufan4568:

The Old3DS+New3DS 10.2.0-28 system update was released on October 19, 2015. This Old3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN. This New3DS update was released for the following regions: USA, EUR, JPN, and KOR.

Security flaws fixed: see below.

==Change-log==
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/667/p/430/c/267 Official] USA change-log:
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience

==System Titles==

The following titles were updated: [[Home Menu]], [[CVer]], Old3DS+New3DS NATIVE_FIRM, Old3DS+New3DS [[Internet Browser]], and [[NVer]].

===NATIVE_FIRM===
The only FIRM sysmodule that was really updated is the following, minus a single word in the FS-module codebin.
* pm was updated. [[PMApp:LaunchTitle]] now executes svcBreak() when trying to launch safe-mode sysmodule/applet titles.

For Old3DS, the FIRM arm9-section wasn't changed at all: same FIRM section hash from the previous version. Nothing was really changed in the New3DS arm9-section either.

No code in the ARM11-kernel was changed(the binary is *exactly* the same minus two words involved with configmem version fields init).

===Home Menu===
Only the codebin was changed. The size of .text only increased by 0x18-bytes.

Only one function was updated: the theme-loading function. The changes in this code block the latest version of [[menuhax]] at the time of sysupdate release. See [[3DS_Userland_Flaws|here]] for details.

===Internet Browser===
See [[Internet Browser|here]] for details, vuln fixing included.

==See Also==
System update report(s):
* [http://yls8.mtheall.com/ninupdates/reports.php?date=10-19-15_08-05-19&sys=ctr]
* [http://yls8.mtheall.com/ninupdates/reports.php?date=10-19-15_08-05-28&sys=ktr]

[[Category:Firmware Versions]]

10.0.0-27

2023-11-26T09:40:06Z

Emufan4568:

The Old3DS+New3DS 10.0.0-27 system update was released on September 8, 2015. This Old3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN. This New3DS update was released for the following regions: USA, EUR, JPN, CHN, and KOR.

Security flaws fixed: yes, see the ARM11-kernel section [[3DS_System_Flaws|here]].

==Change-log==
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/667/p/430/c/267 Official] USA change-log:
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience

==System Titles==
<fill this in (manually) later>

=== [[FIRM|NATIVE_FIRM]] ===
Minus configmem init, exactly 4 functions were updated in the ARM11-kernel(at least one was for fixing a security issue). See [[3DS_System_Flaws|here]] for details on that.

Only the following FIRM ARM11 modules were updated with the codebin:
* FS module was updated.
* Loader module was updated, the only change was that the version value passed to [[FS:InitializeWithSdkVersion]] was changed from 0x0b0201c8 to 0x0b0400c8.

=== Process9 ===
One of the changes was that main() was updated. Three functions(two initialization functions + launch_firm()) which were previously called directly are now called via a wrapper function with a funcptr parameter. As a result, the main() prologue/epilog changed. This is for temporarily relocating the stack elsewhere(same relocated-stack-addr for all func-calls), just for calling the funcptr(all registers except for r0..r3 are saved/restored before/after calling the funcptr).

Some FS-related code seems to have been changed.

There's also some new UTF-16 strings in the .(ro)data, but there's no(?) known code which actually uses these.

==== New3DS-only ====
No actual code/data was changed in the arm9loader.

During loading, kernel9 copies the entire Process9 NCCH to a relocated base-addr, which is: endaddr - ncchsize. On Old3DS, endaddr is 0x080fffe0. On New3DS, endaddr was 0x080fffe0 prior to v10.0-FIRM, now it's 0x0817ffe0.

The Process9 .bss(which contains the proc9 heaps too) is larger now: previously the .bss ended at address 0x080ff080, now it ends at 0x08117040.

Therefore, *all* of the extended New3DS-only arm9mem gets overwritten during FIRM boot with v10.0.

There were no New3DS-only Process9 code changes.

==See Also==
System update report(s):
* [http://yls8.mtheall.com/ninupdates/reports.php?date=09-08-15_09-34-44&sys=ctr]
* [http://yls8.mtheall.com/ninupdates/reports.php?date=09-08-15_09-34-53&sys=ktr]

[[Category:Firmware Versions]]

9.6.0-24

2023-11-26T09:39:42Z

Emufan4568:

The 9.6.0-24 system update was released on March 23, 2015.

== Change-log ==
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/231 Official] change-log:
* A Home Menu Layout setting has been added to HOME Menu Settings. Users can save and load up to 8 layouts of the HOME Menu with different theme and software icon arrangements
* Additional categories have been added to the Theme Shop under “View More” for easier navigation
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience

* Nintendo 3DS, Nintendo 3DS XL, and Nintendo 2DS Systems Only:
** amiibo Settings has been added to HOME Menu Settings. amiibo Settings allows users to register an amiibo owner and nickname, delete data written to an amiibo by supported software, or reset an amiibo*
**This feature will require a peripheral device scheduled to launch in 2015

==System Titles==
All updated New3DS-only titles except for [[NVer]] and NATIVE_FIRM were switched to the new NCCH crypto.

The following system applications were updated: System Settings, eShop, and System Transfer.

The New3DS-only placeholder menu system-application was updated(still a stub).

The following system applets were updated: Home Menu, error applet, mint, Miiverse applet, amiibo Settings, and the New3DS [[Internet Browser]].

The following system-modules were updated: Config, GSP(Old3DS/New3DS), PTM(Old3DS/New3DS), Download Play, HTTP, NIM, SSL, IR, NS, act, and NFC(Old3DS/New3DS).

The following CFAs were updated: 0004009B00010402, 0004009B00012302(and the equivalent non-USA-region titles), NGWord bad word list, Nintendo Zone hotspot list, [[NVer]](Old3DS/New3DS), [[CVer]], and 0004001B00018002. [[CVer]] had a [[CVer|new]] file added to RomFS.

The Old3DS [[Fangate_updater]] title was updated.

Old3DS/New3DS NATIVE_FIRM was updated.

Many other titles were updated/added for only KOR-region.

===New3DS NATIVE_FIRM===
====arm9loader====
The arm9loader was updated.

Old version of firm generated and initialized keyX for keyslots 0x15, 0x16, 0x18-0x1F. This version keeps the old algorithm for keyslots 0x11, 0x15, 0x18.

For keyslots 0x16, 0x19-0x1F it uses a new key for keyslot 0x11, but the actual algorithm has not been changed. This time the keyslot 0x11 seed is loaded from (nand_sector96+0x10) instead of (nand_sector96+0). They also changed the initialization vector for the 0x19-0x1F key-generation to a new hardcoded key.

Since we don't know the decrypted value at (nand_sector96+0x10), we don't know the new key for keyslot 0x11, and we cannot generate keys for the updated keyslots 0x16, 0x19-0x1F. Thus they plugged their hole and we can no longer decrypt arm9-binary without an arm9 code-execution exploit compatible with 9.6.0-X or <tricks where some of these *require* nand-modding>.

On panic, arm9loader now clears keyslots 0x15, 0x16, 0x18, 0x19, 0x19-0x1F. Previous versions only cleared 0-7, 0x15, 0x16.

====Process9====
The only actual code change for New3DS-only Process9 was that support for a new [[NCCH]] crypto flag 0xB was added.

===NATIVE_FIRM===
The ARM11-kernel and Process9 were updated. All of the ARM11-modules were updated, FS-module had the most changes among these modules.

The following is all of the changes for the (Old3DS) ARM11-kernel:
* 4 functions all with the same following changes were updated, one of these functions is called by [[SVC|svcWaitSynchronization1]]. Code was added which checks whether a certain s64 variable is <=0, when it is the variable value is set to 0x7FFFFFFFFFFFFFFF.
* The only other updated function appears to be memory related?

==See Also==
System update reports:
* [http://yls8.mtheall.com/ninupdates/reports.php?date=03-23-15_08-05-03&sys=ctr]
* [http://yls8.mtheall.com/ninupdates/reports.php?date=03-23-15_08-05-13&sys=ktr]

[[Category:Firmware Versions]]

9.5.0-22

2023-11-26T09:39:27Z

Emufan4568:

The 9.5.0-22 system update was released on February 2, 2015.

== Change-log ==
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/231 Official] change-log:
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience.

== System Titles ==
The following titles were updated: [[eShop]], [[Home Menu]], [[CVer]], and Old3DS/New3DS [[NVer]].

The GPIO system-module and the [[NFC_Services|NFC]] New3DS system-module were updated.

Old3DS/New3DS NATIVE_FIRM was updated. None of the Old3DS/New3DS system-titles updated with 9.5.0-22 actually require this NATIVE_FIRM.

===[[Home Menu]]===
These changes are minor, this includes removal of some throw_fatalerr() func calls.

===GPIO system-module===
These changes are minor. Code was added to the function handling GPIO service command 0x000A0042, for closing the input handle when an error occurs in this function.

===NATIVE_FIRM===
In Old3DS/New3DS Process9 only *one* u32 was changed: the address of the FIRM header used during FIRM launch. This fixes [[3DS_System_Flaws#FIRM_Process9|firmlaunch-hax]].

There was no actual code changes in the ARM11 kernel.

===New3DS NATIVE_FIRM===
The ARM9-loader has added a new keyX with keyslot 0x16 that is generated on hard-boot. The ARM9 binary is now encrypted with this keyslot, instead of the [[FIRM|original]] one.

This new crypto is rather useless due to Nintendo failing yet again. The [[3DS_System_Flaws|flaws]] which allowed for this were fixed with 9.5.0-X.

=See Also=
System update reports:
* [http://yls8.mtheall.com/ninupdates/reports.php?date=02-02-15_07-05-07&sys=ctr]
* [http://yls8.mtheall.com/ninupdates/reports.php?date=02-02-15_07-17-33&sys=ctr]
* [http://yls8.mtheall.com/ninupdates/reports.php?date=02-02-15_07-38-28&sys=ctr]
* [http://yls8.mtheall.com/ninupdates/reports.php?date=02-02-15_07-55-18&sys=ctr]

[[Category:Firmware Versions]]

9.3.0-21

2023-11-26T09:39:04Z

Emufan4568:

The 9.3.0-21 system update was released on December 8, 2014.

== Change-log ==
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/231 Official] change-log:

Changes to the HOME Menu:
* A Shuffle Favorites feature has been added under Change Theme in HOME Menu Settings. Users can choose multiple themes and have their theme change when the system is left in Sleep Mode from the HOME Menu or turned on after being off
* Available software updates can now be downloaded from the HOME Menu
* Users can now capture screenshots with both the upper and lower screens included
Improvements to system stability and usability:
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience

Japanese New3DS-exclusive change log:
* Added support for various Japanese NFC wallets
* Added "amiibo Settings" in HOME Menu
* It is possible to delete the data which registered the owner and nickname of amiibo, written to amiibo.

== System Titles ==

The following new titles were added: [[Fangate_updater]], Old3DS NFC system-module, and the amiibo Settings system-applet.

The following applications were updated: [[eShop]] and Nintendo Network ID Settings.

The placeholder New3DS "menu" application was updated for all regions, this is still stubbed. Likewise for the USA placeholder "friend" application. The JPN [[New_3DS]] [[Health and Safety Information]] application was updated.

The following applets were updated: [[Home Menu]], Miiverse, memolib, appletEd, PNOTE_AP, and mint.

The New3DS [[Internet Browser]] was updated for all regions.

[[CVer]], [[NVer]], and New3DS NVer were updated. The bad-word list and the NZone hotspot list were updated.

0004009B00012302 + equivalent titleIDs for other regions and 0004001B00018002 were updated.

The following system-modules were updated: Cfg, HID, AC, NIM, IR, RO, NS, act, camera(Old3DS), GSP(Old3DS), and i2c(Old3DS).

The following New3DS system-modules were updated: camera, GSP, i2c, nfc, and qtm.

Old3DS and New3DS NATIVE_FIRM were updated.

=Details=
Multiple [[3DS_System_Flaws|system flaws]] were fixed, this includes a later-stage [[3DS_System_Flaws|system flaw]](separate from anything listed in the below NATIVE_FIRM section) used in [[Ninjhax]]. Ninjhax was not completely blocked.

Support for amiibo was added. Support for the Old3DS NFC peripheral(which communicates with 3DS via IR) was added.

All updated New3DS titles now use New3DS-specific NCCH crypto, see [[NCCH|here]].

==NATIVE_FIRM==
Most of the ARM11 kernel changes were to fix an ARM11 kernel [[3DS_System_Flaws|flaw]].

All ARM9 kernel changes:
* The ARM9 kernel equivalent of the above code involved with the above ARM11 kernel flaw was updated, the changes for that are exactly the same.
* An unknown kernel function was updated, this function seems to be ARM9-kernel specific.

All Process9 changes:
* The code for validating the [[NCCH/Extended_Header|exheader]] was updated: the total number of service-access-control entries this uses was changed from 0x20 to 0x22, and the valid range for "ARM9 Descriptor Version" was changed.
* Keytype value 0x9 support was added to [[PSPXI:EncryptDecryptAes]].
* The New3DS-only commands for [[Process_Services_PXI]] were removed, the code/data for those were moved into [[NFC_Services|NFC]] module.
* Support for New3DS-only [[NCCH]] encryption was added.
* Support for gamecard savedata encryption using New3DS-only keyslots was added, see [[NCSD|here]].

=See Also=
System update reports:
* [http://yls8.mtheall.com/ninupdates/reports.php?date=12-08-14_07-05-03&sys=ctr]
* [http://yls8.mtheall.com/ninupdates/reports.php?date=12-08-14_07-15-03&sys=ctr]
* [http://yls8.mtheall.com/ninupdates/reports.php?date=12-08-14_07-25-04&sys=ctr]
* [http://yls8.mtheall.com/ninupdates/reports.php?date=12-08-14_07-35-04&sys=ctr]
* [http://yls8.mtheall.com/ninupdates/reports.php?date=12-08-14_07-45-04&sys=ctr]

[[Category:Firmware Versions]]

9.0.0-20

2023-11-26T09:38:28Z

Emufan4568:

The 9.0.0-20 system update was released on October 6, 2014.

== Change-log ==
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/231 Official] change-log:
* Users can now use themes to customize the design and sounds of the HOME Menu
* Five themes are pre-installed and additional themes can be purchased from the Theme Shop
* Themes can be changed by using settings located within the HOME Menu settings
* A feature has been added that allows users to capture screenshots of their HOME Menu
* The Nintendo eShop Title Information page has been updated to provide easier access to any available videos, demos, user reviews, and other information
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience

See [[Home_Menu/Themes|here]] regarding themes.

== System Titles ==
=== 3DS ===
The following system-modules were updated: AM, camera, cfg, codec, gsp, hid, ac, [[StreetPass|cecd]], CSND, dlp, http, ndm, NIM, NWM, SOC, SSL, PS, friends, IR, [[SpotPass|BOSS]], news(notifications), RO, NS, and act. For at least some of these modules(including NWM), this was just a rebuild with the latest CTRSDK(only change in .code was the CTRSDK version value(s) used with [[ErrDisp]]).

The following applications were updated: System Settings, Download Play, Nintendo 3DS Camera, eShop, System Transfer, and NNID settings.

The following "applets" were updated: [[ErrDisp]], Home Menu, camera, Instruction Manual, Game Notes, Friend List, Notifications, error, Software Keyboard, appletEd, PNOTE_AP, SNOTE_AP, extrapad, mint, Miiverse, and Miiverse memolib.

An applet with TID-low 00008B02 was [[Title_list|added]], "solv3". The description from the ExeFS icon is "Post to Miiverse".

The following titles were also updated: 0004009B00012302, EULA CFA, NGWord bad word list CFA, [[Nintendo Zone]] hotspot list CFA, [[NVer]], [[CVer]], 0004001B00018002, 0004001B00018102, and 0004001B00018202.

[[NS_CFA]] was updated, the following new file was added to the RomFS: "qtm_black_list".

==== Old3DS FIRM ====
NATIVE_FIRM was also updated.

The Process9 FIRM-launch code now "clears" certain [[AES_Registers|AES]] keyslots, see [[AES_Registers|here]].

==== Application crashes ====
Starting with 9.0.0-20 on retail, the system may now triggers a [[ErrDisp|fatal-error]] when an application crashes(this is the error-code fatal-error). At the time of writing this does not apply to New3DS.

This error(0xd8c3fbf3) is caused by Home Menu failing to allocate LINEAR-memory.

=== New3DS ===
This update added the system-titles for New3DS to SOAP, for the following regions: USA, EUR, and JPN. See [[8.1.0-0_New3DS|here]] for the launch-day JPN New3DS system-version.

Most of the New3DS titles listed from SOAP here are from the launch-day system-version [[8.1.0-0_New3DS|available]] on CDN. Some of the actual New3DS-specific changes with 9.0.0-20, is that the following New3DS titles were updated: [[FIRM|NATIVE_FIRM]] and [[NVer]]. The latest version of both of these titles have the same HTTP Last-modified date as the [[8.1.0-0_New3DS]].

The New3DS version of the [[Internet Browser]] was added, the exheader name is "SKATER"(original 3DS name was "spider").

The following New3DS-only system applications were updated: [[microSD Management]], "menu" placeholder application, and the "cherry" placeholder application.

This update also added the newly updated System-Transfer application(not New3DS specific) to New3DS. This title is not installed with [[8.1.0-0_New3DS]].

The following New3DS-specific system modules were updated: Camera, nfc, mvd, and qtm.

See [[Title_list]] for the rest of the titles which got updated on New3DS with 9.0.0-20(note that [[8.1.0-0_New3DS]] has certain 9.0.0-20 titles pre-installed).

=See Also=
System update reports:
* [http://yls8.mtheall.com/ninupdates/reports.php?date=10-06-14_08-05-03&sys=ctr]
* [http://yls8.mtheall.com/ninupdates/reports.php?date=10-06-14_08-15-03&sys=ctr]
* [http://yls8.mtheall.com/ninupdates/reports.php?date=10-06-14_08-25-03&sys=ctr]
* [http://yls8.mtheall.com/ninupdates/reports.php?date=10-06-14_08-35-12&sys=ctr]

[[Category:Firmware Versions]]

8.1.0-0 New3DS

2023-11-26T09:37:58Z

Emufan4568:

This is the system-version that ships with launch-day JPN [[New_3DS]] systems. The TMD HTTP Last-modified date for these titles is September 26, 2014.

Most of the system titles which are not New3DS specific, are from [[8.1.0-18]]. When a New3DS version of a system-title is available, only the New3DS title is installed, the Old3DS version is not installed.

This launch system-version has title-versions specific to this launch system-version, for titles which aren't New3DS specific(and also titles from [[9.0.0-20]]): [[CVer]], 0004001B00018202, 0004001B00018102(same title-version as [[9.0.0-20]]), [[NS CFA]](same title-version as [[9.0.0-20]]), [[Nintendo 3DS Camera]](same title-version as [[9.0.0-20]]), [[Download Play]](same title-version as [[9.0.0-20]]), [[Download Play]](same title-version as [[9.0.0-20]]), [[System Settings]], [[ErrDisp]](same title-version as [[9.0.0-20]]), [[Home Menu]], Camera applet(same title-version as [[9.0.0-20]]), Instruction Manual applet(same title-version as [[9.0.0-20]]), Game Notes applet(same title-version as [[9.0.0-20]]), Friend List applet(same title-version as [[9.0.0-20]]), Notifications applet, Miiverse applet(same title-version as [[9.0.0-20]]), Software Keyboard applet(same title-version as [[9.0.0-20]]), appletEd(same title-version as [[9.0.0-20]]), PNOTE_AP, SNOTE_AP,(same title-version as [[9.0.0-20]]), mint, extrapad, memolib, and error applet.

See [[Title_list]] for the full 8.1.0-0_New3DS title-listing, for titles which aren't New3DS-specific.

The system-transfer application is not installed with this system-version.

=== New3DS System Titles ===
New3DS versions of the SAFE_MODE system-modules were added, the only New3DS SAFE_MODE system-modules which were not added are: camera, [[StreetPass|cecd]], MP, and NDM.

Besides the 3 new modules below, New3DS versions of the following native system-modules were added: camera, GSP, i2c, MCU, PTM, and spi.

The following 3 new sysmodules were added(not available for SAFE_MODE):
* [[NFC_Services|NFC]] -- talking to NFC hardware (over I2C).
* [[MVD_Services|MVD]]
* [[QTM_Services|QTM]] -- camera headtracking? (over I2C).

5 new applications for New3DS-only were added. See [[Title_list|here]] regarding the new applications. Besides those applications, New3DS versions of the following applications were added: "Health and Safety Information" and Face Raiders.

The New3DS versions of the following SAFE_MODE applets were added: [[ErrDisp]], error, and swkbd(Software Keyboard).

A New3DS version of [[NVer]] was added. Therefore, there could be future New3DS-only system-updates.

Note that the New3DS Internet Browser is not available on this system-version(spider and SKATER titles are not installed), it was added with [[9.0.0-20|this]]. Trying to launch the browser results in the system going to the system-update section under [[System Settings]].

==== FIRM ====
New3DS versions of all 4 [[FIRM]] titles were added.

New3DS FIRM uses an additional crypto layer on the ARM9 FIRM section via a loader at the end of the ARM9 binary, see [[FIRM|here]].

[[Category:Firmware Versions]]

8.0.0-18

2023-11-26T09:37:29Z

Emufan4568:

The 8.0.0-18 system update was released on July 7, 2014.

== Change-log ==
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/231 Official] change-log:

* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience.

== System Titles ==
eShop, [[NVer]], [[CVer]], and the [[Nintendo_Zone|NZone]] hotspots list were updated. The "masterkey.bin" [[CVer|file]] in the CVer RomFS was updated(different u32 value at offset 0x0 and different random data). The "cup_list" file was removed from the CVer RomFS as well.

The 0004009B00012302 USA title(and the equivalent titleIDs for the other regions) was updated. "romfs:/300000.bin" was added, "romfs:/<Region>_<Language>/300000_msbt_LZ.bin" was added for all of the directories in the RomFS too(the msbt files contain messages involving eShop).

All non-SAFE_MODE system modules were updated. The CTRSDK crt0 code was updated: code was added for using [[SVC|svcGetProcessInfo]] with type=20, the output value is written to a state field. Due to this change, any titles using this additional new code will not work on pre-v8.0 NATIVE_FIRM: this triggers a [[ErrDisp|fatal-error]], when ErrDisp was launched successfully to begin with. The CTRSDK LINEAR-memory vaddr->physaddr conversion code was basically replaced with code which uses the above field, however when the vaddr is within the memory for the [[NS]] SharedFont the conversion code can use either of the mappings(0x14000000/0x30000000).

Certain modules had the actual module code updated as well, such as [[GSP_Services|GSP]] and [[IR_Services|IR]], and likely others. GSP and CSND modules were updated to support LINEAR addresses in the range 0x30000000-0x40000000.

Note that unlike past CTRSDK versions(specifically CTRSDK v7.* for system-version v7.x), the CTRSDK version for system-version v8.x is v9.*.

[[ErrDisp]], eShop mint applet(used for accessing eShop outside of the eShop application, like DLC), and SNOTE_AP were updated, these now use the v7.0 NCCH encryption. None of the other updated titles use the v7.0 NCCH encryption(besides the ones which use it already). Due to [[ErrDisp]] being updated, this breaks booting 8.0.0-18 on physical <=v4.x systems where the key-data for the v7.0 NCCH crypto wasn't initialized correctly.

== [[FIRM]] ==

NATIVE_FIRM was updated. The ARM9-kernel, [[FIRM|Process9]], the ARM11-kernel, and all of the ARM11 FIRM-modules were updated.

Process9 had minor / various other changes, including gamecard-related code changes. Support for new exheader/accessdesc fields were [[NCCH/Extended_Header|implemented]]. [[Filesystem_services_PXI|FSPXI:GetSpecialContentIndex]] was updated to add support for a new value(unknown where the field for that originates). Process9 now uses VRAM size 0x600000 instead of 0x400000 for [[FIRM]](during FIRM launch) section address+size verification, and for the memory-clear code for the FIRM-launch panic function.

The LINEAR memory region has been moved to virtual address 0x30000000, however in certain cases the 0x14000000 mapping is used instead for backwards-compatibility(see [[SVC|here]] and [[Memory_layout|here]]). When the v8.0 NATIVE_FIRM is running, any process which uses the new 0x30000000 LINEAR-memory mapping will not work with <v8.0 system-modules for LINEAR memory(such as GSP/CSND module).

Most of the ARM11 FIRM-modules changes are likely minor. Certain code in pm-module was updated to clear bitmask 0xF0000000 in programID-lows(other code in pm-module was changed too). When handling the exheader dependency list, pm-module now skips handling titles in this list which have any bits in programID-low bitmask 0xF0000000 set(this is currently hard-coded). The exheader dependency list handling change is for the [[New 3DS]] [[Title_list|system-module]](s), which do not exist on 8.0.0-18.

ARM11 kernel changes(besides various other (minor) changes):
* Multiple [[SVC|SVCs]] were stubbed(that is, these only return an error now).
* The code for svcControlMemory was updated.
* The code for svcGetProcessInfo was updated: previously a total of 9 type values were handled, this now handles a total of 24 type values.
* The code for svcStartInterProcessDma was updated. When the DmaConfig userland->kernelmode data-copy fails(like when the DmaConfig address is not readable from userland), this SVC now returns an error. Certain fields in the DmaConfig structure are now validated.
* The end-address for process [[Memory_layout|memory]] has been changed from virtual-address 0x20000000, to 0x40000000. Therefore, the L1 MMU table size for each process is now 0x1000-bytes, previously it was 0x800-bytes.
* The [[KProcess]] structure was changed.
* The privileged-mode memory layout was changed, see [[Memory_layout|here]].

== See Also ==
* System update [http://yls8.mtheall.com/ninupdates/reports.php?date=07-07-14_10-13-44&sys=ctr report]

[[Category:Firmware Versions]]

7.2.0-17

2023-11-26T09:37:12Z

Emufan4568:

The 7.2.0-17 system update was released on May 12, 2014.

== Change-log ==
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/231 Official] change-log:

* Added e-mail support to Parental Controls, allowing parents that have forgotten their PIN to send themselves an e-mail with instructions on unlocking Parental Controls.
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience.

== System Titles ==
System Settings, eShop, and the NNID Settings application were updated. All three of these applications now use the [[NCCH]] encryption added with [[7.0.0-13]], none of the other updated titles were updated to use the new NCCH encryption.

The USA 0004009B00012302 USA title was updated, the other regions of that title were updated as well. The 0004001B00018002 title was updated. The NZone hotspot list was updated. NVer and CVer were updated. A new file named "masterkey.bin" was added to the CVer RomFS, see [[CVer|here]]. The mint and olv(Miiverse) applets were updated.

The "eula" CFA was updated, for only EUR.

The following system modules were updated: cfg, HID, NIM, NWM, RO, NS, and act.

== FIRM ==

NATIVE_FIRM was updated. The only actual updated code in NATIVE_FIRM was [[FIRM|Process9]], and the FIRM ARM11 modules.

== See Also ==
* System update [http://yls8.mtheall.com/ninupdates/reports.php?date=05-12-14_08-05-03&sys=ctr report]

[[Category:Firmware Versions]]

7.0.0-13

2023-11-26T09:36:53Z

Emufan4568:

The 7.0.0-13 system update was released on December 9, 2013.

== Change-log ==
Official change-log:

* Added support for Nintendo Network IDs
* Added support for Miiverse
* Added a Software Update Notification
* Removed the limit to system transfers
* Changed the start-up method of Nintendo 3DS Camera from the HOME Menu to require pressing the L and R Buttons simultaneously
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience

=Applications=
The following applications were updated: [[System Settings]], [[Activity Log]](non-JPN), [[Nintendo 3DS Camera]](non-JPN), [[Nintendo 3DS Sound]], [[Mii Maker]], [[StreetPass Mii Plaza]], [[eShop]], [[System Transfer]], [[Face Raiders]], and [[AR Games]]. A new title was added where the TID-High is the application TID-High.

==System Settings fix==
The NVRAM DS settings [[3DS_exploits|vulnerability]] in System Settings was fixed by adding the following code for the string length fields: before copying the data, the updated function will use the actual max length of the string for copying data if the length from the settings is too large.

=System CFAs=
[[NS CFA]] was updated, 3 [[Title_list|new]] titles with TID-high 0004001B were added as well.

The "area:" archive, an unknown archive, and the "eula:" archive were updated.

The [[Nintendo Zone]] hotspot list, [[CVer]], and [[NVer]] were updated.

=System Titles=
[[Home Menu]], [[Internet Browser]], Friend List applet, swkbd applet, and mint applet were updated. 2 [[Title_list|new]] titles with TID-High 00040030 were added.

=System Modules=
The following system modules were updated: cfg, codec, MCU, PTM, AC, [[StreetPass|CECD]], http, NIM, friends, [[SpotPass|BOSS]], and [[NS]] were updated. A [[Title_list|new]] system module was added: "act" for handling Nintendo Network accounts.

=FIRM and whitelist=
NATIVE_FIRM and the DS gamecard whitelist were updated.

NATIVE_FIRM now supports a new encryption method for certain [[NCCH]] sections, when a flag in the NCCH header is set. The keyslot for this is now initialized during NATIVE_FIRM boot from the same function which initializes the 6.0 gamecard [[Savegames|savegame]] keyY, see the [[NCCH]] page for details. No 7.0.0-13 system titles seem to use this new encryption, this is presumably enabled by default for all titles built starting with 7.0.0-13+ for non-system titles: the first known title to use this was the updated version of the eShop YouTube application.

[[Category:Firmware Versions]]

6.1.0-11

2023-11-26T09:36:27Z

Emufan4568:

The 6.1.0-11 system update was released on June 27, 2013, in USA. Elsewhere, the system-version is 6.1.0-12.

=== Changelog ===
Official changelog:
* "Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience."

=== System modules and other titles ===
[[NS]] and the [[Config_Services|cfg]] module were updated. [[CVer]] for the system-version was updated as well.

=== [[FIRM]] ===
NATIVE_FIRM was updated.

The only actual updated code in NATIVE_FIRM was FS module and the loader module.

[[Category:Firmware Versions]]

6.0.0-11

2023-11-26T09:36:09Z

Emufan4568:

The 6.0.0-11 system update was released on June 17, 2013, in USA. Elsewhere, the system-version is 6.0.0-12.

=== Changelog ===
Official changelog:
* "Users can now back up save data for downloadable versions of Nintendo 3DS software and most Virtual Console games"
* "Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience "

See [[SD Savedata Backups]] regarding the SD file-copy .sav backup feature.

=== Applications ===
[[System Settings]] and the SAFE_MODE [[System_Settings#System_Updater|System Updater]] application were updated. For each region except USA, the [[Nintendo 3DS Camera]] application, the [[StreetPass Mii Plaza]] application, and the [[Health and Safety Information]] application were updated.

The non-USA update for [[StreetPass Mii Plaza]] added support for DLC to this application.

=== System Titles ===
[[Home Menu]] and [[NS CFA]] were updated for [[SD Savedata Backups]]. [[NS]] was updated for handling the new ctr_backup_black_list file in [[NS CFA]]. The [[Nintendo Zone]] hotspot list CFA was updated. [[SD Savedata Backups]](for copying the .sav backups on SD etc) is implemented in either NS, or Home Menu / System Settings.

The following system modules were updated: [[Application_Manager_Services|AM]], camera, cfg, DSP, GSP, MCU, PTM, [[StreetPass|CECD]], [[NIM Services|NIM]], [[Process Services‎|PS]], [[SpotPass|BOSS]], and NWM(including the SAFE_MODE NWM).

=== [[FIRM]] and other titles ===
All FIRM titles(NATIVE_FIRM, AGB_FIRM, and TWL_FIRM) were updated, the DS whitelist was updated as well.

All of the ARM11 modules stored in NATIVE_FIRM were updated.

Process9 had the following changes:
* Support for a new [[NCSD|gamecard]] [[Savegames|savegame]] keyY generation method was implemented, enabled via [[NCSD]] flags. Every gamecard which has a system-update >= [[2.2.0-X]](in the [[System Update CFA]] NCSD partition) uses the keyY generation method added with [[2.2.0-X]], therefore every game which would release with this 6.0.0-X system-update would use this new keyY generation method.
* Code which is likely gamecard-related was added/changed as well.
* Various other changes.
* Some cmd-handler code checking the buf-headers' value now uses "& 0xFD" instead of "& 0xFF".
* Process9 no longer uses the CTRSDK heap code.

[[Category:Firmware Versions]]

5.1.0-11

2023-11-26T09:35:48Z

Emufan4568:

=== Official Changelog ===
* "Resolves an issue that may prevent access to the System Settings or other features after a system update error."

=== Summary ===
This update only fixed a FIRM [[5.0.0-11|update]] failure which occurred in some cases.

=== System Modules ===
NS was [[NS|updated]]. This updated NS checks [[Configuration Memory]] fields every time the system boots, and when those fields are set NS will use command [[AM:InstallNATIVEFIRM]].

===NATIVE_FIRM and other titles===
[[FIRM|NATIVE_FIRM]] and [[CVer]] were updated. The NATIVE_FIRM changes were minor.

[[Category:Firmware Versions]]

5.0.0-11

2023-11-26T09:35:15Z

Emufan4568:

=== Official Changelog ===
* "Users will no longer need to close the Nintendo eShop application to ensure the "Download Later" feature works while the Nintendo 3DS is in Sleep Mode."
* "Other improvements to usability have been made, including the ability to download software update data in the background."
* "Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience."

=== Update Failure ===
In some cases the system failed to install the updated NATIVE_FIRM to the NAND [[FIRM]] partitions, thus the system still [[Bootloader|booted]] from the previous version of the [[FIRM]] stored in the NAND partition which was not written to. This then caused launching the updated System Settings and eShop applications mentioned below to fail, since application [[NCCH#CXI|CXIs]] built with the updated CTR-SDK moved the logo data from the ExeFS to a separate NCCH section.

This update failure was fixed with [[5.1.0-11]]. When this [[FIRM]] install fails with this update the [[System Settings#System Updater|System Updater]] is still accessible via the [[Configuration_Memory|UPDATEFLAG]] PAD button-combo, since the System Updater title was not yet updated when the FIRM install failed.

===Applications===
System Settings, System Transfer, and eShop (including the mint applet) were updated.

Home Menu, Game Notes, Instruction Manual, ErrDisp, and Internet Browser were updated. ErrDisp now displays more debug info on dev/debug units, including what exactly triggered a data/prefetch abort etc.

===System Modules===
All system modules were updated.

===NATIVE_FIRM and other titles===
NATIVE_FIRM and the whitelist were updated. NGWord and the NZone hotspots title were updated as well.

Multiple NATIVE_FIRM vulnerabilities were fixed, this includes all known Process9 PXI-service code execution vulns at the time when the update was released. These were vulns in [[FIRM|Process9]] PXI services, the ARM11-kernel flaws which were fixed do not allow ARM11 kernel-mode code-execution. The system does not delete/block 3DS savegame haxx at all with this update, however the code execution haxx used by this was fixed.

The system can now optionally load the [[NCCH#CXI|CXI]] logo from a cleartext region in the CXI instead of from ExeFS. NATIVE_FIRM versions prior to 5.0.0-11 can't access the logo data in applications built since 5.0.0-11. Therefore regardless of gamecard system-updates, applications built since 5.0.0-11 can only be run with the 5.0.0-11+ NATIVE_FIRM. Note that only home menu seems to use the NCCH logo data, system modules like [[NS]] don't use the logo data.

A new command was added for [[Application_Manager_Services_PXI|AMPXI]].

[[Category:Firmware Versions]]

4.0.0-7

2023-11-26T09:34:41Z

Emufan4568:

'''Ability to add folders'''

Probably the biggest new feature, this lets you organise your Home Menu with folders. Here's how they work.
Select an unoccupied tile and select "Create Folder".
Tap "Edit Settings" if you want to name your folder, but remember: only the first letter shows up on its Home Menu icon. The full name appears on the top screen when you tap the folder.
Press your stylus onto an icon for a second and you'll 'pick it up'.
Drag it over to the folder and take your stylus off the screen to 'drop' the icon into the folder.
That's pretty much all there is to it. You can't put folders inside other folders, so don't try to nest them.

Video: http://youtu.be/Uo8cm9rpAA4

'''eShop Revamp'''

The other most noticeable improvement is to the eShop. Here's what's new:
* New layout — now split into two rows, the bottom is for easy access to 3DS Download Software, 3DS Virtual Console, DSiWare and 3DS Demos, while the top row is for the usual curated list and 'themes'. The search bar is now at the top, too.
* QR Code option — the 3DS has been able to scan QR codes for ever, but now the eShop gives you a bespoke option. Tap this in the Settings/Other menu, scan a QR code and it'll open the relevant page in the eShop.
* Download Later - You can now choose to download later when downloading. Meaning you can decide to download later after you chose to download it (kind of a cancel button for downloading).

'''Ability to patch games'''

This is a big one. Nintendo has added the ability for games — both retail and download — to receive updates in the form of patches or free add-on content. Here's what will be available in future.
Mario Kart 7 will get an update to address glitches. This update will be released in May, so don't go looking for it now.
Mighty Switch Force! will get five extra levels and a quick-retry button, all for free.

'''ErrDisp updated'''

[[ErrDisp]] was updated however it's unknown what changed. When the ARM11 kernel terminates an application process including when it crashed, the system now returns to [[Home Menu]]. Prior to this update, the system hanged when application processes terminated.

'''TWL_FIRM updated'''

TWL_FIRM and the whitelist was updated, blocking the savegame exploits for Cooking Coach and Classic Word Games, and blocked flash cards.

[[Category:Firmware Versions]]

2.2.0-X

2023-11-26T09:33:43Z

Emufan4568:

This update is included in the gamecard [[System Update CFA]] starting with "Super Mario 3D Land".

=== 00040030 ===
[[ErrDisp]], [[Home Menu]], and the Friends-list applet were updated.

=== System Modules ===
The following system modules were updated: codec, HID, PTM, cecd, dlp, http, NWM, friends, IR, BOSS, news, and NS.

=== [[FIRM]] and other titles ===
NATIVE_FIRM and the DS whitelist were updated.

This updated NATIVE_FIRM added support for a new [[NCSD]] flag for gamecard savegames. When this flag[7] is set, the new CTR method is used, and the hashed keyY method implemented since [[2.0.0-2]] is used. This updated NATIVE_FIRM also added [[PSPXI:EncryptDecryptAes|EncryptDecryptAes]] support for keytype8.

The kernels updated with this NATIVE_FIRM now checks the [[NCCH|CXI]] exheader "kernel release version" field, when that field is higher than the current kernel version the kernel will return an error.

[[Category:Firmware Versions]]

11.1.0-34

2023-11-26T09:32:15Z

Emufan4568:

The Old3DS+New3DS 11.1.0-34 system update was released on September 13, 2016. This Old3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN. This New3DS update was released for the following regions: USA, EUR, JPN, CHN, KOR, and TWN.

Security flaws fixed: yes.

==Change-log==
[http://en-americas-support.nintendo.com/app/answers/detail/a_id/667/p/430/c/267 Official] USA change-log:
* Further improvements to overall system stability and other minor adjustments have been made to enhance the user experience

==System Titles==
The updated titles were Home Menu, Internet Browser, NGWord bad word list CFA, Nintendo Zone hotspot list CFA, NVer, CVer, DSP, friends, NS and NATIVE_FIRM. In JPN and KOR, the error string list CFA was additionally updated.

===NATIVE_FIRM===

====ARM9====
No changes to Old3DS/New3DS code at all(plaintext FIRM ARM9 binary / arm9loader).

Only differences are in the minversion list, which updated the minimum versions for Home Menu, Internet Browser, DSP, friends, NS, and NATIVE_FIRM to latest.

====ARM11-kernel====
Exactly 3 functions were updated, these are for [[Memory_Management]]. Validation code for [[Memory_Management|memchunk-headers]] was changed. In the New3DS kernel:
* L_fff1aab0, prev ver @ L_fff1aab0.
* L_fff1c730, prev ver @ L_fff1c6f0.
* L_fff26410, prev ver @ L_fff26394.

All three functions now prevent negative chunk sizes to be used, which could have been used with hypotetical kernel-memory-read vulnerabilities to exploit the memory-management code.

The first function ("validateChunk") now makes sure that:
chunk + currentChunkSize >= currentChunk

when checking that the current chunk doesn't overlap with either the previous or next one.

The second function ("Kern::ControlMemory"), aside from other small changes, now makes additional checks on the previously allocated memory chunk; the code for that is now:
if(chunkSizeInPages >= regionSize >> 12 || chunk < regionBase || chunk + chunkSize < chunk || chunk + chunkSize > regionBase + regionSize) panic;

The third function ("insertChunk") now makes the following checks:
if(chunkSizeInPages >= regionSize >> 12 || regionBase + regionSize < chunk + chunkSize) panic;
// ...
if(leftChunk && leftChunk + leftChunkSize <= leftChunk) panic; // this check was already done on 'right'

====FIRM-modules====
Only the following FIRM-modules were updated: fs and loader.

=====loader=====
It appears only one function changed in loader: L_140022b8 previously @ L_140022b8. Codebin physical memory randomization was enabled for all of the following titles:
* USA/EUR "VVVVVV"
* USA/EUR/JPN "Freakyforms Deluxe: Your Creations, Alive!"
* USA/EUR/JPN "Pokémon Super Mystery Dungeon"
* "Pokémon Omega Ruby" + "Pokémon Alpha Sapphire"
* USA/EUR/JPN "Citizens of Earth"
* "Pokémon Picross"

=====fs=====
0x18-bytes were added to an u32 array in .rodata containing a list of title uniqueIDs, with the additional data at address 0x00134094. This array was already in FS-module. A new UTF-16 string "/updated.dat" was added @ .rodata 0x0013411c.

The titles in this list are:
* "Pokémon X"
* "Pokémon Y"
* "Pokémon Omega Ruby"
* "Pokémon Alpha Sapphire"
* "Pokémon Sun"
* "Pokémon Moon"

A new FSUSER [[FS:CheckUpdatedDat|command]] was added. If the command returns an error, the caller assumes false.

All code changes:
* LT_10d8b0: New func, the actual handler for the new command.
* LT_111480: Updated, prev ver @ LT_111330. After writing 0x27 to struct+4, this now writes 0x6 to struct+16.
* L_129434: New func, calls LT_10d8b0. This function is called by the cmdhandler.
* L_12b4fc: Updated, prev ver @ L_12b330. FSUSER cmdhandler, now calls L_129434 for the new command.

====NS====
The code for [[APT:IsTitleAllowed]] was updated.

It now adds a version check for SmileBASIC, and enforces minimum [[Titles|major-versions]] 7 for JAP and 2 for USA.
This means that smilehax is impossible on latest firmware.

Same function also now checks for the "Animal Crossing: New Leaf" title in EUR+JAP+USA, and checks if [[Titles|major-version]] is higher than 3.
If version is <=3, it calls the new fs [[FS:CheckUpdatedDat|command]] with the title-id of the Animal Crossing game.
If the new fs command returns true, it returns that the game is not allowed to be launched, otherwise it will launch it despite being too old.

This functionality appears to be for preventing the user from switching from an newer version of the application to an older version, where the newer version isn't released yet at the time the sysupdate was released. The newer version would (presumably) write to savedata [[FS:CheckUpdatedDat|"/updated.dat"]], which would trigger launch-not-allowed if the user tries to run an older version of the application.

The only other changes are for some initialization-related(?) code, which seem to be minor.

====DSP-sysmodule====
The only actual ''code'' change was that the handler function called by the [[DSP:RegisterInterruptEvents]] function was updated. Validation code was added for the input at the beginning of the function.

====friends-sysmodule====
Like past updates, the only codebin change was for updating the fpdver(6->7).

===Home Menu===
The icon vulns were [[3DS_Userland_Flaws|fixed]], hence latest menuhax as of sysupdate release was fixed for this system-version. The only code changes were for updating 2 functions, for fixing these 2 vulns(RomFS wasn't changed).

===Internet Browser===
See [[Internet_Browser|here]] for details. The [[Internet_Browser|browser-version-check]] pages for the old browser versions were updated just [https://yls8.mtheall.com/ninupdates/browserupdate/ minutes] after the sysupdate was released, unlike like past updates where it took weeks.

==See Also==
System update report(s):
* [https://yls8.mtheall.com/ninupdates/reports.php?date=09-13-16_12-05-19&sys=ctr]
* [https://yls8.mtheall.com/ninupdates/reports.php?date=09-13-16_12-05-28&sys=ktr]

[[Category:Firmware Versions]]

GPU/Internal Registers

2023-09-13T16:22:59Z

Emufan4568: /* GPUREG_SH_OUTMAP_Oi */

[[Category:GPU]]

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).

In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.

For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).

Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.

The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.

=== Command Header ===
{| class="wikitable" border="1"
! Bit
! Description
|-
| 0-15
| Command ID
|-
| 16-19
| Parameter mask
|-
| 20-27
| Number of extra parameters (may be zero)
|-
| 28-30
| Unused
|-
| 31
| Consecutive writing mode
|}

=== Parameter masking ===

Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]

=== Data Types ===

{| class="wikitable" border="1"
! Name
! Description
|-
| signed
| Signed integer
|-
| unsigned
| Unsigned integer
|-
| floatX.Y.Z
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits
|-
| fixedX.Y.Z
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits
|}

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|PICA_REG_INTERRUPT
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]
|?
|PICA_REG_FRAGOP_CLIP
|-
| 0048
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]
|?
|PICA_REG_FRAGOP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]
|?
|PICA_REG_FRAGOP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]
|?
|PICA_REG_FRAGOP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]
|?
|PICA_REG_FRAGOP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]
|
|PICA_REG_EARLY_DEPTH_CLEAR
|-
| 0064
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]
|?
|PICA_REG_FRAGOP_WSCALE
|-
| 006E
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]
|?
|PICA_REG_TEXTURE3_PROCTEX0
|-
| 00A9
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]
|?
|PICA_REG_TEXTURE3_PROCTEX1
|-
| 00AA
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]
|?
|PICA_REG_TEXTURE3_PROCTEX2
|-
| 00AB
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]
|?
|PICA_REG_TEXTURE3_PROCTEX3
|-
| 00AC
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]
|?
|PICA_REG_TEXTURE3_PROCTEX4
|-
| 00AD
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]
|?
|PICA_REG_TEXTURE3_PROCTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]
|?
|PICA_REG_PROCTEX_LUT
|-
| 00B0
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]
| ?
|PICA_REG_PROCTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]
| ?
|PICA_REG_PROCTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]
| ?
|PICA_REG_PROCTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]
| ?
|PICA_REG_PROCTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]
| ?
|PICA_REG_PROCTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]
| ?
|PICA_REG_PROCTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]
| ?
|PICA_REG_PROCTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]
| ?
|PICA_REG_PROCTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]
|
|PICA_REG_FRAGOP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]
|?
|PICA_REG_FRAGOP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS
|-
| 019B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS
|-
| 01AB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS
|-
| 01BB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA5
|-
| 01CE
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]
|
|PICA_REG_POST_VERTEX_CACHE_NUM
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH0
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH1
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH0
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH1
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|PICA_REG_COMMAND_BUF_KICK_CH0
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|PICA_REG_COMMAND_BUF_KICK_CH1
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_GS_FLOAT_DATA0
|-
| 0292
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0293
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0294
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0295
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0296
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0297
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0298
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_VS_FLOAT_DATA0
|-
| 02C2
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C3
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C4
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C5
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C6
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C7
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C8
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)
|}

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

=== GPUREG_FACECULLING_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Culling mode
|}

This register is used to configure the face culling mode.

Culling mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Front Face (Counter Clockwise)
|-
| 2
| Back Face (Counter Clockwise)
|}

=== GPUREG_VIEWPORT_WIDTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, width / 2
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.

=== GPUREG_VIEWPORT_INVW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / width
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.

=== GPUREG_VIEWPORT_HEIGHT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, height / 2
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.

=== GPUREG_VIEWPORT_INVH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / height
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.

=== GPUREG_FRAGOP_CLIP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable clipping planes.

=== GPUREG_FRAGOP_CLIP_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Clipping plane coefficient ''i''
|}

This register is used to configure clipping plane coefficients.

=== GPUREG_DEPTHMAP_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near - Far
|}

This register is used to configure the depth range scale.

=== GPUREG_DEPTHMAP_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near + Polygon Offset
|}

This register is used to configure the depth range bias.

=== GPUREG_SH_OUTMAP_TOTAL ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of following attributes
|}

This register is used to configure the total shader output map attributes.

=== GPUREG_SH_OUTMAP_O''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Semantic for the x component of the register.
|-
| 8-12
| unsigned, Semantic for the y component of the register.
|-
| 16-20
| unsigned, Semantic for the z component of the register.
|-
| 24-28
| unsigned, Semantic for the w component of the register.
|}

These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.

Semantics that have not been mapped to a component of an output register have a value of 1

Semantic values:

{| class="wikitable" border="1"
! Value
! Semantic
! Description
|-
| 0x00
| position.x
| rowspan="4" | Vertex Position
|-
| 0x01
| position.y
|-
| 0x02
| position.z
|-
| 0x03
| position.w
|-
| 0x04
| normquat.x
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)
|-
| 0x05
| normquat.y
|-
| 0x06
| normquat.z
|-
| 0x07
| normquat.w
|-
| 0x08
| color.r
| rowspan="4" | Vertex color
|-
| 0x09
| color.g
|-
| 0x0A
| color.b
|-
| 0x0B
| color.a
|-
| 0x0C
| texcoord0.u
| rowspan="2" | Texture coordinates for texture 0
|-
| 0x0D
| texcoord0.v
|-
| 0x0E
| texcoord1.u
| rowspan="2" | Texture coordinates for texture 1
|-
| 0x0F
| texcoord1.v
|-
| 0x10
| texcoord0.w
|

|-
| 0x12
| view.x
| rowspan="3" | View vector (for fragment lighting)
|-
| 0x13
| view.y
|-
| 0x14
| view.z

|-
| 0x16
| texcoord2.u
| rowspan="2" | Texture coordinates for texture 2
|-
| 0x17
| texcoord2.v

|-
| 0x1F
| Unused component
| Should be set for unused components of the output register
|}

=== GPUREG_EARLYDEPTH_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Early depth function
|}

This register configures the early depth test function.

Early depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| >=
|-
| 1
| >
|-
| 2
| <=
|-
| 3
| <
|}

=== GPUREG_EARLYDEPTH_TEST1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register sets whether the early depth test is enabled.

=== GPUREG_EARLYDEPTH_CLEAR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = clear)
|}

This register triggers clearing the early depth data.

=== GPUREG_SH_OUTATTR_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Use texture coordinates (0 = don't use, 1 = use)
|}

This register is used to configure the shader output attribute mode.

=== GPUREG_SCISSORTEST_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Enabled (0 = disabled, 3 = enabled)
|}

This register is used to enable scissor testing.

=== GPUREG_SCISSORTEST_POS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X1
|-
| 16-25
| unsigned, Y1
|}

This register is used to configure the scissor test start position.

=== GPUREG_SCISSORTEST_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X2
|-
| 16-25
| unsigned, Y2
|}

This register is used to configure the scissor test end position.

=== GPUREG_VIEWPORT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| signed, X
|-
| 16-25
| signed, Y
|}

This register is used to configure the viewport position.

=== GPUREG_EARLYDEPTH_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| unsigned, Clear value
|}

This register is used to configure the early depth clear value.

=== GPUREG_DEPTHMAP_ENABLE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable depth range.

=== GPUREG_RENDERBUF_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register is used to configure the output framebuffer dimensions.

=== GPUREG_SH_OUTATTR_CLOCK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, 'position.z' present (0 = absent, 1 = present)
|-
| 1
| unsigned, 'color' component present (0 = absent, 1 = present)
|-
| 8
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)
|-
| 9
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)
|-
| 10
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)
|-
| 16
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)
|-
| 24
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)
|}

This register controls the clock supply to parts relating to certain attributes.

== Texturing registers ==

=== GPUREG_TEXUNIT_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| 0x0
|-
| 8-9
| unsigned, Texture 3 coordinates
|-
| 10
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)
|-
| 12
| 0x1
|-
| 13
| unsigned, Texture 2 coordinates
|-
| 16
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)
|-
| 17-31
| 0x0
|}

This register is used to enable texture units.

Texture 3 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 0
|-
| 1
| Texture 1
|-
| 2
| Texture 2
|}

Texture 2 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 2
|-
| 1
| Texture 1
|}

=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to set a texture unit's border color.

=== GPUREG_TEXUNIT''i''_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Height
|-
| 16-26
| unsigned, Width
|}

This register is used to set a texture unit's dimensions.

=== GPUREG_TEXUNIT''i''_PARAM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, Magnification filter
|-
| 2
| unsigned, Minification filter
|-
| 4-5
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4
|-
| 8-10
| unsigned, Wrap T
|-
| 12-14
| unsigned, Wrap S
|-
| 16-17
| 0x0
|-
| 20
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)
|-
| 24
| unsigned, Mipmap filter
|-
| 28-30
| unsigned, Type (Texture 0 only)
|}

This register is used to set a texture unit's extra parameters.

Filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|}

Wrap values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to edge
|-
| 1
| Clamp to border
|-
| 2
| Repeat
|-
| 3
| Mirrored repeat
|}

Type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 2D
|-
| 1
| Cube map
|-
| 2
| Shadow 2D
|-
| 3
| Projection
|-
| 4
| Shadow cube
|-
| 5
| Disabled
|}

=== GPUREG_TEXUNIT''i''_LOD ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.4.8, Bias
|-
| 16-19
| unsigned, Max Level
|-
| 24-27
| unsigned, Min Level
|}

This register is used to configure a texture unit's level of detail.

=== GPUREG_TEXUNIT''i''_ADDR''i'' ===

First ADDR register:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Texture physical address >> 3
|}

Subsequent ADDR registers:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-21
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)
|}

This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.

If the texture is a cube:

{| class="wikitable" border="1"
! Register
! Description
|-
| ADDR1
| Positive X
|-
| ADDR2
| Negative X
|-
| ADDR3
| Positive Y
|-
| ADDR4
| Negative Y
|-
| ADDR5
| Positive Z
|-
| ADDR6
| Negative Z
|}

Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.

=== GPUREG_TEXUNIT''i''_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Perspective (0 = perspective, 1 = not perspective)
|-
| 1-23
| fixed0.0.24, Z bias (upper 23 bits)
|}

This register is used to set a texture unit's shadow texture properties.

=== GPUREG_TEXUNIT''i''_TYPE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Format
|}

This register is used to set a texture unit's data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
! GL Format
! GL Data Type
|-
| 0x0
| RGBA8888
| GL_RGBA
| GL_UNSIGNED_BYTE
|-
| 0x1
| RGB888
| GL_RGB
| GL_UNSIGNED_BYTE
|-
| 0x2
| RGBA5551
| GL_RGBA
| GL_UNSIGNED_SHORT_5_5_5_1
|-
| 0x3
| RGB565
| GL_RGB
| GL_UNSIGNED_SHORT_5_6_5
|-
| 0x4
| RGBA4444
| GL_RGBA
| GL_UNSIGNED_SHORT_4_4_4_4
|-
| 0x5
| IA8
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x6
| HILO8
|
|
|-
| 0x7
| I8
| GL_LUMINANCE
| GL_UNSIGNED_BYTE
|-
| 0x8
| A8
| GL_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x9
| IA44
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE_4_4_EXT
|-
| 0xA
| I4
|
|
|-
| 0xB
| A4
| GL_ALPHA
| GL_UNSIGNED_NIBBLE_EXT
|-
| 0xC
| ETC1
| GL_ETC1_RGB8_OES
|
|-
| 0xD
| ETC1A4
|
|
|}

=== GPUREG_LIGHTING_ENABLE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable lighting.

=== GPUREG_TEXUNIT3_PROCTEX0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, U-direction clamp
|-
| 3-5
| unsigned, V-direction clamp
|-
| 6-9
| unsigned, RGB mapping function
|-
| 10-13
| unsigned, Alpha mapping function
|-
| 14
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)
|-
| 15
| unsigned, Noise enabled (0 = disabled, 1 = enabled)
|-
| 16-17
| unsigned, U-direction shift
|-
| 18-19
| unsigned, V-direction shift
|-
| 20-27
| float1.5.10, Texture bias (lower 8 bits)
|}

This register is used to configure the procedural texture unit.

Clamp values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to zero
|-
| 1
| Clamp to edge
|-
| 2
| Symmetrical repeat
|-
| 3
| Mirrored repeat
|-
| 4
| Pulse
|}

Mapping function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| U
|-
| 1
| U²
|-
| 2
| V
|-
| 3
| V²
|-
| 4
| (U + V) / 2
|-
| 5
| (U² + V²) / 2
|-
| 6
| sqrt(U² + V²)
|-
| 7
| Minimum
|-
| 8
| Maximum
|-
| 9
| Rmax
|}

Shift values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Odd
|-
| 2
| Even
|}

=== GPUREG_TEXUNIT3_PROCTEX1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, U-direction noise amplitude
|-
| 16-31
| float1.5.10, U-direction noise phase
|}

This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, V-direction noise amplitude
|-
| 16-31
| float1.5.10, V-direction noise phase
|}

This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, U-direction noise frequency
|-
| 16-31
| float1.5.10, V-direction noise frequency
|}

This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.

=== GPUREG_TEXUNIT3_PROCTEX4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Minification filter
|-
| 3-6
| Min LOD (usually 0)
|-
| 7-10
| Max LOD (usually 6)
|-
| 11-18
| unsigned, Texture width
|-
| 19-26
| float1.5.10, Texture bias (upper 8 bits)
|}

This register is used to configure the procedural texture unit.

Minification filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|-
| 2
| Nearest, Mipmap Nearest
|-
| 3
| Linear, Mipmap Nearest
|-
| 4
| Nearest, Mipmap Linear
|-
| 5
| Linear, Mipmap Linear
|}

=== GPUREG_TEXUNIT3_PROCTEX5 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Texture offset (Mipmap level 0 / base level)
|-
| 8-15
| unsigned, mipmap level 1 offset (usually 0x80)
|-
| 16-23
| unsigned, mipmap level 2 offset (usually 0xC0)
|-
| 24-31
| unsigned, mipmap level 3 offset (usually 0xE0)
|}

This register is used to set the procedural texture unit's offset. Mipmap level 4-7 seems to be hardcoded at offset 0xF0, 0xF8, 0xFC and 0xFE .

=== GPUREG_PROCTEX_LUT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Index
|-
| 8-11
| unsigned, Reference table
|}

This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.

Reference table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Noise table
|-
| 2
| RGB mapping function table
|-
| 3
| Alpha mapping function table
|-
| 4
| Color table
|-
| 5
| Color difference table
|}

=== GPUREG_PROCTEX_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.

==== Noise Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement ( [0.5,1.0) mapped to [-1.0,0) ), Difference from next element
|}

==== RGB Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement, Difference from next element
|}

==== Alpha Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement, Difference from next element
|}

==== Color Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

==== Color Difference Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Half of red difference between current and next color table elements
|-
| 8-15
| signed, Half of green difference between current and next color table elements
|-
| 16-23
| signed, Half of blue difference between current and next color table elements
|-
| 24-31
| signed, Half of alpha difference between current and next color table elements
|}

=== GPUREG_TEXENV''i''_SOURCE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB source 0
|-
| 4-7
| unsigned, RGB source 1
|-
| 8-11
| unsigned, RGB source 2
|-
| 16-19
| unsigned, Alpha source 0
|-
| 20-23
| unsigned, Alpha source 1
|-
| 24-27
| unsigned, Alpha source 2
|}

This register configures a texture combiner's sources.

Source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Primary color
|-
| 1
| Fragment primary color
|-
| 2
| Fragment secondary color
|-
| 3
| Texture 0
|-
| 4
| Texture 1
|-
| 5
| Texture 2
|-
| 6
| Texture 3
|-
| 13
| Previous buffer
|-
| 14
| Constant (from GPUREG_TEXENV''i''_COLOR)
|-
| 15
| Previous
|}

Using previous source in the first TEV stage returns the primary color, while previous buffer returns zero.

=== GPUREG_TEXENV''i''_OPERAND ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB operand 0
|-
| 4-7
| unsigned, RGB operand 1
|-
| 8-11
| unsigned, RGB operand 2
|-
| 12-14
| unsigned, Alpha operand 0
|-
| 16-18
| unsigned, Alpha operand 1
|-
| 20-22
| unsigned, Alpha operand 2
|}

This register configures a texture combiner's operands.

RGB operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source color
|-
| 1
| One minus source color
|-
| 2
| Source alpha
|-
| 3
| One minus source alpha
|-
| 4
| Source red
|-
| 5
| One minus source red
|-
| 8
| Source green
|-
| 9
| One minus source green
|-
| 12
| Source blue
|-
| 13
| One minus source blue
|}

Alpha operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source alpha
|-
| 1
| One minus source alpha
|-
| 2
| Source red
|-
| 3
| One minus source red
|-
| 4
| Source green
|-
| 5
| One minus source green
|-
| 6
| Source blue
|-
| 7
| One minus source blue
|}

=== GPUREG_TEXENV''i''_COMBINER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB combine
|-
| 16-19
| unsigned, Alpha combine
|}

This register configures a texture combiner's combine mode.

Combine values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Replace
|-
| 1
| Modulate
|-
| 2
| Add
|-
| 3
| Add signed
|-
| 4
| Interpolate
|-
| 5
| Subtract
|-
| 6
| Dot3 RGB
|-
| 7
| Dot3 RGBA
|-
| 8
| Multiply then add
|-
| 9
| Add then multiply
|}

=== GPUREG_TEXENV''i''_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register configures a texture combiner's constant color.

=== GPUREG_TEXENV''i''_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, RGB scale
|-
| 16-17
| unsigned, Alpha scale
|}

This register configures a texture combiner's scale value.

Scale values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|}

=== GPUREG_TEXENV_UPDATE_BUFFER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fog mode
|-
| 3
| unsigned, Shading density source
|-
| 8
| unsigned, TexEnv 1 RGB buffer input
|-
| 9
| unsigned, TexEnv 2 RGB buffer input
|-
| 10
| unsigned, TexEnv 3 RGB buffer input
|-
| 11
| unsigned, TexEnv 4 RGB buffer input
|-
| 12
| unsigned, TexEnv 1 alpha buffer input
|-
| 13
| unsigned, TexEnv 2 alpha buffer input
|-
| 14
| unsigned, TexEnv 3 alpha buffer input
|-
| 15
| unsigned, TexEnv 4 alpha buffer input
|-
| 16
| unsigned, Z flip (0 = don't flip, 1 = flip)
|-
| 24-25
| 0x0
|}

This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.

Fog mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Disabled
|-
| 5
| Fog
|-
| 7
| Gas
|}

Shading density source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Plain density
|-
| 1
| Depth density
|}

Buffer input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Previous buffer
|-
| 1
| Previous
|}

=== GPUREG_FOG_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

This register is used to configure the color of fog.

=== GPUREG_GAS_ATTENUATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas density attenuation
|}

This register is used to configure the gas density attenuation.

=== GPUREG_GAS_ACCMAX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas maximum density accumulation
|}

This register is used to configure the gas maximum density accumulation.

=== GPUREG_FOG_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.

=== GPUREG_FOG_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.

==== Fog Look-Up Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Difference from next element
|-
| 13-23
| fixed0.0.11, Value
|}

=== GPUREG_TEXENV_BUFFER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the texture combiner buffer color.

== Framebuffer registers ==

=== GPUREG_COLOR_OPERATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Fragment operation mode
|-
| 8
| unsigned, Blend mode
|-
| 16-25
| 0x0E4
|}

This register is used to configure the fragment operation mode and whether to use logic ops or blending.

Fragment operation mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Default
|-
| 1
| Gas
|-
| 3
| Shadow
|}

Blend mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Logic op
|-
| 1
| Blend
|}

=== GPUREG_BLEND_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, RGB equation
|-
| 8-10
| unsigned, Alpha equation
|-
| 16-19
| unsigned, RGB source function
|-
| 20-23
| unsigned, RGB destination function
|-
| 24-27
| unsigned, Alpha source function
|-
| 28-31
| unsigned, Alpha destination function
|}

This register is used to configure the blending function.

'''Equation values:'''

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Add
|-
| 1
| Subtract
|-
| 2
| Reverse subtract
|-
| 3
| Minimum
|-
| 4
| Maximum
|}

Blend equations 5, 6, 7 appear to behave the same as blend equation 0 (Add)

'''Function values:'''

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Zero
|-
| 1
| One
|-
| 2
| Source color
|-
| 3
| One minus source color
|-
| 4
| Destination color
|-
| 5
| One minus destination color
|-
| 6
| Source alpha
|-
| 7
| One minus source alpha
|-
| 8
| Destination alpha
|-
| 9
| One minus destination alpha
|-
| 10
| Constant color
|-
| 11
| One minus constant color
|-
| 12
| Constant alpha
|-
| 13
| One minus constant alpha
|-
| 14
| Source alpha saturate
|}

=== GPUREG_LOGIC_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Logic op
|}

This register is used to configure the logic op.

Logic op values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clear
|-
| 1
| AND
|-
| 2
| Reverse AND
|-
| 3
| Copy
|-
| 4
| Set
|-
| 5
| Inverted copy
|-
| 6
| Noop
|-
| 7
| Invert
|-
| 8
| NAND
|-
| 9
| OR
|-
| 10
| NOR
|-
| 11
| XOR
|-
| 12
| Equivalent
|-
| 13
| Inverted AND
|-
| 14
| Reverse OR
|-
| 15
| Inverted OR
|}

=== GPUREG_BLEND_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the blending color.

=== GPUREG_FRAGOP_ALPHA_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Reference value
|}

This register is used to configure alpha testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Buffer mask
|-
| 16-23
| signed, Reference value
|-
| 24-31
| unsigned, Mask
|}

This register is used to configure stencil testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fail operation
|-
| 4-6
| unsigned, Z-fail operation
|-
| 8-10
| unsigned, Z-pass operation
|}

This register is used to configure stencil result operations.

Operation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Keep
|-
| 1
| Zero
|-
| 2
| Replace
|-
| 3
| Increment
|-
| 4
| Decrement
|-
| 5
| Invert
|-
| 6
| Increment and wrap
|-
| 7
| Decrement and wrap
|}

=== GPUREG_DEPTH_COLOR_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Depth function
|-
| 8
| unsigned, Red write enabled (0 = disabled, 1 = enabled)
|-
| 9
| unsigned, Green write enabled (0 = disabled, 1 = enabled)
|-
| 10
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)
|-
| 11
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)
|-
| 12
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
|}

This register is used to depth testing and framebuffer write masking.

Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.

Depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = invalidate)
|-
| 1-31
| 0x0
|}

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = flush)
|-
| 1-31
| 0x0
|}

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_COLORBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow read (0 = disable, 0xF = enable)
|}

This register configures read access from the color buffer.

=== GPUREG_COLORBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow write (0 = disable, 0xF = enable)
|}

This register configures write access to the color buffer.

=== GPUREG_DEPTHBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil read (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth read (0 = disable, 1 = enable)
|}

This register configures read access from the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil write (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth write (0 = disable, 1 = enable)
|}

This register configures write access to the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Format
|}

This register configures the depth buffer data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil
|}

=== GPUREG_COLORBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Pixel size
|-
| 16-18
| unsigned, Format
|}

This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.

Pixel size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit color
|-
| 2
| 32-bit color
|}

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| RGBA8/Gas
|-
| 2
| RGB5A1
|-
| 3
| RGB565
|-
| 4
| RGBA4
|}

=== GPUREG_EARLYDEPTH_TEST2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register enables the early depth test.

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Render block mode
|}

This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

Render block mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8x8 blocks
|-
| 1
| 32x32 blocks
|}

=== GPUREG_DEPTHBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Depth buffer physical address >> 3
|}

This register configures the depth buffer physical address.

=== GPUREG_COLORBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Color buffer physical address >> 3
|}

This register configures the color buffer physical address.

=== GPUREG_FRAMEBUFFER_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register configures the framebuffer dimensions.

=== GPUREG_GAS_LIGHT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Planar shading minimum intensity
|-
| 8-15
| unsigned, Planar shading maximum intensity
|-
| 16-23
| unsigned, Planar shading density attenuation
|}

This register configures gas light planar shading.

=== GPUREG_GAS_LIGHT_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading minimum intensity
|-
| 8-15
| unsigned, View shading maximum intensity
|-
| 16-23
| unsigned, View shading density attenuation
|}

This register configures gas light view shading.

=== GPUREG_GAS_LIGHT_Z_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading effect in line-of-sight direction
|-
| 8
| Gas color LUT input
|}

This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.

Color LUT input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Gas density
|-
| 1
| Light factor
|}

=== GPUREG_GAS_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.

=== GPUREG_GAS_LUT_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.

==== Gas Look-Up Table ====

16 elements:

First 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Red
|-
| 8-15
| signed, Green
|-
| 16-23
| signed, Blue
|}

Last 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

=== GPUREG_GAS_DELTAZ_DEPTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| fixed0.16.8, Depth direction attenuation proportion
|-
| 24-25
| unsigned, Depth function
|}

This register is used to configure the gas depth direction attenuation proportion, as well as the gas depth function.

Gas depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Greater than/Greater than or equal
|-
| 3
| Less than/Less than or equal/Equal/Not equal
|}

=== GPUREG_FRAGOP_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Sum of penumbra scale and penumbra bias
|-
| 16-31
| float1.5.10, Penumbra scale with reversed sign
|}

This register is used to configure shadow properties.

== Fragment lighting registers ==

=== GPUREG_LIGHT''i''_SPECULAR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.

=== GPUREG_LIGHT''i''_SPECULAR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.

=== GPUREG_LIGHT''i''_DIFFUSE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

=== GPUREG_LIGHT''i''_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.

=== GPUREG_LIGHT''i''_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, X coordinate
|-
| 16-31
| float1.5.10, Y coordinate
|}

These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Z coordinate
|}

These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, X coordinate (negated)
|-
| 16-28
| fixed1.1.11, Y coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Z coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Light type (0 = positional light, 1 = directional light)
|-
| 1
| unsigned, Two side diffuse (0 = one side, 1 = both sides)
|-
| 2
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)
|-
| 3
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)
|}

This register configures a light's properties.

=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation bias
|}

These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation scale
|}

These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHTING_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

=== GPUREG_LIGHTING_NUM_LIGHTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of active lights - 1
|}

This register configures the number of active lights.

=== GPUREG_LIGHTING_CONFIG0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)
|-
| 2-3
| unsigned, Fresnel selector
|-
| 4-7
| unsigned, Light environment configuration
|-
| 8-11
| 0x4
|-
| 16
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)
|-
| 17
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)
|-
| 18
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)
|-
| 19
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)
|-
| 22-23
| unsigned, Bump map texture unit
|-
| 24-25
| unsigned, Shadow map texture unit
|-
| 27
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)
|-
| 28-29
| unsigned, Bump mode
|-
| 30
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)
|-
| 31
| 0x1
|}

This register configures the light environment.

Fresnel selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Primary alpha
|-
| 2
| Secondary alpha
|-
| 3
| Primary and secondary alpha
|}

The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.

Light environment configuration values:

{| class="wikitable" border="1"
! Value
! Description
! Available LUTs
|-
| 0
| Configuration 0
| D0, RR, SP, DA
|-
| 1
| Configuration 1
| FR, RR, SP, DA
|-
| 2
| Configuration 2
| D0, D1, RR, DA
|-
| 3
| Configuration 3
| D0, D1, FR, DA
|-
| 4
| Configuration 4
| All except for FR
|-
| 5
| Configuration 5
| All except for D1
|-
| 6
| Configuration 6
| All except for RB and RG
|-
| 8
| Configuration 7
| All
|}

Bump mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Not used
|-
| 1
| Use as bump map
|-
| 2
| Use as tangent map
|}

=== GPUREG_LIGHTING_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)
|-
| 1
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)
|-
| 2
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)
|-
| 3
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)
|-
| 4
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)
|-
| 6
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)
|-
| 7
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)
|-
| 8
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)
|-
| 10
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)
|-
| 11
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)
|-
| 12
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)
|-
| 14
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)
|-
| 15
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)
|-
| 16
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)
|-
| 18
| 0x1
|-
| 19
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
|-
| 20
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 1 = disabled)
|-
| 22
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 1 = disabled)
|-
| 24
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 26
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 27
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 28
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 29
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 30
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 31
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)
|}

This register is used to disable various aspects of the light environment.

=== GPUREG_LIGHTING_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Starting index
|-
| 8-12
| unsigned, Look-up table
|}

This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.

Lookup table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| D0
|-
| 1
| D1
|-
| 3
| FR
|-
| 4
| RB
|-
| 5
| RG
|-
| 6
| RR
|-
| 8-15
| SP0-7
|-
| 16-23
| DA0-7
|}

=== GPUREG_LIGHTING_ENABLE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Disabled (0 = enabled, 1 = disabled)
|}

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

=== GPUREG_LIGHTING_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

Lighting LUT data is written here.

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.

Format of an entry:

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Entry value
|-
| 12-23
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation
|}

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)
|}

This register controls whether the absolute value of the input is taken before using a LUT.

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Input selector for D0
|-
| 4-6
| unsigned, Input selector for D1
|-
| 8-10
| unsigned, Input selector for SP
|-
| 12-14
| unsigned, Input selector for FR
|-
| 16-18
| unsigned, Input selector for RB
|-
| 20-22
| unsigned, Input selector for RG
|-
| 24-26
| unsigned, Input selector for RR
|}

This register selects the input from LUTs.

Input selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Scaler selector for D0
|-
| 4-6
| unsigned, Scaler selector for D1
|-
| 8-10
| unsigned, Scaler selector for SP
|-
| 12-14
| unsigned, Scaler selector for FR
|-
| 16-18
| unsigned, Scaler selector for RB
|-
| 20-22
| unsigned, Scaler selector for RG
|-
| 24-26
| unsigned, Scaler selector for RR
|}

This register controls the scaling that is applied to the output of a LUT.

Scaler selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, ID of the 1st enabled light
|-
| 4-6
| unsigned, ID of the 2nd enabled light
|-
| 8-10
| unsigned, ID of the 3rd enabled light
|-
| 12-14
| unsigned, ID of the 4th enabled light
|-
| 16-18
| unsigned, ID of the 5th enabled light
|-
| 20-22
| unsigned, ID of the 6th enabled light
|-
| 24-26
| unsigned, ID of the 7th enabled light
|-
| 28-30
| unsigned, ID of the 8th enabled light
|}

This register sets the IDs of enabled light sources.

== Geometry pipeline registers ==

=== GPUREG_ATTRIBBUFFERS_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-28
| unsigned, Vertex arrays base address
|}

This register sets the base address of all vertex arrays.

=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 0 type
|-
| 2-3
| unsigned, Vertex attribute 0 size
|-
| 4-5
| unsigned, Vertex attribute 1 type
|-
| 6-7
| unsigned, Vertex attribute 1 size
|-
| 8-9
| unsigned, Vertex attribute 2 type
|-
| 10-11
| unsigned, Vertex attribute 2 size
|-
| 12-13
| unsigned, Vertex attribute 3 type
|-
| 14-15
| unsigned, Vertex attribute 3 size
|-
| 16-17
| unsigned, Vertex attribute 4 type
|-
| 18-19
| unsigned, Vertex attribute 4 size
|-
| 20-21
| unsigned, Vertex attribute 5 type
|-
| 22-23
| unsigned, Vertex attribute 5 size
|-
| 24-25
| unsigned, Vertex attribute 6 type
|-
| 26-27
| unsigned, Vertex attribute 6 size
|-
| 28-29
| unsigned, Vertex attribute 7 type
|-
| 30-31
| unsigned, Vertex attribute 7 size
|}

This register configures the types and sizes of the first 8 vertex attributes.

Vertex attribute type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Byte
|-
| 1
| Unsigned byte
|-
| 2
| Short
|-
| 3
| Float
|}

Vertex attribute size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8 bits
|-
| 1
| 16 bits
|-
| 2
| 24 bits
|-
| 3
| 32 bits
|}

=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 8 type
|-
| 2-3
| unsigned, Vertex attribute 8 size
|-
| 4-5
| unsigned, Vertex attribute 9 type
|-
| 6-7
| unsigned, Vertex attribute 9 size
|-
| 8-9
| unsigned, Vertex attribute 10 type
|-
| 10-11
| unsigned, Vertex attribute 10 size
|-
| 12-13
| unsigned, Vertex attribute 11 type
|-
| 14-15
| unsigned, Vertex attribute 11 size
|-
| 16-27
| unsigned, Fixed vertex attribute mask
|-
| 28-31
| unsigned, Total vertex attribute count - 1
|}

This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.

See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.

=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|}

This register configures the offset of a vertex array from the base vertex arrays address.

=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 1
|-
| 4-7
| unsigned, Component 2
|-
| 8-11
| unsigned, Component 3
|-
| 12-15
| unsigned, Component 4
|-
| 16-19
| unsigned, Component 5
|-
| 20-23
| unsigned, Component 6
|-
| 24-27
| unsigned, Component 7
|-
| 28-31
| unsigned, Component 8
|}

This register configures the first 8 component types of a vertex array.

Component values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Vertex attribute 0
|-
| 1
| Vertex attribute 1
|-
| 2
| Vertex attribute 2
|-
| 3
| Vertex attribute 3
|-
| 4
| Vertex attribute 4
|-
| 5
| Vertex attribute 5
|-
| 6
| Vertex attribute 6
|-
| 7
| Vertex attribute 7
|-
| 8
| Vertex attribute 8
|-
| 9
| Vertex attribute 9
|-
| 10
| Vertex attribute 10
|-
| 11
| Vertex attribute 11
|-
| 12
| 4-byte padding
|-
| 13
| 8-byte padding
|-
| 14
| 12-byte padding
|-
| 15
| 16-byte padding
|}

=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 9
|-
| 4-7
| unsigned, Component 10
|-
| 8-11
| unsigned, Component 11
|-
| 12-15
| unsigned, Component 12
|-
| 16-23
| unsigned, Bytes per vertex
|-
| 28-31
| unsigned, Total number of components
|}

This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.

See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.

=== GPUREG_INDEXBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|-
| 31
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)
|}

This register configures the index array used when drawing elements.

=== GPUREG_NUMVERTICES ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Number of vertices to render
|}

This register sets the number of vertices to render.

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|-
| 9
| 0x0
|-
| 31
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_VERTEX_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Starting vertex offset
|}

This register sets the offset of the first vertex in an array to render.

=== GPUREG_POST_VERTEX_CACHE_NUM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)
|}

This register configures the post-vertex cache.

=== GPUREG_DRAWARRAYS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw arrays)
|}

This register triggers drawing vertex arrays.

=== GPUREG_DRAWELEMENTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw elements)
|}

This register triggers drawing vertex array elements.

=== GPUREG_VTX_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)
|}

This register triggers clearing the post-vertex cache.

=== GPUREG_FIXEDATTRIB_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)
|}

This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

=== GPUREG_FIXEDATTRIB_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| colspan="2" | '''DATA0:'''
|-
| 0-7
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)
|-
| 8-31
| float1.7.16, Vertex attribute element 4 (W)
|-
| colspan="2" | '''DATA1:'''
|-
| 0-15
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)
|-
| 16-31
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)
|-
| colspan="2" | '''DATA2:'''
|-
| 0-23
| float1.7.16, Vertex attribute element 1 (X)
|-
| 24-31
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)
|}

Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.

=== GPUREG_CMDBUF_SIZE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 0 >> 3
|}

This register sets the size of the first command buffer.

=== GPUREG_CMDBUF_SIZE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 1 >> 3
|}

This register sets the size of the second command buffer.

=== GPUREG_CMDBUF_ADDR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 0 >> 3
|}

This register sets the physical address of the first command buffer.

=== GPUREG_CMDBUF_ADDR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 1 >> 3
|}

This register sets the physical address of the second command buffer.

=== GPUREG_CMDBUF_JUMP0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)
|}

This register triggers a jump to the first command buffer.

=== GPUREG_CMDBUF_JUMP1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)
|}

This register triggers a jump to the second command buffer.

=== GPUREG_VSH_NUM_ATTR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader input attributes - 1
|}

This register sets the number of vertex shader input attributes.

=== GPUREG_VSH_COM_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)
|}

This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.

=== GPUREG_START_DRAW_FUNC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Mode (0 = drawing, 1 = configuration)
|-
| 1-7
| 0x0
|}

This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.

=== GPUREG_VSH_OUTMAP_TOTAL1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_VSH_OUTMAP_TOTAL2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_GSH_MISC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)
|}

This register configures miscellaneous geometry shader properties.

=== GPUREG_GEOSTAGE_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_GSH_MISC1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)
|}

This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.

=== GPUREG_PRIMITIVE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|-
| 8-9
| unsigned, Primitive mode
|}

This register configures primitive drawing.

Primitive mode value:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Triangles
|-
| 1
| Triangle strip
|-
| 2
| Triangle fan
|-
| 3
| Geometry primitive
|}

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = reset primitive)
|-
| 1-31
| 0x0
|}

This register triggers resetting primitive drawing.

== Shader registers ==

=== GPUREG_''SH''_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Boolean register b0 value (0 = false, 1 = true)
|-
| 1
| unsigned, Boolean register b1 value (0 = false, 1 = true)
|-
| 2
| unsigned, Boolean register b2 value (0 = false, 1 = true)
|-
| 3
| unsigned, Boolean register b3 value (0 = false, 1 = true)
|-
| 4
| unsigned, Boolean register b4 value (0 = false, 1 = true)
|-
| 5
| unsigned, Boolean register b5 value (0 = false, 1 = true)
|-
| 6
| unsigned, Boolean register b6 value (0 = false, 1 = true)
|-
| 7
| unsigned, Boolean register b7 value (0 = false, 1 = true)
|-
| 8
| unsigned, Boolean register b8 value (0 = false, 1 = true)
|-
| 9
| unsigned, Boolean register b9 value (0 = false, 1 = true)
|-
| 10
| unsigned, Boolean register b10 value (0 = false, 1 = true)
|-
| 11
| unsigned, Boolean register b11 value (0 = false, 1 = true)
|-
| 12
| unsigned, Boolean register b12 value (0 = false, 1 = true)
|-
| 13
| unsigned, Boolean register b13 value (0 = false, 1 = true)
|-
| 14
| unsigned, Boolean register b14 value (0 = false, 1 = true)
|-
| 15
| unsigned, Boolean register b15 value (0 = false, 1 = true)
|-
| 16-31
| 0x7FFF
|}

This register is used to set a shader unit's boolean registers.

=== GPUREG_''SH''_INTUNIFORM_I''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Integer register i''i'' X value
|-
| 8-15
| unsigned, Integer register i''i'' Y value
|-
| 16-23
| unsigned, Integer register i''i'' Z value
|-
| 24-31
| unsigned, Integer register i''i'' W value
|}

These registers are used to set a shader unit's integer registers.

=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Input vertex attributes - 1
|-
| 8-15
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)
|-
| 16-23
| 0x0
|-
| 24-31
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)
|}

This register is used to configure a shader unit's input buffer.

=== GPUREG_''SH''_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Code entry point offset, in 32-bit words
|-
| 16-31
| 0x7FFF
|}

This register sets a shader unit's code entry point.

For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.

For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 0 input register index
|-
| 4-7
| unsigned, Vertex attribute 1 input register index
|-
| 8-11
| unsigned, Vertex attribute 2 input register index
|-
| 12-15
| unsigned, Vertex attribute 3 input register index
|-
| 16-19
| unsigned, Vertex attribute 4 input register index
|-
| 20-23
| unsigned, Vertex attribute 5 input register index
|-
| 24-27
| unsigned, Vertex attribute 6 input register index
|-
| 28-31
| unsigned, Vertex attribute 7 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 8 input register index
|-
| 4-7
| unsigned, Vertex attribute 9 input register index
|-
| 8-11
| unsigned, Vertex attribute 10 input register index
|-
| 12-15
| unsigned, Vertex attribute 11 input register index
|-
| 16-19
| unsigned, Vertex attribute 12 input register index
|-
| 20-23
| unsigned, Vertex attribute 13 input register index
|-
| 24-27
| unsigned, Vertex attribute 14 input register index
|-
| 28-31
| unsigned, Vertex attribute 15 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_''SH''_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)
|-
| 4
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)
|-
| 5
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)
|-
| 6
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)
|-
| 7
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 8
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 9
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 10
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 11
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 12
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 13
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 14
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 15
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 16-31
| 0x0
|}

This register toggles a shader unit's output registers.

=== GPUREG_''SH''_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Signal transfer end (0 = idle, non-zero = signal)
|}

This register's value should be set to 1 in order to finalize the transfer of shader code.

=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)
|}

This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.

=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Floating-point register component data
|}

This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_''SH''_CODETRANSFER_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader code offset
|}

This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.

=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader instruction data
|}

This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.

=== GPUREG_''SH''_OPDESCS_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader operand descriptor offset
|}

This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.

=== GPUREG_''SH''_OPDESCS_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader operand descriptor data
|}

This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.

GPU/Internal Registers

2023-09-13T16:21:29Z

Emufan4568: /* GPUREG_SH_OUTMAP_Oi */

[[Category:GPU]]

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).

In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.

For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).

Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.

The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.

=== Command Header ===
{| class="wikitable" border="1"
! Bit
! Description
|-
| 0-15
| Command ID
|-
| 16-19
| Parameter mask
|-
| 20-27
| Number of extra parameters (may be zero)
|-
| 28-30
| Unused
|-
| 31
| Consecutive writing mode
|}

=== Parameter masking ===

Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]

=== Data Types ===

{| class="wikitable" border="1"
! Name
! Description
|-
| signed
| Signed integer
|-
| unsigned
| Unsigned integer
|-
| floatX.Y.Z
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits
|-
| fixedX.Y.Z
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits
|}

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|PICA_REG_INTERRUPT
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]
|?
|PICA_REG_FRAGOP_CLIP
|-
| 0048
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]
|?
|PICA_REG_FRAGOP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]
|?
|PICA_REG_FRAGOP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]
|?
|PICA_REG_FRAGOP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]
|?
|PICA_REG_FRAGOP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]
|
|PICA_REG_EARLY_DEPTH_CLEAR
|-
| 0064
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]
|?
|PICA_REG_FRAGOP_WSCALE
|-
| 006E
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]
|?
|PICA_REG_TEXTURE3_PROCTEX0
|-
| 00A9
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]
|?
|PICA_REG_TEXTURE3_PROCTEX1
|-
| 00AA
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]
|?
|PICA_REG_TEXTURE3_PROCTEX2
|-
| 00AB
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]
|?
|PICA_REG_TEXTURE3_PROCTEX3
|-
| 00AC
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]
|?
|PICA_REG_TEXTURE3_PROCTEX4
|-
| 00AD
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]
|?
|PICA_REG_TEXTURE3_PROCTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]
|?
|PICA_REG_PROCTEX_LUT
|-
| 00B0
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]
| ?
|PICA_REG_PROCTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]
| ?
|PICA_REG_PROCTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]
| ?
|PICA_REG_PROCTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]
| ?
|PICA_REG_PROCTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]
| ?
|PICA_REG_PROCTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]
| ?
|PICA_REG_PROCTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]
| ?
|PICA_REG_PROCTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]
| ?
|PICA_REG_PROCTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]
|
|PICA_REG_FRAGOP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]
|?
|PICA_REG_FRAGOP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS
|-
| 019B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS
|-
| 01AB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS
|-
| 01BB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA5
|-
| 01CE
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]
|
|PICA_REG_POST_VERTEX_CACHE_NUM
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH0
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH1
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH0
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH1
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|PICA_REG_COMMAND_BUF_KICK_CH0
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|PICA_REG_COMMAND_BUF_KICK_CH1
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_GS_FLOAT_DATA0
|-
| 0292
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0293
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0294
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0295
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0296
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0297
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0298
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_VS_FLOAT_DATA0
|-
| 02C2
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C3
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C4
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C5
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C6
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C7
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C8
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)
|}

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

=== GPUREG_FACECULLING_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Culling mode
|}

This register is used to configure the face culling mode.

Culling mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Front Face (Counter Clockwise)
|-
| 2
| Back Face (Counter Clockwise)
|}

=== GPUREG_VIEWPORT_WIDTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, width / 2
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.

=== GPUREG_VIEWPORT_INVW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / width
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.

=== GPUREG_VIEWPORT_HEIGHT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, height / 2
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.

=== GPUREG_VIEWPORT_INVH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / height
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.

=== GPUREG_FRAGOP_CLIP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable clipping planes.

=== GPUREG_FRAGOP_CLIP_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Clipping plane coefficient ''i''
|}

This register is used to configure clipping plane coefficients.

=== GPUREG_DEPTHMAP_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near - Far
|}

This register is used to configure the depth range scale.

=== GPUREG_DEPTHMAP_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near + Polygon Offset
|}

This register is used to configure the depth range bias.

=== GPUREG_SH_OUTMAP_TOTAL ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of following attributes
|}

This register is used to configure the total shader output map attributes.

=== GPUREG_SH_OUTMAP_O''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Semantic for the x component of the register.
|-
| 8-12
| unsigned, Semantic for the y component of the register.
|-
| 16-20
| unsigned, Semantic for the z component of the register.
|-
| 24-28
| unsigned, Semantic for the w component of the register.
|}

These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.
Semantics that have not been mapped to a component of an output register have a value of 1

Semantic values:

{| class="wikitable" border="1"
! Value
! Semantic
! Description
|-
| 0x00
| position.x
| rowspan="4" | Vertex Position
|-
| 0x01
| position.y
|-
| 0x02
| position.z
|-
| 0x03
| position.w
|-
| 0x04
| normquat.x
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)
|-
| 0x05
| normquat.y
|-
| 0x06
| normquat.z
|-
| 0x07
| normquat.w
|-
| 0x08
| color.r
| rowspan="4" | Vertex color
|-
| 0x09
| color.g
|-
| 0x0A
| color.b
|-
| 0x0B
| color.a
|-
| 0x0C
| texcoord0.u
| rowspan="2" | Texture coordinates for texture 0
|-
| 0x0D
| texcoord0.v
|-
| 0x0E
| texcoord1.u
| rowspan="2" | Texture coordinates for texture 1
|-
| 0x0F
| texcoord1.v
|-
| 0x10
| texcoord0.w
|

|-
| 0x12
| view.x
| rowspan="3" | View vector (for fragment lighting)
|-
| 0x13
| view.y
|-
| 0x14
| view.z

|-
| 0x16
| texcoord2.u
| rowspan="2" | Texture coordinates for texture 2
|-
| 0x17
| texcoord2.v

|-
| 0x1F
| Unused component
| Should be set for unused components of the output register
|}

=== GPUREG_EARLYDEPTH_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Early depth function
|}

This register configures the early depth test function.

Early depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| >=
|-
| 1
| >
|-
| 2
| <=
|-
| 3
| <
|}

=== GPUREG_EARLYDEPTH_TEST1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register sets whether the early depth test is enabled.

=== GPUREG_EARLYDEPTH_CLEAR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = clear)
|}

This register triggers clearing the early depth data.

=== GPUREG_SH_OUTATTR_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Use texture coordinates (0 = don't use, 1 = use)
|}

This register is used to configure the shader output attribute mode.

=== GPUREG_SCISSORTEST_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Enabled (0 = disabled, 3 = enabled)
|}

This register is used to enable scissor testing.

=== GPUREG_SCISSORTEST_POS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X1
|-
| 16-25
| unsigned, Y1
|}

This register is used to configure the scissor test start position.

=== GPUREG_SCISSORTEST_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X2
|-
| 16-25
| unsigned, Y2
|}

This register is used to configure the scissor test end position.

=== GPUREG_VIEWPORT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| signed, X
|-
| 16-25
| signed, Y
|}

This register is used to configure the viewport position.

=== GPUREG_EARLYDEPTH_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| unsigned, Clear value
|}

This register is used to configure the early depth clear value.

=== GPUREG_DEPTHMAP_ENABLE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable depth range.

=== GPUREG_RENDERBUF_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register is used to configure the output framebuffer dimensions.

=== GPUREG_SH_OUTATTR_CLOCK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, 'position.z' present (0 = absent, 1 = present)
|-
| 1
| unsigned, 'color' component present (0 = absent, 1 = present)
|-
| 8
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)
|-
| 9
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)
|-
| 10
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)
|-
| 16
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)
|-
| 24
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)
|}

This register controls the clock supply to parts relating to certain attributes.

== Texturing registers ==

=== GPUREG_TEXUNIT_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| 0x0
|-
| 8-9
| unsigned, Texture 3 coordinates
|-
| 10
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)
|-
| 12
| 0x1
|-
| 13
| unsigned, Texture 2 coordinates
|-
| 16
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)
|-
| 17-31
| 0x0
|}

This register is used to enable texture units.

Texture 3 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 0
|-
| 1
| Texture 1
|-
| 2
| Texture 2
|}

Texture 2 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 2
|-
| 1
| Texture 1
|}

=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to set a texture unit's border color.

=== GPUREG_TEXUNIT''i''_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Height
|-
| 16-26
| unsigned, Width
|}

This register is used to set a texture unit's dimensions.

=== GPUREG_TEXUNIT''i''_PARAM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, Magnification filter
|-
| 2
| unsigned, Minification filter
|-
| 4-5
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4
|-
| 8-10
| unsigned, Wrap T
|-
| 12-14
| unsigned, Wrap S
|-
| 16-17
| 0x0
|-
| 20
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)
|-
| 24
| unsigned, Mipmap filter
|-
| 28-30
| unsigned, Type (Texture 0 only)
|}

This register is used to set a texture unit's extra parameters.

Filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|}

Wrap values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to edge
|-
| 1
| Clamp to border
|-
| 2
| Repeat
|-
| 3
| Mirrored repeat
|}

Type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 2D
|-
| 1
| Cube map
|-
| 2
| Shadow 2D
|-
| 3
| Projection
|-
| 4
| Shadow cube
|-
| 5
| Disabled
|}

=== GPUREG_TEXUNIT''i''_LOD ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.4.8, Bias
|-
| 16-19
| unsigned, Max Level
|-
| 24-27
| unsigned, Min Level
|}

This register is used to configure a texture unit's level of detail.

=== GPUREG_TEXUNIT''i''_ADDR''i'' ===

First ADDR register:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Texture physical address >> 3
|}

Subsequent ADDR registers:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-21
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)
|}

This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.

If the texture is a cube:

{| class="wikitable" border="1"
! Register
! Description
|-
| ADDR1
| Positive X
|-
| ADDR2
| Negative X
|-
| ADDR3
| Positive Y
|-
| ADDR4
| Negative Y
|-
| ADDR5
| Positive Z
|-
| ADDR6
| Negative Z
|}

Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.

=== GPUREG_TEXUNIT''i''_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Perspective (0 = perspective, 1 = not perspective)
|-
| 1-23
| fixed0.0.24, Z bias (upper 23 bits)
|}

This register is used to set a texture unit's shadow texture properties.

=== GPUREG_TEXUNIT''i''_TYPE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Format
|}

This register is used to set a texture unit's data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
! GL Format
! GL Data Type
|-
| 0x0
| RGBA8888
| GL_RGBA
| GL_UNSIGNED_BYTE
|-
| 0x1
| RGB888
| GL_RGB
| GL_UNSIGNED_BYTE
|-
| 0x2
| RGBA5551
| GL_RGBA
| GL_UNSIGNED_SHORT_5_5_5_1
|-
| 0x3
| RGB565
| GL_RGB
| GL_UNSIGNED_SHORT_5_6_5
|-
| 0x4
| RGBA4444
| GL_RGBA
| GL_UNSIGNED_SHORT_4_4_4_4
|-
| 0x5
| IA8
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x6
| HILO8
|
|
|-
| 0x7
| I8
| GL_LUMINANCE
| GL_UNSIGNED_BYTE
|-
| 0x8
| A8
| GL_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x9
| IA44
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE_4_4_EXT
|-
| 0xA
| I4
|
|
|-
| 0xB
| A4
| GL_ALPHA
| GL_UNSIGNED_NIBBLE_EXT
|-
| 0xC
| ETC1
| GL_ETC1_RGB8_OES
|
|-
| 0xD
| ETC1A4
|
|
|}

=== GPUREG_LIGHTING_ENABLE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable lighting.

=== GPUREG_TEXUNIT3_PROCTEX0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, U-direction clamp
|-
| 3-5
| unsigned, V-direction clamp
|-
| 6-9
| unsigned, RGB mapping function
|-
| 10-13
| unsigned, Alpha mapping function
|-
| 14
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)
|-
| 15
| unsigned, Noise enabled (0 = disabled, 1 = enabled)
|-
| 16-17
| unsigned, U-direction shift
|-
| 18-19
| unsigned, V-direction shift
|-
| 20-27
| float1.5.10, Texture bias (lower 8 bits)
|}

This register is used to configure the procedural texture unit.

Clamp values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to zero
|-
| 1
| Clamp to edge
|-
| 2
| Symmetrical repeat
|-
| 3
| Mirrored repeat
|-
| 4
| Pulse
|}

Mapping function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| U
|-
| 1
| U²
|-
| 2
| V
|-
| 3
| V²
|-
| 4
| (U + V) / 2
|-
| 5
| (U² + V²) / 2
|-
| 6
| sqrt(U² + V²)
|-
| 7
| Minimum
|-
| 8
| Maximum
|-
| 9
| Rmax
|}

Shift values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Odd
|-
| 2
| Even
|}

=== GPUREG_TEXUNIT3_PROCTEX1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, U-direction noise amplitude
|-
| 16-31
| float1.5.10, U-direction noise phase
|}

This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, V-direction noise amplitude
|-
| 16-31
| float1.5.10, V-direction noise phase
|}

This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, U-direction noise frequency
|-
| 16-31
| float1.5.10, V-direction noise frequency
|}

This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.

=== GPUREG_TEXUNIT3_PROCTEX4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Minification filter
|-
| 3-6
| Min LOD (usually 0)
|-
| 7-10
| Max LOD (usually 6)
|-
| 11-18
| unsigned, Texture width
|-
| 19-26
| float1.5.10, Texture bias (upper 8 bits)
|}

This register is used to configure the procedural texture unit.

Minification filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|-
| 2
| Nearest, Mipmap Nearest
|-
| 3
| Linear, Mipmap Nearest
|-
| 4
| Nearest, Mipmap Linear
|-
| 5
| Linear, Mipmap Linear
|}

=== GPUREG_TEXUNIT3_PROCTEX5 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Texture offset (Mipmap level 0 / base level)
|-
| 8-15
| unsigned, mipmap level 1 offset (usually 0x80)
|-
| 16-23
| unsigned, mipmap level 2 offset (usually 0xC0)
|-
| 24-31
| unsigned, mipmap level 3 offset (usually 0xE0)
|}

This register is used to set the procedural texture unit's offset. Mipmap level 4-7 seems to be hardcoded at offset 0xF0, 0xF8, 0xFC and 0xFE .

=== GPUREG_PROCTEX_LUT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Index
|-
| 8-11
| unsigned, Reference table
|}

This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.

Reference table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Noise table
|-
| 2
| RGB mapping function table
|-
| 3
| Alpha mapping function table
|-
| 4
| Color table
|-
| 5
| Color difference table
|}

=== GPUREG_PROCTEX_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.

==== Noise Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement ( [0.5,1.0) mapped to [-1.0,0) ), Difference from next element
|}

==== RGB Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement, Difference from next element
|}

==== Alpha Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement, Difference from next element
|}

==== Color Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

==== Color Difference Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Half of red difference between current and next color table elements
|-
| 8-15
| signed, Half of green difference between current and next color table elements
|-
| 16-23
| signed, Half of blue difference between current and next color table elements
|-
| 24-31
| signed, Half of alpha difference between current and next color table elements
|}

=== GPUREG_TEXENV''i''_SOURCE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB source 0
|-
| 4-7
| unsigned, RGB source 1
|-
| 8-11
| unsigned, RGB source 2
|-
| 16-19
| unsigned, Alpha source 0
|-
| 20-23
| unsigned, Alpha source 1
|-
| 24-27
| unsigned, Alpha source 2
|}

This register configures a texture combiner's sources.

Source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Primary color
|-
| 1
| Fragment primary color
|-
| 2
| Fragment secondary color
|-
| 3
| Texture 0
|-
| 4
| Texture 1
|-
| 5
| Texture 2
|-
| 6
| Texture 3
|-
| 13
| Previous buffer
|-
| 14
| Constant (from GPUREG_TEXENV''i''_COLOR)
|-
| 15
| Previous
|}

Using previous source in the first TEV stage returns the primary color, while previous buffer returns zero.

=== GPUREG_TEXENV''i''_OPERAND ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB operand 0
|-
| 4-7
| unsigned, RGB operand 1
|-
| 8-11
| unsigned, RGB operand 2
|-
| 12-14
| unsigned, Alpha operand 0
|-
| 16-18
| unsigned, Alpha operand 1
|-
| 20-22
| unsigned, Alpha operand 2
|}

This register configures a texture combiner's operands.

RGB operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source color
|-
| 1
| One minus source color
|-
| 2
| Source alpha
|-
| 3
| One minus source alpha
|-
| 4
| Source red
|-
| 5
| One minus source red
|-
| 8
| Source green
|-
| 9
| One minus source green
|-
| 12
| Source blue
|-
| 13
| One minus source blue
|}

Alpha operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source alpha
|-
| 1
| One minus source alpha
|-
| 2
| Source red
|-
| 3
| One minus source red
|-
| 4
| Source green
|-
| 5
| One minus source green
|-
| 6
| Source blue
|-
| 7
| One minus source blue
|}

=== GPUREG_TEXENV''i''_COMBINER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB combine
|-
| 16-19
| unsigned, Alpha combine
|}

This register configures a texture combiner's combine mode.

Combine values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Replace
|-
| 1
| Modulate
|-
| 2
| Add
|-
| 3
| Add signed
|-
| 4
| Interpolate
|-
| 5
| Subtract
|-
| 6
| Dot3 RGB
|-
| 7
| Dot3 RGBA
|-
| 8
| Multiply then add
|-
| 9
| Add then multiply
|}

=== GPUREG_TEXENV''i''_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register configures a texture combiner's constant color.

=== GPUREG_TEXENV''i''_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, RGB scale
|-
| 16-17
| unsigned, Alpha scale
|}

This register configures a texture combiner's scale value.

Scale values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|}

=== GPUREG_TEXENV_UPDATE_BUFFER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fog mode
|-
| 3
| unsigned, Shading density source
|-
| 8
| unsigned, TexEnv 1 RGB buffer input
|-
| 9
| unsigned, TexEnv 2 RGB buffer input
|-
| 10
| unsigned, TexEnv 3 RGB buffer input
|-
| 11
| unsigned, TexEnv 4 RGB buffer input
|-
| 12
| unsigned, TexEnv 1 alpha buffer input
|-
| 13
| unsigned, TexEnv 2 alpha buffer input
|-
| 14
| unsigned, TexEnv 3 alpha buffer input
|-
| 15
| unsigned, TexEnv 4 alpha buffer input
|-
| 16
| unsigned, Z flip (0 = don't flip, 1 = flip)
|-
| 24-25
| 0x0
|}

This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.

Fog mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Disabled
|-
| 5
| Fog
|-
| 7
| Gas
|}

Shading density source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Plain density
|-
| 1
| Depth density
|}

Buffer input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Previous buffer
|-
| 1
| Previous
|}

=== GPUREG_FOG_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

This register is used to configure the color of fog.

=== GPUREG_GAS_ATTENUATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas density attenuation
|}

This register is used to configure the gas density attenuation.

=== GPUREG_GAS_ACCMAX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas maximum density accumulation
|}

This register is used to configure the gas maximum density accumulation.

=== GPUREG_FOG_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.

=== GPUREG_FOG_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.

==== Fog Look-Up Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Difference from next element
|-
| 13-23
| fixed0.0.11, Value
|}

=== GPUREG_TEXENV_BUFFER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the texture combiner buffer color.

== Framebuffer registers ==

=== GPUREG_COLOR_OPERATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Fragment operation mode
|-
| 8
| unsigned, Blend mode
|-
| 16-25
| 0x0E4
|}

This register is used to configure the fragment operation mode and whether to use logic ops or blending.

Fragment operation mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Default
|-
| 1
| Gas
|-
| 3
| Shadow
|}

Blend mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Logic op
|-
| 1
| Blend
|}

=== GPUREG_BLEND_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, RGB equation
|-
| 8-10
| unsigned, Alpha equation
|-
| 16-19
| unsigned, RGB source function
|-
| 20-23
| unsigned, RGB destination function
|-
| 24-27
| unsigned, Alpha source function
|-
| 28-31
| unsigned, Alpha destination function
|}

This register is used to configure the blending function.

'''Equation values:'''

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Add
|-
| 1
| Subtract
|-
| 2
| Reverse subtract
|-
| 3
| Minimum
|-
| 4
| Maximum
|}

Blend equations 5, 6, 7 appear to behave the same as blend equation 0 (Add)

'''Function values:'''

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Zero
|-
| 1
| One
|-
| 2
| Source color
|-
| 3
| One minus source color
|-
| 4
| Destination color
|-
| 5
| One minus destination color
|-
| 6
| Source alpha
|-
| 7
| One minus source alpha
|-
| 8
| Destination alpha
|-
| 9
| One minus destination alpha
|-
| 10
| Constant color
|-
| 11
| One minus constant color
|-
| 12
| Constant alpha
|-
| 13
| One minus constant alpha
|-
| 14
| Source alpha saturate
|}

=== GPUREG_LOGIC_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Logic op
|}

This register is used to configure the logic op.

Logic op values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clear
|-
| 1
| AND
|-
| 2
| Reverse AND
|-
| 3
| Copy
|-
| 4
| Set
|-
| 5
| Inverted copy
|-
| 6
| Noop
|-
| 7
| Invert
|-
| 8
| NAND
|-
| 9
| OR
|-
| 10
| NOR
|-
| 11
| XOR
|-
| 12
| Equivalent
|-
| 13
| Inverted AND
|-
| 14
| Reverse OR
|-
| 15
| Inverted OR
|}

=== GPUREG_BLEND_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the blending color.

=== GPUREG_FRAGOP_ALPHA_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Reference value
|}

This register is used to configure alpha testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Buffer mask
|-
| 16-23
| signed, Reference value
|-
| 24-31
| unsigned, Mask
|}

This register is used to configure stencil testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fail operation
|-
| 4-6
| unsigned, Z-fail operation
|-
| 8-10
| unsigned, Z-pass operation
|}

This register is used to configure stencil result operations.

Operation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Keep
|-
| 1
| Zero
|-
| 2
| Replace
|-
| 3
| Increment
|-
| 4
| Decrement
|-
| 5
| Invert
|-
| 6
| Increment and wrap
|-
| 7
| Decrement and wrap
|}

=== GPUREG_DEPTH_COLOR_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Depth function
|-
| 8
| unsigned, Red write enabled (0 = disabled, 1 = enabled)
|-
| 9
| unsigned, Green write enabled (0 = disabled, 1 = enabled)
|-
| 10
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)
|-
| 11
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)
|-
| 12
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
|}

This register is used to depth testing and framebuffer write masking.

Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.

Depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = invalidate)
|-
| 1-31
| 0x0
|}

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = flush)
|-
| 1-31
| 0x0
|}

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_COLORBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow read (0 = disable, 0xF = enable)
|}

This register configures read access from the color buffer.

=== GPUREG_COLORBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow write (0 = disable, 0xF = enable)
|}

This register configures write access to the color buffer.

=== GPUREG_DEPTHBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil read (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth read (0 = disable, 1 = enable)
|}

This register configures read access from the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil write (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth write (0 = disable, 1 = enable)
|}

This register configures write access to the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Format
|}

This register configures the depth buffer data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil
|}

=== GPUREG_COLORBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Pixel size
|-
| 16-18
| unsigned, Format
|}

This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.

Pixel size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit color
|-
| 2
| 32-bit color
|}

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| RGBA8/Gas
|-
| 2
| RGB5A1
|-
| 3
| RGB565
|-
| 4
| RGBA4
|}

=== GPUREG_EARLYDEPTH_TEST2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register enables the early depth test.

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Render block mode
|}

This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

Render block mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8x8 blocks
|-
| 1
| 32x32 blocks
|}

=== GPUREG_DEPTHBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Depth buffer physical address >> 3
|}

This register configures the depth buffer physical address.

=== GPUREG_COLORBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Color buffer physical address >> 3
|}

This register configures the color buffer physical address.

=== GPUREG_FRAMEBUFFER_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register configures the framebuffer dimensions.

=== GPUREG_GAS_LIGHT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Planar shading minimum intensity
|-
| 8-15
| unsigned, Planar shading maximum intensity
|-
| 16-23
| unsigned, Planar shading density attenuation
|}

This register configures gas light planar shading.

=== GPUREG_GAS_LIGHT_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading minimum intensity
|-
| 8-15
| unsigned, View shading maximum intensity
|-
| 16-23
| unsigned, View shading density attenuation
|}

This register configures gas light view shading.

=== GPUREG_GAS_LIGHT_Z_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading effect in line-of-sight direction
|-
| 8
| Gas color LUT input
|}

This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.

Color LUT input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Gas density
|-
| 1
| Light factor
|}

=== GPUREG_GAS_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.

=== GPUREG_GAS_LUT_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.

==== Gas Look-Up Table ====

16 elements:

First 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Red
|-
| 8-15
| signed, Green
|-
| 16-23
| signed, Blue
|}

Last 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

=== GPUREG_GAS_DELTAZ_DEPTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| fixed0.16.8, Depth direction attenuation proportion
|-
| 24-25
| unsigned, Depth function
|}

This register is used to configure the gas depth direction attenuation proportion, as well as the gas depth function.

Gas depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Greater than/Greater than or equal
|-
| 3
| Less than/Less than or equal/Equal/Not equal
|}

=== GPUREG_FRAGOP_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Sum of penumbra scale and penumbra bias
|-
| 16-31
| float1.5.10, Penumbra scale with reversed sign
|}

This register is used to configure shadow properties.

== Fragment lighting registers ==

=== GPUREG_LIGHT''i''_SPECULAR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.

=== GPUREG_LIGHT''i''_SPECULAR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.

=== GPUREG_LIGHT''i''_DIFFUSE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

=== GPUREG_LIGHT''i''_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.

=== GPUREG_LIGHT''i''_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, X coordinate
|-
| 16-31
| float1.5.10, Y coordinate
|}

These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Z coordinate
|}

These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, X coordinate (negated)
|-
| 16-28
| fixed1.1.11, Y coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Z coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Light type (0 = positional light, 1 = directional light)
|-
| 1
| unsigned, Two side diffuse (0 = one side, 1 = both sides)
|-
| 2
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)
|-
| 3
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)
|}

This register configures a light's properties.

=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation bias
|}

These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation scale
|}

These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHTING_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

=== GPUREG_LIGHTING_NUM_LIGHTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of active lights - 1
|}

This register configures the number of active lights.

=== GPUREG_LIGHTING_CONFIG0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)
|-
| 2-3
| unsigned, Fresnel selector
|-
| 4-7
| unsigned, Light environment configuration
|-
| 8-11
| 0x4
|-
| 16
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)
|-
| 17
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)
|-
| 18
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)
|-
| 19
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)
|-
| 22-23
| unsigned, Bump map texture unit
|-
| 24-25
| unsigned, Shadow map texture unit
|-
| 27
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)
|-
| 28-29
| unsigned, Bump mode
|-
| 30
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)
|-
| 31
| 0x1
|}

This register configures the light environment.

Fresnel selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Primary alpha
|-
| 2
| Secondary alpha
|-
| 3
| Primary and secondary alpha
|}

The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.

Light environment configuration values:

{| class="wikitable" border="1"
! Value
! Description
! Available LUTs
|-
| 0
| Configuration 0
| D0, RR, SP, DA
|-
| 1
| Configuration 1
| FR, RR, SP, DA
|-
| 2
| Configuration 2
| D0, D1, RR, DA
|-
| 3
| Configuration 3
| D0, D1, FR, DA
|-
| 4
| Configuration 4
| All except for FR
|-
| 5
| Configuration 5
| All except for D1
|-
| 6
| Configuration 6
| All except for RB and RG
|-
| 8
| Configuration 7
| All
|}

Bump mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Not used
|-
| 1
| Use as bump map
|-
| 2
| Use as tangent map
|}

=== GPUREG_LIGHTING_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)
|-
| 1
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)
|-
| 2
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)
|-
| 3
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)
|-
| 4
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)
|-
| 6
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)
|-
| 7
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)
|-
| 8
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)
|-
| 10
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)
|-
| 11
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)
|-
| 12
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)
|-
| 14
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)
|-
| 15
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)
|-
| 16
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)
|-
| 18
| 0x1
|-
| 19
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
|-
| 20
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 1 = disabled)
|-
| 22
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 1 = disabled)
|-
| 24
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 26
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 27
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 28
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 29
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 30
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 31
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)
|}

This register is used to disable various aspects of the light environment.

=== GPUREG_LIGHTING_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Starting index
|-
| 8-12
| unsigned, Look-up table
|}

This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.

Lookup table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| D0
|-
| 1
| D1
|-
| 3
| FR
|-
| 4
| RB
|-
| 5
| RG
|-
| 6
| RR
|-
| 8-15
| SP0-7
|-
| 16-23
| DA0-7
|}

=== GPUREG_LIGHTING_ENABLE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Disabled (0 = enabled, 1 = disabled)
|}

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

=== GPUREG_LIGHTING_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

Lighting LUT data is written here.

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.

Format of an entry:

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Entry value
|-
| 12-23
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation
|}

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)
|}

This register controls whether the absolute value of the input is taken before using a LUT.

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Input selector for D0
|-
| 4-6
| unsigned, Input selector for D1
|-
| 8-10
| unsigned, Input selector for SP
|-
| 12-14
| unsigned, Input selector for FR
|-
| 16-18
| unsigned, Input selector for RB
|-
| 20-22
| unsigned, Input selector for RG
|-
| 24-26
| unsigned, Input selector for RR
|}

This register selects the input from LUTs.

Input selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Scaler selector for D0
|-
| 4-6
| unsigned, Scaler selector for D1
|-
| 8-10
| unsigned, Scaler selector for SP
|-
| 12-14
| unsigned, Scaler selector for FR
|-
| 16-18
| unsigned, Scaler selector for RB
|-
| 20-22
| unsigned, Scaler selector for RG
|-
| 24-26
| unsigned, Scaler selector for RR
|}

This register controls the scaling that is applied to the output of a LUT.

Scaler selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, ID of the 1st enabled light
|-
| 4-6
| unsigned, ID of the 2nd enabled light
|-
| 8-10
| unsigned, ID of the 3rd enabled light
|-
| 12-14
| unsigned, ID of the 4th enabled light
|-
| 16-18
| unsigned, ID of the 5th enabled light
|-
| 20-22
| unsigned, ID of the 6th enabled light
|-
| 24-26
| unsigned, ID of the 7th enabled light
|-
| 28-30
| unsigned, ID of the 8th enabled light
|}

This register sets the IDs of enabled light sources.

== Geometry pipeline registers ==

=== GPUREG_ATTRIBBUFFERS_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-28
| unsigned, Vertex arrays base address
|}

This register sets the base address of all vertex arrays.

=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 0 type
|-
| 2-3
| unsigned, Vertex attribute 0 size
|-
| 4-5
| unsigned, Vertex attribute 1 type
|-
| 6-7
| unsigned, Vertex attribute 1 size
|-
| 8-9
| unsigned, Vertex attribute 2 type
|-
| 10-11
| unsigned, Vertex attribute 2 size
|-
| 12-13
| unsigned, Vertex attribute 3 type
|-
| 14-15
| unsigned, Vertex attribute 3 size
|-
| 16-17
| unsigned, Vertex attribute 4 type
|-
| 18-19
| unsigned, Vertex attribute 4 size
|-
| 20-21
| unsigned, Vertex attribute 5 type
|-
| 22-23
| unsigned, Vertex attribute 5 size
|-
| 24-25
| unsigned, Vertex attribute 6 type
|-
| 26-27
| unsigned, Vertex attribute 6 size
|-
| 28-29
| unsigned, Vertex attribute 7 type
|-
| 30-31
| unsigned, Vertex attribute 7 size
|}

This register configures the types and sizes of the first 8 vertex attributes.

Vertex attribute type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Byte
|-
| 1
| Unsigned byte
|-
| 2
| Short
|-
| 3
| Float
|}

Vertex attribute size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8 bits
|-
| 1
| 16 bits
|-
| 2
| 24 bits
|-
| 3
| 32 bits
|}

=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 8 type
|-
| 2-3
| unsigned, Vertex attribute 8 size
|-
| 4-5
| unsigned, Vertex attribute 9 type
|-
| 6-7
| unsigned, Vertex attribute 9 size
|-
| 8-9
| unsigned, Vertex attribute 10 type
|-
| 10-11
| unsigned, Vertex attribute 10 size
|-
| 12-13
| unsigned, Vertex attribute 11 type
|-
| 14-15
| unsigned, Vertex attribute 11 size
|-
| 16-27
| unsigned, Fixed vertex attribute mask
|-
| 28-31
| unsigned, Total vertex attribute count - 1
|}

This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.

See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.

=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|}

This register configures the offset of a vertex array from the base vertex arrays address.

=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 1
|-
| 4-7
| unsigned, Component 2
|-
| 8-11
| unsigned, Component 3
|-
| 12-15
| unsigned, Component 4
|-
| 16-19
| unsigned, Component 5
|-
| 20-23
| unsigned, Component 6
|-
| 24-27
| unsigned, Component 7
|-
| 28-31
| unsigned, Component 8
|}

This register configures the first 8 component types of a vertex array.

Component values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Vertex attribute 0
|-
| 1
| Vertex attribute 1
|-
| 2
| Vertex attribute 2
|-
| 3
| Vertex attribute 3
|-
| 4
| Vertex attribute 4
|-
| 5
| Vertex attribute 5
|-
| 6
| Vertex attribute 6
|-
| 7
| Vertex attribute 7
|-
| 8
| Vertex attribute 8
|-
| 9
| Vertex attribute 9
|-
| 10
| Vertex attribute 10
|-
| 11
| Vertex attribute 11
|-
| 12
| 4-byte padding
|-
| 13
| 8-byte padding
|-
| 14
| 12-byte padding
|-
| 15
| 16-byte padding
|}

=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 9
|-
| 4-7
| unsigned, Component 10
|-
| 8-11
| unsigned, Component 11
|-
| 12-15
| unsigned, Component 12
|-
| 16-23
| unsigned, Bytes per vertex
|-
| 28-31
| unsigned, Total number of components
|}

This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.

See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.

=== GPUREG_INDEXBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|-
| 31
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)
|}

This register configures the index array used when drawing elements.

=== GPUREG_NUMVERTICES ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Number of vertices to render
|}

This register sets the number of vertices to render.

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|-
| 9
| 0x0
|-
| 31
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_VERTEX_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Starting vertex offset
|}

This register sets the offset of the first vertex in an array to render.

=== GPUREG_POST_VERTEX_CACHE_NUM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)
|}

This register configures the post-vertex cache.

=== GPUREG_DRAWARRAYS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw arrays)
|}

This register triggers drawing vertex arrays.

=== GPUREG_DRAWELEMENTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw elements)
|}

This register triggers drawing vertex array elements.

=== GPUREG_VTX_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)
|}

This register triggers clearing the post-vertex cache.

=== GPUREG_FIXEDATTRIB_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)
|}

This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

=== GPUREG_FIXEDATTRIB_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| colspan="2" | '''DATA0:'''
|-
| 0-7
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)
|-
| 8-31
| float1.7.16, Vertex attribute element 4 (W)
|-
| colspan="2" | '''DATA1:'''
|-
| 0-15
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)
|-
| 16-31
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)
|-
| colspan="2" | '''DATA2:'''
|-
| 0-23
| float1.7.16, Vertex attribute element 1 (X)
|-
| 24-31
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)
|}

Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.

=== GPUREG_CMDBUF_SIZE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 0 >> 3
|}

This register sets the size of the first command buffer.

=== GPUREG_CMDBUF_SIZE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 1 >> 3
|}

This register sets the size of the second command buffer.

=== GPUREG_CMDBUF_ADDR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 0 >> 3
|}

This register sets the physical address of the first command buffer.

=== GPUREG_CMDBUF_ADDR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 1 >> 3
|}

This register sets the physical address of the second command buffer.

=== GPUREG_CMDBUF_JUMP0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)
|}

This register triggers a jump to the first command buffer.

=== GPUREG_CMDBUF_JUMP1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)
|}

This register triggers a jump to the second command buffer.

=== GPUREG_VSH_NUM_ATTR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader input attributes - 1
|}

This register sets the number of vertex shader input attributes.

=== GPUREG_VSH_COM_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)
|}

This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.

=== GPUREG_START_DRAW_FUNC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Mode (0 = drawing, 1 = configuration)
|-
| 1-7
| 0x0
|}

This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.

=== GPUREG_VSH_OUTMAP_TOTAL1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_VSH_OUTMAP_TOTAL2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_GSH_MISC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)
|}

This register configures miscellaneous geometry shader properties.

=== GPUREG_GEOSTAGE_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_GSH_MISC1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)
|}

This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.

=== GPUREG_PRIMITIVE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|-
| 8-9
| unsigned, Primitive mode
|}

This register configures primitive drawing.

Primitive mode value:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Triangles
|-
| 1
| Triangle strip
|-
| 2
| Triangle fan
|-
| 3
| Geometry primitive
|}

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = reset primitive)
|-
| 1-31
| 0x0
|}

This register triggers resetting primitive drawing.

== Shader registers ==

=== GPUREG_''SH''_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Boolean register b0 value (0 = false, 1 = true)
|-
| 1
| unsigned, Boolean register b1 value (0 = false, 1 = true)
|-
| 2
| unsigned, Boolean register b2 value (0 = false, 1 = true)
|-
| 3
| unsigned, Boolean register b3 value (0 = false, 1 = true)
|-
| 4
| unsigned, Boolean register b4 value (0 = false, 1 = true)
|-
| 5
| unsigned, Boolean register b5 value (0 = false, 1 = true)
|-
| 6
| unsigned, Boolean register b6 value (0 = false, 1 = true)
|-
| 7
| unsigned, Boolean register b7 value (0 = false, 1 = true)
|-
| 8
| unsigned, Boolean register b8 value (0 = false, 1 = true)
|-
| 9
| unsigned, Boolean register b9 value (0 = false, 1 = true)
|-
| 10
| unsigned, Boolean register b10 value (0 = false, 1 = true)
|-
| 11
| unsigned, Boolean register b11 value (0 = false, 1 = true)
|-
| 12
| unsigned, Boolean register b12 value (0 = false, 1 = true)
|-
| 13
| unsigned, Boolean register b13 value (0 = false, 1 = true)
|-
| 14
| unsigned, Boolean register b14 value (0 = false, 1 = true)
|-
| 15
| unsigned, Boolean register b15 value (0 = false, 1 = true)
|-
| 16-31
| 0x7FFF
|}

This register is used to set a shader unit's boolean registers.

=== GPUREG_''SH''_INTUNIFORM_I''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Integer register i''i'' X value
|-
| 8-15
| unsigned, Integer register i''i'' Y value
|-
| 16-23
| unsigned, Integer register i''i'' Z value
|-
| 24-31
| unsigned, Integer register i''i'' W value
|}

These registers are used to set a shader unit's integer registers.

=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Input vertex attributes - 1
|-
| 8-15
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)
|-
| 16-23
| 0x0
|-
| 24-31
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)
|}

This register is used to configure a shader unit's input buffer.

=== GPUREG_''SH''_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Code entry point offset, in 32-bit words
|-
| 16-31
| 0x7FFF
|}

This register sets a shader unit's code entry point.

For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.

For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 0 input register index
|-
| 4-7
| unsigned, Vertex attribute 1 input register index
|-
| 8-11
| unsigned, Vertex attribute 2 input register index
|-
| 12-15
| unsigned, Vertex attribute 3 input register index
|-
| 16-19
| unsigned, Vertex attribute 4 input register index
|-
| 20-23
| unsigned, Vertex attribute 5 input register index
|-
| 24-27
| unsigned, Vertex attribute 6 input register index
|-
| 28-31
| unsigned, Vertex attribute 7 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 8 input register index
|-
| 4-7
| unsigned, Vertex attribute 9 input register index
|-
| 8-11
| unsigned, Vertex attribute 10 input register index
|-
| 12-15
| unsigned, Vertex attribute 11 input register index
|-
| 16-19
| unsigned, Vertex attribute 12 input register index
|-
| 20-23
| unsigned, Vertex attribute 13 input register index
|-
| 24-27
| unsigned, Vertex attribute 14 input register index
|-
| 28-31
| unsigned, Vertex attribute 15 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_''SH''_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)
|-
| 4
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)
|-
| 5
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)
|-
| 6
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)
|-
| 7
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 8
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 9
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 10
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 11
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 12
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 13
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 14
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 15
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 16-31
| 0x0
|}

This register toggles a shader unit's output registers.

=== GPUREG_''SH''_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Signal transfer end (0 = idle, non-zero = signal)
|}

This register's value should be set to 1 in order to finalize the transfer of shader code.

=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)
|}

This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.

=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Floating-point register component data
|}

This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_''SH''_CODETRANSFER_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader code offset
|}

This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.

=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader instruction data
|}

This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.

=== GPUREG_''SH''_OPDESCS_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader operand descriptor offset
|}

This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.

=== GPUREG_''SH''_OPDESCS_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader operand descriptor data
|}

This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.

GPU/Internal Registers

2023-08-25T19:38:02Z

Emufan4568: Document previous usage in the first TEV stage

[[Category:GPU]]

== Overview ==

GPU internal registers are written to through GPU commands. They are used to control the GPU's behavior, that is to say tell it to draw stuff and how we want it drawn.

Each command is at least 8 bytes wide. The first word is the command parameter and the second word constitutes the command header. Optionally, more parameter words may follow (potentially including a padding word to align commands to multiples of 8 bytes).

In the simplest case, a command is exactly 8 bytes wide. You can think of such a command as writing the parameter word to an internal register (the index of which is given in the command header). The more general case where more than one parameter word is given is equivalent to multiple simple commands (one for each parameter word). If consecutive writing mode is enabled in the command header, the current command index will be incremented after each parameter write. Otherwise, the parameters will be consecutively written to the same register.

For example, the sequence "0xAAAAAAAA 0x802F011C 0xBBBBBBBB 0xCCCCCCCC" is equivalent to a call to commands 0xF011C with parameter 0xAAAAAAAA, 0xF011D with parameter 0xBBBBBBBB and 0xF011E with parameter 0xCCCCCCCC. If consecutive writing mode were disabled, the command would be equivalent to three consecutive calls to 0xF011C (once with parameter 0xAAAAAAAA, once with 0xBBBBBBBB, and finally with 0xCCCCCCCC).

Invalid GPU command parameters including NaN floats can cause the GPU to hang, which then causes the GSP module to hang as well.

The size of GPU command buffers must be 0x10-byte aligned; the lower 3 bits of the size are cleared. A common pitfall is having the finalization command (write to register 0x0010) not executed because it was the last 8 bytes of a non-0x10 byte aligned command buffer, and having the GPU hang as a result.

=== Command Header ===
{| class="wikitable" border="1"
! Bit
! Description
|-
| 0-15
| Command ID
|-
| 16-19
| Parameter mask
|-
| 20-27
| Number of extra parameters (may be zero)
|-
| 28-30
| Unused
|-
| 31
| Consecutive writing mode
|}

=== Parameter masking ===

Using a value other than 0xF, parts of a word in internal GPU memory can be updated without touching the other bits of it. For example, setting bit 16 to zero indicates that the least significant byte of the parameter will not be overwritten, setting bit 17 to zero indicates that the parameter's second LSB will not be overwritten, etc. This means that for instance commands 0x00010107 and 0x00020107 refer to the same thing but write different parts of the parameter.

=== Types ===

There are three main types of registers :
* configuration registers, which directly map to various rendering properties (for example: [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]])
* data transfer registers, which can be seen as FIFOs that let us send sequential chunks of data to the GPU, such as shader code or 1D samplers (for example: [[#GPUREG_SH_CODETRANSFER_DATA|GPUREG_GSH_CODETRANSFER_DATA]])
* action triggering registers, which tell the GPU to do something, like draw a primitive (for example: [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]])

=== Aliases ===

It is possible for multiple register (sequential) IDs to correspond to the same register. This is done to leverage the consecutive writing mode for GPU commands, which makes it possible for a single command to write data to multiple sequential register IDs. For example, register IDs 02C1 through 02C8 all correspond to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']] so that a consecutively writing command based at 02C0 will write its first parameter to [[#GPUREG_VSH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]] and ever subsequent ones to [[#GPUREG_VSH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA''i'']]

=== Data Types ===

{| class="wikitable" border="1"
! Name
! Description
|-
| signed
| Signed integer
|-
| unsigned
| Unsigned integer
|-
| floatX.Y.Z
| Floating-point number with X sign bits, Y exponent bits, and Z mantissa bits
|-
| fixedX.Y.Z
| Fixed-point number with X sign bits, Y integer bits, and Z fractional bits
|}

== Register list ==

=== Miscellaneous registers (0x000-0x03F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0000
| [[#GPUREG_0000|GPUREG_0000]]
|
|
|-
| 0001
| [[#GPUREG_0001|GPUREG_0001]]
|
|
|-
| 0002
| [[#GPUREG_0002|GPUREG_0002]]
|
|
|-
| 0003
| [[#GPUREG_0003|GPUREG_0003]]
|
|
|-
| 0004
| [[#GPUREG_0004|GPUREG_0004]]
|
|
|-
| 0005
| [[#GPUREG_0005|GPUREG_0005]]
|
|
|-
| 0006
| [[#GPUREG_0006|GPUREG_0006]]
|
|
|-
| 0007
| [[#GPUREG_0007|GPUREG_0007]]
|
|
|-
| 0008
| [[#GPUREG_0008|GPUREG_0008]]
|
|
|-
| 0009
| [[#GPUREG_0009|GPUREG_0009]]
|
|
|-
| 000A
| [[#GPUREG_000A|GPUREG_000A]]
|
|
|-
| 000B
| [[#GPUREG_000B|GPUREG_000B]]
|
|
|-
| 000C
| [[#GPUREG_000C|GPUREG_000C]]
|
|
|-
| 000D
| [[#GPUREG_000D|GPUREG_000D]]
|
|
|-
| 000E
| [[#GPUREG_000E|GPUREG_000E]]
|
|
|-
| 000F
| [[#GPUREG_000F|GPUREG_000F]]
|
|
|-
| 0010
| [[#GPUREG_FINALIZE|GPUREG_FINALIZE]]
|
|PICA_REG_INTERRUPT
|-
| 0011
| [[#GPUREG_0011|GPUREG_0011]]
|
|
|-
| 0012
| [[#GPUREG_0012|GPUREG_0012]]
|
|
|-
| 0013
| [[#GPUREG_0013|GPUREG_0013]]
|
|
|-
| 0014
| [[#GPUREG_0014|GPUREG_0014]]
|
|
|-
| 0015
| [[#GPUREG_0015|GPUREG_0015]]
|
|
|-
| 0016
| [[#GPUREG_0016|GPUREG_0016]]
|
|
|-
| 0017
| [[#GPUREG_0017|GPUREG_0017]]
|
|
|-
| 0018
| [[#GPUREG_0018|GPUREG_0018]]
|
|
|-
| 0019
| [[#GPUREG_0019|GPUREG_0019]]
|
|
|-
| 001A
| [[#GPUREG_001A|GPUREG_001A]]
|
|
|-
| 001B
| [[#GPUREG_001B|GPUREG_001B]]
|
|
|-
| 001C
| [[#GPUREG_001C|GPUREG_001C]]
|
|
|-
| 001D
| [[#GPUREG_001D|GPUREG_001D]]
|
|
|-
| 001E
| [[#GPUREG_001E|GPUREG_001E]]
|
|
|-
| 001F
| [[#GPUREG_001F|GPUREG_001F]]
|
|
|-
| 0020
| [[#GPUREG_0020|GPUREG_0020]]
|
|
|-
| 0021
| [[#GPUREG_0021|GPUREG_0021]]
|
|
|-
| 0022
| [[#GPUREG_0022|GPUREG_0022]]
|
|
|-
| 0023
| [[#GPUREG_0023|GPUREG_0023]]
|
|
|-
| 0024
| [[#GPUREG_0024|GPUREG_0024]]
|
|
|-
| 0025
| [[#GPUREG_0025|GPUREG_0025]]
|
|
|-
| 0026
| [[#GPUREG_0026|GPUREG_0026]]
|
|
|-
| 0027
| [[#GPUREG_0027|GPUREG_0027]]
|
|
|-
| 0028
| [[#GPUREG_0028|GPUREG_0028]]
|
|
|-
| 0029
| [[#GPUREG_0029|GPUREG_0029]]
|
|
|-
| 002A
| [[#GPUREG_002A|GPUREG_002A]]
|
|
|-
| 002B
| [[#GPUREG_002B|GPUREG_002B]]
|
|
|-
| 002C
| [[#GPUREG_002C|GPUREG_002C]]
|
|
|-
| 002D
| [[#GPUREG_002D|GPUREG_002D]]
|
|
|-
| 002E
| [[#GPUREG_002E|GPUREG_002E]]
|
|
|-
| 002F
| [[#GPUREG_002F|GPUREG_002F]]
|
|
|-
| 0030
| [[#GPUREG_0030|GPUREG_0030]]
|
|
|-
| 0031
| [[#GPUREG_0031|GPUREG_0031]]
|
|
|-
| 0032
| [[#GPUREG_0032|GPUREG_0032]]
|
|
|-
| 0033
| [[#GPUREG_0033|GPUREG_0033]]
|
|
|-
| 0034
| [[#GPUREG_0034|GPUREG_0034]]
|
|
|-
| 0035
| [[#GPUREG_0035|GPUREG_0035]]
|
|
|-
| 0036
| [[#GPUREG_0036|GPUREG_0036]]
|
|
|-
| 0037
| [[#GPUREG_0037|GPUREG_0037]]
|
|
|-
| 0038
| [[#GPUREG_0038|GPUREG_0038]]
|
|
|-
| 0039
| [[#GPUREG_0039|GPUREG_0039]]
|
|
|-
| 003A
| [[#GPUREG_003A|GPUREG_003A]]
|
|
|-
| 003B
| [[#GPUREG_003B|GPUREG_003B]]
|
|
|-
| 003C
| [[#GPUREG_003C|GPUREG_003C]]
|
|
|-
| 003D
| [[#GPUREG_003D|GPUREG_003D]]
|
|
|-
| 003E
| [[#GPUREG_003E|GPUREG_003E]]
|
|
|-
| 003F
| [[#GPUREG_003F|GPUREG_003F]]
|
|
|}

=== Rasterizer registers (0x040-0x07F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0040
| [[#GPUREG_FACECULLING_CONFIG|GPUREG_FACECULLING_CONFIG]]
|
|PICA_REG_CULL_FACE
|-
| 0041
| [[#GPUREG_VIEWPORT_WIDTH|GPUREG_VIEWPORT_WIDTH]]
|
|PICA_REG_VIEWPORT_WIDTH1
|-
| 0042
| [[#GPUREG_VIEWPORT_INVW|GPUREG_VIEWPORT_INVW]]
|
|PICA_REG_VIEWPORT_WIDTH2
|-
| 0043
| [[#GPUREG_VIEWPORT_HEIGHT|GPUREG_VIEWPORT_HEIGHT]]
|
|PICA_REG_VIEWPORT_HEIGHT1
|-
| 0044
| [[#GPUREG_VIEWPORT_INVH|GPUREG_VIEWPORT_INVH]]
|
|PICA_REG_VIEWPORT_HEIGHT2
|-
| 0045
| [[#GPUREG_0045|GPUREG_0045]]
|
|
|-
| 0046
| [[#GPUREG_0046|GPUREG_0046]]
|
|
|-
| 0047
| [[#GPUREG_FRAGOP_CLIP|GPUREG_FRAGOP_CLIP]]
|?
|PICA_REG_FRAGOP_CLIP
|-
| 0048
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA0]]
|?
|PICA_REG_FRAGOP_CLIP_DATA1
|-
| 0049
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA1]]
|?
|PICA_REG_FRAGOP_CLIP_DATA2
|-
| 004A
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA2]]
|?
|PICA_REG_FRAGOP_CLIP_DATA3
|-
| 004B
| [[#GPUREG_FRAGOP_CLIP_DATAi|GPUREG_FRAGOP_CLIP_DATA3]]
|?
|PICA_REG_FRAGOP_CLIP_DATA4
|-
| 004C
| [[#GPUREG_004C|GPUREG_004C]]
|
|
|-
| 004D
| [[#GPUREG_DEPTHMAP_SCALE|GPUREG_DEPTHMAP_SCALE]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA1
|-
| 004E
| [[#GPUREG_DEPTHMAP_OFFSET|GPUREG_DEPTHMAP_OFFSET]]
| As f24
|PICA_REG_FRAGOP_WSCALE_DATA2
|-
| 004F
| [[#GPUREG_SH_OUTMAP_TOTAL|GPUREG_SH_OUTMAP_TOTAL]]
|
|PICA_REG_GS_OUT_REG_NUM0 / PICA_REG_VS_OUT_REG_NUM0
|-
| 0050
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O0]]
|
|PICA_REG_GS_OUT_ATTR0 / PICA_REG_VS_OUT_ATTR0
|-
| 0051
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O1]]
|
|PICA_REG_GS_OUT_ATTR1 / PICA_REG_VS_OUT_ATTR1
|-
| 0052
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O2]]
|
|PICA_REG_GS_OUT_ATTR2 / PICA_REG_VS_OUT_ATTR2
|-
| 0053
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O3]]
|
|PICA_REG_GS_OUT_ATTR3 / PICA_REG_VS_OUT_ATTR3
|-
| 0054
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O4]]
|
|PICA_REG_GS_OUT_ATTR4 / PICA_REG_VS_OUT_ATTR4
|-
| 0055
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O5]]
|
|PICA_REG_GS_OUT_ATTR5 / PICA_REG_VS_OUT_ATTR5
|-
| 0056
| [[#GPUREG_SH_OUTMAP_Oi|GPUREG_SH_OUTMAP_O6]]
|
|PICA_REG_GS_OUT_ATTR6 / PICA_REG_VS_OUT_ATTR6
|-
| 0057
| [[#GPUREG_0057|GPUREG_0057]]
|
|
|-
| 0058
| [[#GPUREG_0058|GPUREG_0058]]
|
|
|-
| 0059
| [[#GPUREG_0059|GPUREG_0059]]
|
|
|-
| 005A
| [[#GPUREG_005A|GPUREG_005A]]
|
|
|-
| 005B
| [[#GPUREG_005B|GPUREG_005B]]
|
|
|-
| 005C
| [[#GPUREG_005C|GPUREG_005C]]
|
|
|-
| 005D
| [[#GPUREG_005D|GPUREG_005D]]
|
|
|-
| 005E
| [[#GPUREG_005E|GPUREG_005E]]
|
|
|-
| 005F
| [[#GPUREG_005F|GPUREG_005F]]
|
|
|-
| 0060
| [[#GPUREG_0060|GPUREG_0060]]
|
|
|-
| 0061
| [[#GPUREG_EARLYDEPTH_FUNC|GPUREG_EARLYDEPTH_FUNC]]
|?
|PICA_REG_EARLY_DEPTH_FUNC
|-
| 0062
| [[#GPUREG_EARLYDEPTH_TEST1|GPUREG_EARLYDEPTH_TEST1]]
|?
|PICA_REG_EARLY_DEPTH_TEST1
|-
| 0063
| [[#GPUREG_EARLYDEPTH_CLEAR|GPUREG_EARLYDEPTH_CLEAR]]
|
|PICA_REG_EARLY_DEPTH_CLEAR
|-
| 0064
| [[#GPUREG_SH_OUTATTR_MODE|GPUREG_SH_OUTATTR_MODE]]
|?
|PICA_REG_GS_OUT_ATTR_MODE / PICA_REG_VS_OUT_ATTR_MODE
|-
| 0065
| [[#GPUREG_SCISSORTEST_MODE|GPUREG_SCISSORTEST_MODE]]
|
|PICA_REG_SCISSOR
|-
| 0066
| [[#GPUREG_SCISSORTEST_POS|GPUREG_SCISSORTEST_POS]]
|
|PICA_REG_SCISSOR_XY
|-
| 0067
| [[#GPUREG_SCISSORTEST_DIM|GPUREG_SCISSORTEST_DIM]]
|
|PICA_REG_SCISSOR_SIZE
|-
| 0068
| [[#GPUREG_VIEWPORT_XY|GPUREG_VIEWPORT_XY]]
|
|PICA_REG_VIEWPORT_XY
|-
| 0069
| [[#GPUREG_0069|GPUREG_0069]]
|
|
|-
| 006A
| [[#GPUREG_EARLYDEPTH_DATA|GPUREG_EARLYDEPTH_DATA]]
|
|PICA_REG_EARLY_DEPTH_DATA
|-
| 006B
| [[#GPUREG_006B|GPUREG_006B]]
|
|
|-
| 006C
| [[#GPUREG_006C|GPUREG_006C]]
|
|
|-
| 006D
| [[#GPUREG_DEPTHMAP_ENABLE|GPUREG_DEPTHMAP_ENABLE]]
|?
|PICA_REG_FRAGOP_WSCALE
|-
| 006E
| [[#GPUREG_RENDERBUF_DIM|GPUREG_RENDERBUF_DIM]]
|?
|PICA_REG_RENDER_BUF_RESOLUTION1
|-
| 006F
| [[#GPUREG_SH_OUTATTR_CLOCK|GPUREG_SH_OUTATTR_CLOCK]]
|?
|PICA_REG_GS_OUT_ATTR_CLK / PICA_REG_VS_OUT_ATTR_CLK
|-
| 0070
| [[#GPUREG_0070|GPUREG_0070]]
|
|
|-
| 0071
| [[#GPUREG_0071|GPUREG_0071]]
|
|
|-
| 0072
| [[#GPUREG_0072|GPUREG_0072]]
|
|
|-
| 0073
| [[#GPUREG_0073|GPUREG_0073]]
|
|
|-
| 0074
| [[#GPUREG_0074|GPUREG_0074]]
|
|
|-
| 0075
| [[#GPUREG_0075|GPUREG_0075]]
|
|
|-
| 0076
| [[#GPUREG_0076|GPUREG_0076]]
|
|
|-
| 0077
| [[#GPUREG_0077|GPUREG_0077]]
|
|
|-
| 0078
| [[#GPUREG_0078|GPUREG_0078]]
|
|
|-
| 0079
| [[#GPUREG_0079|GPUREG_0079]]
|
|
|-
| 007A
| [[#GPUREG_007A|GPUREG_007A]]
|
|
|-
| 007B
| [[#GPUREG_007B|GPUREG_007B]]
|
|
|-
| 007C
| [[#GPUREG_007C|GPUREG_007C]]
|
|
|-
| 007D
| [[#GPUREG_007D|GPUREG_007D]]
|
|
|-
| 007E
| [[#GPUREG_007E|GPUREG_007E]]
|
|
|-
| 007F
| [[#GPUREG_007F|GPUREG_007F]]
|
|
|}

=== Texturing registers (0x080-0x0FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0080
| [[#GPUREG_TEXUNIT_CONFIG|GPUREG_TEXUNIT_CONFIG]]
|
|PICA_REG_TEXTURE_FUNC
|-
| 0081
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT0_BORDER_COLOR]]
|
|PICA_REG_TEXTURE0_BORDER_COLOR
|-
| 0082
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT0_DIM]]
|
|PICA_REG_TEXTURE0_SIZE
|-
| 0083
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT0_PARAM]]
|
|PICA_REG_TEXTURE0_WRAP_FILTER
|-
| 0084
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT0_LOD]]
|?
|PICA_REG_TEXTURE0_LOD
|-
| 0085
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR1]]
|
|PICA_REG_TEXTURE0_ADDR1
|-
| 0086
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR2]]
|
|PICA_REG_TEXTURE0_ADDR2
|-
| 0087
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR3]]
|
|PICA_REG_TEXTURE0_ADDR3
|-
| 0088
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR4]]
|
|PICA_REG_TEXTURE0_ADDR4
|-
| 0089
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR5]]
|
|PICA_REG_TEXTURE0_ADDR5
|-
| 008A
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT0_ADDR6]]
|
|PICA_REG_TEXTURE0_ADDR6
|-
| 008B
| [[#GPUREG_TEXUNITi_SHADOW|GPUREG_TEXUNIT0_SHADOW]]
|?
|PICA_REG_TEXTURE0_SHADOW
|-
| 008C
| [[#GPUREG_008C|GPUREG_008C]]
|
|
|-
| 008D
| [[#GPUREG_008D|GPUREG_008D]]
|
|
|-
| 008E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT0_TYPE]]
|?
|PICA_REG_TEXTURE0_FORMAT
|-
| 008F
| [[#GPUREG_LIGHTING_ENABLE0|GPUREG_LIGHTING_ENABLE0]]
|?
|PICA_REG_FRAG_LIGHT_EN0
|-
| 0090
| [[#GPUREG_0090|GPUREG_0090]]
|
|
|-
| 0091
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT1_BORDER_COLOR]]
|
|PICA_REG_TEXTURE1_BORDER_COLOR
|-
| 0092
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT1_DIM]]
|
|PICA_REG_TEXTURE1_SIZE
|-
| 0093
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT1_PARAM]]
|
|PICA_REG_TEXTURE1_WRAP_FILTER
|-
| 0094
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT1_LOD]]
|?
|PICA_REG_TEXTURE1_LOD
|-
| 0095
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT1_ADDR]]
|
|PICA_REG_TEXTURE1_ADDR
|-
| 0096
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT1_TYPE]]
|
|PICA_REG_TEXTURE1_FORMAT
|-
| 0097
| [[#GPUREG_0097|GPUREG_0097]]
|
|
|-
| 0098
| [[#GPUREG_0098|GPUREG_0098]]
|
|
|-
| 0099
| [[#GPUREG_TEXUNITi_BORDER_COLOR|GPUREG_TEXUNIT2_BORDER_COLOR]]
|
|PICA_REG_TEXTURE2_BORDER_COLOR
|-
| 009A
| [[#GPUREG_TEXUNITi_DIM|GPUREG_TEXUNIT2_DIM]]
|
|PICA_REG_TEXTURE2_SIZE
|-
| 009B
| [[#GPUREG_TEXUNITi_PARAM|GPUREG_TEXUNIT2_PARAM]]
|
|PICA_REG_TEXTURE2_WRAP_FILTER
|-
| 009C
| [[#GPUREG_TEXUNITi_LOD|GPUREG_TEXUNIT2_LOD]]
|?
|PICA_REG_TEXTURE2_LOD
|-
| 009D
| [[#GPUREG_TEXUNITi_ADDRi|GPUREG_TEXUNIT2_ADDR]]
|
|PICA_REG_TEXTURE2_ADDR
|-
| 009E
| [[#GPUREG_TEXUNITi_TYPE|GPUREG_TEXUNIT2_TYPE]]
|
|PICA_REG_TEXTURE2_FORMAT
|-
| 009F
| [[#GPUREG_009F|GPUREG_009F]]
|
|
|-
| 00A0
| [[#GPUREG_00A0|GPUREG_00A0]]
|
|
|-
| 00A1
| [[#GPUREG_00A1|GPUREG_00A1]]
|
|
|-
| 00A2
| [[#GPUREG_00A2|GPUREG_00A2]]
|
|
|-
| 00A3
| [[#GPUREG_00A3|GPUREG_00A3]]
|
|
|-
| 00A4
| [[#GPUREG_00A4|GPUREG_00A4]]
|
|
|-
| 00A5
| [[#GPUREG_00A5|GPUREG_00A5]]
|
|
|-
| 00A6
| [[#GPUREG_00A6|GPUREG_00A6]]
|
|
|-
| 00A7
| [[#GPUREG_00A7|GPUREG_00A7]]
|
|
|-
| 00A8
| [[#GPUREG_TEXUNIT3_PROCTEX0|GPUREG_TEXUNIT3_PROCTEX0]]
|?
|PICA_REG_TEXTURE3_PROCTEX0
|-
| 00A9
| [[#GPUREG_TEXUNIT3_PROCTEX1|GPUREG_TEXUNIT3_PROCTEX1]]
|?
|PICA_REG_TEXTURE3_PROCTEX1
|-
| 00AA
| [[#GPUREG_TEXUNIT3_PROCTEX2|GPUREG_TEXUNIT3_PROCTEX2]]
|?
|PICA_REG_TEXTURE3_PROCTEX2
|-
| 00AB
| [[#GPUREG_TEXUNIT3_PROCTEX3|GPUREG_TEXUNIT3_PROCTEX3]]
|?
|PICA_REG_TEXTURE3_PROCTEX3
|-
| 00AC
| [[#GPUREG_TEXUNIT3_PROCTEX4|GPUREG_TEXUNIT3_PROCTEX4]]
|?
|PICA_REG_TEXTURE3_PROCTEX4
|-
| 00AD
| [[#GPUREG_TEXUNIT3_PROCTEX5|GPUREG_TEXUNIT3_PROCTEX5]]
|?
|PICA_REG_TEXTURE3_PROCTEX5
|-
| 00AE
| [[#GPUREG_00AE|GPUREG_00AE]]
|
|
|-
| 00AF
| [[#GPUREG_PROCTEX_LUT|GPUREG_PROCTEX_LUT]]
|?
|PICA_REG_PROCTEX_LUT
|-
| 00B0
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA0]]
| ?
|PICA_REG_PROCTEX_LUT_DATA0
|-
| 00B1
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA1]]
| ?
|PICA_REG_PROCTEX_LUT_DATA1
|-
| 00B2
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA2]]
| ?
|PICA_REG_PROCTEX_LUT_DATA2
|-
| 00B3
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA3]]
| ?
|PICA_REG_PROCTEX_LUT_DATA3
|-
| 00B4
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA4]]
| ?
|PICA_REG_PROCTEX_LUT_DATA4
|-
| 00B5
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA5]]
| ?
|PICA_REG_PROCTEX_LUT_DATA5
|-
| 00B6
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA6]]
| ?
|PICA_REG_PROCTEX_LUT_DATA6
|-
| 00B7
| [[#GPUREG_PROCTEX_LUT_DATAi|GPUREG_PROCTEX_LUT_DATA7]]
| ?
|PICA_REG_PROCTEX_LUT_DATA7
|-
| 00B8
| [[#GPUREG_00B8|GPUREG_00B8]]
|
|
|-
| 00B9
| [[#GPUREG_00B9|GPUREG_00B9]]
|
|
|-
| 00BA
| [[#GPUREG_00BA|GPUREG_00BA]]
|
|
|-
| 00BB
| [[#GPUREG_00BB|GPUREG_00BB]]
|
|
|-
| 00BC
| [[#GPUREG_00BC|GPUREG_00BC]]
|
|
|-
| 00BD
| [[#GPUREG_00BD|GPUREG_00BD]]
|
|
|-
| 00BE
| [[#GPUREG_00BE|GPUREG_00BE]]
|
|
|-
| 00BF
| [[#GPUREG_00BF|GPUREG_00BF]]
|
|
|-
| 00C0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV0_SOURCE]]
|
|PICA_REG_TEX_ENV_0
|-
| 00C1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV0_OPERAND]]
|
|PICA_REG_TEX_ENV_0_OPERAND
|-
| 00C2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV0_COMBINER]]
|
|PICA_REG_TEX_ENV_0_COMBINE
|-
| 00C3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV0_COLOR]]
|
|PICA_REG_TEX_ENV_0_COLOR
|-
| 00C4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV0_SCALE]]
|
|PICA_REG_TEX_ENV_0_SCALE
|-
| 00C5
| [[#GPUREG_00C5|GPUREG_00C5]]
|
|
|-
| 00C6
| [[#GPUREG_00C6|GPUREG_00C6]]
|
|
|-
| 00C7
| [[#GPUREG_00C7|GPUREG_00C7]]
|
|
|-
| 00C8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV1_SOURCE]]
|
|PICA_REG_TEX_ENV_1
|-
| 00C9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV1_OPERAND]]
|
|PICA_REG_TEX_ENV_1_OPERAND
|-
| 00CA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV1_COMBINER]]
|
|PICA_REG_TEX_ENV_1_COMBINE
|-
| 00CB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV1_COLOR]]
|
|PICA_REG_TEX_ENV_1_COLOR
|-
| 00CC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV1_SCALE]]
|
|PICA_REG_TEX_ENV_1_SCALE
|-
| 00CD
| [[#GPUREG_00CD|GPUREG_00CD]]
|
|
|-
| 00CE
| [[#GPUREG_00CE|GPUREG_00CE]]
|
|
|-
| 00CF
| [[#GPUREG_00CF|GPUREG_00CF]]
|
|
|-
| 00D0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV2_SOURCE]]
|
|PICA_REG_TEX_ENV_2
|-
| 00D1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV2_OPERAND]]
|
|PICA_REG_TEX_ENV_2_OPERAND
|-
| 00D2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV2_COMBINER]]
|
|PICA_REG_TEX_ENV_2_COMBINE
|-
| 00D3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV2_COLOR]]
|
|PICA_REG_TEX_ENV_2_COLOR
|-
| 00D4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV2_SCALE]]
|
|PICA_REG_TEX_ENV_2_SCALE
|-
| 00D5
| [[#GPUREG_00D5|GPUREG_00D5]]
|
|
|-
| 00D6
| [[#GPUREG_00D6|GPUREG_00D6]]
|
|
|-
| 00D7
| [[#GPUREG_00D7|GPUREG_00D7]]
|
|
|-
| 00D8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV3_SOURCE]]
|
|PICA_REG_TEX_ENV_3
|-
| 00D9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV3_OPERAND]]
|
|PICA_REG_TEX_ENV_3_OPERAND
|-
| 00DA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV3_COMBINER]]
|
|PICA_REG_TEX_ENV_3_COMBINE
|-
| 00DB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV3_COLOR]]
|
|PICA_REG_TEX_ENV_3_COLOR
|-
| 00DC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV3_SCALE]]
|
|PICA_REG_TEX_ENV_3_SCALE
|-
| 00DD
| [[#GPUREG_00DD|GPUREG_00DD]]
|
|
|-
| 00DE
| [[#GPUREG_00DE|GPUREG_00DE]]
|
|
|-
| 00DF
| [[#GPUREG_00DF|GPUREG_00DF]]
|
|
|-
| 00E0
| [[#GPUREG_TEXENV_UPDATE_BUFFER|GPUREG_TEXENV_UPDATE_BUFFER]]
|?
|PICA_REG_GAS_FOG_MODE / PICA_REG_TEX_ENV_BUF_INPUT
|-
| 00E1
| [[#GPUREG_FOG_COLOR|GPUREG_FOG_COLOR]]
|?
|PICA_REG_FOG_COLOR
|-
| 00E2
| [[#GPUREG_00E2|GPUREG_00E2]]
|
|
|-
| 00E3
| [[#GPUREG_00E3|GPUREG_00E3]]
|
|
|-
| 00E4
| [[#GPUREG_GAS_ATTENUATION|GPUREG_GAS_ATTENUATION]]
|?
|PICA_REG_GAS_ATTENUATION
|-
| 00E5
| [[#GPUREG_GAS_ACCMAX|GPUREG_GAS_ACCMAX]]
|?
|PICA_REG_GAS_ACCMAX
|-
| 00E6
| [[#GPUREG_FOG_LUT_INDEX|GPUREG_FOG_LUT_INDEX]]
|?
|PICA_REG_FOG_LUT_INDEX
|-
| 00E7
| [[#GPUREG_00E7|GPUREG_00E7]]
|
|
|-
| 00E8
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA0]]
|?
|PICA_REG_FOG_LUT_DATA0
|-
| 00E9
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA1]]
|?
|PICA_REG_FOG_LUT_DATA1
|-
| 00EA
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA2]]
|?
|PICA_REG_FOG_LUT_DATA2
|-
| 00EB
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA3]]
|?
|PICA_REG_FOG_LUT_DATA3
|-
| 00EC
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA4]]
|?
|PICA_REG_FOG_LUT_DATA4
|-
| 00ED
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA5]]
|?
|PICA_REG_FOG_LUT_DATA5
|-
| 00EE
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA6]]
|?
|PICA_REG_FOG_LUT_DATA6
|-
| 00EF
| [[#GPUREG_FOG_LUT_DATAi|GPUREG_FOG_LUT_DATA7]]
|?
|PICA_REG_FOG_LUT_DATA7
|-
| 00F0
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV4_SOURCE]]
|
|PICA_REG_TEX_ENV_4
|-
| 00F1
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV4_OPERAND]]
|
|PICA_REG_TEX_ENV_4_OPERAND
|-
| 00F2
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV4_COMBINER]]
|
|PICA_REG_TEX_ENV_4_COMBINE
|-
| 00F3
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV4_COLOR]]
|
|PICA_REG_TEX_ENV_4_COLOR
|-
| 00F4
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV4_SCALE]]
|
|PICA_REG_TEX_ENV_4_SCALE
|-
| 00F5
| [[#GPUREG_00F5|GPUREG_00F5]]
|
|
|-
| 00F6
| [[#GPUREG_00F6|GPUREG_00F6]]
|
|
|-
| 00F7
| [[#GPUREG_00F7|GPUREG_00F7]]
|
|
|-
| 00F8
| [[#GPUREG_TEXENVi_SOURCE|GPUREG_TEXENV5_SOURCE]]
|
|PICA_REG_TEX_ENV_5
|-
| 00F9
| [[#GPUREG_TEXENVi_OPERAND|GPUREG_TEXENV5_OPERAND]]
|
|PICA_REG_TEX_ENV_5_OPERAND
|-
| 00FA
| [[#GPUREG_TEXENVi_COMBINER|GPUREG_TEXENV5_COMBINER]]
|
|PICA_REG_TEX_ENV_5_COMBINE
|-
| 00FB
| [[#GPUREG_TEXENVi_COLOR|GPUREG_TEXENV5_COLOR]]
|
|PICA_REG_TEX_ENV_5_COLOR
|-
| 00FC
| [[#GPUREG_TEXENVi_SCALE|GPUREG_TEXENV5_SCALE]]
|
|PICA_REG_TEX_ENV_5_SCALE
|-
| 00FD
| [[#GPUREG_TEXENV_BUFFER_COLOR|GPUREG_TEXENV_BUFFER_COLOR]]
|?
|PICA_REG_TEX_ENV_BUF_COLOR
|-
| 00FE
| [[#GPUREG_00FE|GPUREG_00FE]]
|
|
|-
| 00FF
| [[#GPUREG_00FF|GPUREG_00FF]]
|
|
|}

=== Framebuffer registers (0x100-0x13F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0100
| [[#GPUREG_COLOR_OPERATION|GPUREG_COLOR_OPERATION]]
|
|PICA_REG_COLOR_OPERATION
|-
| 0101
| [[#GPUREG_BLEND_FUNC|GPUREG_BLEND_FUNC]]
|
|PICA_REG_BLEND_FUNC
|-
| 0102
| [[#GPUREG_LOGIC_OP|GPUREG_LOGIC_OP]]
|
|PICA_REG_LOGIC_OP
|-
| 0103
| [[#GPUREG_BLEND_COLOR|GPUREG_BLEND_COLOR]]
|
|PICA_REG_BLEND_COLOR
|-
| 0104
| [[#GPUREG_FRAGOP_ALPHA_TEST|GPUREG_FRAGOP_ALPHA_TEST]]
|
|PICA_REG_FRAGOP_ALPHA_TEST
|-
| 0105
| [[#GPUREG_STENCIL_TEST|GPUREG_STENCIL_TEST]]
|
|PICA_REG_STENCIL_TEST
|-
| 0106
| [[#GPUREG_STENCIL_OP|GPUREG_STENCIL_OP]]
|
|PICA_REG_STENCIL_OP
|-
| 0107
| [[#GPUREG_DEPTH_COLOR_MASK|GPUREG_DEPTH_COLOR_MASK]]
|
|PICA_REG_DEPTH_COLOR_MASK
|-
| 0108
| [[#GPUREG_0108|GPUREG_0108]]
|
|
|-
| 0109
| [[#GPUREG_0109|GPUREG_0109]]
|
|
|-
| 010A
| [[#GPUREG_010A|GPUREG_010A]]
|
|
|-
| 010B
| [[#GPUREG_010B|GPUREG_010B]]
|
|
|-
| 010C
| [[#GPUREG_010C|GPUREG_010C]]
|
|
|-
| 010D
| [[#GPUREG_010D|GPUREG_010D]]
|
|
|-
| 010E
| [[#GPUREG_010E|GPUREG_010E]]
|
|
|-
| 010F
| [[#GPUREG_010F|GPUREG_010F]]
|
|
|-
| 0110
| [[#GPUREG_FRAMEBUFFER_INVALIDATE|GPUREG_FRAMEBUFFER_INVALIDATE]]
|
|PICA_REG_COLOR_BUFFER_CLEAR0
|-
| 0111
| [[#GPUREG_FRAMEBUFFER_FLUSH|GPUREG_FRAMEBUFFER_FLUSH]]
|
|PICA_REG_COLOR_BUFFER_CLEAR1
|-
| 0112
| [[#GPUREG_COLORBUFFER_READ|GPUREG_COLORBUFFER_READ]]
|
|PICA_REG_COLOR_BUFFER_READ
|-
| 0113
| [[#GPUREG_COLORBUFFER_WRITE|GPUREG_COLORBUFFER_WRITE]]
|
|PICA_REG_COLOR_BUFFER_WRITE
|-
| 0114
| [[#GPUREG_DEPTHBUFFER_READ|GPUREG_DEPTHBUFFER_READ]]
|
|PICA_REG_DEPTH_STENCIL_READ
|-
| 0115
| [[#GPUREG_DEPTHBUFFER_WRITE|GPUREG_DEPTHBUFFER_WRITE]]
|
|PICA_REG_DEPTH_STENCIL_WRITE
|-
| 0116
| [[#GPUREG_DEPTHBUFFER_FORMAT|GPUREG_DEPTHBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_DEPTH_MODE
|-
| 0117
| [[#GPUREG_COLORBUFFER_FORMAT|GPUREG_COLORBUFFER_FORMAT]]
|
|PICA_REG_RENDER_BUF_COLOR_MODE
|-
| 0118
| [[#GPUREG_EARLYDEPTH_TEST2|GPUREG_EARLYDEPTH_TEST2]]
|?
|PICA_REG_EARLY_DEPTH_TEST2
|-
| 0119
| [[#GPUREG_0119|GPUREG_0119]]
|
|
|-
| 011A
| [[#GPUREG_011A|GPUREG_011A]]
|
|
|-
| 011B
| [[#GPUREG_FRAMEBUFFER_BLOCK32|GPUREG_FRAMEBUFFER_BLOCK32]]
|
|PICA_REG_RENDER_BLOCK_FORMAT
|-
| 011C
| [[#GPUREG_DEPTHBUFFER_LOC|GPUREG_DEPTHBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_DEPTH_ADDR
|-
| 011D
| [[#GPUREG_COLORBUFFER_LOC|GPUREG_COLORBUFFER_LOC]]
|
|PICA_REG_RENDER_BUF_COLOR_ADDR
|-
| 011E
| [[#GPUREG_FRAMEBUFFER_DIM|GPUREG_FRAMEBUFFER_DIM]]
|
|PICA_REG_RENDER_BUF_RESOLUTION0
|-
| 011F
| [[#GPUREG_011F|GPUREG_011F]]
|
|
|-
| 0120
| [[#GPUREG_GAS_LIGHT_XY|GPUREG_GAS_LIGHT_XY]]
|?
|PICA_REG_GAS_LIGHT_XY
|-
| 0121
| [[#GPUREG_GAS_LIGHT_Z|GPUREG_GAS_LIGHT_Z]]
|?
|PICA_REG_GAS_LIGHT_Z
|-
| 0122
| [[#GPUREG_GAS_LIGHT_Z_COLOR|GPUREG_GAS_LIGHT_Z_COLOR]]
|?
|PICA_REG_GAS_LIGHT_Z_COLOR
|-
| 0123
| [[#GPUREG_GAS_LUT_INDEX|GPUREG_GAS_LUT_INDEX]]
|?
|PICA_REG_GAS_LUT_INDEX
|-
| 0124
| [[#GPUREG_GAS_LUT_DATA|GPUREG_GAS_LUT_DATA]]
|?
|PICA_REG_GAS_LUT_DATA
|-
| 0125
| [[#GPUREG_0125|GPUREG_0125]]
|
|
|-
| 0126
| [[#GPUREG_GAS_DELTAZ_DEPTH|GPUREG_GAS_DELTAZ_DEPTH]]
|?
|PICA_REG_GAS_DELTAZ_DEPTH
|-
| 0127
| [[#GPUREG_0127|GPUREG_0127]]
|
|
|-
| 0128
| [[#GPUREG_0128|GPUREG_0128]]
|
|
|-
| 0129
| [[#GPUREG_0129|GPUREG_0129]]
|
|
|-
| 012A
| [[#GPUREG_012A|GPUREG_012A]]
|
|
|-
| 012B
| [[#GPUREG_012B|GPUREG_012B]]
|
|
|-
| 012C
| [[#GPUREG_012C|GPUREG_012C]]
|
|
|-
| 012D
| [[#GPUREG_012D|GPUREG_012D]]
|
|
|-
| 012E
| [[#GPUREG_012E|GPUREG_012E]]
|
|
|-
| 012F
| [[#GPUREG_012F|GPUREG_012F]]
|
|
|-
| 0130
| [[#GPUREG_FRAGOP_SHADOW|GPUREG_FRAGOP_SHADOW]]
|?
|PICA_REG_FRAGOP_SHADOW
|-
| 0131
| [[#GPUREG_0131|GPUREG_0131]]
|
|
|-
| 0132
| [[#GPUREG_0132|GPUREG_0132]]
|
|
|-
| 0133
| [[#GPUREG_0133|GPUREG_0133]]
|
|
|-
| 0134
| [[#GPUREG_0134|GPUREG_0134]]
|
|
|-
| 0135
| [[#GPUREG_0135|GPUREG_0135]]
|
|
|-
| 0136
| [[#GPUREG_0136|GPUREG_0136]]
|
|
|-
| 0137
| [[#GPUREG_0137|GPUREG_0137]]
|
|
|-
| 0138
| [[#GPUREG_0138|GPUREG_0138]]
|
|
|-
| 0139
| [[#GPUREG_0139|GPUREG_0139]]
|
|
|-
| 013A
| [[#GPUREG_013A|GPUREG_013A]]
|
|
|-
| 013B
| [[#GPUREG_013B|GPUREG_013B]]
|
|
|-
| 013C
| [[#GPUREG_013C|GPUREG_013C]]
|
|
|-
| 013D
| [[#GPUREG_013D|GPUREG_013D]]
|
|
|-
| 013E
| [[#GPUREG_013E|GPUREG_013E]]
|
|
|-
| 013F
| [[#GPUREG_013F|GPUREG_013F]]
|
|
|}

=== Fragment lighting registers (0x140-0x1FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0140
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT0_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR0 / PICA_REG_FRAG_LIGHT_START
|-
| 0141
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT0_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT0_SPECULAR1
|-
| 0142
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT0_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT0_DIFFUSE
|-
| 0143
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT0_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT0_AMBIENT
|-
| 0144
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT0_XY]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_XY
|-
| 0145
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT0_Z]]
|?
|PICA_REG_FRAG_LIGHT0_POSITION_Z
|-
| 0146
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT0_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_XY
|-
| 0147
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT0_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT0_SPOT_Z
|-
| 0148
| [[#GPUREG_0148|GPUREG_0148]]
|
|
|-
| 0149
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT0_CONFIG]]
|
|PICA_REG_FRAG_LIGHT0_TYPE
|-
| 014A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT0_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_BIAS
|-
| 014B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT0_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT0_DIST_ATTN_SCALE
|-
| 014C
| [[#GPUREG_014C|GPUREG_014C]]
|
|
|-
| 014D
| [[#GPUREG_014D|GPUREG_014D]]
|
|
|-
| 014E
| [[#GPUREG_014E|GPUREG_014E]]
|
|
|-
| 014F
| [[#GPUREG_014F|GPUREG_014F]]
|
|
|-
| 0150
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT1_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR0
|-
| 0151
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT1_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT1_SPECULAR1
|-
| 0152
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT1_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT1_DIFFUSE
|-
| 0153
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT1_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT1_AMBIENT
|-
| 0154
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT1_XY]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_XY
|-
| 0155
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT1_Z]]
|?
|PICA_REG_FRAG_LIGHT1_POSITION_Z
|-
| 0156
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT1_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_XY
|-
| 0157
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT1_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT1_SPOT_Z
|-
| 0158
| [[#GPUREG_0158|GPUREG_0158]]
|
|
|-
| 0159
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT1_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT1_TYPE
|-
| 015A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT1_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_BIAS
|-
| 015B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT1_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT1_DIST_ATTN_SCALE
|-
| 015C
| [[#GPUREG_015C|GPUREG_015C]]
|
|
|-
| 015D
| [[#GPUREG_015D|GPUREG_015D]]
|
|
|-
| 015E
| [[#GPUREG_015E|GPUREG_015E]]
|
|
|-
| 015F
| [[#GPUREG_015F|GPUREG_015F]]
|
|
|-
| 0160
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT2_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR0
|-
| 0161
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT2_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT2_SPECULAR1
|-
| 0162
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT2_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT2_DIFFUSE
|-
| 0163
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT2_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT2_AMBIENT
|-
| 0164
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT2_XY]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_XY
|-
| 0165
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT2_Z]]
|?
|PICA_REG_FRAG_LIGHT2_POSITION_Z
|-
| 0166
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT2_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_XY
|-
| 0167
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT2_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT2_SPOT_Z
|-
| 0168
| [[#GPUREG_0168|GPUREG_0168]]
|
|
|-
| 0169
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT2_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT2_TYPE
|-
| 016A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT2_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_BIAS
|-
| 016B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT2_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT2_DIST_ATTN_SCALE
|-
| 016C
| [[#GPUREG_016C|GPUREG_016C]]
|
|
|-
| 016D
| [[#GPUREG_016D|GPUREG_016D]]
|
|
|-
| 016E
| [[#GPUREG_016E|GPUREG_016E]]
|
|
|-
| 016F
| [[#GPUREG_016F|GPUREG_016F]]
|
|
|-
| 0170
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT3_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR0
|-
| 0171
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT3_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT3_SPECULAR1
|-
| 0172
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT3_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT3_DIFFUSE
|-
| 0173
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT3_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT3_AMBIENT
|-
| 0174
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT3_XY]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_XY
|-
| 0175
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT3_Z]]
|?
|PICA_REG_FRAG_LIGHT3_POSITION_Z
|-
| 0176
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT3_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_XY
|-
| 0177
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT3_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT3_SPOT_Z
|-
| 0178
| [[#GPUREG_0178|GPUREG_0178]]
|
|
|-
| 0179
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT3_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT3_TYPE
|-
| 017A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT3_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_BIAS
|-
| 017B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT3_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT3_DIST_ATTN_SCALE
|-
| 017C
| [[#GPUREG_017C|GPUREG_017C]]
|
|
|-
| 017D
| [[#GPUREG_017D|GPUREG_017D]]
|
|
|-
| 017E
| [[#GPUREG_017E|GPUREG_017E]]
|
|
|-
| 017F
| [[#GPUREG_017F|GPUREG_017F]]
|
|
|-
| 0180
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT4_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR0
|-
| 0181
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT4_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT4_SPECULAR1
|-
| 0182
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT4_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT4_DIFFUSE
|-
| 0183
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT4_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT4_AMBIENT
|-
| 0184
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT4_XY]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_XY
|-
| 0185
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT4_Z]]
|?
|PICA_REG_FRAG_LIGHT4_POSITION_Z
|-
| 0186
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT4_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_XY
|-
| 0187
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT4_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT4_SPOT_Z
|-
| 0188
| [[#GPUREG_0188|GPUREG_0188]]
|
|
|-
| 0189
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT4_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT4_TYPE
|-
| 018A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT4_ATTENUATION_BIAS]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_BIAS
|-
| 018B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT4_ATTENUATION_SCALE]]
|?
|PICA_REG_FRAG_LIGHT4_DIST_ATTN_SCALE
|-
| 018C
| [[#GPUREG_018C|GPUREG_018C]]
|
|
|-
| 018D
| [[#GPUREG_018D|GPUREG_018D]]
|
|
|-
| 018E
| [[#GPUREG_018E|GPUREG_018E]]
|
|
|-
| 018F
| [[#GPUREG_018F|GPUREG_018F]]
|
|
|-
| 0190
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT5_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR0
|-
| 0191
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT5_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT5_SPECULAR1
|-
| 0192
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT5_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT5_DIFFUSE
|-
| 0193
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT5_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT5_AMBIENT
|-
| 0194
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT5_XY]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_XY
|-
| 0195
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT5_Z]]
|?
|PICA_REG_FRAG_LIGHT5_POSITION_Z
|-
| 0196
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT5_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_XY
|-
| 0197
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT5_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT5_SPOT_Z
|-
| 0198
| [[#GPUREG_0198|GPUREG_0198]]
|
|
|-
| 0199
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT5_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT5_TYPE
|-
| 019A
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT5_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_BIAS
|-
| 019B
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT5_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT5_DIST_ATTN_SCALE
|-
| 019C
| [[#GPUREG_019C|GPUREG_019C]]
|
|
|-
| 019D
| [[#GPUREG_019D|GPUREG_019D]]
|
|
|-
| 019E
| [[#GPUREG_019E|GPUREG_019E]]
|
|
|-
| 019F
| [[#GPUREG_019F|GPUREG_019F]]
|
|
|-
| 01A0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT6_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR0
|-
| 01A1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT6_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT6_SPECULAR1
|-
| 01A2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT6_DIFFUSE]]
|
|PICA_REG_FRAG_LIGHT6_DIFFUSE
|-
| 01A3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT6_AMBIENT]]
|
|PICA_REG_FRAG_LIGHT6_AMBIENT
|-
| 01A4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT6_XY]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_XY
|-
| 01A5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT6_Z]]
|
|PICA_REG_FRAG_LIGHT6_POSITION_Z
|-
| 01A6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT6_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_XY
|-
| 01A7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT6_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT6_SPOT_Z
|-
| 01A8
| [[#GPUREG_01A8|GPUREG_01A8]]
|
|
|-
| 01A9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT6_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT6_TYPE
|-
| 01AA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT6_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_BIAS
|-
| 01AB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT6_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT6_DIST_ATTN_SCALE
|-
| 01AC
| [[#GPUREG_01AC|GPUREG_01AC]]
|
|
|-
| 01AD
| [[#GPUREG_01AD|GPUREG_01AD]]
|
|
|-
| 01AE
| [[#GPUREG_01AE|GPUREG_01AE]]
|
|
|-
| 01AF
| [[#GPUREG_01AF|GPUREG_01AF]]
|
|
|-
| 01B0
| [[#GPUREG_LIGHTi_SPECULAR0|GPUREG_LIGHT7_SPECULAR0]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR0
|-
| 01B1
| [[#GPUREG_LIGHTi_SPECULAR1|GPUREG_LIGHT7_SPECULAR1]]
|?
|PICA_REG_FRAG_LIGHT7_SPECULAR1
|-
| 01B2
| [[#GPUREG_LIGHTi_DIFFUSE|GPUREG_LIGHT7_DIFFUSE]]
|?
|PICA_REG_FRAG_LIGHT7_DIFFUSE
|-
| 01B3
| [[#GPUREG_LIGHTi_AMBIENT|GPUREG_LIGHT7_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT7_AMBIENT
|-
| 01B4
| [[#GPUREG_LIGHTi_XY|GPUREG_LIGHT7_XY]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_XY
|-
| 01B5
| [[#GPUREG_LIGHTi_Z|GPUREG_LIGHT7_Z]]
|?
|PICA_REG_FRAG_LIGHT7_POSITION_Z
|-
| 01B6
| [[#GPUREG_LIGHTi_SPOTDIR_XY|GPUREG_LIGHT7_SPOTDIR_XY]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_XY
|-
| 01B7
| [[#GPUREG_LIGHTi_SPOTDIR_Z|GPUREG_LIGHT7_SPOTDIR_Z]]
|?
|PICA_REG_FRAG_LIGHT7_SPOT_Z
|-
| 01B8
| [[#GPUREG_01B8|GPUREG_01B8]]
|
|
|-
| 01B9
| [[#GPUREG_LIGHTi_CONFIG|GPUREG_LIGHT7_CONFIG]]
|?
|PICA_REG_FRAG_LIGHT7_TYPE
|-
| 01BA
| [[#GPUREG_LIGHTi_ATTENUATION_BIAS|GPUREG_LIGHT7_ATTENUATION_BIAS]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_BIAS
|-
| 01BB
| [[#GPUREG_LIGHTi_ATTENUATION_SCALE|GPUREG_LIGHT7_ATTENUATION_SCALE]]
|
|PICA_REG_FRAG_LIGHT7_DIST_ATTN_SCALE
|-
| 01BC
| [[#GPUREG_01BC|GPUREG_01BC]]
|
|
|-
| 01BD
| [[#GPUREG_01BD|GPUREG_01BD]]
|
|
|-
| 01BE
| [[#GPUREG_01BE|GPUREG_01BE]]
|
|
|-
| 01BF
| [[#GPUREG_01BF|GPUREG_01BF]]
|
|
|-
| 01C0
| [[#GPUREG_LIGHTING_AMBIENT|GPUREG_LIGHTING_AMBIENT]]
|?
|PICA_REG_FRAG_LIGHT_AMBIENT
|-
| 01C1
| [[#GPUREG_01C1|GPUREG_01C1]]
|
|
|-
| 01C2
| [[#GPUREG_LIGHTING_NUM_LIGHTS|GPUREG_LIGHTING_NUM_LIGHTS]]
|?
|PICA_REG_FRAG_LIGHT_SRC_NUM
|-
| 01C3
| [[#GPUREG_LIGHTING_CONFIG0|GPUREG_LIGHTING_CONFIG0]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE0
|-
| 01C4
| [[#GPUREG_LIGHTING_CONFIG1|GPUREG_LIGHTING_CONFIG1]]
|?
|PICA_REG_FRAG_LIGHT_FUNC_MODE1
|-
| 01C5
| [[#GPUREG_LIGHTING_LUT_INDEX|GPUREG_LIGHTING_LUT_INDEX]]
|?
|PICA_REG_FRAG_LIGHT_LUT
|-
| 01C6
| [[#GPUREG_LIGHTING_ENABLE1|GPUREG_LIGHTING_ENABLE1]]
|?
|PICA_REG_FRAG_LIGHT_EN1
|-
| 01C7
| [[#GPUREG_01C7|GPUREG_01C7]]
|
|
|-
| 01C8
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA0]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA0
|-
| 01C9
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA1]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA1
|-
| 01CA
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA2]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA2
|-
| 01CB
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA3]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA3
|-
| 01CC
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA4]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA4
|-
| 01CD
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA5]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA5
|-
| 01CE
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA6]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA6
|-
| 01CF
| [[#GPUREG_LIGHTING_LUT_DATAi|GPUREG_LIGHTING_LUT_DATA7]]
|?
|PICA_REG_FRAG_LIGHT_LUT_DATA7
|-
| 01D0
| [[#GPUREG_LIGHTING_LUTINPUT_ABS|GPUREG_LIGHTING_LUTINPUT_ABS]]
|?
|PICA_REG_FRAG_LIGHT_ABSLUTINPUT
|-
| 01D1
| [[#GPUREG_LIGHTING_LUTINPUT_SELECT|GPUREG_LIGHTING_LUTINPUT_SELECT]]
|?
|PICA_REG_FRAG_LIGHT_LUTINPUT
|-
| 01D2
| [[#GPUREG_LIGHTING_LUTINPUT_SCALE|GPUREG_LIGHTING_LUTINPUT_SCALE]]
|?
|PICA_REG_FRAG_LIGHT_LUTSCALE
|-
| 01D3
| [[#GPUREG_01D3|GPUREG_01D3]]
|
|
|-
| 01D4
| [[#GPUREG_01D4|GPUREG_01D4]]
|
|
|-
| 01D5
| [[#GPUREG_01D5|GPUREG_01D5]]
|
|
|-
| 01D6
| [[#GPUREG_01D6|GPUREG_01D6]]
|
|
|-
| 01D7
| [[#GPUREG_01D7|GPUREG_01D7]]
|
|
|-
| 01D8
| [[#GPUREG_01D8|GPUREG_01D8]]
|
|
|-
| 01D9
| [[#GPUREG_LIGHTING_LIGHT_PERMUTATION|GPUREG_LIGHTING_LIGHT_PERMUTATION]]
|?
|PICA_REG_FRAG_LIGHT_SRC_EN_ID
|-
| 01DA
| [[#GPUREG_01DA|GPUREG_01DA]]
|
|
|-
| 01DB
| [[#GPUREG_01DB|GPUREG_01DB]]
|
|
|-
| 01DC
| [[#GPUREG_01DC|GPUREG_01DC]]
|
|
|-
| 01DD
| [[#GPUREG_01DD|GPUREG_01DD]]
|
|
|-
| 01DE
| [[#GPUREG_01DE|GPUREG_01DE]]
|
|
|-
| 01DF
| [[#GPUREG_01DF|GPUREG_01DF]]
|
|
|-
| 01E0
| [[#GPUREG_01E0|GPUREG_01E0]]
|
|
|-
| 01E1
| [[#GPUREG_01E1|GPUREG_01E1]]
|
|
|-
| 01E2
| [[#GPUREG_01E2|GPUREG_01E2]]
|
|
|-
| 01E3
| [[#GPUREG_01E3|GPUREG_01E3]]
|
|
|-
| 01E4
| [[#GPUREG_01E4|GPUREG_01E4]]
|
|
|-
| 01E5
| [[#GPUREG_01E5|GPUREG_01E5]]
|
|
|-
| 01E6
| [[#GPUREG_01E6|GPUREG_01E6]]
|
|
|-
| 01E7
| [[#GPUREG_01E7|GPUREG_01E7]]
|
|
|-
| 01E8
| [[#GPUREG_01E8|GPUREG_01E8]]
|
|
|-
| 01E9
| [[#GPUREG_01E9|GPUREG_01E9]]
|
|
|-
| 01EA
| [[#GPUREG_01EA|GPUREG_01EA]]
|
|
|-
| 01EB
| [[#GPUREG_01EB|GPUREG_01EB]]
|
|
|-
| 01EC
| [[#GPUREG_01EC|GPUREG_01EC]]
|
|
|-
| 01ED
| [[#GPUREG_01ED|GPUREG_01ED]]
|
|
|-
| 01EE
| [[#GPUREG_01EE|GPUREG_01EE]]
|
|
|-
| 01EF
| [[#GPUREG_01EF|GPUREG_01EF]]
|
|
|-
| 01F0
| [[#GPUREG_01F0|GPUREG_01F0]]
|
|
|-
| 01F1
| [[#GPUREG_01F1|GPUREG_01F1]]
|
|
|-
| 01F2
| [[#GPUREG_01F2|GPUREG_01F2]]
|
|
|-
| 01F3
| [[#GPUREG_01F3|GPUREG_01F3]]
|
|
|-
| 01F4
| [[#GPUREG_01F4|GPUREG_01F4]]
|
|
|-
| 01F5
| [[#GPUREG_01F5|GPUREG_01F5]]
|
|
|-
| 01F6
| [[#GPUREG_01F6|GPUREG_01F6]]
|
|
|-
| 01F7
| [[#GPUREG_01F7|GPUREG_01F7]]
|
|
|-
| 01F8
| [[#GPUREG_01F8|GPUREG_01F8]]
|
|
|-
| 01F9
| [[#GPUREG_01F9|GPUREG_01F9]]
|
|
|-
| 01FA
| [[#GPUREG_01FA|GPUREG_01FA]]
|
|
|-
| 01FB
| [[#GPUREG_01FB|GPUREG_01FB]]
|
|
|-
| 01FC
| [[#GPUREG_01FC|GPUREG_01FC]]
|
|
|-
| 01FD
| [[#GPUREG_01FD|GPUREG_01FD]]
|
|
|-
| 01FE
| [[#GPUREG_01FE|GPUREG_01FE]]
|
|
|-
| 01FF
| [[#GPUREG_01FF|GPUREG_01FF]]
|
|
|}

=== Geometry pipeline registers (0x200-0x27F) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 0200
| [[#GPUREG_ATTRIBBUFFERS_LOC|GPUREG_ATTRIBBUFFERS_LOC]]
|
|PICA_REG_VTX_ATTR_ARRAYS_BASE_ADDR
|-
| 0201
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_LOW|GPUREG_ATTRIBBUFFERS_FORMAT_LOW]]
|
|PICA_REG_VTX_ATTR_ARRAYS0
|-
| 0202
| [[#GPUREG_ATTRIBBUFFERS_FORMAT_HIGH|GPUREG_ATTRIBBUFFERS_FORMAT_HIGH]]
|
|PICA_REG_VTX_ATTR_ARRAYS1
|-
| 0203
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER0_OFFSET]]
|
|PICA_REG_LOAD_ARRAY0_ATTR_OFFSET
|-
| 0204
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER0_CONFIG1]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT0
|-
| 0205
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER0_CONFIG2]]
|
|PICA_REG_LOAD_ARRAY0_ELEMENT1
|-
| 0206
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER1_OFFSET]]
|
|
|-
| 0207
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER1_CONFIG1]]
|
|
|-
| 0208
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER1_CONFIG2]]
|
|
|-
| 0209
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER2_OFFSET]]
|
|
|-
| 020A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER2_CONFIG1]]
|
|
|-
| 020B
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER2_CONFIG2]]
|
|
|-
| 020C
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER3_OFFSET]]
|
|
|-
| 020D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER3_CONFIG1]]
|
|
|-
| 020E
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER3_CONFIG2]]
|
|
|-
| 020F
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER4_OFFSET]]
|
|
|-
| 0210
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER4_CONFIG1]]
|
|
|-
| 0211
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER4_CONFIG2]]
|
|
|-
| 0212
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER5_OFFSET]]
|
|
|-
| 0213
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER5_CONFIG1]]
|
|
|-
| 0214
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER5_CONFIG2]]
|
|
|-
| 0215
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER6_OFFSET]]
|
|
|-
| 0216
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER6_CONFIG1]]
|
|
|-
| 0217
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER6_CONFIG2]]
|
|
|-
| 0218
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER7_OFFSET]]
|
|
|-
| 0219
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER7_CONFIG1]]
|
|
|-
| 021A
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER7_CONFIG2]]
|
|
|-
| 021B
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER8_OFFSET]]
|
|
|-
| 021C
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER8_CONFIG1]]
|
|
|-
| 021D
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER8_CONFIG2]]
|
|
|-
| 021E
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER9_OFFSET]]
|
|
|-
| 021F
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER9_CONFIG1]]
|
|
|-
| 0220
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER9_CONFIG2]]
|
|
|-
| 0221
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER10_OFFSET]]
|
|
|-
| 0222
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER10_CONFIG1]]
|
|
|-
| 0223
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER10_CONFIG2]]
|
|
|-
| 0224
| [[#GPUREG_ATTRIBBUFFERi_OFFSET|GPUREG_ATTRIBBUFFER11_OFFSET]]
|
|
|-
| 0225
| [[#GPUREG_ATTRIBBUFFERi_CONFIG1|GPUREG_ATTRIBBUFFER11_CONFIG1]]
|
|
|-
| 0226
| [[#GPUREG_ATTRIBBUFFERi_CONFIG2|GPUREG_ATTRIBBUFFER11_CONFIG2]]
|
|
|-
| 0227
| [[#GPUREG_INDEXBUFFER_CONFIG|GPUREG_INDEXBUFFER_CONFIG]]
|
|PICA_REG_INDEX_ARRAY_ADDR_OFFSET
|-
| 0228
| [[#GPUREG_NUMVERTICES|GPUREG_NUMVERTICES]]
|
|PICA_REG_DRAW_VERTEX_NUM
|-
| 0229
| [[#GPUREG_GEOSTAGE_CONFIG|GPUREG_GEOSTAGE_CONFIG]]
| ?
|PICA_REG_DRAW_MODE0
|-
| 022A
| [[#GPUREG_VERTEX_OFFSET|GPUREG_VERTEX_OFFSET]]
|
|PICA_REG_DRAW_VERTEX_OFFSET
|-
| 022B
| [[#GPUREG_022B|GPUREG_022B]]
|
|
|-
| 022C
| [[#GPUREG_022C|GPUREG_022C]]
|
|
|-
| 022D
| [[#GPUREG_POST_VERTEX_CACHE_NUM|GPUREG_POST_VERTEX_CACHE_NUM]]
|
|PICA_REG_POST_VERTEX_CACHE_NUM
|-
| 022E
| [[#GPUREG_DRAWARRAYS|GPUREG_DRAWARRAYS]]
|
|PICA_REG_START_DRAW_ARRAY
|-
| 022F
| [[#GPUREG_DRAWELEMENTS|GPUREG_DRAWELEMENTS]]
|
|PICA_REG_START_DRAW_ELEMENT
|-
| 0230
| [[#GPUREG_0230|GPUREG_0230]]
|
|
|-
| 0231
| [[#GPUREG_VTX_FUNC|GPUREG_VTX_FUNC]]
|?
|PICA_REG_VTX_FUNC
|-
| 0232
| [[#GPUREG_FIXEDATTRIB_INDEX|GPUREG_FIXEDATTRIB_INDEX]]
|?
|PICA_REG_VS_FIXED_ATTR
|-
| 0233
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA0]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA0
|-
| 0234
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA1]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA1
|-
| 0235
| [[#GPUREG_FIXEDATTRIB_DATAi|GPUREG_FIXEDATTRIB_DATA2]]
|?
|PICA_REG_VS_FIXED_ATTR_DATA2
|-
| 0236
| [[#GPUREG_0236|GPUREG_0236]]
|
|
|-
| 0237
| [[#GPUREG_0237|GPUREG_0237]]
|
|
|-
| 0238
| [[#GPUREG_CMDBUF_SIZE0|GPUREG_CMDBUF_SIZE0]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH0
|-
| 0239
| [[#GPUREG_CMDBUF_SIZE1|GPUREG_CMDBUF_SIZE1]]
|
|PICA_REG_COMMAND_BUF_SIZE_CH1
|-
| 023A
| [[#GPUREG_CMDBUF_ADDR0|GPUREG_CMDBUF_ADDR0]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH0
|-
| 023B
| [[#GPUREG_CMDBUF_ADDR1|GPUREG_CMDBUF_ADDR1]]
|
|PICA_REG_COMMAND_BUF_ADDR_CH1
|-
| 023C
| [[#GPUREG_CMDBUF_JUMP0|GPUREG_CMDBUF_JUMP0]]
|
|PICA_REG_COMMAND_BUF_KICK_CH0
|-
| 023D
| [[#GPUREG_CMDBUF_JUMP1|GPUREG_CMDBUF_JUMP1]]
|
|PICA_REG_COMMAND_BUF_KICK_CH1
|-
| 023E
| [[#GPUREG_023E|GPUREG_023E]]
|
|
|-
| 023F
| [[#GPUREG_023F|GPUREG_023F]]
|
|
|-
| 0240
| [[#GPUREG_0240|GPUREG_0240]]
|
|
|-
| 0241
| [[#GPUREG_0241|GPUREG_0241]]
|
|
|-
| 0242
| [[#GPUREG_VSH_NUM_ATTR|GPUREG_VSH_NUM_ATTR]]
|?
|PICA_REG_VS_ATTR_NUM1
|-
| 0243
| [[#GPUREG_0243|GPUREG_0243]]
|
|
|-
| 0244
| [[#GPUREG_VSH_COM_MODE|GPUREG_VSH_COM_MODE]]
|?
|PICA_REG_VS_COM_MODE
|-
| 0245
| [[#GPUREG_START_DRAW_FUNC0|GPUREG_START_DRAW_FUNC0]]
|?
|PICA_REG_START_DRAW_FUNC0
|-
| 0246
| [[#GPUREG_0246|GPUREG_0246]]
|
|
|-
| 0247
| [[#GPUREG_0247|GPUREG_0247]]
|
|
|-
| 0248
| [[#GPUREG_0248|GPUREG_0248]]
|
|
|-
| 0249
| [[#GPUREG_0249|GPUREG_0249]]
|
|
|-
| 024A
| [[#GPUREG_VSH_OUTMAP_TOTAL1|GPUREG_VSH_OUTMAP_TOTAL1]]
|?
|PICA_REG_VS_OUT_REG_NUM1
|-
| 024B
| [[#GPUREG_024B|GPUREG_024B]]
|
|
|-
| 024C
| [[#GPUREG_024C|GPUREG_024C]]
|
|
|-
| 024D
| [[#GPUREG_024D|GPUREG_024D]]
|
|
|-
| 024E
| [[#GPUREG_024E|GPUREG_024E]]
|
|
|-
| 024F
| [[#GPUREG_024F|GPUREG_024F]]
|
|
|-
| 0250
| [[#GPUREG_0250|GPUREG_0250]]
|
|
|-
| 0251
| [[#GPUREG_VSH_OUTMAP_TOTAL2|GPUREG_VSH_OUTMAP_TOTAL2]]
|?
|PICA_REG_VS_OUT_REG_NUM2
|-
| 0252
| [[#GPUREG_GSH_MISC0|GPUREG_GSH_MISC0]]
|?
|PICA_REG_GS_MISC_REG0
|-
| 0253
| [[#GPUREG_GEOSTAGE_CONFIG2|GPUREG_GEOSTAGE_CONFIG2]]
|?
|PICA_REG_DRAW_MODE1
|-
| 0254
| [[#GPUREG_GSH_MISC1|GPUREG_GSH_MISC1]]
|?
|PICA_REG_GS_MISC_REG1
|-
| 0255
| [[#GPUREG_0255|GPUREG_0255]]
|
|
|-
| 0256
| [[#GPUREG_0256|GPUREG_0256]]
|
|
|-
| 0257
| [[#GPUREG_0257|GPUREG_0257]]
|
|
|-
| 0258
| [[#GPUREG_0258|GPUREG_0258]]
|
|
|-
| 0259
| [[#GPUREG_0259|GPUREG_0259]]
|
|
|-
| 025A
| [[#GPUREG_025A|GPUREG_025A]]
|
|
|-
| 025B
| [[#GPUREG_025B|GPUREG_025B]]
|
|
|-
| 025C
| [[#GPUREG_025C|GPUREG_025C]]
|
|
|-
| 025D
| [[#GPUREG_025D|GPUREG_025D]]
|
|
|-
| 025E
| [[#GPUREG_PRIMITIVE_CONFIG|GPUREG_PRIMITIVE_CONFIG]]
| ?
|PICA_REG_GS_OUT_REG_NUM3 / PICA_REG_DRAW_MODE2 / PICA_REG_VS_OUT_REG_NUM3
|-
| 025F
| [[#GPUREG_RESTART_PRIMITIVE|GPUREG_RESTART_PRIMITIVE]]
|?
|PICA_REG_START_DRAW_FUNC1
|-
| 0260
| [[#GPUREG_0260|GPUREG_0260]]
|
|
|-
| 0261
| [[#GPUREG_0261|GPUREG_0261]]
|
|
|-
| 0262
| [[#GPUREG_0262|GPUREG_0262]]
|
|
|-
| 0263
| [[#GPUREG_0263|GPUREG_0263]]
|
|
|-
| 0264
| [[#GPUREG_0264|GPUREG_0264]]
|
|
|-
| 0265
| [[#GPUREG_0265|GPUREG_0265]]
|
|
|-
| 0266
| [[#GPUREG_0266|GPUREG_0266]]
|
|
|-
| 0267
| [[#GPUREG_0267|GPUREG_0267]]
|
|
|-
| 0268
| [[#GPUREG_0268|GPUREG_0268]]
|
|
|-
| 0269
| [[#GPUREG_0269|GPUREG_0269]]
|
|
|-
| 026A
| [[#GPUREG_026A|GPUREG_026A]]
|
|
|-
| 026B
| [[#GPUREG_026B|GPUREG_026B]]
|
|
|-
| 026C
| [[#GPUREG_026C|GPUREG_026C]]
|
|
|-
| 026D
| [[#GPUREG_026D|GPUREG_026D]]
|
|
|-
| 026E
| [[#GPUREG_026E|GPUREG_026E]]
|
|
|-
| 026F
| [[#GPUREG_026F|GPUREG_026F]]
|
|
|-
| 0270
| [[#GPUREG_0270|GPUREG_0270]]
|
|
|-
| 0271
| [[#GPUREG_0271|GPUREG_0271]]
|
|
|-
| 0272
| [[#GPUREG_0272|GPUREG_0272]]
|
|
|-
| 0273
| [[#GPUREG_0273|GPUREG_0273]]
|
|
|-
| 0274
| [[#GPUREG_0274|GPUREG_0274]]
|
|
|-
| 0275
| [[#GPUREG_0275|GPUREG_0275]]
|
|
|-
| 0276
| [[#GPUREG_0276|GPUREG_0276]]
|
|
|-
| 0277
| [[#GPUREG_0277|GPUREG_0277]]
|
|
|-
| 0278
| [[#GPUREG_0278|GPUREG_0278]]
|
|
|-
| 0279
| [[#GPUREG_0279|GPUREG_0279]]
|
|
|-
| 027A
| [[#GPUREG_027A|GPUREG_027A]]
|
|
|-
| 027B
| [[#GPUREG_027B|GPUREG_027B]]
|
|
|-
| 027C
| [[#GPUREG_027C|GPUREG_027C]]
|
|
|-
| 027D
| [[#GPUREG_027D|GPUREG_027D]]
|
|
|-
| 027E
| [[#GPUREG_027E|GPUREG_027E]]
|
|
|-
| 027F
| [[#GPUREG_027F|GPUREG_027F]]
|
|
|}

=== Shader registers (0x280-0x2DF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
! colspan=4 | Geometry shader
|-
| 0280
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_GSH_BOOLUNIFORM]]
|
|PICA_REG_GS_BOOL
|-
| 0281
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I0]]
|
|PICA_REG_GS_INT0
|-
| 0282
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I1]]
|
|PICA_REG_GS_INT1
|-
| 0283
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I2]]
|
|PICA_REG_GS_INT2
|-
| 0284
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_GSH_INTUNIFORM_I3]]
|
|PICA_REG_GS_INT3
|-
| 0285
| [[#GPUREG_0285|GPUREG_0285]]
|
|
|-
| 0286
| [[#GPUREG_0286|GPUREG_0286]]
|
|
|-
| 0287
| [[#GPUREG_0287|GPUREG_0287]]
|
|
|-
| 0288
| [[#GPUREG_0288|GPUREG_0288]]
|
|
|-
| 0289
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_GSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_GS_ATTR_NUM
|-
| 028A
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_GSH_ENTRYPOINT]]
|
|PICA_REG_GS_START_ADDR
|-
| 028B
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_GSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP0
|-
| 028C
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_GSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_GS_ATTR_IN_REG_MAP1
|-
| 028D
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_GSH_OUTMAP_MASK]]
|
|PICA_REG_GS_OUT_REG_MASK
|-
| 028E
| [[#GPUREG_028E|GPUREG_028E]]
|
|
|-
| 028F
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_GSH_CODETRANSFER_END]]
|
|PICA_REG_GS_PROG_RENEWAL_END
|-
| 0290
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_GSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_GS_FLOAT_ADDR
|-
| 0291
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_GS_FLOAT_DATA0
|-
| 0292
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_GS_FLOAT_DATA1
|-
| 0293
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_GS_FLOAT_DATA2
|-
| 0294
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_GS_FLOAT_DATA3
|-
| 0295
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_GS_FLOAT_DATA4
|-
| 0296
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_GS_FLOAT_DATA5
|-
| 0297
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_GS_FLOAT_DATA6
|-
| 0298
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_GSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_GS_FLOAT_DATA7
|-
| 0299
| [[#GPUREG_0299|GPUREG_0299]]
|
|
|-
| 029A
| [[#GPUREG_029A|GPUREG_029A]]
|
|
|-
| 029B
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_GSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_GS_PROG_ADDR
|-
| 029C
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA0]]
|
|PICA_REG_GS_PROG_DATA0
|-
| 029D
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA1]]
|
|PICA_REG_GS_PROG_DATA1
|-
| 029E
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA2]]
|
|PICA_REG_GS_PROG_DATA2
|-
| 029F
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA3]]
|
|PICA_REG_GS_PROG_DATA3
|-
| 02A0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA4]]
|
|PICA_REG_GS_PROG_DATA4
|-
| 02A1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA5]]
|
|PICA_REG_GS_PROG_DATA5
|-
| 02A2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA6]]
|
|PICA_REG_GS_PROG_DATA6
|-
| 02A3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_GSH_CODETRANSFER_DATA7]]
|
|PICA_REG_GS_PROG_DATA7
|-
| 02A4
| [[#GPUREG_02A4|GPUREG_02A4]]
|
|
|-
| 02A5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_GSH_OPDESCS_INDEX]]
|
|PICA_REG_GS_PROG_SWIZZLE_ADDR
|-
| 02A6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA0]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA0
|-
| 02A7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA1]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA1
|-
| 02A8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA2]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA2
|-
| 02A9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA3]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA3
|-
| 02AA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA4]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA4
|-
| 02AB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA5]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA5
|-
| 02AC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA6]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA6
|-
| 02AD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_GSH_OPDESCS_DATA7]]
|
|PICA_REG_GS_PROG_SWIZZLE_DATA7
|-
| 02AE
| [[#GPUREG_02AE|GPUREG_02AE]]
|
|
|-
| 02AF
| [[#GPUREG_02AF|GPUREG_02AF]]
|
|
|-
! colspan=4 | Vertex shader
|-
| 02B0
| [[#GPUREG_SH_BOOLUNIFORM|GPUREG_VSH_BOOLUNIFORM]]
|
|PICA_REG_VS_BOOL
|-
| 02B1
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I0]]
|
|PICA_REG_VS_INT0
|-
| 02B2
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I1]]
|
|PICA_REG_VS_INT1
|-
| 02B3
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I2]]
|
|PICA_REG_VS_INT2
|-
| 02B4
| [[#GPUREG_SH_INTUNIFORM_Ii|GPUREG_VSH_INTUNIFORM_I3]]
|
|PICA_REG_VS_INT3
|-
| 02B5
| [[#GPUREG_02B5|GPUREG_02B5]]
|
|
|-
| 02B6
| [[#GPUREG_02B6|GPUREG_02B6]]
|
|
|-
| 02B7
| [[#GPUREG_02B7|GPUREG_02B7]]
|
|
|-
| 02B8
| [[#GPUREG_02B8|GPUREG_02B8]]
|
|
|-
| 02B9
| [[#GPUREG_SH_INPUTBUFFER_CONFIG|GPUREG_VSH_INPUTBUFFER_CONFIG]]
|
|PICA_REG_VS_ATTR_NUM0
|-
| 02BA
| [[#GPUREG_SH_ENTRYPOINT|GPUREG_VSH_ENTRYPOINT]]
|
|PICA_REG_VS_START_ADDR
|-
| 02BB
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_LOW|GPUREG_VSH_ATTRIBUTES_PERMUTATION_LOW]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP0
|-
| 02BC
| [[#GPUREG_SH_ATTRIBUTES_PERMUTATION_HIGH|GPUREG_VSH_ATTRIBUTES_PERMUTATION_HIGH]]
|
|PICA_REG_VS_ATTR_IN_REG_MAP1
|-
| 02BD
| [[#GPUREG_SH_OUTMAP_MASK|GPUREG_VSH_OUTMAP_MASK]]
|
|PICA_REG_VS_OUT_REG_MASK
|-
| 02BE
| [[#GPUREG_02BE|GPUREG_02BE]]
|
|
|-
| 02BF
| [[#GPUREG_SH_CODETRANSFER_END|GPUREG_VSH_CODETRANSFER_END]]
|
|PICA_REG_VS_PROG_RENEWAL_END
|-
| 02C0
| [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_VSH_FLOATUNIFORM_INDEX]]
|
|PICA_REG_VS_FLOAT_ADDR
|-
| 02C1
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA0]]
|
|PICA_REG_VS_FLOAT_DATA0
|-
| 02C2
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA1]]
|
|PICA_REG_VS_FLOAT_DATA1
|-
| 02C3
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA2]]
|
|PICA_REG_VS_FLOAT_DATA2
|-
| 02C4
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA3]]
|
|PICA_REG_VS_FLOAT_DATA3
|-
| 02C5
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA4]]
|
|PICA_REG_VS_FLOAT_DATA4
|-
| 02C6
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA5]]
|
|PICA_REG_VS_FLOAT_DATA5
|-
| 02C7
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA6]]
|
|PICA_REG_VS_FLOAT_DATA6
|-
| 02C8
| [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_VSH_FLOATUNIFORM_DATA7]]
|
|PICA_REG_VS_FLOAT_DATA7
|-
| 02C9
| [[#GPUREG_02C9|GPUREG_02C9]]
|
|
|-
| 02CA
| [[#GPUREG_02CA|GPUREG_02CA]]
|
|
|-
| 02CB
| [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_VSH_CODETRANSFER_INDEX]]
| ?
|PICA_REG_VS_PROG_ADDR
|-
| 02CC
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA0]]
|
|PICA_REG_VS_PROG_DATA0
|-
| 02CD
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA1]]
|
|PICA_REG_VS_PROG_DATA1
|-
| 02CE
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA2]]
|
|PICA_REG_VS_PROG_DATA2
|-
| 02CF
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA3]]
|
|PICA_REG_VS_PROG_DATA3
|-
| 02D0
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA4]]
|
|PICA_REG_VS_PROG_DATA4
|-
| 02D1
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA5]]
|
|PICA_REG_VS_PROG_DATA5
|-
| 02D2
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA6]]
|
|PICA_REG_VS_PROG_DATA6
|-
| 02D3
| [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_VSH_CODETRANSFER_DATA7]]
|
|PICA_REG_VS_PROG_DATA7
|-
| 02D4
| [[#GPUREG_02D4|GPUREG_02D4]]
|
|
|-
| 02D5
| [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_VSH_OPDESCS_INDEX]]
| ?
|PICA_REG_VS_PROG_SWIZZLE_ADDR
|-
| 02D6
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA0]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA0
|-
| 02D7
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA1]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA1
|-
| 02D8
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA2]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA2
|-
| 02D9
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA3]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA3
|-
| 02DA
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA4]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA4
|-
| 02DB
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA5]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA5
|-
| 02DC
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA6]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA6
|-
| 02DD
| [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_VSH_OPDESCS_DATA7]]
|
|PICA_REG_VS_PROG_SWIZZLE_DATA7
|-
| 02DE
| [[#GPUREG_02DE|GPUREG_02DE]]
|
|
|-
| 02DF
| [[#GPUREG_02DF|GPUREG_02DF]]
|
|
|}

=== Unknown registers (0x2E0-0x2FF) ===

{| class="wikitable" border="1"
! Register ID
! Register name
! Notes
! Official Name
|-
| 02E0
| [[#GPUREG_02E0|GPUREG_02E0]]
|
|
|-
| 02E1
| [[#GPUREG_02E1|GPUREG_02E1]]
|
|
|-
| 02E2
| [[#GPUREG_02E2|GPUREG_02E2]]
|
|
|-
| 02E3
| [[#GPUREG_02E3|GPUREG_02E3]]
|
|
|-
| 02E4
| [[#GPUREG_02E4|GPUREG_02E4]]
|
|
|-
| 02E5
| [[#GPUREG_02E5|GPUREG_02E5]]
|
|
|-
| 02E6
| [[#GPUREG_02E6|GPUREG_02E6]]
|
|
|-
| 02E7
| [[#GPUREG_02E7|GPUREG_02E7]]
|
|
|-
| 02E8
| [[#GPUREG_02E8|GPUREG_02E8]]
|
|
|-
| 02E9
| [[#GPUREG_02E9|GPUREG_02E9]]
|
|
|-
| 02EA
| [[#GPUREG_02EA|GPUREG_02EA]]
|
|
|-
| 02EB
| [[#GPUREG_02EB|GPUREG_02EB]]
|
|
|-
| 02EC
| [[#GPUREG_02EC|GPUREG_02EC]]
|
|
|-
| 02ED
| [[#GPUREG_02ED|GPUREG_02ED]]
|
|
|-
| 02EE
| [[#GPUREG_02EE|GPUREG_02EE]]
|
|
|-
| 02EF
| [[#GPUREG_02EF|GPUREG_02EF]]
|
|
|-
| 02F0
| [[#GPUREG_02F0|GPUREG_02F0]]
|
|
|-
| 02F1
| [[#GPUREG_02F1|GPUREG_02F1]]
|
|
|-
| 02F2
| [[#GPUREG_02F2|GPUREG_02F2]]
|
|
|-
| 02F3
| [[#GPUREG_02F3|GPUREG_02F3]]
|
|
|-
| 02F4
| [[#GPUREG_02F4|GPUREG_02F4]]
|
|
|-
| 02F5
| [[#GPUREG_02F5|GPUREG_02F5]]
|
|
|-
| 02F6
| [[#GPUREG_02F6|GPUREG_02F6]]
|
|
|-
| 02F7
| [[#GPUREG_02F7|GPUREG_02F7]]
|
|
|-
| 02F8
| [[#GPUREG_02F8|GPUREG_02F8]]
|
|
|-
| 02F9
| [[#GPUREG_02F9|GPUREG_02F9]]
|
|
|-
| 02FA
| [[#GPUREG_02FA|GPUREG_02FA]]
|
|
|-
| 02FB
| [[#GPUREG_02FB|GPUREG_02FB]]
|
|
|-
| 02FC
| [[#GPUREG_02FC|GPUREG_02FC]]
|
|
|-
| 02FD
| [[#GPUREG_02FD|GPUREG_02FD]]
|
|
|-
| 02FE
| [[#GPUREG_02FE|GPUREG_02FE]]
|
|
|-
| 02FF
| [[#GPUREG_02FF|GPUREG_02FF]]
|
|
|}

== Miscellaneous registers ==

=== GPUREG_FINALIZE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger P3D Interrupt (0 = idle, non-zero = trigger)
|}

Writing to this register seems to signal the GPU to stop processing GPU commands from the current buffer; any command following a write to this register will be ignored. The value written to this register does not appear to matter, although 0x12345678 is the value typically written by commercial software.
Failure to write to this register in any command buffer will result in the GPU hanging.

== Rasterizer registers ==

=== GPUREG_FACECULLING_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Culling mode
|}

This register is used to configure the face culling mode.

Culling mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Front Face (Counter Clockwise)
|-
| 2
| Back Face (Counter Clockwise)
|}

=== GPUREG_VIEWPORT_WIDTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, width / 2
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_INVW.

=== GPUREG_VIEWPORT_INVW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / width
|}

This register is used to configure the viewport width, along with GPUREG_VIEWPORT_WIDTH.

=== GPUREG_VIEWPORT_HEIGHT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, height / 2
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_INVH.

=== GPUREG_VIEWPORT_INVH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-31
| float1.7.23, 2 / height
|}

This register is used to configure the viewport height, along with GPUREG_VIEWPORT_HEIGHT.

=== GPUREG_FRAGOP_CLIP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable clipping planes.

=== GPUREG_FRAGOP_CLIP_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Clipping plane coefficient ''i''
|}

This register is used to configure clipping plane coefficients.

=== GPUREG_DEPTHMAP_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near - Far
|}

This register is used to configure the depth range scale.

=== GPUREG_DEPTHMAP_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| float1.7.16, Near + Polygon Offset
|}

This register is used to configure the depth range bias.

=== GPUREG_SH_OUTMAP_TOTAL ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of following attributes
|}

This register is used to configure the total shader output map attributes.

=== GPUREG_SH_OUTMAP_O''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Semantic for the x component of the register.
|-
| 8-12
| unsigned, Semantic for the y component of the register.
|-
| 16-20
| unsigned, Semantic for the z component of the register.
|-
| 24-28
| unsigned, Semantic for the w component of the register.
|}

These registers map components of the corresponding vertex shader output register to specific fixed-function semantics.

Semantic values:

{| class="wikitable" border="1"
! Value
! Semantic
! Description
|-
| 0x00
| position.x
| rowspan="4" | Vertex Position
|-
| 0x01
| position.y
|-
| 0x02
| position.z
|-
| 0x03
| position.w
|-
| 0x04
| normquat.x
| rowspan="4" | Quaternion specifying the normal/tangent frame (for fragment lighting)
|-
| 0x05
| normquat.y
|-
| 0x06
| normquat.z
|-
| 0x07
| normquat.w
|-
| 0x08
| color.r
| rowspan="4" | Vertex color
|-
| 0x09
| color.g
|-
| 0x0A
| color.b
|-
| 0x0B
| color.a
|-
| 0x0C
| texcoord0.u
| rowspan="2" | Texture coordinates for texture 0
|-
| 0x0D
| texcoord0.v
|-
| 0x0E
| texcoord1.u
| rowspan="2" | Texture coordinates for texture 1
|-
| 0x0F
| texcoord1.v
|-
| 0x10
| texcoord0.w
|

|-
| 0x12
| view.x
| rowspan="3" | View vector (for fragment lighting)
|-
| 0x13
| view.y
|-
| 0x14
| view.z

|-
| 0x16
| texcoord2.u
| rowspan="2" | Texture coordinates for texture 2
|-
| 0x17
| texcoord2.v

|-
| 0x1F
| Unused component
| Should be set for unused components of the output register
|}

=== GPUREG_EARLYDEPTH_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Early depth function
|}

This register configures the early depth test function.

Early depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| >=
|-
| 1
| >
|-
| 2
| <=
|-
| 3
| <
|}

=== GPUREG_EARLYDEPTH_TEST1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register sets whether the early depth test is enabled.

=== GPUREG_EARLYDEPTH_CLEAR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = clear)
|}

This register triggers clearing the early depth data.

=== GPUREG_SH_OUTATTR_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Use texture coordinates (0 = don't use, 1 = use)
|}

This register is used to configure the shader output attribute mode.

=== GPUREG_SCISSORTEST_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Enabled (0 = disabled, 3 = enabled)
|}

This register is used to enable scissor testing.

=== GPUREG_SCISSORTEST_POS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X1
|-
| 16-25
| unsigned, Y1
|}

This register is used to configure the scissor test start position.

=== GPUREG_SCISSORTEST_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| unsigned, X2
|-
| 16-25
| unsigned, Y2
|}

This register is used to configure the scissor test end position.

=== GPUREG_VIEWPORT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-9
| signed, X
|-
| 16-25
| signed, Y
|}

This register is used to configure the viewport position.

=== GPUREG_EARLYDEPTH_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| unsigned, Clear value
|}

This register is used to configure the early depth clear value.

=== GPUREG_DEPTHMAP_ENABLE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable depth range.

=== GPUREG_RENDERBUF_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register is used to configure the output framebuffer dimensions.

=== GPUREG_SH_OUTATTR_CLOCK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, 'position.z' present (0 = absent, 1 = present)
|-
| 1
| unsigned, 'color' component present (0 = absent, 1 = present)
|-
| 8
| unsigned, 'texcoord0' component present (0 = absent, 1 = present)
|-
| 9
| unsigned, 'texcoord1' component present (0 = absent, 1 = present)
|-
| 10
| unsigned, 'texcoord2' component present (0 = absent, 1 = present)
|-
| 16
| unsigned, 'texcoord0.w' present (0 = absent, 1 = present)
|-
| 24
| unsigned, 'normquat' or 'view' component present (0 = absent, 1 = present)
|}

This register controls the clock supply to parts relating to certain attributes.

== Texturing registers ==

=== GPUREG_TEXUNIT_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Texture 0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Texture 1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Texture 2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| 0x0
|-
| 8-9
| unsigned, Texture 3 coordinates
|-
| 10
| unsigned, Texture 3 enabled (0 = disabled, 1 = enabled)
|-
| 12
| 0x1
|-
| 13
| unsigned, Texture 2 coordinates
|-
| 16
| unsigned, Clear texture cache (0 = don't clear, 1 = clear)
|-
| 17-31
| 0x0
|}

This register is used to enable texture units.

Texture 3 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 0
|-
| 1
| Texture 1
|-
| 2
| Texture 2
|}

Texture 2 coordinates values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Texture 2
|-
| 1
| Texture 1
|}

=== GPUREG_TEXUNIT''i''_BORDER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to set a texture unit's border color.

=== GPUREG_TEXUNIT''i''_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Height
|-
| 16-26
| unsigned, Width
|}

This register is used to set a texture unit's dimensions.

=== GPUREG_TEXUNIT''i''_PARAM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, Magnification filter
|-
| 2
| unsigned, Minification filter
|-
| 4-5
| unsigned, ETC1 (0 = not ETC1, 2 = ETC1) note: still 0 for ETC1A4
|-
| 8-10
| unsigned, Wrap T
|-
| 12-14
| unsigned, Wrap S
|-
| 16-17
| 0x0
|-
| 20
| unsigned, Shadow (Texture 0 only, 0 = not shadow, 1 = shadow)
|-
| 24
| unsigned, Mipmap filter
|-
| 28-30
| unsigned, Type (Texture 0 only)
|}

This register is used to set a texture unit's extra parameters.

Filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|}

Wrap values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to edge
|-
| 1
| Clamp to border
|-
| 2
| Repeat
|-
| 3
| Mirrored repeat
|}

Type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 2D
|-
| 1
| Cube map
|-
| 2
| Shadow 2D
|-
| 3
| Projection
|-
| 4
| Shadow cube
|-
| 5
| Disabled
|}

=== GPUREG_TEXUNIT''i''_LOD ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.4.8, Bias
|-
| 16-19
| unsigned, Max Level
|-
| 24-27
| unsigned, Min Level
|}

This register is used to configure a texture unit's level of detail.

=== GPUREG_TEXUNIT''i''_ADDR''i'' ===

First ADDR register:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Texture physical address >> 3
|}

Subsequent ADDR registers:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-21
| unsigned, Texture physical address >> 3 (upper 6 bits reused from first ADDR register)
|}

This register is used to set a texture unit's physical address(es) in memory. Individual texels in a texture are laid out in memory as a [http://en.wikipedia.org/wiki/Z-order_curve Z-order curve]. Mipmap data is stored directly following the main texture data.

If the texture is a cube:

{| class="wikitable" border="1"
! Register
! Description
|-
| ADDR1
| Positive X
|-
| ADDR2
| Negative X
|-
| ADDR3
| Positive Y
|-
| ADDR4
| Negative Y
|-
| ADDR5
| Positive Z
|-
| ADDR6
| Negative Z
|}

Otherwise, ADDR(1) points to a 2D texture, and the rest are empty.

=== GPUREG_TEXUNIT''i''_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Perspective (0 = perspective, 1 = not perspective)
|-
| 1-23
| fixed0.0.24, Z bias (upper 23 bits)
|}

This register is used to set a texture unit's shadow texture properties.

=== GPUREG_TEXUNIT''i''_TYPE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Format
|}

This register is used to set a texture unit's data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
! GL Format
! GL Data Type
|-
| 0x0
| RGBA8888
| GL_RGBA
| GL_UNSIGNED_BYTE
|-
| 0x1
| RGB888
| GL_RGB
| GL_UNSIGNED_BYTE
|-
| 0x2
| RGBA5551
| GL_RGBA
| GL_UNSIGNED_SHORT_5_5_5_1
|-
| 0x3
| RGB565
| GL_RGB
| GL_UNSIGNED_SHORT_5_6_5
|-
| 0x4
| RGBA4444
| GL_RGBA
| GL_UNSIGNED_SHORT_4_4_4_4
|-
| 0x5
| IA8
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x6
| HILO8
|
|
|-
| 0x7
| I8
| GL_LUMINANCE
| GL_UNSIGNED_BYTE
|-
| 0x8
| A8
| GL_ALPHA
| GL_UNSIGNED_BYTE
|-
| 0x9
| IA44
| GL_LUMINANCE_ALPHA
| GL_UNSIGNED_BYTE_4_4_EXT
|-
| 0xA
| I4
|
|
|-
| 0xB
| A4
| GL_ALPHA
| GL_UNSIGNED_NIBBLE_EXT
|-
| 0xC
| ETC1
| GL_ETC1_RGB8_OES
|
|-
| 0xD
| ETC1A4
|
|
|}

=== GPUREG_LIGHTING_ENABLE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register is used to enable lighting.

=== GPUREG_TEXUNIT3_PROCTEX0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, U-direction clamp
|-
| 3-5
| unsigned, V-direction clamp
|-
| 6-9
| unsigned, RGB mapping function
|-
| 10-13
| unsigned, Alpha mapping function
|-
| 14
| unsigned, Handle alpha separately (0 = don't separate, 1 = separate)
|-
| 15
| unsigned, Noise enabled (0 = disabled, 1 = enabled)
|-
| 16-17
| unsigned, U-direction shift
|-
| 18-19
| unsigned, V-direction shift
|-
| 20-27
| float1.5.10, Texture bias (lower 8 bits)
|}

This register is used to configure the procedural texture unit.

Clamp values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clamp to zero
|-
| 1
| Clamp to edge
|-
| 2
| Symmetrical repeat
|-
| 3
| Mirrored repeat
|-
| 4
| Pulse
|}

Mapping function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| U
|-
| 1
| U²
|-
| 2
| V
|-
| 3
| V²
|-
| 4
| (U + V) / 2
|-
| 5
| (U² + V²) / 2
|-
| 6
| sqrt(U² + V²)
|-
| 7
| Minimum
|-
| 8
| Maximum
|-
| 9
| Rmax
|}

Shift values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Odd
|-
| 2
| Even
|}

=== GPUREG_TEXUNIT3_PROCTEX1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, U-direction noise amplitude
|-
| 16-31
| float1.5.10, U-direction noise phase
|}

This register is used to configure the procedural texture unit's U-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| fixed1.3.12, V-direction noise amplitude
|-
| 16-31
| float1.5.10, V-direction noise phase
|}

This register is used to configure the procedural texture unit's V-direction noise amplitude/phase.

=== GPUREG_TEXUNIT3_PROCTEX3 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, U-direction noise frequency
|-
| 16-31
| float1.5.10, V-direction noise frequency
|}

This register is used to configure the procedural texture unit's U-direction and V-direction noise frequency.

=== GPUREG_TEXUNIT3_PROCTEX4 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Minification filter
|-
| 3-6
| Min LOD (usually 0)
|-
| 7-10
| Max LOD (usually 6)
|-
| 11-18
| unsigned, Texture width
|-
| 19-26
| float1.5.10, Texture bias (upper 8 bits)
|}

This register is used to configure the procedural texture unit.

Minification filter values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Nearest
|-
| 1
| Linear
|-
| 2
| Nearest, Mipmap Nearest
|-
| 3
| Linear, Mipmap Nearest
|-
| 4
| Nearest, Mipmap Linear
|-
| 5
| Linear, Mipmap Linear
|}

=== GPUREG_TEXUNIT3_PROCTEX5 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Texture offset (Mipmap level 0 / base level)
|-
| 8-15
| unsigned, mipmap level 1 offset (usually 0x80)
|-
| 16-23
| unsigned, mipmap level 2 offset (usually 0xC0)
|-
| 24-31
| unsigned, mipmap level 3 offset (usually 0xE0)
|}

This register is used to set the procedural texture unit's offset. Mipmap level 4-7 seems to be hardcoded at offset 0xF0, 0xF8, 0xFC and 0xFE .

=== GPUREG_PROCTEX_LUT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Index
|-
| 8-11
| unsigned, Reference table
|}

This register is used to set which look-up table to write to, with GPUREG_PROCTEX_LUT_DATA''i'', at what index.

Reference table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Noise table
|-
| 2
| RGB mapping function table
|-
| 3
| Alpha mapping function table
|-
| 4
| Color table
|-
| 5
| Color difference table
|}

=== GPUREG_PROCTEX_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the table selected with GPUREG_PROCTEX_LUT, starting at the selected index.

==== Noise Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement ( [0.5,1.0) mapped to [-1.0,0) ), Difference from next element
|}

==== RGB Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement, Difference from next element
|}

==== Alpha Mapping Function Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Value
|-
| 12-23
| fixed0.0.12 with two's complement, Difference from next element
|}

==== Color Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

==== Color Difference Table ====

256 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Half of red difference between current and next color table elements
|-
| 8-15
| signed, Half of green difference between current and next color table elements
|-
| 16-23
| signed, Half of blue difference between current and next color table elements
|-
| 24-31
| signed, Half of alpha difference between current and next color table elements
|}

=== GPUREG_TEXENV''i''_SOURCE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB source 0
|-
| 4-7
| unsigned, RGB source 1
|-
| 8-11
| unsigned, RGB source 2
|-
| 16-19
| unsigned, Alpha source 0
|-
| 20-23
| unsigned, Alpha source 1
|-
| 24-27
| unsigned, Alpha source 2
|}

This register configures a texture combiner's sources.

Source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Primary color
|-
| 1
| Fragment primary color
|-
| 2
| Fragment secondary color
|-
| 3
| Texture 0
|-
| 4
| Texture 1
|-
| 5
| Texture 2
|-
| 6
| Texture 3
|-
| 13
| Previous buffer
|-
| 14
| Constant (from GPUREG_TEXENV''i''_COLOR)
|-
| 15
| Previous
|}

Using previous source in the first TEV stage returns the primary color, while previous buffer returns zero.

=== GPUREG_TEXENV''i''_OPERAND ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB operand 0
|-
| 4-7
| unsigned, RGB operand 1
|-
| 8-11
| unsigned, RGB operand 2
|-
| 12-14
| unsigned, Alpha operand 0
|-
| 16-18
| unsigned, Alpha operand 1
|-
| 20-22
| unsigned, Alpha operand 2
|}

This register configures a texture combiner's operands.

RGB operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source color
|-
| 1
| One minus source color
|-
| 2
| Source alpha
|-
| 3
| One minus source alpha
|-
| 4
| Source red
|-
| 5
| One minus source red
|-
| 8
| Source green
|-
| 9
| One minus source green
|-
| 12
| Source blue
|-
| 13
| One minus source blue
|}

Alpha operand values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Source alpha
|-
| 1
| One minus source alpha
|-
| 2
| Source red
|-
| 3
| One minus source red
|-
| 4
| Source green
|-
| 5
| One minus source green
|-
| 6
| Source blue
|-
| 7
| One minus source blue
|}

=== GPUREG_TEXENV''i''_COMBINER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, RGB combine
|-
| 16-19
| unsigned, Alpha combine
|}

This register configures a texture combiner's combine mode.

Combine values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Replace
|-
| 1
| Modulate
|-
| 2
| Add
|-
| 3
| Add signed
|-
| 4
| Interpolate
|-
| 5
| Subtract
|-
| 6
| Dot3 RGB
|-
| 7
| Dot3 RGBA
|-
| 8
| Multiply then add
|-
| 9
| Add then multiply
|}

=== GPUREG_TEXENV''i''_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register configures a texture combiner's constant color.

=== GPUREG_TEXENV''i''_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, RGB scale
|-
| 16-17
| unsigned, Alpha scale
|}

This register configures a texture combiner's scale value.

Scale values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|}

=== GPUREG_TEXENV_UPDATE_BUFFER ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fog mode
|-
| 3
| unsigned, Shading density source
|-
| 8
| unsigned, TexEnv 1 RGB buffer input
|-
| 9
| unsigned, TexEnv 2 RGB buffer input
|-
| 10
| unsigned, TexEnv 3 RGB buffer input
|-
| 11
| unsigned, TexEnv 4 RGB buffer input
|-
| 12
| unsigned, TexEnv 1 alpha buffer input
|-
| 13
| unsigned, TexEnv 2 alpha buffer input
|-
| 14
| unsigned, TexEnv 3 alpha buffer input
|-
| 15
| unsigned, TexEnv 4 alpha buffer input
|-
| 16
| unsigned, Z flip (0 = don't flip, 1 = flip)
|-
| 24-25
| 0x0
|}

This register is shared between the gas/fog mode configuration and texture combiner buffer inputs. Texture combiner buffer inputs are typically written with a mask of 0x2, and the gas/fog mode configuration is typically written with a mask of 0x5.

Fog mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Disabled
|-
| 5
| Fog
|-
| 7
| Gas
|}

Shading density source values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Plain density
|-
| 1
| Depth density
|}

Buffer input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Previous buffer
|-
| 1
| Previous
|}

=== GPUREG_FOG_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

This register is used to configure the color of fog.

=== GPUREG_GAS_ATTENUATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas density attenuation
|}

This register is used to configure the gas density attenuation.

=== GPUREG_GAS_ACCMAX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Gas maximum density accumulation
|}

This register is used to configure the gas maximum density accumulation.

=== GPUREG_FOG_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_FOG_LUT_DATA''i''.

=== GPUREG_FOG_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the fog look-up table, starting at the index selected with GPUREG_FOG_LUT_INDEX.

==== Fog Look-Up Table ====

128 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Difference from next element
|-
| 13-23
| fixed0.0.11, Value
|}

=== GPUREG_TEXENV_BUFFER_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the texture combiner buffer color.

== Framebuffer registers ==

=== GPUREG_COLOR_OPERATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Fragment operation mode
|-
| 8
| unsigned, Blend mode
|-
| 16-25
| 0x0E4
|}

This register is used to configure the fragment operation mode and whether to use logic ops or blending.

Fragment operation mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Default
|-
| 1
| Gas
|-
| 3
| Shadow
|}

Blend mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Logic op
|-
| 1
| Blend
|}

=== GPUREG_BLEND_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, RGB equation
|-
| 8-10
| unsigned, Alpha equation
|-
| 16-19
| unsigned, RGB source function
|-
| 20-23
| unsigned, RGB destination function
|-
| 24-27
| unsigned, Alpha source function
|-
| 28-31
| unsigned, Alpha destination function
|}

This register is used to configure the blending function.

'''Equation values:'''

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Add
|-
| 1
| Subtract
|-
| 2
| Reverse subtract
|-
| 3
| Minimum
|-
| 4
| Maximum
|}

Blend equations 5, 6, 7 appear to behave the same as blend equation 0 (Add)

'''Function values:'''

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Zero
|-
| 1
| One
|-
| 2
| Source color
|-
| 3
| One minus source color
|-
| 4
| Destination color
|-
| 5
| One minus destination color
|-
| 6
| Source alpha
|-
| 7
| One minus source alpha
|-
| 8
| Destination alpha
|-
| 9
| One minus destination alpha
|-
| 10
| Constant color
|-
| 11
| One minus constant color
|-
| 12
| Constant alpha
|-
| 13
| One minus constant alpha
|-
| 14
| Source alpha saturate
|}

=== GPUREG_LOGIC_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Logic op
|}

This register is used to configure the logic op.

Logic op values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Clear
|-
| 1
| AND
|-
| 2
| Reverse AND
|-
| 3
| Copy
|-
| 4
| Set
|-
| 5
| Inverted copy
|-
| 6
| Noop
|-
| 7
| Invert
|-
| 8
| NAND
|-
| 9
| OR
|-
| 10
| NOR
|-
| 11
| XOR
|-
| 12
| Equivalent
|-
| 13
| Inverted AND
|-
| 14
| Reverse OR
|-
| 15
| Inverted OR
|}

=== GPUREG_BLEND_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|-
| 24-31
| unsigned, Alpha
|}

This register is used to configure the blending color.

=== GPUREG_FRAGOP_ALPHA_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Reference value
|}

This register is used to configure alpha testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_TEST ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Function
|-
| 8-15
| unsigned, Buffer mask
|-
| 16-23
| signed, Reference value
|-
| 24-31
| unsigned, Mask
|}

This register is used to configure stencil testing.

Function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_STENCIL_OP ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Fail operation
|-
| 4-6
| unsigned, Z-fail operation
|-
| 8-10
| unsigned, Z-pass operation
|}

This register is used to configure stencil result operations.

Operation values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Keep
|-
| 1
| Zero
|-
| 2
| Replace
|-
| 3
| Increment
|-
| 4
| Decrement
|-
| 5
| Invert
|-
| 6
| Increment and wrap
|-
| 7
| Decrement and wrap
|}

=== GPUREG_DEPTH_COLOR_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Depth test enabled (0 = disabled, 1 = enabled)
|-
| 4-6
| unsigned, Depth function
|-
| 8
| unsigned, Red write enabled (0 = disabled, 1 = enabled)
|-
| 9
| unsigned, Green write enabled (0 = disabled, 1 = enabled)
|-
| 10
| unsigned, Blue write enabled (0 = disabled, 1 = enabled)
|-
| 11
| unsigned, Alpha write enabled (0 = disabled, 1 = enabled)
|-
| 12
| unsigned, Depth write enabled (0 = disabled, 1 = enabled)
|}

This register is used to depth testing and framebuffer write masking.

Note that setting the "Depth test enabled" bit to 0 will ''not'' also disable depth writes. It will instead behave as if the depth function were set to "Always". To completely disable depth-related operations both the depth test and depth write bits must be disabled.

Depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Equal
|-
| 3
| Not equal
|-
| 4
| Less than
|-
| 5
| Less than or equal
|-
| 6
| Greater than
|-
| 7
| Greater than or equal
|}

=== GPUREG_FRAMEBUFFER_INVALIDATE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = invalidate)
|-
| 1-31
| 0x0
|}

Writing 1 to this register invalidates the framebuffer cache. This should be done when changing the framebuffer or when it is cleared before rendering. Note that it does '''not''' flush the cache, so it should always be preceded by a write to GPUREG_FRAMEBUFFER_FLUSH.

=== GPUREG_FRAMEBUFFER_FLUSH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = flush)
|-
| 1-31
| 0x0
|}

Writing 1 to this register flushes the framebuffer cache to memory. This should be done after rendering before changing the framebuffer or using rendering results.

=== GPUREG_COLORBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow read (0 = disable, 0xF = enable)
|}

This register configures read access from the color buffer.

=== GPUREG_COLORBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Allow write (0 = disable, 0xF = enable)
|}

This register configures write access to the color buffer.

=== GPUREG_DEPTHBUFFER_READ ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil read (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth read (0 = disable, 1 = enable)
|}

This register configures read access from the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_WRITE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Allow stencil write (0 = disable, 1 = enable)
|-
| 1
| unsigned, Allow depth write (0 = disable, 1 = enable)
|}

This register configures write access to the depth and stencil buffers.

=== GPUREG_DEPTHBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Format
|}

This register configures the depth buffer data format.

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit depth
|-
| 2
| 24-bit depth
|-
| 3
| 24-bit depth + 8-bit stencil
|}

=== GPUREG_COLORBUFFER_FORMAT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Pixel size
|-
| 16-18
| unsigned, Format
|}

This register configures the color buffer data format. Color components are laid out in reverse byte order in memory, with the most significant bits used first.

Pixel size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 16-bit color
|-
| 2
| 32-bit color
|}

Format values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| RGBA8/Gas
|-
| 2
| RGB5A1
|-
| 3
| RGB565
|-
| 4
| RGBA4
|}

=== GPUREG_EARLYDEPTH_TEST2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Enabled (0 = disabled, 1 = enabled)
|}

This register enables the early depth test.

=== GPUREG_FRAMEBUFFER_BLOCK32 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Render block mode
|}

This register configures the framebuffer block mode. To untile the color buffer when using the 32x32 block format, use bit 16 of the [[GPU/External_Registers#Transfer_Engine|display transfer flags]]. It is unknown if there are any advantages to using the 32x32 format.

Render block mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8x8 blocks
|-
| 1
| 32x32 blocks
|}

=== GPUREG_DEPTHBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Depth buffer physical address >> 3
|}

This register configures the depth buffer physical address.

=== GPUREG_COLORBUFFER_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Color buffer physical address >> 3
|}

This register configures the color buffer physical address.

=== GPUREG_FRAMEBUFFER_DIM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-10
| unsigned, Width
|-
| 12-21
| unsigned, Height - 1
|-
| 24
| 0x1
|}

This register configures the framebuffer dimensions.

=== GPUREG_GAS_LIGHT_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Planar shading minimum intensity
|-
| 8-15
| unsigned, Planar shading maximum intensity
|-
| 16-23
| unsigned, Planar shading density attenuation
|}

This register configures gas light planar shading.

=== GPUREG_GAS_LIGHT_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading minimum intensity
|-
| 8-15
| unsigned, View shading maximum intensity
|-
| 16-23
| unsigned, View shading density attenuation
|}

This register configures gas light view shading.

=== GPUREG_GAS_LIGHT_Z_COLOR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, View shading effect in line-of-sight direction
|-
| 8
| Gas color LUT input
|}

This register configures gas light shading in the line-of-sight direction, and the input to the gas color LUT.

Color LUT input values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Gas density
|-
| 1
| Light factor
|}

=== GPUREG_GAS_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Index
|}

This register is used to set what index to write to with GPUREG_GAS_LUT_DATA''i''.

=== GPUREG_GAS_LUT_DATA ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| LUT data
|}

These registers behave as a FIFO queue. Each write to these registers writes the provided value to the gas look-up table, starting at the index selected with GPUREG_GAS_LUT_INDEX.

==== Gas Look-Up Table ====

16 elements:

First 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| signed, Red
|-
| 8-15
| signed, Green
|-
| 16-23
| signed, Blue
|}

Last 8 elements:
{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Red
|-
| 8-15
| unsigned, Green
|-
| 16-23
| unsigned, Blue
|}

=== GPUREG_GAS_DELTAZ_DEPTH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| fixed0.16.8, Depth direction attenuation proportion
|-
| 24-25
| unsigned, Depth function
|}

This register is used to configure the gas depth direction attenuation proportion, as well as the gas depth function.

Gas depth function values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Never
|-
| 1
| Always
|-
| 2
| Greater than/Greater than or equal
|-
| 3
| Less than/Less than or equal/Equal/Not equal
|}

=== GPUREG_FRAGOP_SHADOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Sum of penumbra scale and penumbra bias
|-
| 16-31
| float1.5.10, Penumbra scale with reversed sign
|}

This register is used to configure shadow properties.

== Fragment lighting registers ==

=== GPUREG_LIGHT''i''_SPECULAR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular0 color of the corresponding light. Usually set to material_specular0*lightX_specular0.

=== GPUREG_LIGHT''i''_SPECULAR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the specular1 color of the corresponding light. Usually set to material_specular1*lightX_specular1.

=== GPUREG_LIGHT''i''_DIFFUSE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the diffuse color of the corresponding light. Usually set to material_diffuse*lightX_diffuse.

=== GPUREG_LIGHT''i''_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

These registers contain the ambient color of the corresponding light. Usually set to material_ambient*lightX_ambient.

=== GPUREG_LIGHT''i''_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, X coordinate
|-
| 16-31
| float1.5.10, Y coordinate
|}

These registers (along with GPUREG_LIGHT''i''_Z) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| float1.5.10, Z coordinate
|}

These registers (along with GPUREG_LIGHT''i''_XY) represent the light position (for a positional light) or the light direction vector (for a directional light) of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_XY ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, X coordinate (negated)
|-
| 16-28
| fixed1.1.11, Y coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_Z) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_SPOTDIR_Z ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-12
| fixed1.1.11, Z coordinate (negated)
|}

These registers (along with GPUREG_LIGHT''i''_SPOTDIR_XY) represent the spot direction (unitary) vector of the corresponding light.

=== GPUREG_LIGHT''i''_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Light type (0 = positional light, 1 = directional light)
|-
| 1
| unsigned, Two side diffuse (0 = one side, 1 = both sides)
|-
| 2
| unsigned, Use geometric factor 0 (0 = don't use, 1 = use)
|-
| 3
| unsigned, Use geometric factor 1 (0 = don't use, 1 = use)
|}

This register configures a light's properties.

=== GPUREG_LIGHT''i''_ATTENUATION_BIAS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation bias
|}

These registers contain the distance attenuation bias value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHT''i''_ATTENUATION_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-19
| float1.7.12, Distance attenuation scale
|}

These registers contain the distance attenuation scale value of the corresponding light. The attenuation factor is DA(clip(bias + scale*distance, 0.0, 1.0)).

=== GPUREG_LIGHTING_AMBIENT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Blue
|-
| 10-17
| unsigned, Green
|-
| 20-27
| unsigned, Red
|}

This register contains the initial value of the fragment primary color before the partial colors that correspond to each enabled light are added. Usually set to material_emission + material_ambient*scene_ambient.

=== GPUREG_LIGHTING_NUM_LIGHTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Number of active lights - 1
|}

This register configures the number of active lights.

=== GPUREG_LIGHTING_CONFIG0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Shadow factor enabled (0 = disabled, 1 = enabled) (usually accompanied by bit 16, 17, or 18)
|-
| 2-3
| unsigned, Fresnel selector
|-
| 4-7
| unsigned, Light environment configuration
|-
| 8-11
| 0x4
|-
| 16
| unsigned, Apply shadow attenuation to primary color (0 = don't apply, 1 = apply)
|-
| 17
| unsigned, Apply shadow attenuation to secondary color (0 = don't apply, 1 = apply)
|-
| 18
| unsigned, Invert shadow attenuation (0 = don't invert, 1 = invert)
|-
| 19
| unsigned, Apply shadow attenuation to alpha component (0 = don't apply, 1 = apply)
|-
| 22-23
| unsigned, Bump map texture unit
|-
| 24-25
| unsigned, Shadow map texture unit
|-
| 27
| unsigned, Clamp highlights (0 = disabled, 1 = enabled)
|-
| 28-29
| unsigned, Bump mode
|-
| 30
| unsigned, Recalculate bump vectors (0 = enabled, 1 = disabled) (usually set to 1 when bump mode is not 0)
|-
| 31
| 0x1
|}

This register configures the light environment.

Fresnel selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| None
|-
| 1
| Primary alpha
|-
| 2
| Secondary alpha
|-
| 3
| Primary and secondary alpha
|}

The light environment configuration controls which LUTs are available for use. If a LUT is not available in the selected configuration, its value will always read a constant 1.0 regardless of the enable state in GPUREG_LIGHTING_CONFIG1. If RR is enabled but not RG or RB, the output of RR is used for the three components; Red, Green and Blue.

Light environment configuration values:

{| class="wikitable" border="1"
! Value
! Description
! Available LUTs
|-
| 0
| Configuration 0
| D0, RR, SP, DA
|-
| 1
| Configuration 1
| FR, RR, SP, DA
|-
| 2
| Configuration 2
| D0, D1, RR, DA
|-
| 3
| Configuration 3
| D0, D1, FR, DA
|-
| 4
| Configuration 4
| All except for FR
|-
| 5
| Configuration 5
| All except for D1
|-
| 6
| Configuration 6
| All except for RB and RG
|-
| 8
| Configuration 7
| All
|}

Bump mode values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Not used
|-
| 1
| Use as bump map
|-
| 2
| Use as tangent map
|}

=== GPUREG_LIGHTING_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Fragment light source 0 shadows disabled (0 = enabled, 1 = disabled)
|-
| 1
| unsigned, Fragment light source 1 shadows disabled (0 = enabled, 1 = disabled)
|-
| 2
| unsigned, Fragment light source 2 shadows disabled (0 = enabled, 1 = disabled)
|-
| 3
| unsigned, Fragment light source 3 shadows disabled (0 = enabled, 1 = disabled)
|-
| 4
| unsigned, Fragment light source 4 shadows disabled (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, Fragment light source 5 shadows disabled (0 = enabled, 1 = disabled)
|-
| 6
| unsigned, Fragment light source 6 shadows disabled (0 = enabled, 1 = disabled)
|-
| 7
| unsigned, Fragment light source 7 shadows disabled (0 = enabled, 1 = disabled)
|-
| 8
| unsigned, Fragment light source 0 spot light disabled (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, Fragment light source 1 spot light disabled (0 = enabled, 1 = disabled)
|-
| 10
| unsigned, Fragment light source 2 spot light disabled (0 = enabled, 1 = disabled)
|-
| 11
| unsigned, Fragment light source 3 spot light disabled (0 = enabled, 1 = disabled)
|-
| 12
| unsigned, Fragment light source 4 spot light disabled (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, Fragment light source 5 spot light disabled (0 = enabled, 1 = disabled)
|-
| 14
| unsigned, Fragment light source 6 spot light disabled (0 = enabled, 1 = disabled)
|-
| 15
| unsigned, Fragment light source 7 spot light disabled (0 = enabled, 1 = disabled)
|-
| 16
| unsigned, Term 0 distribution component D0 LUT disabled (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, Term 1 distribution component D1 LUT disabled (0 = enabled, 1 = disabled)
|-
| 18
| 0x1
|-
| 19
| unsigned, Fresnel FR LUT disabled (0 = enabled, 1 = disabled)
|-
| 20
| unsigned, Term 1 reflection component RB LUT disabled (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, Term 1 reflection component RG LUT disabled (0 = enabled, 1 = disabled)
|-
| 22
| unsigned, Term 1 reflection component RR LUT disabled (0 = enabled, 1 = disabled)
|-
| 24
| unsigned, Fragment light source 0 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, Fragment light source 1 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 26
| unsigned, Fragment light source 2 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 27
| unsigned, Fragment light source 3 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 28
| unsigned, Fragment light source 4 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 29
| unsigned, Fragment light source 5 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 30
| unsigned, Fragment light source 6 distance attenuation disabled (0 = enabled, 1 = disabled)
|-
| 31
| unsigned, Fragment light source 7 distance attenuation disabled (0 = enabled, 1 = disabled)
|}

This register is used to disable various aspects of the light environment.

=== GPUREG_LIGHTING_LUT_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Starting index
|-
| 8-12
| unsigned, Look-up table
|}

This register controls which LUT and what offset into it the GPUREG_LIGHTING_LUT_DATA''i'' register writes to.

Lookup table values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| D0
|-
| 1
| D1
|-
| 3
| FR
|-
| 4
| RB
|-
| 5
| RG
|-
| 6
| RR
|-
| 8-15
| SP0-7
|-
| 16-23
| DA0-7
|}

=== GPUREG_LIGHTING_ENABLE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Disabled (0 = enabled, 1 = disabled)
|}

This register is set to 1 when fragment lighting is disabled, and to 0 when it is enabled.

=== GPUREG_LIGHTING_LUT_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-23
| LUT data
|}

Lighting LUT data is written here.

A LUT contains data for the input domain [-1.0, 1.0], which is indexed using a signed 8-bit number [-128, 127]. Therefore a LUT contains 256 entries. The index of a value is (int)(x/127.0f) & 0xFF.

DA: The input domain is [0.0, 1.0], and the index is an unsigned 8-bit number [0, 255] instead.

Format of an entry:

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| fixed0.0.12, Entry value
|-
| 12-23
| fixed1.0.11, Absolute value of the difference between the next entry and this entry, used to implement linear interpolation
|}

=== GPUREG_LIGHTING_LUTINPUT_ABS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1
| unsigned, abs() flag for the input of D0 (0 = enabled, 1 = disabled)
|-
| 5
| unsigned, abs() flag for the input of D1 (0 = enabled, 1 = disabled)
|-
| 9
| unsigned, abs() flag for the input of SP (0 = enabled, 1 = disabled)
|-
| 13
| unsigned, abs() flag for the input of FR (0 = enabled, 1 = disabled)
|-
| 17
| unsigned, abs() flag for the input of RB (0 = enabled, 1 = disabled)
|-
| 21
| unsigned, abs() flag for the input of RG (0 = enabled, 1 = disabled)
|-
| 25
| unsigned, abs() flag for the input of RR (0 = enabled, 1 = disabled)
|}

This register controls whether the absolute value of the input is taken before using a LUT.

=== GPUREG_LIGHTING_LUTINPUT_SELECT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Input selector for D0
|-
| 4-6
| unsigned, Input selector for D1
|-
| 8-10
| unsigned, Input selector for SP
|-
| 12-14
| unsigned, Input selector for FR
|-
| 16-18
| unsigned, Input selector for RB
|-
| 20-22
| unsigned, Input selector for RG
|-
| 24-26
| unsigned, Input selector for RR
|}

This register selects the input from LUTs.

Input selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| N·H
|-
| 1
| V·H
|-
| 2
| N·V
|-
| 3
| L·N
|-
| 4
| -L·P (aka Spotlight aka SP)
|-
| 5
| cos φ (aka CP)
|}

=== GPUREG_LIGHTING_LUTINPUT_SCALE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, Scaler selector for D0
|-
| 4-6
| unsigned, Scaler selector for D1
|-
| 8-10
| unsigned, Scaler selector for SP
|-
| 12-14
| unsigned, Scaler selector for FR
|-
| 16-18
| unsigned, Scaler selector for RB
|-
| 20-22
| unsigned, Scaler selector for RG
|-
| 24-26
| unsigned, Scaler selector for RR
|}

This register controls the scaling that is applied to the output of a LUT.

Scaler selector values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 1x
|-
| 1
| 2x
|-
| 2
| 4x
|-
| 3
| 8x
|-
| 6
| 0.25x
|-
| 7
| 0.5x
|}

=== GPUREG_LIGHTING_LIGHT_PERMUTATION ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-2
| unsigned, ID of the 1st enabled light
|-
| 4-6
| unsigned, ID of the 2nd enabled light
|-
| 8-10
| unsigned, ID of the 3rd enabled light
|-
| 12-14
| unsigned, ID of the 4th enabled light
|-
| 16-18
| unsigned, ID of the 5th enabled light
|-
| 20-22
| unsigned, ID of the 6th enabled light
|-
| 24-26
| unsigned, ID of the 7th enabled light
|-
| 28-30
| unsigned, ID of the 8th enabled light
|}

This register sets the IDs of enabled light sources.

== Geometry pipeline registers ==

=== GPUREG_ATTRIBBUFFERS_LOC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 1-28
| unsigned, Vertex arrays base address
|}

This register sets the base address of all vertex arrays.

=== GPUREG_ATTRIBBUFFERS_FORMAT_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 0 type
|-
| 2-3
| unsigned, Vertex attribute 0 size
|-
| 4-5
| unsigned, Vertex attribute 1 type
|-
| 6-7
| unsigned, Vertex attribute 1 size
|-
| 8-9
| unsigned, Vertex attribute 2 type
|-
| 10-11
| unsigned, Vertex attribute 2 size
|-
| 12-13
| unsigned, Vertex attribute 3 type
|-
| 14-15
| unsigned, Vertex attribute 3 size
|-
| 16-17
| unsigned, Vertex attribute 4 type
|-
| 18-19
| unsigned, Vertex attribute 4 size
|-
| 20-21
| unsigned, Vertex attribute 5 type
|-
| 22-23
| unsigned, Vertex attribute 5 size
|-
| 24-25
| unsigned, Vertex attribute 6 type
|-
| 26-27
| unsigned, Vertex attribute 6 size
|-
| 28-29
| unsigned, Vertex attribute 7 type
|-
| 30-31
| unsigned, Vertex attribute 7 size
|}

This register configures the types and sizes of the first 8 vertex attributes.

Vertex attribute type values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Byte
|-
| 1
| Unsigned byte
|-
| 2
| Short
|-
| 3
| Float
|}

Vertex attribute size values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| 8 bits
|-
| 1
| 16 bits
|-
| 2
| 24 bits
|-
| 3
| 32 bits
|}

=== GPUREG_ATTRIBBUFFERS_FORMAT_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Vertex attribute 8 type
|-
| 2-3
| unsigned, Vertex attribute 8 size
|-
| 4-5
| unsigned, Vertex attribute 9 type
|-
| 6-7
| unsigned, Vertex attribute 9 size
|-
| 8-9
| unsigned, Vertex attribute 10 type
|-
| 10-11
| unsigned, Vertex attribute 10 size
|-
| 12-13
| unsigned, Vertex attribute 11 type
|-
| 14-15
| unsigned, Vertex attribute 11 size
|-
| 16-27
| unsigned, Fixed vertex attribute mask
|-
| 28-31
| unsigned, Total vertex attribute count - 1
|}

This register configures the types and sizes of the last 4 vertex attributes, along with the attribute mask and the total attribute count.

See GPUREG_ATTRIBBUFFERS_FORMAT_LOW for vertex attribute type and size values.

=== GPUREG_ATTRIBBUFFER''i''_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|}

This register configures the offset of a vertex array from the base vertex arrays address.

=== GPUREG_ATTRIBBUFFER''i''_CONFIG1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 1
|-
| 4-7
| unsigned, Component 2
|-
| 8-11
| unsigned, Component 3
|-
| 12-15
| unsigned, Component 4
|-
| 16-19
| unsigned, Component 5
|-
| 20-23
| unsigned, Component 6
|-
| 24-27
| unsigned, Component 7
|-
| 28-31
| unsigned, Component 8
|}

This register configures the first 8 component types of a vertex array.

Component values:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Vertex attribute 0
|-
| 1
| Vertex attribute 1
|-
| 2
| Vertex attribute 2
|-
| 3
| Vertex attribute 3
|-
| 4
| Vertex attribute 4
|-
| 5
| Vertex attribute 5
|-
| 6
| Vertex attribute 6
|-
| 7
| Vertex attribute 7
|-
| 8
| Vertex attribute 8
|-
| 9
| Vertex attribute 9
|-
| 10
| Vertex attribute 10
|-
| 11
| Vertex attribute 11
|-
| 12
| 4-byte padding
|-
| 13
| 8-byte padding
|-
| 14
| 12-byte padding
|-
| 15
| 16-byte padding
|}

=== GPUREG_ATTRIBBUFFER''i''_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Component 9
|-
| 4-7
| unsigned, Component 10
|-
| 8-11
| unsigned, Component 11
|-
| 12-15
| unsigned, Component 12
|-
| 16-23
| unsigned, Bytes per vertex
|-
| 28-31
| unsigned, Total number of components
|}

This register configures the last 4 component types of a vertex array, along with the bytes per vertex and the total number of components.

See GPUREG_ATTRIBBUFFER''i''_CONFIG1 for component values.

=== GPUREG_INDEXBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-27
| unsigned, Offset from base vertex arrays address
|-
| 31
| Index type (0 = unsigned byte, 1 = unsigned short or drawing arrays)
|}

This register configures the index array used when drawing elements.

=== GPUREG_NUMVERTICES ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Number of vertices to render
|}

This register sets the number of vertices to render.

=== GPUREG_GEOSTAGE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-1
| unsigned, Geometry shader in use (0 = not in use, 2 = in use)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|-
| 9
| 0x0
|-
| 31
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_VERTEX_OFFSET ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Starting vertex offset
|}

This register sets the offset of the first vertex in an array to render.

=== GPUREG_POST_VERTEX_CACHE_NUM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Number of entries in the post-vertex cache (usually 0x4 or 0x84)
|}

This register configures the post-vertex cache.

=== GPUREG_DRAWARRAYS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw arrays)
|}

This register triggers drawing vertex arrays.

=== GPUREG_DRAWELEMENTS ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = draw elements)
|}

This register triggers drawing vertex array elements.

=== GPUREG_VTX_FUNC ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = clear post-vertex cache)
|}

This register triggers clearing the post-vertex cache.

=== GPUREG_FIXEDATTRIB_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Fixed attribute index (0-11, 0xF = immediate-mode submission)
|}

This register selects the index of the fixed attribute to be input with GPUREG_FIXEDATTRIB_DATA''i''. See [[GPU/Fixed Vertex Attributes]] and [[GPU/Immediate-Mode Vertex Submission]] for usage info.

=== GPUREG_FIXEDATTRIB_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| colspan="2" | '''DATA0:'''
|-
| 0-7
| float1.7.16, Vertex attribute element 3 (Z) (bits 16-23)
|-
| 8-31
| float1.7.16, Vertex attribute element 4 (W)
|-
| colspan="2" | '''DATA1:'''
|-
| 0-15
| float1.7.16, Vertex attribute element 2 (Y) (bits 8-23)
|-
| 16-31
| float1.7.16, Vertex attribute element 3 (Z) (bits 0-15)
|-
| colspan="2" | '''DATA2:'''
|-
| 0-23
| float1.7.16, Vertex attribute element 1 (X)
|-
| 24-31
| float1.7.16, Vertex attribute element 2 (Y) (bits 0-7)
|}

Accepts four 24-bit floating-point values that make up a vertex attribute. Stored in the fixed attribute currently specified with GPUREG_FIXEDATTRIB_INDEX. If immediate-mode vertex submission is enabled (by writing 0xF to the index register) then vertex data is input here directly.

=== GPUREG_CMDBUF_SIZE0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 0 >> 3
|}

This register sets the size of the first command buffer.

=== GPUREG_CMDBUF_SIZE1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-20
| unsigned, Size of command buffer 1 >> 3
|}

This register sets the size of the second command buffer.

=== GPUREG_CMDBUF_ADDR0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 0 >> 3
|}

This register sets the physical address of the first command buffer.

=== GPUREG_CMDBUF_ADDR1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-28
| unsigned, Physical address of command buffer 1 >> 3
|}

This register sets the physical address of the second command buffer.

=== GPUREG_CMDBUF_JUMP0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 0)
|}

This register triggers a jump to the first command buffer.

=== GPUREG_CMDBUF_JUMP1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Trigger (0 = idle, non-zero = execute command buffer 1)
|}

This register triggers a jump to the second command buffer.

=== GPUREG_VSH_NUM_ATTR ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader input attributes - 1
|}

This register sets the number of vertex shader input attributes.

=== GPUREG_VSH_COM_MODE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Geometry shader configuration enabled (0 = disabled, 1 = enabled)
|}

This register sets whether to use the geometry shader configuration or reuse the vertex shader configuration for the geometry shader shading unit.

=== GPUREG_START_DRAW_FUNC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Mode (0 = drawing, 1 = configuration)
|-
| 1-7
| 0x0
|}

This register is related to drawing. When the mode value is set to 1, rendering is not performed properly. When set to 0, changes to the vertex shader configuration registers are not applied correctly. Because of this, it is usually initialized to 1, set to 0 immediately before triggering a draw, and set back to 1 immediately after triggering a draw.

=== GPUREG_VSH_OUTMAP_TOTAL1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_VSH_OUTMAP_TOTAL2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|}

This register sets the number of vertex shader output map registers.

=== GPUREG_GSH_MISC0 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Misc data (0x00000001 = Reserved geometry shader subdivision in use, 0x01004302 = Particle system in use, 0 otherwise)
|}

This register configures miscellaneous geometry shader properties.

=== GPUREG_GEOSTAGE_CONFIG2 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Function indicator (with vertex buffers: 0 = draw elements, 1 = draw arrays, without: 0 = not inputting, 1 = inputting vertex attribute data)
|-
| 8
| unsigned, Drawing triangle elements (0 = not, 1 = drawing triangle elements)
|}

This register configures the geometry stage of the GPU pipeline.

When using vertex buffers, bit 0 is set to 1 before drawing arrays, and cleared to 0 immediately after. When using immediate mode to directly input vertex attribute data, bit 0 is set to 1 before inputting vertex attribute data, and cleared to 0 immediately after. While bit 0 is set to 1, some register writes outside of the 0x200-0x254 and 0x280-0x2DF ranges may be processed incorrectly.

When using vertex buffers and drawing elements in triangles mode, bit 8 is set to 1, else it is set to 0.

=== GPUREG_GSH_MISC1 ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-4
| unsigned, Reserved geometry shader subdivision type (2 = Loop, 3 = Catmull-Clark)
|}

This register configures the type of reserved geometry shader subdivision in use. The value is ignored when a subdivision is not in use.

=== GPUREG_PRIMITIVE_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Number of vertex shader output map registers - 1
|-
| 8-9
| unsigned, Primitive mode
|}

This register configures primitive drawing.

Primitive mode value:

{| class="wikitable" border="1"
! Value
! Description
|-
| 0
| Triangles
|-
| 1
| Triangle strip
|-
| 2
| Triangle fan
|-
| 3
| Geometry primitive
|}

=== GPUREG_RESTART_PRIMITIVE ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Trigger (0 = idle, 1 = reset primitive)
|-
| 1-31
| 0x0
|}

This register triggers resetting primitive drawing.

== Shader registers ==

=== GPUREG_''SH''_BOOLUNIFORM ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Boolean register b0 value (0 = false, 1 = true)
|-
| 1
| unsigned, Boolean register b1 value (0 = false, 1 = true)
|-
| 2
| unsigned, Boolean register b2 value (0 = false, 1 = true)
|-
| 3
| unsigned, Boolean register b3 value (0 = false, 1 = true)
|-
| 4
| unsigned, Boolean register b4 value (0 = false, 1 = true)
|-
| 5
| unsigned, Boolean register b5 value (0 = false, 1 = true)
|-
| 6
| unsigned, Boolean register b6 value (0 = false, 1 = true)
|-
| 7
| unsigned, Boolean register b7 value (0 = false, 1 = true)
|-
| 8
| unsigned, Boolean register b8 value (0 = false, 1 = true)
|-
| 9
| unsigned, Boolean register b9 value (0 = false, 1 = true)
|-
| 10
| unsigned, Boolean register b10 value (0 = false, 1 = true)
|-
| 11
| unsigned, Boolean register b11 value (0 = false, 1 = true)
|-
| 12
| unsigned, Boolean register b12 value (0 = false, 1 = true)
|-
| 13
| unsigned, Boolean register b13 value (0 = false, 1 = true)
|-
| 14
| unsigned, Boolean register b14 value (0 = false, 1 = true)
|-
| 15
| unsigned, Boolean register b15 value (0 = false, 1 = true)
|-
| 16-31
| 0x7FFF
|}

This register is used to set a shader unit's boolean registers.

=== GPUREG_''SH''_INTUNIFORM_I''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Integer register i''i'' X value
|-
| 8-15
| unsigned, Integer register i''i'' Y value
|-
| 16-23
| unsigned, Integer register i''i'' Z value
|-
| 24-31
| unsigned, Integer register i''i'' W value
|}

These registers are used to set a shader unit's integer registers.

=== GPUREG_''SH''_INPUTBUFFER_CONFIG ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Input vertex attributes - 1
|-
| 8-15
| unsigned, Use reserved geometry shader subdivision (0 = don't use, 1 = use) (always 0 for vertex shaders)
|-
| 16-23
| 0x0
|-
| 24-31
| unsigned, Use geometry shader (0x8 = use, 0xA0 = don't use) (always 0xA0 for vertex shaders)
|}

This register is used to configure a shader unit's input buffer.

=== GPUREG_''SH''_ENTRYPOINT ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-15
| unsigned, Code entry point offset, in 32-bit words
|-
| 16-31
| 0x7FFF
|}

This register sets a shader unit's code entry point.

For geometry shaders, this sets the entry point for the single shader unit which can be dedicated to running geometry shaders, regardless of the current geometry stage mode. This is means that while this register is normally used to set the geometry shader entry point, it can also be used to set this single shader unit to run from a different entry point than the other three, even when running a vertex shader.

For vertex shaders, this sets the entry point for the shader units set to vertex shader mode. Depending on the current geometry stage mode this can include either all 4 shader units or just 3 of them.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_LOW ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 0 input register index
|-
| 4-7
| unsigned, Vertex attribute 1 input register index
|-
| 8-11
| unsigned, Vertex attribute 2 input register index
|-
| 12-15
| unsigned, Vertex attribute 3 input register index
|-
| 16-19
| unsigned, Vertex attribute 4 input register index
|-
| 20-23
| unsigned, Vertex attribute 5 input register index
|-
| 24-27
| unsigned, Vertex attribute 6 input register index
|-
| 28-31
| unsigned, Vertex attribute 7 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for the first 8 attributes. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 1st attribute.

=== GPUREG_''SH''_ATTRIBUTES_PERMUTATION_HIGH ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-3
| unsigned, Vertex attribute 8 input register index
|-
| 4-7
| unsigned, Vertex attribute 9 input register index
|-
| 8-11
| unsigned, Vertex attribute 10 input register index
|-
| 12-15
| unsigned, Vertex attribute 11 input register index
|-
| 16-19
| unsigned, Vertex attribute 12 input register index
|-
| 20-23
| unsigned, Vertex attribute 13 input register index
|-
| 24-27
| unsigned, Vertex attribute 14 input register index
|-
| 28-31
| unsigned, Vertex attribute 15 input register index
|}

This register sets the shader unit input register index which will correspond to each attribute contained by the input buffer (which in the case of geometry shaders is the vertex shader output buffer) for attributes 8 through 15. For example, having bits 0-3 set to 5 means that, in the shader program, v5 will contain the input buffer's 9th attribute.

=== GPUREG_''SH''_OUTMAP_MASK ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0
| unsigned, Output register o0 enabled (0 = disabled, 1 = enabled)
|-
| 1
| unsigned, Output register o1 enabled (0 = disabled, 1 = enabled)
|-
| 2
| unsigned, Output register o2 enabled (0 = disabled, 1 = enabled)
|-
| 3
| unsigned, Output register o3 enabled (0 = disabled, 1 = enabled)
|-
| 4
| unsigned, Output register o4 enabled (0 = disabled, 1 = enabled)
|-
| 5
| unsigned, Output register o5 enabled (0 = disabled, 1 = enabled)
|-
| 6
| unsigned, Output register o6 enabled (0 = disabled, 1 = enabled)
|-
| 7
| unsigned, Output register o7 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 8
| unsigned, Output register o8 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 9
| unsigned, Output register o9 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 10
| unsigned, Output register o10 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 11
| unsigned, Output register o11 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 12
| unsigned, Output register o12 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 13
| unsigned, Output register o13 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 14
| unsigned, Output register o14 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 15
| unsigned, Output register o15 enabled (0 = disabled, 1 = enabled) (vertex shader only)
|-
| 16-31
| 0x0
|}

This register toggles a shader unit's output registers.

=== GPUREG_''SH''_CODETRANSFER_END ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Signal transfer end (0 = idle, non-zero = signal)
|}

This register's value should be set to 1 in order to finalize the transfer of shader code.

=== GPUREG_''SH''_FLOATUNIFORM_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-7
| unsigned, Target floating-point register index (range 0-95, where 0 = c0 and 95 = c95)
|-
| 31
| unsigned, Transfer mode (0 = float1.7.16, 1 = float1.8.23)
|}

This register sets the shader unit's target floating-point register and transfer mode for the data transfer system. As such it is typically used right before [[#GPUREG_SH_FLOATUNIFORM_DATAi|GPUREG_''SH''_FLOATUNIFORM_DATA''i'']], though writing to one register does not make writing to the other mandatory.

=== GPUREG_''SH''_FLOATUNIFORM_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| Floating-point register component data
|}

This register is used to set the components of a shader unit's floating-point registers, each having 4 components. The data format which should be written to it depends on the transfer mode set with [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]]. This register functions as a FIFO queue: after each time a 4-component uniform register is successfully set, the target register index is incremented, meaning that groups of uniforms with contiguous register IDs can be set with only one initial write to [[#GPUREG_SH_FLOATUNIFORM_INDEX|GPUREG_''SH''_FLOATUNIFORM_INDEX]].

* In the case of float24 transfer mode, data should be sent by writing three words which are the concatenation of the float24 value of the uniform register's 4 components, in the reverse order. Assuming each letter corresponds to 4 bits, the format becomes:
** first word : ZZWWWWWW
** second word : YYYYZZZZ
** third word : XXXXXXYY
* In the case of float32 transfer mode, data should be sent by writing four words which are each the float32 value of the uniform register's 4 components, in the reverse order.

=== GPUREG_''SH''_CODETRANSFER_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader code offset
|}

This register is used to set the offset at which upcoming shader code data transferred through [[#GPUREG_SH_CODETRANSFER_DATAi|GPUREG_''SH''_CODETRANSFER_DATA''i'']] should be written.

=== GPUREG_''SH''_CODETRANSFER_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader instruction data
|}

This register is used to transfer shader code data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader code memory bank at the offset initially set by [[#GPUREG_SH_CODETRANSFER_INDEX|GPUREG_''SH''_CODETRANSFER_INDEX]]. The offset in question is incremented after each write to this register.

=== GPUREG_''SH''_OPDESCS_INDEX ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-11
| unsigned, Target shader operand descriptor offset
|}

This register is used to set the offset at which upcoming shader operand descriptor data transferred through [[#GPUREG_SH_OPDESCS_DATAi|GPUREG_''SH''_OPDESCS_DATA''i'']] should be written.

=== GPUREG_''SH''_OPDESCS_DATA''i'' ===

{| class="wikitable" border="1"
! Bits
! Description
|-
| 0-31
| unsigned, Shader operand descriptor data
|}

This register is used to transfer shader operand descriptor data. This register behaves as a FIFO queue: each write to this register writes the provided value to the GPU shader operand descriptor memory bank at the offset initially set by [[#GPUREG_SH_OPDESCS_INDEX|GPUREG_''SH''_OPDESCS_INDEX]]. The offset in question is incremented after each write to this register.